cam_soc_util.h 22 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _CAM_SOC_UTIL_H_
  6. #define _CAM_SOC_UTIL_H_
  7. #include <linux/slab.h>
  8. #include <linux/clk.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/io.h>
  11. #include <linux/delay.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/i2c.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <linux/debugfs.h>
  16. #include <linux/of_fdt.h>
  17. #include "cam_io_util.h"
  18. #include <media/cam_defs.h>
  19. #define NO_SET_RATE -1
  20. #define INIT_RATE -2
  21. /* maximum number of device block */
  22. #define CAM_SOC_MAX_BLOCK 7
  23. /* maximum number of device base */
  24. #define CAM_SOC_MAX_BASE CAM_SOC_MAX_BLOCK
  25. /* maximum number of device regulator */
  26. #define CAM_SOC_MAX_REGULATOR 10
  27. /* maximum number of device clock */
  28. #define CAM_SOC_MAX_CLK 32
  29. /* DDR device types */
  30. #define DDR_TYPE_LPDDR4 6
  31. #define DDR_TYPE_LPDDR4X 7
  32. #define DDR_TYPE_LPDDR5 8
  33. #define DDR_TYPE_LPDDR5X 9
  34. /**
  35. * enum cam_vote_level - Enum for voting level
  36. *
  37. * @CAM_SUSPEND_VOTE : Suspend vote
  38. * @CAM_MINSVS_VOTE : Min SVS vote
  39. * @CAM_LOWSVS_VOTE : Low SVS vote
  40. * @CAM_SVS_VOTE : SVS vote
  41. * @CAM_SVSL1_VOTE : SVS Plus vote
  42. * @CAM_NOMINAL_VOTE : Nominal vote
  43. * @CAM_NOMINALL1_VOTE: Nominal plus vote
  44. * @CAM_TURBO_VOTE : Turbo vote
  45. * @CAM_MAX_VOTE : Max voting level, This is invalid level.
  46. */
  47. enum cam_vote_level {
  48. CAM_SUSPEND_VOTE,
  49. CAM_MINSVS_VOTE,
  50. CAM_LOWSVS_VOTE,
  51. CAM_SVS_VOTE,
  52. CAM_SVSL1_VOTE,
  53. CAM_NOMINAL_VOTE,
  54. CAM_NOMINALL1_VOTE,
  55. CAM_TURBO_VOTE,
  56. CAM_MAX_VOTE,
  57. };
  58. /* pinctrl states */
  59. #define CAM_SOC_PINCTRL_STATE_SLEEP "cam_suspend"
  60. #define CAM_SOC_PINCTRL_STATE_DEFAULT "cam_default"
  61. /**
  62. * struct cam_soc_reg_map: Information about the mapped register space
  63. *
  64. * @mem_base: Starting location of MAPPED register space
  65. * @mem_cam_base: Starting offset of this register space compared
  66. * to ENTIRE Camera register space
  67. * @size: Size of register space
  68. **/
  69. struct cam_soc_reg_map {
  70. void __iomem *mem_base;
  71. uint32_t mem_cam_base;
  72. resource_size_t size;
  73. };
  74. /**
  75. * struct cam_soc_pinctrl_info: Information about pinctrl data
  76. *
  77. * @pinctrl: pintrl object
  78. * @gpio_state_active: default pinctrl state
  79. * @gpio_state_suspend suspend state of pinctrl
  80. **/
  81. struct cam_soc_pinctrl_info {
  82. struct pinctrl *pinctrl;
  83. struct pinctrl_state *gpio_state_active;
  84. struct pinctrl_state *gpio_state_suspend;
  85. };
  86. /**
  87. * struct cam_soc_gpio_data: Information about the gpio pins
  88. *
  89. * @cam_gpio_common_tbl: It is list of al the gpios present in gpios node
  90. * @cam_gpio_common_tbl_size: It is equal to number of gpios prsent in
  91. * gpios node in DTSI
  92. * @cam_gpio_req_tbl It is list of al the requesetd gpios
  93. * @cam_gpio_req_tbl_size: It is size of requested gpios
  94. **/
  95. struct cam_soc_gpio_data {
  96. struct gpio *cam_gpio_common_tbl;
  97. uint8_t cam_gpio_common_tbl_size;
  98. struct gpio *cam_gpio_req_tbl;
  99. uint8_t cam_gpio_req_tbl_size;
  100. };
  101. /**
  102. * struct cam_hw_soc_info: Soc information pertaining to specific instance of
  103. * Camera hardware driver module
  104. *
  105. * @pdev: Platform device pointer
  106. * @device: Device pointer
  107. * @hw_version: Camera device version
  108. * @index: Instance id for the camera device
  109. * @dev_name: Device Name
  110. * @irq_name: Name of the irq associated with the device
  111. * @label_name: label name
  112. * @irq_line: Irq resource
  113. * @irq_data: Private data that is passed when IRQ is requested
  114. * @compatible: Compatible string associated with the device
  115. * @num_mem_block: Number of entry in the "reg-names"
  116. * @mem_block_name: Array of the reg block name
  117. * @mem_block_cam_base: Array of offset of this register space compared
  118. * to ENTIRE Camera register space
  119. * @mem_block: Associated resource structs
  120. * @reg_map: Array of Mapped register info for the "reg-names"
  121. * @num_reg_map: Number of mapped register space associated
  122. * with mem_block. num_reg_map = num_mem_block in
  123. * most cases
  124. * @reserve_mem: Whether to reserve memory for Mem blocks
  125. * @num_rgltr: Number of regulators
  126. * @rgltr_name: Array of regulator names
  127. * @rgltr_ctrl_support: Whether regulator control is supported
  128. * @rgltr_min_volt: Array of minimum regulator voltage
  129. * @rgltr_max_volt: Array of maximum regulator voltage
  130. * @rgltr_op_mode: Array of regulator operation mode
  131. * @rgltr_type: Array of regulator names
  132. * @rgltr: Array of associated regulator resources
  133. * @rgltr_delay: Array of regulator delay values
  134. * @num_clk: Number of clocks
  135. * @clk_name: Array of clock names
  136. * @clk: Array of associated clock resources
  137. * @clk_rate: 2D array of clock rates representing clock rate
  138. * values at different vote levels
  139. * @prev_clk_level Last vote level
  140. * @src_clk_idx: Source clock index that is rate-controllable
  141. * @clk_level_valid: Indicates whether corresponding level is valid
  142. * @scl_clk_count: Number of scalable clocks present
  143. * @scl_clk_idx: Index of scalable clocks
  144. * @gpio_data: Pointer to gpio info
  145. * @pinctrl_info: Pointer to pinctrl info
  146. * @dentry: Debugfs entry
  147. * @clk_level_override: Clk level set from debugfs
  148. * @clk_control: Enable/disable clk rate control through debugfs
  149. * @cam_cx_ipeak_enable cx-ipeak enable/disable flag
  150. * @cam_cx_ipeak_bit cx-ipeak mask for driver
  151. * @soc_private: Soc private data
  152. */
  153. struct cam_hw_soc_info {
  154. struct platform_device *pdev;
  155. struct device *dev;
  156. uint32_t hw_version;
  157. uint32_t index;
  158. const char *dev_name;
  159. const char *irq_name;
  160. const char *label_name;
  161. struct resource *irq_line;
  162. void *irq_data;
  163. const char *compatible;
  164. uint32_t num_mem_block;
  165. const char *mem_block_name[CAM_SOC_MAX_BLOCK];
  166. uint32_t mem_block_cam_base[CAM_SOC_MAX_BLOCK];
  167. struct resource *mem_block[CAM_SOC_MAX_BLOCK];
  168. struct cam_soc_reg_map reg_map[CAM_SOC_MAX_BASE];
  169. uint32_t num_reg_map;
  170. uint32_t reserve_mem;
  171. uint32_t num_rgltr;
  172. const char *rgltr_name[CAM_SOC_MAX_REGULATOR];
  173. uint32_t rgltr_ctrl_support;
  174. uint32_t rgltr_min_volt[CAM_SOC_MAX_REGULATOR];
  175. uint32_t rgltr_max_volt[CAM_SOC_MAX_REGULATOR];
  176. uint32_t rgltr_op_mode[CAM_SOC_MAX_REGULATOR];
  177. uint32_t rgltr_type[CAM_SOC_MAX_REGULATOR];
  178. struct regulator *rgltr[CAM_SOC_MAX_REGULATOR];
  179. uint32_t rgltr_delay[CAM_SOC_MAX_REGULATOR];
  180. uint32_t use_shared_clk;
  181. uint32_t num_clk;
  182. const char *clk_name[CAM_SOC_MAX_CLK];
  183. struct clk *clk[CAM_SOC_MAX_CLK];
  184. int32_t clk_rate[CAM_MAX_VOTE][CAM_SOC_MAX_CLK];
  185. int32_t prev_clk_level;
  186. int32_t src_clk_idx;
  187. bool clk_level_valid[CAM_MAX_VOTE];
  188. int32_t scl_clk_count;
  189. int32_t scl_clk_idx[CAM_SOC_MAX_CLK];
  190. struct cam_soc_gpio_data *gpio_data;
  191. struct cam_soc_pinctrl_info pinctrl_info;
  192. struct dentry *dentry;
  193. uint32_t clk_level_override;
  194. bool clk_control_enable;
  195. bool cam_cx_ipeak_enable;
  196. int32_t cam_cx_ipeak_bit;
  197. void *soc_private;
  198. };
  199. /*
  200. * CAM_SOC_GET_REG_MAP_START
  201. *
  202. * @brief: This MACRO will get the mapped starting address
  203. * where the register space can be accessed
  204. *
  205. * @__soc_info: Device soc information
  206. * @__base_index: Index of register space in the HW block
  207. *
  208. * @return: Returns a pointer to the mapped register memory
  209. */
  210. #define CAM_SOC_GET_REG_MAP_START(__soc_info, __base_index) \
  211. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  212. NULL : __soc_info->reg_map[__base_index].mem_base)
  213. /*
  214. * CAM_SOC_GET_REG_MAP_CAM_BASE
  215. *
  216. * @brief: This MACRO will get the cam_base of the
  217. * register space
  218. *
  219. * @__soc_info: Device soc information
  220. * @__base_index: Index of register space in the HW block
  221. *
  222. * @return: Returns an int32_t value.
  223. * Failure: -1
  224. * Success: Starting offset of register space compared
  225. * to entire Camera Register Map
  226. */
  227. #define CAM_SOC_GET_REG_MAP_CAM_BASE(__soc_info, __base_index) \
  228. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  229. -1 : __soc_info->reg_map[__base_index].mem_cam_base)
  230. /*
  231. * CAM_SOC_GET_REG_MAP_SIZE
  232. *
  233. * @brief: This MACRO will get the size of the mapped
  234. * register space
  235. *
  236. * @__soc_info: Device soc information
  237. * @__base_index: Index of register space in the HW block
  238. *
  239. * @return: Returns a uint32_t value.
  240. * Failure: 0
  241. * Success: Non-zero size of mapped register space
  242. */
  243. #define CAM_SOC_GET_REG_MAP_SIZE(__soc_info, __base_index) \
  244. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  245. 0 : __soc_info->reg_map[__base_index].size)
  246. /**
  247. * cam_soc_util_get_level_from_string()
  248. *
  249. * @brief: Get the associated vote level for the input string
  250. *
  251. * @string: Input string to compare with.
  252. * @level: Vote level corresponds to input string.
  253. *
  254. * @return: Success or failure
  255. */
  256. int cam_soc_util_get_level_from_string(const char *string,
  257. enum cam_vote_level *level);
  258. /**
  259. * cam_soc_util_get_dt_properties()
  260. *
  261. * @brief: Parse the DT and populate the common properties that
  262. * are part of the soc_info structure - register map,
  263. * clocks, regulators, irq, etc.
  264. *
  265. * @soc_info: Device soc struct to be populated
  266. *
  267. * @return: Success or failure
  268. */
  269. int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info);
  270. /**
  271. * cam_soc_util_request_platform_resource()
  272. *
  273. * @brief: Request regulator, irq, and clock resources
  274. *
  275. * @soc_info: Device soc information
  276. * @handler: Irq handler function pointer
  277. * @irq_data: Irq handler function CB data
  278. *
  279. * @return: Success or failure
  280. */
  281. int cam_soc_util_request_platform_resource(struct cam_hw_soc_info *soc_info,
  282. irq_handler_t handler, void *irq_data);
  283. /**
  284. * cam_soc_util_release_platform_resource()
  285. *
  286. * @brief: Release regulator, irq, and clock resources
  287. *
  288. * @soc_info: Device soc information
  289. *
  290. * @return: Success or failure
  291. */
  292. int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info);
  293. /**
  294. * cam_soc_util_enable_platform_resource()
  295. *
  296. * @brief: Enable regulator, irq resources
  297. *
  298. * @soc_info: Device soc information
  299. * @enable_clocks: Boolean flag:
  300. * TRUE: Enable all clocks in soc_info Now.
  301. * False: Don't enable clocks Now. Driver will
  302. * enable independently.
  303. * @clk_level: Clock level to be applied.
  304. * Applicable only if enable_clocks is true
  305. * Valid range : 0 to (CAM_MAX_VOTE - 1)
  306. * @enable_irq: Boolean flag:
  307. * TRUE: Enable IRQ in soc_info Now.
  308. * False: Don't enable IRQ Now. Driver will
  309. * enable independently.
  310. *
  311. * @return: Success or failure
  312. */
  313. int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info,
  314. bool enable_clocks, enum cam_vote_level clk_level, bool enable_irq);
  315. /**
  316. * cam_soc_util_disable_platform_resource()
  317. *
  318. * @brief: Disable regulator, irq resources
  319. *
  320. * @soc_info: Device soc information
  321. * @disable_irq: Boolean flag:
  322. * TRUE: Disable IRQ in soc_info Now.
  323. * False: Don't disable IRQ Now. Driver will
  324. * disable independently.
  325. *
  326. * @return: Success or failure
  327. */
  328. int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info,
  329. bool disable_clocks, bool disable_irq);
  330. /**
  331. * cam_soc_util_get_clk_round_rate()
  332. *
  333. * @brief: Get the rounded clock rate for the given clock's
  334. * clock rate value
  335. *
  336. * @soc_info: Device soc information
  337. * @clk_index: Clock index in soc_info for which round rate is needed
  338. * @clk_rate: Input clock rate for which rounded rate is needed
  339. *
  340. * @return: Rounded clock rate
  341. */
  342. long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
  343. uint32_t clk_index, unsigned long clk_rate);
  344. /**
  345. * cam_soc_util_set_src_clk_rate()
  346. *
  347. * @brief: Set the rate on the source clock.
  348. *
  349. * @soc_info: Device soc information
  350. * @clk_rate: Clock rate associated with the src clk
  351. *
  352. * @return: success or failure
  353. */
  354. int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
  355. int32_t clk_rate);
  356. /**
  357. * cam_soc_util_get_option_clk_by_name()
  358. *
  359. * @brief: Get reference to optional clk using name
  360. *
  361. * @soc_info: Device soc information
  362. * @clk_name: Name of clock to find reference for
  363. * @clk: Clock reference pointer to be filled if Success
  364. * @clk_index: Clk index in the option clk array to be returned
  365. * @clk_rate: Clk rate in the option clk array
  366. *
  367. * @return: 0: Success
  368. * Negative: Failure
  369. */
  370. int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
  371. const char *clk_name, struct clk **clk, int32_t *clk_index,
  372. int32_t *clk_rate);
  373. /**
  374. * cam_soc_util_clk_put()
  375. *
  376. * @brief: Put clock specified in params
  377. *
  378. * @clk: Reference to the Clock that needs to be put
  379. *
  380. * @return: Success or failure
  381. */
  382. int cam_soc_util_clk_put(struct clk **clk);
  383. /**
  384. * cam_soc_util_clk_enable()
  385. *
  386. * @brief: Enable clock specified in params
  387. *
  388. * @clk: Clock that needs to be turned ON
  389. * @clk_name: Clocks name associated with clk
  390. * @clk_rate: Clocks rate associated with clk
  391. *
  392. * @return: Success or failure
  393. */
  394. int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name,
  395. int32_t clk_rate);
  396. /**
  397. * cam_soc_util_set_clk_rate_level()
  398. *
  399. * @brief: Apply clock rates for the requested level.
  400. * This applies the new requested level for all
  401. * the clocks listed in DT based on their values.
  402. *
  403. * @soc_info: Device soc information
  404. * @clk_level: Clock level number to set
  405. *
  406. * @return: Success or failure
  407. */
  408. int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
  409. enum cam_vote_level clk_level);
  410. /**
  411. * cam_soc_util_clk_disable()
  412. *
  413. * @brief: Disable clock specified in params
  414. *
  415. * @clk: Clock that needs to be turned OFF
  416. * @clk_name: Clocks name associated with clk
  417. *
  418. * @return: Success or failure
  419. */
  420. int cam_soc_util_clk_disable(struct clk *clk, const char *clk_name);
  421. /**
  422. * cam_soc_util_irq_enable()
  423. *
  424. * @brief: Enable IRQ in SOC
  425. *
  426. * @soc_info: Device soc information
  427. *
  428. * @return: Success or failure
  429. */
  430. int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info);
  431. /**
  432. * cam_soc_util_irq_disable()
  433. *
  434. * @brief: Disable IRQ in SOC
  435. *
  436. * @soc_info: Device soc information
  437. *
  438. * @return: Success or failure
  439. */
  440. int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info);
  441. /**
  442. * cam_soc_util_regulator_enable()
  443. *
  444. * @brief: Enable single regulator
  445. *
  446. * @rgltr Regulator that needs to be turned ON
  447. * @rgltr_name Associated Regulator name
  448. * @rgltr_min_volt: Requested minimum volatage
  449. * @rgltr_max_volt: Requested maximum volatage
  450. * @rgltr_op_mode: Requested Load
  451. * @rgltr_delay: Requested delay needed aaftre enabling regulator
  452. *
  453. * @return: Success or failure
  454. */
  455. int cam_soc_util_regulator_enable(struct regulator *rgltr,
  456. const char *rgltr_name,
  457. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  458. uint32_t rgltr_op_mode, uint32_t rgltr_delay);
  459. /**
  460. * cam_soc_util_regulator_enable()
  461. *
  462. * @brief: Disable single regulator
  463. *
  464. * @rgltr Regulator that needs to be turned ON
  465. * @rgltr_name Associated Regulator name
  466. * @rgltr_min_volt: Requested minimum volatage
  467. * @rgltr_max_volt: Requested maximum volatage
  468. * @rgltr_op_mode: Requested Load
  469. * @rgltr_delay: Requested delay needed aaftre enabling regulator
  470. *
  471. * @return: Success or failure
  472. */
  473. int cam_soc_util_regulator_disable(struct regulator *rgltr,
  474. const char *rgltr_name,
  475. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  476. uint32_t rgltr_op_mode, uint32_t rgltr_delay);
  477. /**
  478. * cam_soc_util_w()
  479. *
  480. * @brief: Camera SOC util for register write
  481. *
  482. * @soc_info: Device soc information
  483. * @base_index: Index of register space in the HW block
  484. * @offset: Offset of register to be read
  485. * @data: Value to be written
  486. *
  487. * @return: Success or Failure
  488. */
  489. static inline int cam_soc_util_w(struct cam_hw_soc_info *soc_info,
  490. uint32_t base_index, uint32_t offset, uint32_t data)
  491. {
  492. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  493. return -EINVAL;
  494. return cam_io_w(data,
  495. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  496. }
  497. /**
  498. * cam_soc_util_w_mb()
  499. *
  500. * @brief: Camera SOC util for register write with memory barrier.
  501. * Memory Barrier is only before the write to ensure the
  502. * order. If need to ensure this write is also flushed
  503. * call wmb() independently in the caller.
  504. *
  505. * @soc_info: Device soc information
  506. * @base_index: Index of register space in the HW block
  507. * @offset: Offset of register to be read
  508. * @data: Value to be written
  509. *
  510. * @return: Success or Failure
  511. */
  512. static inline int cam_soc_util_w_mb(struct cam_hw_soc_info *soc_info,
  513. uint32_t base_index, uint32_t offset, uint32_t data)
  514. {
  515. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  516. return -EINVAL;
  517. return cam_io_w_mb(data,
  518. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  519. }
  520. /**
  521. * cam_soc_util_r()
  522. *
  523. * @brief: Camera SOC util for register read
  524. *
  525. * @soc_info: Device soc information
  526. * @base_index: Index of register space in the HW block
  527. * @offset: Offset of register to be read
  528. *
  529. * @return: Value read from the register address
  530. */
  531. static inline uint32_t cam_soc_util_r(struct cam_hw_soc_info *soc_info,
  532. uint32_t base_index, uint32_t offset)
  533. {
  534. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  535. return 0;
  536. return cam_io_r(
  537. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  538. }
  539. /**
  540. * cam_soc_util_r_mb()
  541. *
  542. * @brief: Camera SOC util for register read with memory barrier.
  543. * Memory Barrier is only before the write to ensure the
  544. * order. If need to ensure this write is also flushed
  545. * call rmb() independently in the caller.
  546. *
  547. * @soc_info: Device soc information
  548. * @base_index: Index of register space in the HW block
  549. * @offset: Offset of register to be read
  550. *
  551. * @return: Value read from the register address
  552. */
  553. static inline uint32_t cam_soc_util_r_mb(struct cam_hw_soc_info *soc_info,
  554. uint32_t base_index, uint32_t offset)
  555. {
  556. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  557. return 0;
  558. return cam_io_r_mb(
  559. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  560. }
  561. /**
  562. * cam_soc_util_reg_dump()
  563. *
  564. * @brief: Camera SOC util for dumping a range of register
  565. *
  566. * @soc_info: Device soc information
  567. * @base_index: Index of register space in the HW block
  568. * @offset: Start register offset for the dump
  569. * @size: Size specifying the range for dump
  570. *
  571. * @return: Success or Failure
  572. */
  573. int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info,
  574. uint32_t base_index, uint32_t offset, int size);
  575. void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info);
  576. int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
  577. enum cam_vote_level clk_level);
  578. int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info,
  579. int32_t clk_rate, int clk_idx, int32_t *clk_lvl);
  580. /* Callback to get reg space data for specific HW */
  581. typedef int (*cam_soc_util_regspace_data_cb)(uint32_t reg_base_type,
  582. void *ctx, struct cam_hw_soc_info **soc_info_ptr,
  583. uint32_t *reg_base_idx);
  584. /**
  585. * cam_soc_util_reg_dump_to_cmd_buf()
  586. *
  587. * @brief: Camera SOC util for dumping sets of register ranges to
  588. * to command buffer
  589. *
  590. * @ctx: Context info from specific hardware manager
  591. * @cmd_desc: Command buffer descriptor
  592. * @req_id: Last applied req id for which reg dump is required
  593. * @reg_data_cb: Callback function to get reg space info based on type
  594. * in command buffer
  595. *
  596. * @return: Success or Failure
  597. */
  598. int cam_soc_util_reg_dump_to_cmd_buf(void *ctx,
  599. struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id,
  600. cam_soc_util_regspace_data_cb reg_data_cb);
  601. #endif /* _CAM_SOC_UTIL_H_ */