sde_crtc.c 182 KB

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  1. /*
  2. * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/sort.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/ktime.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/drm_mode.h>
  24. #include <drm/drm_crtc.h>
  25. #include <drm/drm_probe_helper.h>
  26. #include <drm/drm_flip_work.h>
  27. #include "sde_kms.h"
  28. #include "sde_hw_lm.h"
  29. #include "sde_hw_ctl.h"
  30. #include "sde_crtc.h"
  31. #include "sde_plane.h"
  32. #include "sde_hw_util.h"
  33. #include "sde_hw_catalog.h"
  34. #include "sde_color_processing.h"
  35. #include "sde_encoder.h"
  36. #include "sde_connector.h"
  37. #include "sde_vbif.h"
  38. #include "sde_power_handle.h"
  39. #include "sde_core_perf.h"
  40. #include "sde_trace.h"
  41. #define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4)
  42. #define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2)
  43. struct sde_crtc_custom_events {
  44. u32 event;
  45. int (*func)(struct drm_crtc *crtc, bool en,
  46. struct sde_irq_callback *irq);
  47. };
  48. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  49. bool en, struct sde_irq_callback *ad_irq);
  50. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  51. bool en, struct sde_irq_callback *idle_irq);
  52. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  53. struct sde_irq_callback *noirq);
  54. static struct sde_crtc_custom_events custom_events[] = {
  55. {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt},
  56. {DRM_EVENT_CRTC_POWER, sde_crtc_power_interrupt_handler},
  57. {DRM_EVENT_IDLE_NOTIFY, sde_crtc_idle_interrupt_handler},
  58. {DRM_EVENT_HISTOGRAM, sde_cp_hist_interrupt},
  59. {DRM_EVENT_SDE_POWER, sde_crtc_pm_event_handler},
  60. {DRM_EVENT_LTM_HIST, sde_cp_ltm_hist_interrupt},
  61. {DRM_EVENT_LTM_WB_PB, sde_cp_ltm_wb_pb_interrupt},
  62. {DRM_EVENT_LTM_OFF, sde_cp_ltm_off_event_handler},
  63. };
  64. /* default input fence timeout, in ms */
  65. #define SDE_CRTC_INPUT_FENCE_TIMEOUT 10000
  66. /*
  67. * The default input fence timeout is 2 seconds while max allowed
  68. * range is 10 seconds. Any value above 10 seconds adds glitches beyond
  69. * tolerance limit.
  70. */
  71. #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000
  72. /* layer mixer index on sde_crtc */
  73. #define LEFT_MIXER 0
  74. #define RIGHT_MIXER 1
  75. #define MISR_BUFF_SIZE 256
  76. /*
  77. * Time period for fps calculation in micro seconds.
  78. * Default value is set to 1 sec.
  79. */
  80. #define DEFAULT_FPS_PERIOD_1_SEC 1000000
  81. #define MAX_FPS_PERIOD_5_SECONDS 5000000
  82. #define MAX_FRAME_COUNT 1000
  83. #define MILI_TO_MICRO 1000
  84. #define SKIP_STAGING_PIPE_ZPOS 255
  85. static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
  86. {
  87. struct msm_drm_private *priv;
  88. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  89. SDE_ERROR("invalid crtc\n");
  90. return NULL;
  91. }
  92. priv = crtc->dev->dev_private;
  93. if (!priv || !priv->kms) {
  94. SDE_ERROR("invalid kms\n");
  95. return NULL;
  96. }
  97. return to_sde_kms(priv->kms);
  98. }
  99. /**
  100. * sde_crtc_calc_fps() - Calculates fps value.
  101. * @sde_crtc : CRTC structure
  102. *
  103. * This function is called at frame done. It counts the number
  104. * of frames done for every 1 sec. Stores the value in measured_fps.
  105. * measured_fps value is 10 times the calculated fps value.
  106. * For example, measured_fps= 594 for calculated fps of 59.4
  107. */
  108. static void sde_crtc_calc_fps(struct sde_crtc *sde_crtc)
  109. {
  110. ktime_t current_time_us;
  111. u64 fps, diff_us;
  112. current_time_us = ktime_get();
  113. diff_us = (u64)ktime_us_delta(current_time_us,
  114. sde_crtc->fps_info.last_sampled_time_us);
  115. sde_crtc->fps_info.frame_count++;
  116. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  117. /* Multiplying with 10 to get fps in floating point */
  118. fps = ((u64)sde_crtc->fps_info.frame_count)
  119. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  120. do_div(fps, diff_us);
  121. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  122. SDE_DEBUG(" FPS for crtc%d is %d.%d\n",
  123. sde_crtc->base.base.id, (unsigned int)fps/10,
  124. (unsigned int)fps%10);
  125. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  126. sde_crtc->fps_info.frame_count = 0;
  127. }
  128. if (!sde_crtc->fps_info.time_buf)
  129. return;
  130. /**
  131. * Array indexing is based on sliding window algorithm.
  132. * sde_crtc->time_buf has a maximum capacity of MAX_FRAME_COUNT
  133. * time slots. As the count increases to MAX_FRAME_COUNT + 1, the
  134. * counter loops around and comes back to the first index to store
  135. * the next ktime.
  136. */
  137. sde_crtc->fps_info.time_buf[sde_crtc->fps_info.next_time_index++] =
  138. ktime_get();
  139. sde_crtc->fps_info.next_time_index %= MAX_FRAME_COUNT;
  140. }
  141. static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc)
  142. {
  143. if (!sde_crtc)
  144. return;
  145. }
  146. #ifdef CONFIG_DEBUG_FS
  147. static int _sde_debugfs_fps_status_show(struct seq_file *s, void *data)
  148. {
  149. struct sde_crtc *sde_crtc;
  150. u64 fps_int, fps_float;
  151. ktime_t current_time_us;
  152. u64 fps, diff_us;
  153. if (!s || !s->private) {
  154. SDE_ERROR("invalid input param(s)\n");
  155. return -EAGAIN;
  156. }
  157. sde_crtc = s->private;
  158. current_time_us = ktime_get();
  159. diff_us = (u64)ktime_us_delta(current_time_us,
  160. sde_crtc->fps_info.last_sampled_time_us);
  161. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  162. /* Multiplying with 10 to get fps in floating point */
  163. fps = ((u64)sde_crtc->fps_info.frame_count)
  164. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  165. do_div(fps, diff_us);
  166. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  167. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  168. sde_crtc->fps_info.frame_count = 0;
  169. SDE_DEBUG("Measured FPS for crtc%d is %d.%d\n",
  170. sde_crtc->base.base.id, (unsigned int)fps/10,
  171. (unsigned int)fps%10);
  172. }
  173. fps_int = (unsigned int) sde_crtc->fps_info.measured_fps;
  174. fps_float = do_div(fps_int, 10);
  175. seq_printf(s, "fps: %llu.%llu\n", fps_int, fps_float);
  176. return 0;
  177. }
  178. static int _sde_debugfs_fps_status(struct inode *inode, struct file *file)
  179. {
  180. return single_open(file, _sde_debugfs_fps_status_show,
  181. inode->i_private);
  182. }
  183. #endif
  184. static ssize_t fps_periodicity_ms_store(struct device *device,
  185. struct device_attribute *attr, const char *buf, size_t count)
  186. {
  187. struct drm_crtc *crtc;
  188. struct sde_crtc *sde_crtc;
  189. int res;
  190. /* Base of the input */
  191. int cnt = 10;
  192. if (!device || !buf) {
  193. SDE_ERROR("invalid input param(s)\n");
  194. return -EAGAIN;
  195. }
  196. crtc = dev_get_drvdata(device);
  197. if (!crtc)
  198. return -EINVAL;
  199. sde_crtc = to_sde_crtc(crtc);
  200. res = kstrtou32(buf, cnt, &sde_crtc->fps_info.fps_periodic_duration);
  201. if (res < 0)
  202. return res;
  203. if (sde_crtc->fps_info.fps_periodic_duration <= 0)
  204. sde_crtc->fps_info.fps_periodic_duration =
  205. DEFAULT_FPS_PERIOD_1_SEC;
  206. else if ((sde_crtc->fps_info.fps_periodic_duration) * MILI_TO_MICRO >
  207. MAX_FPS_PERIOD_5_SECONDS)
  208. sde_crtc->fps_info.fps_periodic_duration =
  209. MAX_FPS_PERIOD_5_SECONDS;
  210. else
  211. sde_crtc->fps_info.fps_periodic_duration *= MILI_TO_MICRO;
  212. return count;
  213. }
  214. static ssize_t fps_periodicity_ms_show(struct device *device,
  215. struct device_attribute *attr, char *buf)
  216. {
  217. struct drm_crtc *crtc;
  218. struct sde_crtc *sde_crtc;
  219. if (!device || !buf) {
  220. SDE_ERROR("invalid input param(s)\n");
  221. return -EAGAIN;
  222. }
  223. crtc = dev_get_drvdata(device);
  224. if (!crtc)
  225. return -EINVAL;
  226. sde_crtc = to_sde_crtc(crtc);
  227. return scnprintf(buf, PAGE_SIZE, "%d\n",
  228. (sde_crtc->fps_info.fps_periodic_duration)/MILI_TO_MICRO);
  229. }
  230. static ssize_t measured_fps_show(struct device *device,
  231. struct device_attribute *attr, char *buf)
  232. {
  233. struct drm_crtc *crtc;
  234. struct sde_crtc *sde_crtc;
  235. uint64_t fps_int, fps_decimal;
  236. u64 fps = 0, frame_count = 0;
  237. ktime_t current_time;
  238. int i = 0, current_time_index;
  239. u64 diff_us;
  240. if (!device || !buf) {
  241. SDE_ERROR("invalid input param(s)\n");
  242. return -EAGAIN;
  243. }
  244. crtc = dev_get_drvdata(device);
  245. if (!crtc) {
  246. scnprintf(buf, PAGE_SIZE, "fps information not available");
  247. return -EINVAL;
  248. }
  249. sde_crtc = to_sde_crtc(crtc);
  250. if (!sde_crtc->fps_info.time_buf) {
  251. scnprintf(buf, PAGE_SIZE,
  252. "timebuf null - fps information not available");
  253. return -EINVAL;
  254. }
  255. /**
  256. * Whenever the time_index counter comes to zero upon decrementing,
  257. * it is set to the last index since it is the next index that we
  258. * should check for calculating the buftime.
  259. */
  260. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  261. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  262. current_time = ktime_get();
  263. for (i = 0; i < MAX_FRAME_COUNT; i++) {
  264. u64 ptime = (u64)ktime_to_us(current_time);
  265. u64 buftime = (u64)ktime_to_us(
  266. sde_crtc->fps_info.time_buf[current_time_index]);
  267. diff_us = (u64)ktime_us_delta(current_time,
  268. sde_crtc->fps_info.time_buf[current_time_index]);
  269. if (ptime > buftime && diff_us >= (u64)
  270. sde_crtc->fps_info.fps_periodic_duration) {
  271. /* Multiplying with 10 to get fps in floating point */
  272. fps = frame_count * DEFAULT_FPS_PERIOD_1_SEC * 10;
  273. do_div(fps, diff_us);
  274. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  275. SDE_DEBUG("measured fps: %d\n",
  276. sde_crtc->fps_info.measured_fps);
  277. break;
  278. }
  279. current_time_index = (current_time_index == 0) ?
  280. (MAX_FRAME_COUNT - 1) : (current_time_index - 1);
  281. SDE_DEBUG("current time index: %d\n", current_time_index);
  282. frame_count++;
  283. }
  284. if (i == MAX_FRAME_COUNT) {
  285. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  286. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  287. diff_us = (u64)ktime_us_delta(current_time,
  288. sde_crtc->fps_info.time_buf[current_time_index]);
  289. if (diff_us >= sde_crtc->fps_info.fps_periodic_duration) {
  290. /* Multiplying with 10 to get fps in floating point */
  291. fps = (frame_count) * DEFAULT_FPS_PERIOD_1_SEC * 10;
  292. do_div(fps, diff_us);
  293. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  294. }
  295. }
  296. fps_int = (uint64_t) sde_crtc->fps_info.measured_fps;
  297. fps_decimal = do_div(fps_int, 10);
  298. return scnprintf(buf, PAGE_SIZE,
  299. "fps: %d.%d duration:%d frame_count:%lld\n", fps_int, fps_decimal,
  300. sde_crtc->fps_info.fps_periodic_duration, frame_count);
  301. }
  302. static ssize_t vsync_event_show(struct device *device,
  303. struct device_attribute *attr, char *buf)
  304. {
  305. struct drm_crtc *crtc;
  306. struct sde_crtc *sde_crtc;
  307. if (!device || !buf) {
  308. SDE_ERROR("invalid input param(s)\n");
  309. return -EAGAIN;
  310. }
  311. crtc = dev_get_drvdata(device);
  312. sde_crtc = to_sde_crtc(crtc);
  313. return scnprintf(buf, PAGE_SIZE, "VSYNC=%llu\n",
  314. ktime_to_ns(sde_crtc->vblank_last_cb_time));
  315. }
  316. static DEVICE_ATTR_RO(vsync_event);
  317. static DEVICE_ATTR_RO(measured_fps);
  318. static DEVICE_ATTR_RW(fps_periodicity_ms);
  319. static struct attribute *sde_crtc_dev_attrs[] = {
  320. &dev_attr_vsync_event.attr,
  321. &dev_attr_measured_fps.attr,
  322. &dev_attr_fps_periodicity_ms.attr,
  323. NULL
  324. };
  325. static const struct attribute_group sde_crtc_attr_group = {
  326. .attrs = sde_crtc_dev_attrs,
  327. };
  328. static const struct attribute_group *sde_crtc_attr_groups[] = {
  329. &sde_crtc_attr_group,
  330. NULL,
  331. };
  332. static void sde_crtc_destroy(struct drm_crtc *crtc)
  333. {
  334. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  335. SDE_DEBUG("\n");
  336. if (!crtc)
  337. return;
  338. if (sde_crtc->vsync_event_sf)
  339. sysfs_put(sde_crtc->vsync_event_sf);
  340. if (sde_crtc->sysfs_dev)
  341. device_unregister(sde_crtc->sysfs_dev);
  342. if (sde_crtc->blob_info)
  343. drm_property_blob_put(sde_crtc->blob_info);
  344. msm_property_destroy(&sde_crtc->property_info);
  345. sde_cp_crtc_destroy_properties(crtc);
  346. sde_fence_deinit(sde_crtc->output_fence);
  347. _sde_crtc_deinit_events(sde_crtc);
  348. drm_crtc_cleanup(crtc);
  349. mutex_destroy(&sde_crtc->crtc_lock);
  350. kfree(sde_crtc);
  351. }
  352. static bool sde_crtc_mode_fixup(struct drm_crtc *crtc,
  353. const struct drm_display_mode *mode,
  354. struct drm_display_mode *adjusted_mode)
  355. {
  356. SDE_DEBUG("\n");
  357. if ((msm_is_mode_seamless(adjusted_mode) ||
  358. (msm_is_mode_seamless_vrr(adjusted_mode) ||
  359. msm_is_mode_seamless_dyn_clk(adjusted_mode))) &&
  360. (!crtc->enabled)) {
  361. SDE_ERROR("crtc state prevents seamless transition\n");
  362. return false;
  363. }
  364. return true;
  365. }
  366. static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer,
  367. struct sde_plane_state *pstate, struct sde_format *format)
  368. {
  369. uint32_t blend_op, fg_alpha, bg_alpha;
  370. uint32_t blend_type;
  371. struct sde_hw_mixer *lm = mixer->hw_lm;
  372. /* default to opaque blending */
  373. fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA);
  374. bg_alpha = 0xFF - fg_alpha;
  375. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST;
  376. blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
  377. SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
  378. switch (blend_type) {
  379. case SDE_DRM_BLEND_OP_OPAQUE:
  380. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  381. SDE_BLEND_BG_ALPHA_BG_CONST;
  382. break;
  383. case SDE_DRM_BLEND_OP_PREMULTIPLIED:
  384. if (format->alpha_enable) {
  385. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  386. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  387. if (fg_alpha != 0xff) {
  388. bg_alpha = fg_alpha;
  389. blend_op |= SDE_BLEND_BG_MOD_ALPHA |
  390. SDE_BLEND_BG_INV_MOD_ALPHA;
  391. } else {
  392. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  393. }
  394. }
  395. break;
  396. case SDE_DRM_BLEND_OP_COVERAGE:
  397. if (format->alpha_enable) {
  398. blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL |
  399. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  400. if (fg_alpha != 0xff) {
  401. bg_alpha = fg_alpha;
  402. blend_op |= SDE_BLEND_FG_MOD_ALPHA |
  403. SDE_BLEND_BG_MOD_ALPHA |
  404. SDE_BLEND_BG_INV_MOD_ALPHA;
  405. } else {
  406. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  407. }
  408. }
  409. break;
  410. default:
  411. /* do nothing */
  412. break;
  413. }
  414. lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha,
  415. bg_alpha, blend_op);
  416. SDE_DEBUG(
  417. "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n",
  418. (char *) &format->base.pixel_format,
  419. format->alpha_enable, fg_alpha, bg_alpha, blend_op);
  420. }
  421. static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,
  422. struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer,
  423. struct sde_hw_dim_layer *dim_layer)
  424. {
  425. struct sde_crtc_state *cstate;
  426. struct sde_hw_mixer *lm;
  427. struct sde_hw_dim_layer split_dim_layer;
  428. int i;
  429. if (!dim_layer->rect.w || !dim_layer->rect.h) {
  430. SDE_DEBUG("empty dim_layer\n");
  431. return;
  432. }
  433. cstate = to_sde_crtc_state(crtc->state);
  434. SDE_DEBUG("dim_layer - flags:%d, stage:%d\n",
  435. dim_layer->flags, dim_layer->stage);
  436. split_dim_layer.stage = dim_layer->stage;
  437. split_dim_layer.color_fill = dim_layer->color_fill;
  438. /*
  439. * traverse through the layer mixers attached to crtc and find the
  440. * intersecting dim layer rect in each LM and program accordingly.
  441. */
  442. for (i = 0; i < sde_crtc->num_mixers; i++) {
  443. split_dim_layer.flags = dim_layer->flags;
  444. sde_kms_rect_intersect(&cstate->lm_roi[i], &dim_layer->rect,
  445. &split_dim_layer.rect);
  446. if (sde_kms_rect_is_null(&split_dim_layer.rect)) {
  447. /*
  448. * no extra programming required for non-intersecting
  449. * layer mixers with INCLUSIVE dim layer
  450. */
  451. if (split_dim_layer.flags & SDE_DRM_DIM_LAYER_INCLUSIVE)
  452. continue;
  453. /*
  454. * program the other non-intersecting layer mixers with
  455. * INCLUSIVE dim layer of full size for uniformity
  456. * with EXCLUSIVE dim layer config.
  457. */
  458. split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE;
  459. split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE;
  460. memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i],
  461. sizeof(split_dim_layer.rect));
  462. } else {
  463. split_dim_layer.rect.x =
  464. split_dim_layer.rect.x -
  465. cstate->lm_roi[i].x;
  466. split_dim_layer.rect.y =
  467. split_dim_layer.rect.y -
  468. cstate->lm_roi[i].y;
  469. }
  470. SDE_EVT32(DRMID(crtc), dim_layer->stage,
  471. cstate->lm_roi[i].x,
  472. cstate->lm_roi[i].y,
  473. cstate->lm_roi[i].w,
  474. cstate->lm_roi[i].h,
  475. dim_layer->rect.x,
  476. dim_layer->rect.y,
  477. dim_layer->rect.w,
  478. dim_layer->rect.h,
  479. split_dim_layer.rect.x,
  480. split_dim_layer.rect.y,
  481. split_dim_layer.rect.w,
  482. split_dim_layer.rect.h);
  483. SDE_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n",
  484. i, split_dim_layer.rect.x, split_dim_layer.rect.y,
  485. split_dim_layer.rect.w, split_dim_layer.rect.h);
  486. lm = mixer[i].hw_lm;
  487. mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage;
  488. lm->ops.setup_dim_layer(lm, &split_dim_layer);
  489. }
  490. }
  491. void sde_crtc_get_crtc_roi(struct drm_crtc_state *state,
  492. const struct sde_rect **crtc_roi)
  493. {
  494. struct sde_crtc_state *crtc_state;
  495. if (!state || !crtc_roi)
  496. return;
  497. crtc_state = to_sde_crtc_state(state);
  498. *crtc_roi = &crtc_state->crtc_roi;
  499. }
  500. bool sde_crtc_is_crtc_roi_dirty(struct drm_crtc_state *state)
  501. {
  502. struct sde_crtc_state *cstate;
  503. struct sde_crtc *sde_crtc;
  504. if (!state || !state->crtc)
  505. return false;
  506. sde_crtc = to_sde_crtc(state->crtc);
  507. cstate = to_sde_crtc_state(state);
  508. return msm_property_is_dirty(&sde_crtc->property_info,
  509. &cstate->property_state, CRTC_PROP_ROI_V1);
  510. }
  511. static int _sde_crtc_set_roi_v1(struct drm_crtc_state *state,
  512. void __user *usr_ptr)
  513. {
  514. struct drm_crtc *crtc;
  515. struct sde_crtc_state *cstate;
  516. struct sde_drm_roi_v1 roi_v1;
  517. int i;
  518. if (!state) {
  519. SDE_ERROR("invalid args\n");
  520. return -EINVAL;
  521. }
  522. cstate = to_sde_crtc_state(state);
  523. crtc = cstate->base.crtc;
  524. memset(&cstate->user_roi_list, 0, sizeof(cstate->user_roi_list));
  525. if (!usr_ptr) {
  526. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  527. return 0;
  528. }
  529. if (copy_from_user(&roi_v1, usr_ptr, sizeof(roi_v1))) {
  530. SDE_ERROR("crtc%d: failed to copy roi_v1 data\n", DRMID(crtc));
  531. return -EINVAL;
  532. }
  533. SDE_DEBUG("crtc%d: num_rects %d\n", DRMID(crtc), roi_v1.num_rects);
  534. if (roi_v1.num_rects == 0) {
  535. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  536. return 0;
  537. }
  538. if (roi_v1.num_rects > SDE_MAX_ROI_V1) {
  539. SDE_ERROR("crtc%d: too many rects specified: %d\n", DRMID(crtc),
  540. roi_v1.num_rects);
  541. return -EINVAL;
  542. }
  543. cstate->user_roi_list.num_rects = roi_v1.num_rects;
  544. for (i = 0; i < roi_v1.num_rects; ++i) {
  545. cstate->user_roi_list.roi[i] = roi_v1.roi[i];
  546. SDE_DEBUG("crtc%d: roi%d: roi (%d,%d) (%d,%d)\n",
  547. DRMID(crtc), i,
  548. cstate->user_roi_list.roi[i].x1,
  549. cstate->user_roi_list.roi[i].y1,
  550. cstate->user_roi_list.roi[i].x2,
  551. cstate->user_roi_list.roi[i].y2);
  552. SDE_EVT32_VERBOSE(DRMID(crtc),
  553. cstate->user_roi_list.roi[i].x1,
  554. cstate->user_roi_list.roi[i].y1,
  555. cstate->user_roi_list.roi[i].x2,
  556. cstate->user_roi_list.roi[i].y2);
  557. }
  558. return 0;
  559. }
  560. static int _sde_crtc_set_crtc_roi(struct drm_crtc *crtc,
  561. struct drm_crtc_state *state)
  562. {
  563. struct drm_connector *conn;
  564. struct drm_connector_state *conn_state;
  565. struct sde_crtc *sde_crtc;
  566. struct sde_crtc_state *crtc_state;
  567. struct sde_rect *crtc_roi;
  568. struct msm_mode_info mode_info;
  569. int i = 0;
  570. int rc;
  571. bool is_crtc_roi_dirty;
  572. bool is_any_conn_roi_dirty;
  573. if (!crtc || !state)
  574. return -EINVAL;
  575. sde_crtc = to_sde_crtc(crtc);
  576. crtc_state = to_sde_crtc_state(state);
  577. crtc_roi = &crtc_state->crtc_roi;
  578. is_crtc_roi_dirty = sde_crtc_is_crtc_roi_dirty(state);
  579. is_any_conn_roi_dirty = false;
  580. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  581. struct sde_connector *sde_conn;
  582. struct sde_connector_state *sde_conn_state;
  583. struct sde_rect conn_roi;
  584. if (!conn_state || conn_state->crtc != crtc)
  585. continue;
  586. rc = sde_connector_state_get_mode_info(conn_state, &mode_info);
  587. if (rc) {
  588. SDE_ERROR("failed to get mode info\n");
  589. return -EINVAL;
  590. }
  591. sde_conn = to_sde_connector(conn_state->connector);
  592. sde_conn_state = to_sde_connector_state(conn_state);
  593. is_any_conn_roi_dirty = is_any_conn_roi_dirty ||
  594. msm_property_is_dirty(
  595. &sde_conn->property_info,
  596. &sde_conn_state->property_state,
  597. CONNECTOR_PROP_ROI_V1);
  598. if (!mode_info.roi_caps.enabled)
  599. continue;
  600. /*
  601. * current driver only supports same connector and crtc size,
  602. * but if support for different sizes is added, driver needs
  603. * to check the connector roi here to make sure is full screen
  604. * for dsc 3d-mux topology that doesn't support partial update.
  605. */
  606. if (memcmp(&sde_conn_state->rois, &crtc_state->user_roi_list,
  607. sizeof(crtc_state->user_roi_list))) {
  608. SDE_ERROR("%s: crtc -> conn roi scaling unsupported\n",
  609. sde_crtc->name);
  610. return -EINVAL;
  611. }
  612. sde_kms_rect_merge_rectangles(&sde_conn_state->rois, &conn_roi);
  613. SDE_DEBUG("conn_roi x:%u, y:%u, w:%u, h:%u\n",
  614. conn_roi.x, conn_roi.y,
  615. conn_roi.w, conn_roi.h);
  616. SDE_EVT32_VERBOSE(DRMID(crtc), DRMID(conn),
  617. conn_roi.x, conn_roi.y,
  618. conn_roi.w, conn_roi.h);
  619. }
  620. /*
  621. * Check against CRTC ROI and Connector ROI not being updated together.
  622. * This restriction should be relaxed when Connector ROI scaling is
  623. * supported.
  624. */
  625. if (is_any_conn_roi_dirty != is_crtc_roi_dirty) {
  626. SDE_ERROR("connector/crtc rois not updated together\n");
  627. return -EINVAL;
  628. }
  629. sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi);
  630. /* clear the ROI to null if it matches full screen anyways */
  631. if (crtc_roi->x == 0 && crtc_roi->y == 0 &&
  632. crtc_roi->w == state->adjusted_mode.hdisplay &&
  633. crtc_roi->h == state->adjusted_mode.vdisplay)
  634. memset(crtc_roi, 0, sizeof(*crtc_roi));
  635. SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name,
  636. crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h);
  637. SDE_EVT32_VERBOSE(DRMID(crtc), crtc_roi->x, crtc_roi->y, crtc_roi->w,
  638. crtc_roi->h);
  639. return 0;
  640. }
  641. static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc,
  642. struct drm_crtc_state *state)
  643. {
  644. struct sde_crtc *sde_crtc;
  645. struct sde_crtc_state *crtc_state;
  646. struct drm_connector *conn;
  647. struct drm_connector_state *conn_state;
  648. int i;
  649. if (!crtc || !state)
  650. return -EINVAL;
  651. sde_crtc = to_sde_crtc(crtc);
  652. crtc_state = to_sde_crtc_state(state);
  653. if (sde_kms_rect_is_null(&crtc_state->crtc_roi))
  654. return 0;
  655. /* partial update active, check if autorefresh is also requested */
  656. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  657. uint64_t autorefresh;
  658. if (!conn_state || conn_state->crtc != crtc)
  659. continue;
  660. autorefresh = sde_connector_get_property(conn_state,
  661. CONNECTOR_PROP_AUTOREFRESH);
  662. if (autorefresh) {
  663. SDE_ERROR(
  664. "%s: autorefresh & partial crtc roi incompatible %llu\n",
  665. sde_crtc->name, autorefresh);
  666. return -EINVAL;
  667. }
  668. }
  669. return 0;
  670. }
  671. static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc,
  672. struct drm_crtc_state *state, int lm_idx)
  673. {
  674. struct sde_kms *sde_kms;
  675. struct sde_crtc *sde_crtc;
  676. struct sde_crtc_state *crtc_state;
  677. const struct sde_rect *crtc_roi;
  678. const struct sde_rect *lm_bounds;
  679. struct sde_rect *lm_roi;
  680. if (!crtc || !state || lm_idx >= ARRAY_SIZE(crtc_state->lm_bounds))
  681. return -EINVAL;
  682. sde_kms = _sde_crtc_get_kms(crtc);
  683. if (!sde_kms || !sde_kms->catalog) {
  684. SDE_ERROR("invalid parameters\n");
  685. return -EINVAL;
  686. }
  687. sde_crtc = to_sde_crtc(crtc);
  688. crtc_state = to_sde_crtc_state(state);
  689. crtc_roi = &crtc_state->crtc_roi;
  690. lm_bounds = &crtc_state->lm_bounds[lm_idx];
  691. lm_roi = &crtc_state->lm_roi[lm_idx];
  692. if (sde_kms_rect_is_null(crtc_roi))
  693. memcpy(lm_roi, lm_bounds, sizeof(*lm_roi));
  694. else
  695. sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi);
  696. SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx,
  697. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  698. /*
  699. * partial update is not supported with 3dmux dsc or dest scaler.
  700. * hence, crtc roi must match the mixer dimensions.
  701. */
  702. if (crtc_state->num_ds_enabled ||
  703. sde_rm_topology_is_group(&sde_kms->rm, state,
  704. SDE_RM_TOPOLOGY_GROUP_3DMERGE_DSC)) {
  705. if (memcmp(lm_roi, lm_bounds, sizeof(struct sde_rect))) {
  706. SDE_ERROR("Unsupported: Dest scaler/3d mux DSC + PU\n");
  707. return -EINVAL;
  708. }
  709. }
  710. /* if any dimension is zero, clear all dimensions for clarity */
  711. if (sde_kms_rect_is_null(lm_roi))
  712. memset(lm_roi, 0, sizeof(*lm_roi));
  713. return 0;
  714. }
  715. static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc,
  716. struct drm_crtc_state *state)
  717. {
  718. struct sde_crtc *sde_crtc;
  719. struct sde_crtc_state *crtc_state;
  720. u32 disp_bitmask = 0;
  721. int i;
  722. if (!crtc || !state) {
  723. pr_err("Invalid crtc or state\n");
  724. return 0;
  725. }
  726. sde_crtc = to_sde_crtc(crtc);
  727. crtc_state = to_sde_crtc_state(state);
  728. /* pingpong split: one ROI, one LM, two physical displays */
  729. if (crtc_state->is_ppsplit) {
  730. u32 lm_split_width = crtc_state->lm_bounds[0].w / 2;
  731. struct sde_rect *roi = &crtc_state->lm_roi[0];
  732. if (sde_kms_rect_is_null(roi))
  733. disp_bitmask = 0;
  734. else if ((u32)roi->x + (u32)roi->w <= lm_split_width)
  735. disp_bitmask = BIT(0); /* left only */
  736. else if (roi->x >= lm_split_width)
  737. disp_bitmask = BIT(1); /* right only */
  738. else
  739. disp_bitmask = BIT(0) | BIT(1); /* left and right */
  740. } else if (sde_crtc->mixers_swapped) {
  741. disp_bitmask = BIT(0);
  742. } else {
  743. for (i = 0; i < sde_crtc->num_mixers; i++) {
  744. if (!sde_kms_rect_is_null(
  745. &crtc_state->lm_roi[i]))
  746. disp_bitmask |= BIT(i);
  747. }
  748. }
  749. SDE_DEBUG("affected displays 0x%x\n", disp_bitmask);
  750. return disp_bitmask;
  751. }
  752. static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc,
  753. struct drm_crtc_state *state)
  754. {
  755. struct sde_crtc *sde_crtc;
  756. struct sde_crtc_state *crtc_state;
  757. const struct sde_rect *roi[MAX_MIXERS_PER_CRTC];
  758. if (!crtc || !state)
  759. return -EINVAL;
  760. sde_crtc = to_sde_crtc(crtc);
  761. crtc_state = to_sde_crtc_state(state);
  762. if (sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  763. SDE_ERROR("%s: unsupported number of mixers: %d\n",
  764. sde_crtc->name, sde_crtc->num_mixers);
  765. return -EINVAL;
  766. }
  767. /*
  768. * If using pingpong split: one ROI, one LM, two physical displays
  769. * then the ROI must be centered on the panel split boundary and
  770. * be of equal width across the split.
  771. */
  772. if (crtc_state->is_ppsplit) {
  773. u16 panel_split_width;
  774. u32 display_mask;
  775. roi[0] = &crtc_state->lm_roi[0];
  776. if (sde_kms_rect_is_null(roi[0]))
  777. return 0;
  778. display_mask = _sde_crtc_get_displays_affected(crtc, state);
  779. if (display_mask != (BIT(0) | BIT(1)))
  780. return 0;
  781. panel_split_width = crtc_state->lm_bounds[0].w / 2;
  782. if (roi[0]->x + roi[0]->w / 2 != panel_split_width) {
  783. SDE_ERROR("%s: roi x %d w %d split %d\n",
  784. sde_crtc->name, roi[0]->x, roi[0]->w,
  785. panel_split_width);
  786. return -EINVAL;
  787. }
  788. return 0;
  789. }
  790. /*
  791. * On certain HW, if using 2 LM, ROIs must be split evenly between the
  792. * LMs and be of equal width.
  793. */
  794. if (sde_crtc->num_mixers < CRTC_DUAL_MIXERS_ONLY)
  795. return 0;
  796. roi[0] = &crtc_state->lm_roi[0];
  797. roi[1] = &crtc_state->lm_roi[1];
  798. /* if one of the roi is null it's a left/right-only update */
  799. if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1]))
  800. return 0;
  801. /* check lm rois are equal width & first roi ends at 2nd roi */
  802. if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) {
  803. SDE_ERROR(
  804. "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n",
  805. sde_crtc->name, roi[0]->x, roi[0]->w,
  806. roi[1]->x, roi[1]->w);
  807. return -EINVAL;
  808. }
  809. return 0;
  810. }
  811. static int _sde_crtc_check_planes_within_crtc_roi(struct drm_crtc *crtc,
  812. struct drm_crtc_state *state)
  813. {
  814. struct sde_crtc *sde_crtc;
  815. struct sde_crtc_state *crtc_state;
  816. const struct sde_rect *crtc_roi;
  817. const struct drm_plane_state *pstate;
  818. struct drm_plane *plane;
  819. if (!crtc || !state)
  820. return -EINVAL;
  821. /*
  822. * Reject commit if a Plane CRTC destination coordinates fall outside
  823. * the partial CRTC ROI. LM output is determined via connector ROIs,
  824. * if they are specified, not Plane CRTC ROIs.
  825. */
  826. sde_crtc = to_sde_crtc(crtc);
  827. crtc_state = to_sde_crtc_state(state);
  828. crtc_roi = &crtc_state->crtc_roi;
  829. if (sde_kms_rect_is_null(crtc_roi))
  830. return 0;
  831. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  832. struct sde_rect plane_roi, intersection;
  833. if (IS_ERR_OR_NULL(pstate)) {
  834. int rc = PTR_ERR(pstate);
  835. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  836. sde_crtc->name, plane->base.id, rc);
  837. return rc;
  838. }
  839. plane_roi.x = pstate->crtc_x;
  840. plane_roi.y = pstate->crtc_y;
  841. plane_roi.w = pstate->crtc_w;
  842. plane_roi.h = pstate->crtc_h;
  843. sde_kms_rect_intersect(crtc_roi, &plane_roi, &intersection);
  844. if (!sde_kms_rect_is_equal(&plane_roi, &intersection)) {
  845. SDE_ERROR(
  846. "%s: plane%d crtc roi (%d,%d,%d,%d) outside crtc roi (%d,%d,%d,%d)\n",
  847. sde_crtc->name, plane->base.id,
  848. plane_roi.x, plane_roi.y,
  849. plane_roi.w, plane_roi.h,
  850. crtc_roi->x, crtc_roi->y,
  851. crtc_roi->w, crtc_roi->h);
  852. return -E2BIG;
  853. }
  854. }
  855. return 0;
  856. }
  857. static int _sde_crtc_check_rois(struct drm_crtc *crtc,
  858. struct drm_crtc_state *state)
  859. {
  860. struct sde_crtc *sde_crtc;
  861. struct sde_crtc_state *sde_crtc_state;
  862. struct msm_mode_info mode_info;
  863. int rc, lm_idx, i;
  864. if (!crtc || !state)
  865. return -EINVAL;
  866. memset(&mode_info, 0, sizeof(mode_info));
  867. sde_crtc = to_sde_crtc(crtc);
  868. sde_crtc_state = to_sde_crtc_state(state);
  869. /*
  870. * check connector array cached at modeset time since incoming atomic
  871. * state may not include any connectors if they aren't modified
  872. */
  873. for (i = 0; i < sde_crtc_state->num_connectors; i++) {
  874. struct drm_connector *conn = sde_crtc_state->connectors[i];
  875. if (!conn || !conn->state)
  876. continue;
  877. rc = sde_connector_state_get_mode_info(conn->state, &mode_info);
  878. if (rc) {
  879. SDE_ERROR("failed to get mode info\n");
  880. return -EINVAL;
  881. }
  882. if (!mode_info.roi_caps.enabled)
  883. continue;
  884. if (sde_crtc_state->user_roi_list.num_rects >
  885. mode_info.roi_caps.num_roi) {
  886. SDE_ERROR("roi count is exceeding limit, %d > %d\n",
  887. sde_crtc_state->user_roi_list.num_rects,
  888. mode_info.roi_caps.num_roi);
  889. return -E2BIG;
  890. }
  891. rc = _sde_crtc_set_crtc_roi(crtc, state);
  892. if (rc)
  893. return rc;
  894. rc = _sde_crtc_check_autorefresh(crtc, state);
  895. if (rc)
  896. return rc;
  897. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  898. rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx);
  899. if (rc)
  900. return rc;
  901. }
  902. rc = _sde_crtc_check_rois_centered_and_symmetric(crtc, state);
  903. if (rc)
  904. return rc;
  905. rc = _sde_crtc_check_planes_within_crtc_roi(crtc, state);
  906. if (rc)
  907. return rc;
  908. }
  909. return 0;
  910. }
  911. static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc)
  912. {
  913. struct sde_crtc *sde_crtc;
  914. struct sde_crtc_state *cstate;
  915. const struct sde_rect *lm_roi;
  916. struct sde_hw_mixer *hw_lm;
  917. bool right_mixer = false;
  918. bool lm_updated = false;
  919. int lm_idx;
  920. if (!crtc)
  921. return;
  922. sde_crtc = to_sde_crtc(crtc);
  923. cstate = to_sde_crtc_state(crtc->state);
  924. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  925. struct sde_hw_mixer_cfg cfg;
  926. lm_roi = &cstate->lm_roi[lm_idx];
  927. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  928. if (!sde_crtc->mixers_swapped)
  929. right_mixer = lm_idx % MAX_MIXERS_PER_LAYOUT;
  930. if (lm_roi->w != hw_lm->cfg.out_width ||
  931. lm_roi->h != hw_lm->cfg.out_height ||
  932. right_mixer != hw_lm->cfg.right_mixer) {
  933. hw_lm->cfg.out_width = lm_roi->w;
  934. hw_lm->cfg.out_height = lm_roi->h;
  935. hw_lm->cfg.right_mixer = right_mixer;
  936. cfg.out_width = lm_roi->w;
  937. cfg.out_height = lm_roi->h;
  938. cfg.right_mixer = right_mixer;
  939. cfg.flags = 0;
  940. hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
  941. lm_updated = true;
  942. }
  943. SDE_EVT32(DRMID(crtc), lm_idx, lm_roi->x, lm_roi->y, lm_roi->w,
  944. lm_roi->h, right_mixer, lm_updated);
  945. }
  946. if (lm_updated)
  947. sde_cp_crtc_res_change(crtc);
  948. }
  949. struct plane_state {
  950. struct sde_plane_state *sde_pstate;
  951. const struct drm_plane_state *drm_pstate;
  952. int stage;
  953. u32 pipe_id;
  954. };
  955. static int pstate_cmp(const void *a, const void *b)
  956. {
  957. struct plane_state *pa = (struct plane_state *)a;
  958. struct plane_state *pb = (struct plane_state *)b;
  959. int rc = 0;
  960. int pa_zpos, pb_zpos;
  961. enum sde_layout pa_layout, pb_layout;
  962. pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS);
  963. pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS);
  964. pa_layout = pa->sde_pstate->layout;
  965. pb_layout = pb->sde_pstate->layout;
  966. if (pa_zpos != pb_zpos)
  967. rc = pa_zpos - pb_zpos;
  968. else if (pa_layout != pb_layout)
  969. rc = pa_layout - pb_layout;
  970. else
  971. rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
  972. return rc;
  973. }
  974. /*
  975. * validate and set source split:
  976. * use pstates sorted by stage to check planes on same stage
  977. * we assume that all pipes are in source split so its valid to compare
  978. * without taking into account left/right mixer placement
  979. */
  980. static int _sde_crtc_validate_src_split_order(struct drm_crtc *crtc,
  981. struct plane_state *pstates, int cnt)
  982. {
  983. struct plane_state *prv_pstate, *cur_pstate;
  984. enum sde_layout prev_layout, cur_layout;
  985. struct sde_rect left_rect, right_rect;
  986. struct sde_kms *sde_kms;
  987. int32_t left_pid, right_pid;
  988. int32_t stage;
  989. int i, rc = 0;
  990. sde_kms = _sde_crtc_get_kms(crtc);
  991. if (!sde_kms || !sde_kms->catalog) {
  992. SDE_ERROR("invalid parameters\n");
  993. return -EINVAL;
  994. }
  995. for (i = 1; i < cnt; i++) {
  996. prv_pstate = &pstates[i - 1];
  997. cur_pstate = &pstates[i];
  998. prev_layout = prv_pstate->sde_pstate->layout;
  999. cur_layout = cur_pstate->sde_pstate->layout;
  1000. if (prv_pstate->stage != cur_pstate->stage ||
  1001. prev_layout != cur_layout)
  1002. continue;
  1003. stage = cur_pstate->stage;
  1004. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  1005. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1006. prv_pstate->drm_pstate->crtc_y,
  1007. prv_pstate->drm_pstate->crtc_w,
  1008. prv_pstate->drm_pstate->crtc_h, false);
  1009. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1010. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1011. cur_pstate->drm_pstate->crtc_y,
  1012. cur_pstate->drm_pstate->crtc_w,
  1013. cur_pstate->drm_pstate->crtc_h, false);
  1014. if (right_rect.x < left_rect.x) {
  1015. swap(left_pid, right_pid);
  1016. swap(left_rect, right_rect);
  1017. swap(prv_pstate, cur_pstate);
  1018. }
  1019. /*
  1020. * - planes are enumerated in pipe-priority order such that
  1021. * planes with lower drm_id must be left-most in a shared
  1022. * blend-stage when using source split.
  1023. * - planes in source split must be contiguous in width
  1024. * - planes in source split must have same dest yoff and height
  1025. */
  1026. if ((right_pid < left_pid) &&
  1027. !sde_kms->catalog->pipe_order_type) {
  1028. SDE_ERROR(
  1029. "invalid src split cfg, stage:%d left:%d right:%d\n",
  1030. stage, left_pid, right_pid);
  1031. return -EINVAL;
  1032. } else if (right_rect.x != (left_rect.x + left_rect.w)) {
  1033. SDE_ERROR(
  1034. "invalid coordinates, stage:%d l:%d-%d r:%d-%d\n",
  1035. stage, left_rect.x, left_rect.w,
  1036. right_rect.x, right_rect.w);
  1037. return -EINVAL;
  1038. } else if ((left_rect.y != right_rect.y) ||
  1039. (left_rect.h != right_rect.h)) {
  1040. SDE_ERROR(
  1041. "stage:%d invalid yoff/ht: l_yxh:%dx%d r_yxh:%dx%d\n",
  1042. stage, left_rect.y, left_rect.h,
  1043. right_rect.y, right_rect.h);
  1044. return -EINVAL;
  1045. }
  1046. }
  1047. return rc;
  1048. }
  1049. static void _sde_crtc_set_src_split_order(struct drm_crtc *crtc,
  1050. struct plane_state *pstates, int cnt)
  1051. {
  1052. struct plane_state *prv_pstate, *cur_pstate, *nxt_pstate;
  1053. enum sde_layout prev_layout, cur_layout;
  1054. struct sde_kms *sde_kms;
  1055. struct sde_rect left_rect, right_rect;
  1056. int32_t left_pid, right_pid;
  1057. int32_t stage;
  1058. int i;
  1059. sde_kms = _sde_crtc_get_kms(crtc);
  1060. if (!sde_kms || !sde_kms->catalog) {
  1061. SDE_ERROR("invalid parameters\n");
  1062. return;
  1063. }
  1064. if (!sde_kms->catalog->pipe_order_type)
  1065. return;
  1066. for (i = 0; i < cnt; i++) {
  1067. prv_pstate = (i > 0) ? &pstates[i - 1] : NULL;
  1068. cur_pstate = &pstates[i];
  1069. nxt_pstate = ((i + 1) < cnt) ? &pstates[i + 1] : NULL;
  1070. prev_layout = prv_pstate ? prv_pstate->sde_pstate->layout :
  1071. SDE_LAYOUT_NONE;
  1072. cur_layout = cur_pstate->sde_pstate->layout;
  1073. if ((!prv_pstate) || (prv_pstate->stage != cur_pstate->stage)
  1074. || (prev_layout != cur_layout)) {
  1075. /*
  1076. * reset if prv or nxt pipes are not in the same stage
  1077. * as the cur pipe
  1078. */
  1079. if ((!nxt_pstate)
  1080. || (nxt_pstate->stage != cur_pstate->stage)
  1081. || (nxt_pstate->sde_pstate->layout !=
  1082. cur_pstate->sde_pstate->layout))
  1083. cur_pstate->sde_pstate->pipe_order_flags = 0;
  1084. continue;
  1085. }
  1086. stage = cur_pstate->stage;
  1087. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  1088. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1089. prv_pstate->drm_pstate->crtc_y,
  1090. prv_pstate->drm_pstate->crtc_w,
  1091. prv_pstate->drm_pstate->crtc_h, false);
  1092. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1093. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1094. cur_pstate->drm_pstate->crtc_y,
  1095. cur_pstate->drm_pstate->crtc_w,
  1096. cur_pstate->drm_pstate->crtc_h, false);
  1097. if (right_rect.x < left_rect.x) {
  1098. swap(left_pid, right_pid);
  1099. swap(left_rect, right_rect);
  1100. swap(prv_pstate, cur_pstate);
  1101. }
  1102. cur_pstate->sde_pstate->pipe_order_flags = SDE_SSPP_RIGHT;
  1103. prv_pstate->sde_pstate->pipe_order_flags = 0;
  1104. }
  1105. for (i = 0; i < cnt; i++) {
  1106. cur_pstate = &pstates[i];
  1107. sde_plane_setup_src_split_order(
  1108. cur_pstate->drm_pstate->plane,
  1109. cur_pstate->sde_pstate->multirect_index,
  1110. cur_pstate->sde_pstate->pipe_order_flags);
  1111. }
  1112. }
  1113. static void _sde_crtc_setup_blend_cfg_by_stage(struct sde_crtc_mixer *mixer,
  1114. int num_mixers, struct plane_state *pstates, int cnt)
  1115. {
  1116. int i, lm_idx;
  1117. struct sde_format *format;
  1118. bool blend_stage[SDE_STAGE_MAX] = { false };
  1119. u32 blend_type;
  1120. for (i = cnt - 1; i >= 0; i--) {
  1121. blend_type = sde_plane_get_property(pstates[i].sde_pstate,
  1122. PLANE_PROP_BLEND_OP);
  1123. /* stage has already been programmed or BLEND_OP_SKIP type */
  1124. if (blend_stage[pstates[i].sde_pstate->stage] ||
  1125. blend_type == SDE_DRM_BLEND_OP_SKIP)
  1126. continue;
  1127. for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) {
  1128. format = to_sde_format(msm_framebuffer_format(
  1129. pstates[i].sde_pstate->base.fb));
  1130. if (!format) {
  1131. SDE_ERROR("invalid format\n");
  1132. return;
  1133. }
  1134. _sde_crtc_setup_blend_cfg(mixer + lm_idx,
  1135. pstates[i].sde_pstate, format);
  1136. blend_stage[pstates[i].sde_pstate->stage] = true;
  1137. }
  1138. }
  1139. }
  1140. static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc,
  1141. struct drm_crtc_state *old_state, struct sde_crtc *sde_crtc,
  1142. struct sde_crtc_mixer *mixer)
  1143. {
  1144. struct drm_plane *plane;
  1145. struct drm_framebuffer *fb;
  1146. struct drm_plane_state *state;
  1147. struct sde_crtc_state *cstate;
  1148. struct sde_plane_state *pstate = NULL;
  1149. struct plane_state *pstates = NULL;
  1150. struct sde_format *format;
  1151. struct sde_hw_ctl *ctl;
  1152. struct sde_hw_mixer *lm;
  1153. struct sde_hw_stage_cfg *stage_cfg;
  1154. struct sde_rect plane_crtc_roi;
  1155. uint32_t stage_idx, lm_idx, layout_idx;
  1156. int zpos_cnt[MAX_LAYOUTS_PER_CRTC][SDE_STAGE_MAX + 1];
  1157. int i, mode, cnt = 0;
  1158. bool bg_alpha_enable = false, is_secure = false;
  1159. u32 blend_type;
  1160. DECLARE_BITMAP(fetch_active, SSPP_MAX);
  1161. if (!sde_crtc || !crtc->state || !mixer) {
  1162. SDE_ERROR("invalid sde_crtc or mixer\n");
  1163. return;
  1164. }
  1165. ctl = mixer->hw_ctl;
  1166. lm = mixer->hw_lm;
  1167. cstate = to_sde_crtc_state(crtc->state);
  1168. pstates = kcalloc(SDE_PSTATES_MAX,
  1169. sizeof(struct plane_state), GFP_KERNEL);
  1170. if (!pstates)
  1171. return;
  1172. memset(fetch_active, 0, sizeof(fetch_active));
  1173. memset(zpos_cnt, 0, sizeof(zpos_cnt));
  1174. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1175. state = plane->state;
  1176. if (!state)
  1177. continue;
  1178. plane_crtc_roi.x = state->crtc_x;
  1179. plane_crtc_roi.y = state->crtc_y;
  1180. plane_crtc_roi.w = state->crtc_w;
  1181. plane_crtc_roi.h = state->crtc_h;
  1182. pstate = to_sde_plane_state(state);
  1183. fb = state->fb;
  1184. mode = sde_plane_get_property(pstate,
  1185. PLANE_PROP_FB_TRANSLATION_MODE);
  1186. is_secure = ((mode == SDE_DRM_FB_SEC) ||
  1187. (mode == SDE_DRM_FB_SEC_DIR_TRANS)) ?
  1188. true : false;
  1189. set_bit(sde_plane_pipe(plane), fetch_active);
  1190. sde_plane_ctl_flush(plane, ctl, true);
  1191. SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
  1192. crtc->base.id,
  1193. pstate->stage,
  1194. plane->base.id,
  1195. sde_plane_pipe(plane) - SSPP_VIG0,
  1196. state->fb ? state->fb->base.id : -1);
  1197. format = to_sde_format(msm_framebuffer_format(pstate->base.fb));
  1198. if (!format) {
  1199. SDE_ERROR("invalid format\n");
  1200. goto end;
  1201. }
  1202. blend_type = sde_plane_get_property(pstate,
  1203. PLANE_PROP_BLEND_OP);
  1204. if (blend_type != SDE_DRM_BLEND_OP_SKIP) {
  1205. if (pstate->stage == SDE_STAGE_BASE &&
  1206. format->alpha_enable)
  1207. bg_alpha_enable = true;
  1208. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1209. state->fb ? state->fb->base.id : -1,
  1210. state->src_x >> 16, state->src_y >> 16,
  1211. state->src_w >> 16, state->src_h >> 16,
  1212. state->crtc_x, state->crtc_y,
  1213. state->crtc_w, state->crtc_h,
  1214. pstate->rotation, is_secure);
  1215. /*
  1216. * none or left layout will program to layer mixer
  1217. * group 0, right layout will program to layer mixer
  1218. * group 1.
  1219. */
  1220. if (pstate->layout <= SDE_LAYOUT_LEFT)
  1221. layout_idx = 0;
  1222. else
  1223. layout_idx = 1;
  1224. stage_cfg = &sde_crtc->stage_cfg[layout_idx];
  1225. stage_idx = zpos_cnt[layout_idx][pstate->stage]++;
  1226. stage_cfg->stage[pstate->stage][stage_idx] =
  1227. sde_plane_pipe(plane);
  1228. stage_cfg->multirect_index[pstate->stage][stage_idx] =
  1229. pstate->multirect_index;
  1230. SDE_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
  1231. sde_plane_pipe(plane) - SSPP_VIG0,
  1232. pstate->stage,
  1233. pstate->multirect_index,
  1234. pstate->multirect_mode,
  1235. format->base.pixel_format,
  1236. fb ? fb->modifier : 0,
  1237. layout_idx);
  1238. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers;
  1239. lm_idx++) {
  1240. if (bg_alpha_enable && !format->alpha_enable)
  1241. mixer[lm_idx].mixer_op_mode = 0;
  1242. else
  1243. mixer[lm_idx].mixer_op_mode |=
  1244. 1 << pstate->stage;
  1245. }
  1246. }
  1247. if (cnt >= SDE_PSTATES_MAX)
  1248. continue;
  1249. pstates[cnt].sde_pstate = pstate;
  1250. pstates[cnt].drm_pstate = state;
  1251. if (blend_type == SDE_DRM_BLEND_OP_SKIP)
  1252. pstates[cnt].stage = SKIP_STAGING_PIPE_ZPOS;
  1253. else
  1254. pstates[cnt].stage = sde_plane_get_property(
  1255. pstates[cnt].sde_pstate, PLANE_PROP_ZPOS);
  1256. pstates[cnt].pipe_id = sde_plane_pipe(plane);
  1257. cnt++;
  1258. }
  1259. /* blend config update */
  1260. _sde_crtc_setup_blend_cfg_by_stage(mixer, sde_crtc->num_mixers,
  1261. pstates, cnt);
  1262. if (ctl->ops.set_active_pipes)
  1263. ctl->ops.set_active_pipes(ctl, fetch_active);
  1264. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  1265. _sde_crtc_set_src_split_order(crtc, pstates, cnt);
  1266. if (lm && lm->ops.setup_dim_layer) {
  1267. cstate = to_sde_crtc_state(crtc->state);
  1268. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty)) {
  1269. for (i = 0; i < cstate->num_dim_layers; i++)
  1270. _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc,
  1271. mixer, &cstate->dim_layer[i]);
  1272. clear_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  1273. }
  1274. }
  1275. end:
  1276. kfree(pstates);
  1277. }
  1278. static void _sde_crtc_swap_mixers_for_right_partial_update(
  1279. struct drm_crtc *crtc)
  1280. {
  1281. struct sde_crtc *sde_crtc;
  1282. struct sde_crtc_state *cstate;
  1283. struct drm_encoder *drm_enc;
  1284. bool is_right_only;
  1285. bool encoder_in_dsc_merge = false;
  1286. if (!crtc || !crtc->state)
  1287. return;
  1288. sde_crtc = to_sde_crtc(crtc);
  1289. cstate = to_sde_crtc_state(crtc->state);
  1290. if (sde_crtc->num_mixers != CRTC_DUAL_MIXERS_ONLY)
  1291. return;
  1292. drm_for_each_encoder_mask(drm_enc, crtc->dev,
  1293. crtc->state->encoder_mask) {
  1294. if (sde_encoder_is_dsc_merge(drm_enc)) {
  1295. encoder_in_dsc_merge = true;
  1296. break;
  1297. }
  1298. }
  1299. /**
  1300. * For right-only partial update with DSC merge, we swap LM0 & LM1.
  1301. * This is due to two reasons:
  1302. * - On 8996, there is a DSC HW requirement that in DSC Merge Mode,
  1303. * the left DSC must be used, right DSC cannot be used alone.
  1304. * For right-only partial update, this means swap layer mixers to map
  1305. * Left LM to Right INTF. On later HW this was relaxed.
  1306. * - In DSC Merge mode, the physical encoder has already registered
  1307. * PP0 as the master, to switch to right-only we would have to
  1308. * reprogram to be driven by PP1 instead.
  1309. * To support both cases, we prefer to support the mixer swap solution.
  1310. */
  1311. if (!encoder_in_dsc_merge) {
  1312. if (sde_crtc->mixers_swapped) {
  1313. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1314. sde_crtc->mixers_swapped = false;
  1315. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  1316. }
  1317. return;
  1318. }
  1319. is_right_only = sde_kms_rect_is_null(&cstate->lm_roi[0]) &&
  1320. !sde_kms_rect_is_null(&cstate->lm_roi[1]);
  1321. if (is_right_only && !sde_crtc->mixers_swapped) {
  1322. /* right-only update swap mixers */
  1323. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1324. sde_crtc->mixers_swapped = true;
  1325. } else if (!is_right_only && sde_crtc->mixers_swapped) {
  1326. /* left-only or full update, swap back */
  1327. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1328. sde_crtc->mixers_swapped = false;
  1329. }
  1330. SDE_DEBUG("%s: right_only %d swapped %d, mix0->lm%d, mix1->lm%d\n",
  1331. sde_crtc->name, is_right_only, sde_crtc->mixers_swapped,
  1332. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1333. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1334. SDE_EVT32(DRMID(crtc), is_right_only, sde_crtc->mixers_swapped,
  1335. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1336. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1337. }
  1338. /**
  1339. * _sde_crtc_blend_setup - configure crtc mixers
  1340. * @crtc: Pointer to drm crtc structure
  1341. * @old_state: Pointer to old crtc state
  1342. * @add_planes: Whether or not to add planes to mixers
  1343. */
  1344. static void _sde_crtc_blend_setup(struct drm_crtc *crtc,
  1345. struct drm_crtc_state *old_state, bool add_planes)
  1346. {
  1347. struct sde_crtc *sde_crtc;
  1348. struct sde_crtc_state *sde_crtc_state;
  1349. struct sde_crtc_mixer *mixer;
  1350. struct sde_hw_ctl *ctl;
  1351. struct sde_hw_mixer *lm;
  1352. struct sde_ctl_flush_cfg cfg = {0,};
  1353. int i;
  1354. if (!crtc)
  1355. return;
  1356. sde_crtc = to_sde_crtc(crtc);
  1357. sde_crtc_state = to_sde_crtc_state(crtc->state);
  1358. mixer = sde_crtc->mixers;
  1359. SDE_DEBUG("%s\n", sde_crtc->name);
  1360. if (sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  1361. SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers);
  1362. return;
  1363. }
  1364. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1365. if (!mixer[i].hw_lm) {
  1366. SDE_ERROR("invalid lm or ctl assigned to mixer\n");
  1367. return;
  1368. }
  1369. mixer[i].mixer_op_mode = 0;
  1370. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS,
  1371. sde_crtc_state->dirty)) {
  1372. /* clear dim_layer settings */
  1373. lm = mixer[i].hw_lm;
  1374. if (lm->ops.clear_dim_layer)
  1375. lm->ops.clear_dim_layer(lm);
  1376. }
  1377. }
  1378. _sde_crtc_swap_mixers_for_right_partial_update(crtc);
  1379. /* initialize stage cfg */
  1380. memset(&sde_crtc->stage_cfg, 0, sizeof(sde_crtc->stage_cfg));
  1381. if (add_planes)
  1382. _sde_crtc_blend_setup_mixer(crtc, old_state, sde_crtc, mixer);
  1383. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1384. const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i];
  1385. int lm_layout = i / MAX_MIXERS_PER_LAYOUT;
  1386. ctl = mixer[i].hw_ctl;
  1387. lm = mixer[i].hw_lm;
  1388. if (sde_kms_rect_is_null(lm_roi))
  1389. sde_crtc->mixers[i].mixer_op_mode = 0;
  1390. lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
  1391. /* stage config flush mask */
  1392. ctl->ops.update_bitmask_mixer(ctl, mixer[i].hw_lm->idx, 1);
  1393. ctl->ops.get_pending_flush(ctl, &cfg);
  1394. SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
  1395. mixer[i].hw_lm->idx - LM_0,
  1396. mixer[i].mixer_op_mode,
  1397. ctl->idx - CTL_0,
  1398. cfg.pending_flush_mask);
  1399. if (sde_kms_rect_is_null(lm_roi)) {
  1400. SDE_DEBUG(
  1401. "%s: lm%d leave ctl%d mask 0 since null roi\n",
  1402. sde_crtc->name, lm->idx - LM_0,
  1403. ctl->idx - CTL_0);
  1404. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1405. NULL, true);
  1406. } else {
  1407. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1408. &sde_crtc->stage_cfg[lm_layout],
  1409. false);
  1410. }
  1411. }
  1412. _sde_crtc_program_lm_output_roi(crtc);
  1413. }
  1414. int sde_crtc_find_plane_fb_modes(struct drm_crtc *crtc,
  1415. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1416. {
  1417. struct drm_plane *plane;
  1418. struct sde_plane_state *sde_pstate;
  1419. uint32_t mode = 0;
  1420. int rc;
  1421. if (!crtc) {
  1422. SDE_ERROR("invalid state\n");
  1423. return -EINVAL;
  1424. }
  1425. *fb_ns = 0;
  1426. *fb_sec = 0;
  1427. *fb_sec_dir = 0;
  1428. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1429. if (IS_ERR_OR_NULL(plane) || IS_ERR_OR_NULL(plane->state)) {
  1430. rc = PTR_ERR(plane);
  1431. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1432. DRMID(crtc), DRMID(plane), rc);
  1433. return rc;
  1434. }
  1435. sde_pstate = to_sde_plane_state(plane->state);
  1436. mode = sde_plane_get_property(sde_pstate,
  1437. PLANE_PROP_FB_TRANSLATION_MODE);
  1438. switch (mode) {
  1439. case SDE_DRM_FB_NON_SEC:
  1440. (*fb_ns)++;
  1441. break;
  1442. case SDE_DRM_FB_SEC:
  1443. (*fb_sec)++;
  1444. break;
  1445. case SDE_DRM_FB_SEC_DIR_TRANS:
  1446. (*fb_sec_dir)++;
  1447. break;
  1448. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1449. break;
  1450. default:
  1451. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1452. DRMID(plane), mode);
  1453. return -EINVAL;
  1454. }
  1455. }
  1456. return 0;
  1457. }
  1458. int sde_crtc_state_find_plane_fb_modes(struct drm_crtc_state *state,
  1459. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1460. {
  1461. struct drm_plane *plane;
  1462. const struct drm_plane_state *pstate;
  1463. struct sde_plane_state *sde_pstate;
  1464. uint32_t mode = 0;
  1465. int rc;
  1466. if (!state) {
  1467. SDE_ERROR("invalid state\n");
  1468. return -EINVAL;
  1469. }
  1470. *fb_ns = 0;
  1471. *fb_sec = 0;
  1472. *fb_sec_dir = 0;
  1473. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  1474. if (IS_ERR_OR_NULL(pstate)) {
  1475. rc = PTR_ERR(pstate);
  1476. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1477. DRMID(state->crtc), DRMID(plane), rc);
  1478. return rc;
  1479. }
  1480. sde_pstate = to_sde_plane_state(pstate);
  1481. mode = sde_plane_get_property(sde_pstate,
  1482. PLANE_PROP_FB_TRANSLATION_MODE);
  1483. switch (mode) {
  1484. case SDE_DRM_FB_NON_SEC:
  1485. (*fb_ns)++;
  1486. break;
  1487. case SDE_DRM_FB_SEC:
  1488. (*fb_sec)++;
  1489. break;
  1490. case SDE_DRM_FB_SEC_DIR_TRANS:
  1491. (*fb_sec_dir)++;
  1492. break;
  1493. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1494. break;
  1495. default:
  1496. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1497. DRMID(plane), mode);
  1498. return -EINVAL;
  1499. }
  1500. }
  1501. return 0;
  1502. }
  1503. static void _sde_drm_fb_sec_dir_trans(
  1504. struct sde_kms_smmu_state_data *smmu_state, uint32_t secure_level,
  1505. struct sde_mdss_cfg *catalog, bool old_valid_fb, int *ops)
  1506. {
  1507. /* secure display usecase */
  1508. if ((smmu_state->state == ATTACHED)
  1509. && (secure_level == SDE_DRM_SEC_ONLY)) {
  1510. smmu_state->state = catalog->sui_ns_allowed ?
  1511. DETACH_SEC_REQ : DETACH_ALL_REQ;
  1512. smmu_state->secure_level = secure_level;
  1513. smmu_state->transition_type = PRE_COMMIT;
  1514. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1515. if (old_valid_fb)
  1516. *ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE |
  1517. SDE_KMS_OPS_CLEANUP_PLANE_FB);
  1518. if (catalog->sui_misr_supported)
  1519. smmu_state->sui_misr_state =
  1520. SUI_MISR_ENABLE_REQ;
  1521. /* secure camera usecase */
  1522. } else if (smmu_state->state == ATTACHED) {
  1523. smmu_state->state = DETACH_SEC_REQ;
  1524. smmu_state->secure_level = secure_level;
  1525. smmu_state->transition_type = PRE_COMMIT;
  1526. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1527. }
  1528. }
  1529. static void _sde_drm_fb_transactions(
  1530. struct sde_kms_smmu_state_data *smmu_state,
  1531. struct sde_mdss_cfg *catalog, bool old_valid_fb, bool post_commit,
  1532. int *ops)
  1533. {
  1534. if (((smmu_state->state == DETACHED)
  1535. || (smmu_state->state == DETACH_ALL_REQ))
  1536. || ((smmu_state->secure_level == SDE_DRM_SEC_ONLY)
  1537. && ((smmu_state->state == DETACHED_SEC)
  1538. || (smmu_state->state == DETACH_SEC_REQ)))) {
  1539. smmu_state->state = catalog->sui_ns_allowed ?
  1540. ATTACH_SEC_REQ : ATTACH_ALL_REQ;
  1541. smmu_state->transition_type = post_commit ?
  1542. POST_COMMIT : PRE_COMMIT;
  1543. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1544. if (old_valid_fb)
  1545. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1546. if (catalog->sui_misr_supported)
  1547. smmu_state->sui_misr_state =
  1548. SUI_MISR_DISABLE_REQ;
  1549. } else if ((smmu_state->state == DETACHED_SEC)
  1550. || (smmu_state->state == DETACH_SEC_REQ)) {
  1551. smmu_state->state = ATTACH_SEC_REQ;
  1552. smmu_state->transition_type = post_commit ?
  1553. POST_COMMIT : PRE_COMMIT;
  1554. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1555. if (old_valid_fb)
  1556. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1557. }
  1558. }
  1559. /**
  1560. * sde_crtc_get_secure_transition_ops - determines the operations that
  1561. * need to be performed before transitioning to secure state
  1562. * This function should be called after swapping the new state
  1563. * @crtc: Pointer to drm crtc structure
  1564. * Returns the bitmask of operations need to be performed, -Error in
  1565. * case of error cases
  1566. */
  1567. int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
  1568. struct drm_crtc_state *old_crtc_state,
  1569. bool old_valid_fb)
  1570. {
  1571. struct drm_plane *plane;
  1572. struct drm_encoder *encoder;
  1573. struct sde_crtc *sde_crtc;
  1574. struct sde_kms *sde_kms;
  1575. struct sde_mdss_cfg *catalog;
  1576. struct sde_kms_smmu_state_data *smmu_state;
  1577. uint32_t translation_mode = 0, secure_level;
  1578. int ops = 0;
  1579. bool post_commit = false;
  1580. if (!crtc || !crtc->state) {
  1581. SDE_ERROR("invalid crtc\n");
  1582. return -EINVAL;
  1583. }
  1584. sde_kms = _sde_crtc_get_kms(crtc);
  1585. if (!sde_kms)
  1586. return -EINVAL;
  1587. smmu_state = &sde_kms->smmu_state;
  1588. smmu_state->prev_state = smmu_state->state;
  1589. smmu_state->prev_secure_level = smmu_state->secure_level;
  1590. sde_crtc = to_sde_crtc(crtc);
  1591. secure_level = sde_crtc_get_secure_level(crtc, crtc->state);
  1592. catalog = sde_kms->catalog;
  1593. /*
  1594. * SMMU operations need to be delayed in case of video mode panels
  1595. * when switching back to non_secure mode
  1596. */
  1597. drm_for_each_encoder_mask(encoder, crtc->dev,
  1598. crtc->state->encoder_mask) {
  1599. if (sde_encoder_is_dsi_display(encoder))
  1600. post_commit |= sde_encoder_check_curr_mode(encoder,
  1601. MSM_DISPLAY_VIDEO_MODE);
  1602. }
  1603. SDE_DEBUG("crtc%d: secure_level %d old_valid_fb %d post_commit %d\n",
  1604. DRMID(crtc), secure_level, old_valid_fb, post_commit);
  1605. SDE_EVT32_VERBOSE(DRMID(crtc), secure_level, smmu_state->state,
  1606. old_valid_fb, post_commit, SDE_EVTLOG_FUNC_ENTRY);
  1607. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1608. if (!plane->state)
  1609. continue;
  1610. translation_mode = sde_plane_get_property(
  1611. to_sde_plane_state(plane->state),
  1612. PLANE_PROP_FB_TRANSLATION_MODE);
  1613. if (translation_mode > SDE_DRM_FB_SEC_DIR_TRANS) {
  1614. SDE_ERROR("crtc%d: invalid translation_mode %d\n",
  1615. DRMID(crtc), translation_mode);
  1616. return -EINVAL;
  1617. }
  1618. /* we can break if we find sec_dir plane */
  1619. if (translation_mode == SDE_DRM_FB_SEC_DIR_TRANS)
  1620. break;
  1621. }
  1622. mutex_lock(&sde_kms->secure_transition_lock);
  1623. switch (translation_mode) {
  1624. case SDE_DRM_FB_SEC_DIR_TRANS:
  1625. _sde_drm_fb_sec_dir_trans(smmu_state, secure_level,
  1626. catalog, old_valid_fb, &ops);
  1627. break;
  1628. case SDE_DRM_FB_SEC:
  1629. case SDE_DRM_FB_NON_SEC:
  1630. _sde_drm_fb_transactions(smmu_state, catalog,
  1631. old_valid_fb, post_commit, &ops);
  1632. break;
  1633. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1634. ops = 0;
  1635. break;
  1636. default:
  1637. SDE_ERROR("crtc%d: invalid plane fb_mode %d\n",
  1638. DRMID(crtc), translation_mode);
  1639. ops = -EINVAL;
  1640. }
  1641. /* log only during actual transition times */
  1642. if (ops) {
  1643. SDE_DEBUG("crtc%d: state%d sec%d sec_lvl%d type%d ops%x\n",
  1644. DRMID(crtc), smmu_state->state,
  1645. secure_level, smmu_state->secure_level,
  1646. smmu_state->transition_type, ops);
  1647. SDE_EVT32(DRMID(crtc), secure_level, translation_mode,
  1648. smmu_state->state, smmu_state->transition_type,
  1649. smmu_state->secure_level, old_valid_fb,
  1650. post_commit, ops, SDE_EVTLOG_FUNC_EXIT);
  1651. }
  1652. mutex_unlock(&sde_kms->secure_transition_lock);
  1653. return ops;
  1654. }
  1655. /**
  1656. * _sde_crtc_setup_scaler3_lut - Set up scaler lut
  1657. * LUTs are configured only once during boot
  1658. * @sde_crtc: Pointer to sde crtc
  1659. * @cstate: Pointer to sde crtc state
  1660. */
  1661. static int _sde_crtc_set_dest_scaler_lut(struct sde_crtc *sde_crtc,
  1662. struct sde_crtc_state *cstate, uint32_t lut_idx)
  1663. {
  1664. struct sde_hw_scaler3_lut_cfg *cfg;
  1665. struct sde_kms *sde_kms;
  1666. u32 *lut_data = NULL;
  1667. size_t len = 0;
  1668. int ret = 0;
  1669. if (!sde_crtc || !cstate) {
  1670. SDE_ERROR("invalid args\n");
  1671. return -EINVAL;
  1672. }
  1673. sde_kms = _sde_crtc_get_kms(&sde_crtc->base);
  1674. if (!sde_kms)
  1675. return -EINVAL;
  1676. if (is_qseed3_rev_qseed3lite(sde_kms->catalog))
  1677. return 0;
  1678. lut_data = msm_property_get_blob(&sde_crtc->property_info,
  1679. &cstate->property_state, &len, lut_idx);
  1680. if (!lut_data || !len) {
  1681. SDE_DEBUG("%s: lut(%d): cleared: %pK, %zu\n", sde_crtc->name,
  1682. lut_idx, lut_data, len);
  1683. lut_data = NULL;
  1684. len = 0;
  1685. }
  1686. cfg = &cstate->scl3_lut_cfg;
  1687. switch (lut_idx) {
  1688. case CRTC_PROP_DEST_SCALER_LUT_ED:
  1689. cfg->dir_lut = lut_data;
  1690. cfg->dir_len = len;
  1691. break;
  1692. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  1693. cfg->cir_lut = lut_data;
  1694. cfg->cir_len = len;
  1695. break;
  1696. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  1697. cfg->sep_lut = lut_data;
  1698. cfg->sep_len = len;
  1699. break;
  1700. default:
  1701. ret = -EINVAL;
  1702. SDE_ERROR("%s:invalid LUT idx(%d)\n", sde_crtc->name, lut_idx);
  1703. SDE_EVT32(DRMID(&sde_crtc->base), lut_idx, SDE_EVTLOG_ERROR);
  1704. break;
  1705. }
  1706. cfg->is_configured = cfg->dir_lut && cfg->cir_lut && cfg->sep_lut;
  1707. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), ret, lut_idx, len,
  1708. cfg->is_configured);
  1709. return ret;
  1710. }
  1711. void sde_crtc_timeline_status(struct drm_crtc *crtc)
  1712. {
  1713. struct sde_crtc *sde_crtc;
  1714. if (!crtc) {
  1715. SDE_ERROR("invalid crtc\n");
  1716. return;
  1717. }
  1718. sde_crtc = to_sde_crtc(crtc);
  1719. sde_fence_timeline_status(sde_crtc->output_fence, &crtc->base);
  1720. }
  1721. static int _sde_validate_hw_resources(struct sde_crtc *sde_crtc)
  1722. {
  1723. int i;
  1724. /**
  1725. * Check if sufficient hw resources are
  1726. * available as per target caps & topology
  1727. */
  1728. if (!sde_crtc) {
  1729. SDE_ERROR("invalid argument\n");
  1730. return -EINVAL;
  1731. }
  1732. if (!sde_crtc->num_mixers ||
  1733. sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  1734. SDE_ERROR("%s: invalid number mixers: %d\n",
  1735. sde_crtc->name, sde_crtc->num_mixers);
  1736. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1737. SDE_EVTLOG_ERROR);
  1738. return -EINVAL;
  1739. }
  1740. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1741. if (!sde_crtc->mixers[i].hw_lm || !sde_crtc->mixers[i].hw_ctl
  1742. || !sde_crtc->mixers[i].hw_ds) {
  1743. SDE_ERROR("%s:insufficient resources for mixer(%d)\n",
  1744. sde_crtc->name, i);
  1745. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1746. i, sde_crtc->mixers[i].hw_lm,
  1747. sde_crtc->mixers[i].hw_ctl,
  1748. sde_crtc->mixers[i].hw_ds, SDE_EVTLOG_ERROR);
  1749. return -EINVAL;
  1750. }
  1751. }
  1752. return 0;
  1753. }
  1754. /**
  1755. * _sde_crtc_dest_scaler_setup - Set up dest scaler block
  1756. * @crtc: Pointer to drm crtc
  1757. */
  1758. static void _sde_crtc_dest_scaler_setup(struct drm_crtc *crtc)
  1759. {
  1760. struct sde_crtc *sde_crtc;
  1761. struct sde_crtc_state *cstate;
  1762. struct sde_hw_mixer *hw_lm;
  1763. struct sde_hw_ctl *hw_ctl;
  1764. struct sde_hw_ds *hw_ds;
  1765. struct sde_hw_ds_cfg *cfg;
  1766. struct sde_kms *kms;
  1767. u32 op_mode = 0;
  1768. u32 lm_idx = 0, num_mixers = 0;
  1769. int i, count = 0;
  1770. if (!crtc)
  1771. return;
  1772. sde_crtc = to_sde_crtc(crtc);
  1773. cstate = to_sde_crtc_state(crtc->state);
  1774. kms = _sde_crtc_get_kms(crtc);
  1775. num_mixers = sde_crtc->num_mixers;
  1776. count = cstate->num_ds;
  1777. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1778. SDE_EVT32(DRMID(crtc), num_mixers, count, cstate->dirty[0],
  1779. cstate->num_ds_enabled);
  1780. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  1781. SDE_DEBUG("no change in settings, skip commit\n");
  1782. } else if (!kms || !kms->catalog) {
  1783. SDE_ERROR("crtc%d:invalid parameters\n", crtc->base.id);
  1784. } else if (!kms->catalog->mdp[0].has_dest_scaler) {
  1785. SDE_DEBUG("dest scaler feature not supported\n");
  1786. } else if (_sde_validate_hw_resources(sde_crtc)) {
  1787. //do nothing
  1788. } else if ((!cstate->scl3_lut_cfg.is_configured) &&
  1789. (!is_qseed3_rev_qseed3lite(kms->catalog))) {
  1790. SDE_ERROR("crtc%d:no LUT data available\n", crtc->base.id);
  1791. } else {
  1792. for (i = 0; i < count; i++) {
  1793. cfg = &cstate->ds_cfg[i];
  1794. if (!cfg->flags)
  1795. continue;
  1796. lm_idx = cfg->idx;
  1797. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  1798. hw_ctl = sde_crtc->mixers[lm_idx].hw_ctl;
  1799. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  1800. /* Setup op mode - Dual/single */
  1801. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  1802. op_mode |= BIT(hw_ds->idx - DS_0);
  1803. if ((i == count-1) && hw_ds->ops.setup_opmode) {
  1804. op_mode |= (cstate->num_ds_enabled ==
  1805. CRTC_DUAL_MIXERS_ONLY) ?
  1806. SDE_DS_OP_MODE_DUAL : 0;
  1807. hw_ds->ops.setup_opmode(hw_ds, op_mode);
  1808. SDE_EVT32_VERBOSE(DRMID(crtc), op_mode);
  1809. }
  1810. /* Setup scaler */
  1811. if ((cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE) ||
  1812. (cfg->flags &
  1813. SDE_DRM_DESTSCALER_ENHANCER_UPDATE)) {
  1814. if (hw_ds->ops.setup_scaler)
  1815. hw_ds->ops.setup_scaler(hw_ds,
  1816. &cfg->scl3_cfg,
  1817. &cstate->scl3_lut_cfg);
  1818. }
  1819. /*
  1820. * Dest scaler shares the flush bit of the LM in control
  1821. */
  1822. if (hw_ctl && hw_ctl->ops.update_bitmask_mixer)
  1823. hw_ctl->ops.update_bitmask_mixer(
  1824. hw_ctl, hw_lm->idx, 1);
  1825. }
  1826. }
  1827. }
  1828. static void sde_crtc_frame_event_cb(void *data, u32 event)
  1829. {
  1830. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1831. struct sde_crtc *sde_crtc;
  1832. struct msm_drm_private *priv;
  1833. struct sde_crtc_frame_event *fevent;
  1834. struct sde_kms_frame_event_cb_data *cb_data;
  1835. struct drm_plane *plane;
  1836. u32 ubwc_error;
  1837. unsigned long flags;
  1838. u32 crtc_id;
  1839. cb_data = (struct sde_kms_frame_event_cb_data *)data;
  1840. if (!data) {
  1841. SDE_ERROR("invalid parameters\n");
  1842. return;
  1843. }
  1844. crtc = cb_data->crtc;
  1845. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  1846. SDE_ERROR("invalid parameters\n");
  1847. return;
  1848. }
  1849. sde_crtc = to_sde_crtc(crtc);
  1850. priv = crtc->dev->dev_private;
  1851. crtc_id = drm_crtc_index(crtc);
  1852. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1853. SDE_EVT32_VERBOSE(DRMID(crtc), event);
  1854. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  1855. fevent = list_first_entry_or_null(&sde_crtc->frame_event_list,
  1856. struct sde_crtc_frame_event, list);
  1857. if (fevent)
  1858. list_del_init(&fevent->list);
  1859. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  1860. if (!fevent) {
  1861. SDE_ERROR("crtc%d event %d overflow\n",
  1862. crtc->base.id, event);
  1863. SDE_EVT32(DRMID(crtc), event);
  1864. return;
  1865. }
  1866. /* log and clear plane ubwc errors if any */
  1867. if (event & (SDE_ENCODER_FRAME_EVENT_ERROR
  1868. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  1869. | SDE_ENCODER_FRAME_EVENT_DONE)) {
  1870. drm_for_each_plane_mask(plane, crtc->dev,
  1871. sde_crtc->plane_mask_old) {
  1872. ubwc_error = sde_plane_get_ubwc_error(plane);
  1873. if (ubwc_error) {
  1874. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1875. ubwc_error, SDE_EVTLOG_ERROR);
  1876. SDE_DEBUG("crtc%d plane %d ubwc_error %d\n",
  1877. DRMID(crtc), DRMID(plane),
  1878. ubwc_error);
  1879. sde_plane_clear_ubwc_error(plane);
  1880. }
  1881. }
  1882. }
  1883. fevent->event = event;
  1884. fevent->crtc = crtc;
  1885. fevent->connector = cb_data->connector;
  1886. fevent->ts = ktime_get();
  1887. kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work);
  1888. }
  1889. void sde_crtc_prepare_commit(struct drm_crtc *crtc,
  1890. struct drm_crtc_state *old_state)
  1891. {
  1892. struct drm_device *dev;
  1893. struct sde_crtc *sde_crtc;
  1894. struct sde_crtc_state *cstate;
  1895. struct drm_connector *conn;
  1896. struct drm_encoder *encoder;
  1897. struct drm_connector_list_iter conn_iter;
  1898. if (!crtc || !crtc->state) {
  1899. SDE_ERROR("invalid crtc\n");
  1900. return;
  1901. }
  1902. dev = crtc->dev;
  1903. sde_crtc = to_sde_crtc(crtc);
  1904. cstate = to_sde_crtc_state(crtc->state);
  1905. SDE_EVT32_VERBOSE(DRMID(crtc));
  1906. SDE_ATRACE_BEGIN("sde_crtc_prepare_commit");
  1907. /* identify connectors attached to this crtc */
  1908. cstate->num_connectors = 0;
  1909. drm_connector_list_iter_begin(dev, &conn_iter);
  1910. drm_for_each_connector_iter(conn, &conn_iter)
  1911. if (conn->state && conn->state->crtc == crtc &&
  1912. cstate->num_connectors < MAX_CONNECTORS) {
  1913. encoder = conn->state->best_encoder;
  1914. if (encoder)
  1915. sde_encoder_register_frame_event_callback(
  1916. encoder,
  1917. sde_crtc_frame_event_cb,
  1918. crtc);
  1919. cstate->connectors[cstate->num_connectors++] = conn;
  1920. sde_connector_prepare_fence(conn);
  1921. }
  1922. drm_connector_list_iter_end(&conn_iter);
  1923. /* prepare main output fence */
  1924. sde_fence_prepare(sde_crtc->output_fence);
  1925. SDE_ATRACE_END("sde_crtc_prepare_commit");
  1926. }
  1927. /**
  1928. * sde_crtc_complete_flip - signal pending page_flip events
  1929. * Any pending vblank events are added to the vblank_event_list
  1930. * so that the next vblank interrupt shall signal them.
  1931. * However PAGE_FLIP events are not handled through the vblank_event_list.
  1932. * This API signals any pending PAGE_FLIP events requested through
  1933. * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event.
  1934. * if file!=NULL, this is preclose potential cancel-flip path
  1935. * @crtc: Pointer to drm crtc structure
  1936. * @file: Pointer to drm file
  1937. */
  1938. void sde_crtc_complete_flip(struct drm_crtc *crtc,
  1939. struct drm_file *file)
  1940. {
  1941. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1942. struct drm_device *dev = crtc->dev;
  1943. struct drm_pending_vblank_event *event;
  1944. unsigned long flags;
  1945. spin_lock_irqsave(&dev->event_lock, flags);
  1946. event = sde_crtc->event;
  1947. if (!event)
  1948. goto end;
  1949. /*
  1950. * if regular vblank case (!file) or if cancel-flip from
  1951. * preclose on file that requested flip, then send the
  1952. * event:
  1953. */
  1954. if (!file || (event->base.file_priv == file)) {
  1955. sde_crtc->event = NULL;
  1956. DRM_DEBUG_VBL("%s: send event: %pK\n",
  1957. sde_crtc->name, event);
  1958. SDE_EVT32_VERBOSE(DRMID(crtc));
  1959. drm_crtc_send_vblank_event(crtc, event);
  1960. }
  1961. end:
  1962. spin_unlock_irqrestore(&dev->event_lock, flags);
  1963. }
  1964. enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc,
  1965. struct drm_crtc_state *cstate)
  1966. {
  1967. struct drm_encoder *encoder;
  1968. if (!crtc || !crtc->dev || !cstate) {
  1969. SDE_ERROR("invalid crtc\n");
  1970. return INTF_MODE_NONE;
  1971. }
  1972. drm_for_each_encoder_mask(encoder, crtc->dev,
  1973. cstate->encoder_mask) {
  1974. /* continue if copy encoder is encountered */
  1975. if (sde_encoder_in_clone_mode(encoder))
  1976. continue;
  1977. return sde_encoder_get_intf_mode(encoder);
  1978. }
  1979. return INTF_MODE_NONE;
  1980. }
  1981. u32 sde_crtc_get_fps_mode(struct drm_crtc *crtc)
  1982. {
  1983. struct drm_encoder *encoder;
  1984. if (!crtc || !crtc->dev) {
  1985. SDE_ERROR("invalid crtc\n");
  1986. return INTF_MODE_NONE;
  1987. }
  1988. drm_for_each_encoder(encoder, crtc->dev)
  1989. if ((encoder->crtc == crtc)
  1990. && !sde_encoder_in_cont_splash(encoder))
  1991. return sde_encoder_get_fps(encoder);
  1992. return 0;
  1993. }
  1994. static void sde_crtc_vblank_cb(void *data)
  1995. {
  1996. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1997. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1998. /* keep statistics on vblank callback - with auto reset via debugfs */
  1999. if (ktime_compare(sde_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
  2000. sde_crtc->vblank_cb_time = ktime_get();
  2001. else
  2002. sde_crtc->vblank_cb_count++;
  2003. sde_crtc->vblank_last_cb_time = ktime_get();
  2004. sysfs_notify_dirent(sde_crtc->vsync_event_sf);
  2005. drm_crtc_handle_vblank(crtc);
  2006. DRM_DEBUG_VBL("crtc%d\n", crtc->base.id);
  2007. SDE_EVT32_VERBOSE(DRMID(crtc));
  2008. }
  2009. static void _sde_crtc_retire_event(struct drm_connector *connector,
  2010. ktime_t ts, enum sde_fence_event fence_event)
  2011. {
  2012. if (!connector) {
  2013. SDE_ERROR("invalid param\n");
  2014. return;
  2015. }
  2016. SDE_ATRACE_BEGIN("signal_retire_fence");
  2017. sde_connector_complete_commit(connector, ts, fence_event);
  2018. SDE_ATRACE_END("signal_retire_fence");
  2019. }
  2020. static void sde_crtc_frame_event_work(struct kthread_work *work)
  2021. {
  2022. struct msm_drm_private *priv;
  2023. struct sde_crtc_frame_event *fevent;
  2024. struct drm_crtc *crtc;
  2025. struct sde_crtc *sde_crtc;
  2026. struct sde_kms *sde_kms;
  2027. unsigned long flags;
  2028. bool in_clone_mode = false;
  2029. if (!work) {
  2030. SDE_ERROR("invalid work handle\n");
  2031. return;
  2032. }
  2033. fevent = container_of(work, struct sde_crtc_frame_event, work);
  2034. if (!fevent->crtc || !fevent->crtc->state) {
  2035. SDE_ERROR("invalid crtc\n");
  2036. return;
  2037. }
  2038. crtc = fevent->crtc;
  2039. sde_crtc = to_sde_crtc(crtc);
  2040. sde_kms = _sde_crtc_get_kms(crtc);
  2041. if (!sde_kms) {
  2042. SDE_ERROR("invalid kms handle\n");
  2043. return;
  2044. }
  2045. priv = sde_kms->dev->dev_private;
  2046. SDE_ATRACE_BEGIN("crtc_frame_event");
  2047. SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
  2048. ktime_to_ns(fevent->ts));
  2049. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_ENTRY);
  2050. in_clone_mode = (fevent->event & SDE_ENCODER_FRAME_EVENT_CWB_DONE) ?
  2051. true : false;
  2052. if (!in_clone_mode && (fevent->event & (SDE_ENCODER_FRAME_EVENT_ERROR
  2053. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  2054. | SDE_ENCODER_FRAME_EVENT_DONE))) {
  2055. if (atomic_read(&sde_crtc->frame_pending) < 1) {
  2056. /* this should not happen */
  2057. SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n",
  2058. crtc->base.id,
  2059. ktime_to_ns(fevent->ts),
  2060. atomic_read(&sde_crtc->frame_pending));
  2061. SDE_EVT32(DRMID(crtc), fevent->event,
  2062. SDE_EVTLOG_FUNC_CASE1);
  2063. } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) {
  2064. /* release bandwidth and other resources */
  2065. SDE_DEBUG("crtc%d ts:%lld last pending\n",
  2066. crtc->base.id,
  2067. ktime_to_ns(fevent->ts));
  2068. SDE_EVT32(DRMID(crtc), fevent->event,
  2069. SDE_EVTLOG_FUNC_CASE2);
  2070. sde_core_perf_crtc_release_bw(crtc);
  2071. } else {
  2072. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event,
  2073. SDE_EVTLOG_FUNC_CASE3);
  2074. }
  2075. }
  2076. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE) {
  2077. SDE_ATRACE_BEGIN("signal_release_fence");
  2078. sde_fence_signal(sde_crtc->output_fence, fevent->ts,
  2079. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2080. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2081. SDE_ATRACE_END("signal_release_fence");
  2082. }
  2083. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE)
  2084. /* this api should be called without spin_lock */
  2085. _sde_crtc_retire_event(fevent->connector, fevent->ts,
  2086. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2087. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2088. if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)
  2089. SDE_ERROR("crtc%d ts:%lld received panel dead event\n",
  2090. crtc->base.id, ktime_to_ns(fevent->ts));
  2091. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  2092. list_add_tail(&fevent->list, &sde_crtc->frame_event_list);
  2093. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  2094. SDE_ATRACE_END("crtc_frame_event");
  2095. }
  2096. void sde_crtc_complete_commit(struct drm_crtc *crtc,
  2097. struct drm_crtc_state *old_state)
  2098. {
  2099. struct sde_crtc *sde_crtc;
  2100. if (!crtc || !crtc->state) {
  2101. SDE_ERROR("invalid crtc\n");
  2102. return;
  2103. }
  2104. sde_crtc = to_sde_crtc(crtc);
  2105. SDE_EVT32_VERBOSE(DRMID(crtc));
  2106. sde_core_perf_crtc_update(crtc, 0, false);
  2107. }
  2108. /**
  2109. * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout
  2110. * @cstate: Pointer to sde crtc state
  2111. */
  2112. static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate)
  2113. {
  2114. if (!cstate) {
  2115. SDE_ERROR("invalid cstate\n");
  2116. return;
  2117. }
  2118. cstate->input_fence_timeout_ns =
  2119. sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT);
  2120. cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
  2121. }
  2122. /**
  2123. * _sde_crtc_clear_dim_layers_v1 - clear all dim layer settings
  2124. * @cstate: Pointer to sde crtc state
  2125. */
  2126. static void _sde_crtc_clear_dim_layers_v1(struct sde_crtc_state *cstate)
  2127. {
  2128. u32 i;
  2129. if (!cstate)
  2130. return;
  2131. for (i = 0; i < cstate->num_dim_layers; i++)
  2132. memset(&cstate->dim_layer[i], 0, sizeof(cstate->dim_layer[i]));
  2133. cstate->num_dim_layers = 0;
  2134. }
  2135. /**
  2136. * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
  2137. * @cstate: Pointer to sde crtc state
  2138. * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct
  2139. */
  2140. static void _sde_crtc_set_dim_layer_v1(struct drm_crtc *crtc,
  2141. struct sde_crtc_state *cstate, void __user *usr_ptr)
  2142. {
  2143. struct sde_drm_dim_layer_v1 dim_layer_v1;
  2144. struct sde_drm_dim_layer_cfg *user_cfg;
  2145. struct sde_hw_dim_layer *dim_layer;
  2146. u32 count, i;
  2147. struct sde_kms *kms;
  2148. if (!crtc || !cstate) {
  2149. SDE_ERROR("invalid crtc or cstate\n");
  2150. return;
  2151. }
  2152. dim_layer = cstate->dim_layer;
  2153. if (!usr_ptr) {
  2154. /* usr_ptr is null when setting the default property value */
  2155. _sde_crtc_clear_dim_layers_v1(cstate);
  2156. SDE_DEBUG("dim_layer data removed\n");
  2157. goto clear;
  2158. }
  2159. kms = _sde_crtc_get_kms(crtc);
  2160. if (!kms || !kms->catalog) {
  2161. SDE_ERROR("invalid kms\n");
  2162. return;
  2163. }
  2164. if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) {
  2165. SDE_ERROR("failed to copy dim_layer data\n");
  2166. return;
  2167. }
  2168. count = dim_layer_v1.num_layers;
  2169. if (count > SDE_MAX_DIM_LAYERS) {
  2170. SDE_ERROR("invalid number of dim_layers:%d", count);
  2171. return;
  2172. }
  2173. /* populate from user space */
  2174. cstate->num_dim_layers = count;
  2175. for (i = 0; i < count; i++) {
  2176. user_cfg = &dim_layer_v1.layer_cfg[i];
  2177. dim_layer[i].flags = user_cfg->flags;
  2178. dim_layer[i].stage = (kms->catalog->has_base_layer) ?
  2179. user_cfg->stage : user_cfg->stage +
  2180. SDE_STAGE_0;
  2181. dim_layer[i].rect.x = user_cfg->rect.x1;
  2182. dim_layer[i].rect.y = user_cfg->rect.y1;
  2183. dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1;
  2184. dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1;
  2185. dim_layer[i].color_fill = (struct sde_mdss_color) {
  2186. user_cfg->color_fill.color_0,
  2187. user_cfg->color_fill.color_1,
  2188. user_cfg->color_fill.color_2,
  2189. user_cfg->color_fill.color_3,
  2190. };
  2191. SDE_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n",
  2192. i, dim_layer[i].flags, dim_layer[i].stage);
  2193. SDE_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n",
  2194. dim_layer[i].rect.x, dim_layer[i].rect.y,
  2195. dim_layer[i].rect.w, dim_layer[i].rect.h,
  2196. dim_layer[i].color_fill.color_0,
  2197. dim_layer[i].color_fill.color_1,
  2198. dim_layer[i].color_fill.color_2,
  2199. dim_layer[i].color_fill.color_3);
  2200. }
  2201. clear:
  2202. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  2203. }
  2204. /**
  2205. * _sde_crtc_set_dest_scaler - copy dest scaler settings from userspace
  2206. * @sde_crtc : Pointer to sde crtc
  2207. * @cstate : Pointer to sde crtc state
  2208. * @usr_ptr: User ptr for sde_drm_dest_scaler_data struct
  2209. */
  2210. static int _sde_crtc_set_dest_scaler(struct sde_crtc *sde_crtc,
  2211. struct sde_crtc_state *cstate,
  2212. void __user *usr_ptr)
  2213. {
  2214. struct sde_drm_dest_scaler_data ds_data;
  2215. struct sde_drm_dest_scaler_cfg *ds_cfg_usr;
  2216. struct sde_drm_scaler_v2 scaler_v2;
  2217. void __user *scaler_v2_usr;
  2218. int i, count;
  2219. if (!sde_crtc || !cstate) {
  2220. SDE_ERROR("invalid sde_crtc/state\n");
  2221. return -EINVAL;
  2222. }
  2223. SDE_DEBUG("crtc %s\n", sde_crtc->name);
  2224. if (!usr_ptr) {
  2225. SDE_DEBUG("ds data removed\n");
  2226. return 0;
  2227. }
  2228. if (copy_from_user(&ds_data, usr_ptr, sizeof(ds_data))) {
  2229. SDE_ERROR("%s:failed to copy dest scaler data from user\n",
  2230. sde_crtc->name);
  2231. return -EINVAL;
  2232. }
  2233. count = ds_data.num_dest_scaler;
  2234. if (!count) {
  2235. SDE_DEBUG("no ds data available\n");
  2236. return 0;
  2237. }
  2238. if (count > SDE_MAX_DS_COUNT) {
  2239. SDE_ERROR("%s: invalid config: num_ds(%d) max(%d)\n",
  2240. sde_crtc->name, count, SDE_MAX_DS_COUNT);
  2241. SDE_EVT32(DRMID(&sde_crtc->base), count, SDE_EVTLOG_ERROR);
  2242. return -EINVAL;
  2243. }
  2244. /* Populate from user space */
  2245. for (i = 0; i < count; i++) {
  2246. ds_cfg_usr = &ds_data.ds_cfg[i];
  2247. cstate->ds_cfg[i].idx = ds_cfg_usr->index;
  2248. cstate->ds_cfg[i].flags = ds_cfg_usr->flags;
  2249. cstate->ds_cfg[i].lm_width = ds_cfg_usr->lm_width;
  2250. cstate->ds_cfg[i].lm_height = ds_cfg_usr->lm_height;
  2251. memset(&scaler_v2, 0, sizeof(scaler_v2));
  2252. if (ds_cfg_usr->scaler_cfg) {
  2253. scaler_v2_usr =
  2254. (void __user *)((uintptr_t)ds_cfg_usr->scaler_cfg);
  2255. if (copy_from_user(&scaler_v2, scaler_v2_usr,
  2256. sizeof(scaler_v2))) {
  2257. SDE_ERROR("%s:scaler: copy from user failed\n",
  2258. sde_crtc->name);
  2259. return -EINVAL;
  2260. }
  2261. }
  2262. sde_set_scaler_v2(&cstate->ds_cfg[i].scl3_cfg, &scaler_v2);
  2263. SDE_DEBUG("en(%d)dir(%d)de(%d) src(%dx%d) dst(%dx%d)\n",
  2264. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2265. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2266. scaler_v2.dst_width, scaler_v2.dst_height);
  2267. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base),
  2268. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2269. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2270. scaler_v2.dst_width, scaler_v2.dst_height);
  2271. SDE_DEBUG("ds cfg[%d]-ndx(%d) flags(%d) lm(%dx%d)\n",
  2272. i, ds_cfg_usr->index, ds_cfg_usr->flags,
  2273. ds_cfg_usr->lm_width, ds_cfg_usr->lm_height);
  2274. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), i, ds_cfg_usr->index,
  2275. ds_cfg_usr->flags, ds_cfg_usr->lm_width,
  2276. ds_cfg_usr->lm_height);
  2277. }
  2278. cstate->num_ds = count;
  2279. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2280. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), count);
  2281. return 0;
  2282. }
  2283. static int _sde_crtc_check_dest_scaler_lm(struct drm_crtc *crtc,
  2284. struct drm_display_mode *mode, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2285. u32 prev_lm_width, u32 prev_lm_height)
  2286. {
  2287. if (cfg->lm_width > hdisplay || cfg->lm_height > mode->vdisplay
  2288. || !cfg->lm_width || !cfg->lm_height) {
  2289. SDE_ERROR("crtc%d: lm size[%d,%d] display [%d,%d]\n",
  2290. crtc->base.id, cfg->lm_width, cfg->lm_height,
  2291. hdisplay, mode->vdisplay);
  2292. SDE_EVT32(DRMID(crtc), cfg->lm_width, cfg->lm_height,
  2293. hdisplay, mode->vdisplay, SDE_EVTLOG_ERROR);
  2294. return -E2BIG;
  2295. }
  2296. if (!prev_lm_width && !prev_lm_height) {
  2297. prev_lm_width = cfg->lm_width;
  2298. prev_lm_height = cfg->lm_height;
  2299. } else {
  2300. if (cfg->lm_width != prev_lm_width ||
  2301. cfg->lm_height != prev_lm_height) {
  2302. SDE_ERROR("crtc%d:lm left[%d,%d]right[%d %d]\n",
  2303. crtc->base.id, cfg->lm_width,
  2304. cfg->lm_height, prev_lm_width,
  2305. prev_lm_height);
  2306. SDE_EVT32(DRMID(crtc), cfg->lm_width,
  2307. cfg->lm_height, prev_lm_width,
  2308. prev_lm_height, SDE_EVTLOG_ERROR);
  2309. return -EINVAL;
  2310. }
  2311. }
  2312. return 0;
  2313. }
  2314. static int _sde_crtc_check_dest_scaler_cfg(struct drm_crtc *crtc,
  2315. struct sde_crtc *sde_crtc, struct drm_display_mode *mode,
  2316. struct sde_hw_ds *hw_ds, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2317. u32 max_in_width, u32 max_out_width)
  2318. {
  2319. if (cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE ||
  2320. cfg->flags & SDE_DRM_DESTSCALER_ENHANCER_UPDATE) {
  2321. /**
  2322. * Scaler src and dst width shouldn't exceed the maximum
  2323. * width limitation. Also, if there is no partial update
  2324. * dst width and height must match display resolution.
  2325. */
  2326. if (cfg->scl3_cfg.src_width[0] > max_in_width ||
  2327. cfg->scl3_cfg.dst_width > max_out_width ||
  2328. !cfg->scl3_cfg.src_width[0] ||
  2329. !cfg->scl3_cfg.dst_width ||
  2330. (!(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE)
  2331. && (cfg->scl3_cfg.dst_width != hdisplay ||
  2332. cfg->scl3_cfg.dst_height != mode->vdisplay))) {
  2333. SDE_ERROR("crtc%d: ", crtc->base.id);
  2334. SDE_ERROR("src_w(%d) dst(%dx%d) display(%dx%d)",
  2335. cfg->scl3_cfg.src_width[0],
  2336. cfg->scl3_cfg.dst_width,
  2337. cfg->scl3_cfg.dst_height,
  2338. hdisplay, mode->vdisplay);
  2339. SDE_ERROR("num_mixers(%d) flags(%d) ds-%d:\n",
  2340. sde_crtc->num_mixers, cfg->flags,
  2341. hw_ds->idx - DS_0);
  2342. SDE_ERROR("scale_en = %d, DE_en =%d\n",
  2343. cfg->scl3_cfg.enable,
  2344. cfg->scl3_cfg.de.enable);
  2345. SDE_EVT32(DRMID(crtc), cfg->scl3_cfg.enable,
  2346. cfg->scl3_cfg.de.enable, cfg->flags,
  2347. max_in_width, max_out_width,
  2348. cfg->scl3_cfg.src_width[0],
  2349. cfg->scl3_cfg.dst_width,
  2350. cfg->scl3_cfg.dst_height, hdisplay,
  2351. mode->vdisplay, sde_crtc->num_mixers,
  2352. SDE_EVTLOG_ERROR);
  2353. cfg->flags &=
  2354. ~SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2355. cfg->flags &=
  2356. ~SDE_DRM_DESTSCALER_ENHANCER_UPDATE;
  2357. return -EINVAL;
  2358. }
  2359. }
  2360. return 0;
  2361. }
  2362. static int _sde_crtc_check_dest_scaler_validate_ds(struct drm_crtc *crtc,
  2363. struct sde_crtc *sde_crtc, struct sde_crtc_state *cstate,
  2364. struct drm_display_mode *mode, struct sde_hw_ds *hw_ds,
  2365. struct sde_hw_ds_cfg *cfg, u32 hdisplay, u32 *num_ds_enable,
  2366. u32 prev_lm_width, u32 prev_lm_height, u32 max_in_width,
  2367. u32 max_out_width)
  2368. {
  2369. int i, ret;
  2370. u32 lm_idx;
  2371. for (i = 0; i < cstate->num_ds; i++) {
  2372. cfg = &cstate->ds_cfg[i];
  2373. lm_idx = cfg->idx;
  2374. /**
  2375. * Validate against topology
  2376. * No of dest scalers should match the num of mixers
  2377. * unless it is partial update left only/right only use case
  2378. */
  2379. if (lm_idx >= sde_crtc->num_mixers || (i != lm_idx &&
  2380. !(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2381. SDE_ERROR("crtc%d: ds_cfg id(%d):idx(%d), flags(%d)\n",
  2382. crtc->base.id, i, lm_idx, cfg->flags);
  2383. SDE_EVT32(DRMID(crtc), i, lm_idx, cfg->flags,
  2384. SDE_EVTLOG_ERROR);
  2385. return -EINVAL;
  2386. }
  2387. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  2388. if (!max_in_width && !max_out_width) {
  2389. max_in_width = hw_ds->scl->top->maxinputwidth;
  2390. max_out_width = hw_ds->scl->top->maxoutputwidth;
  2391. if (cstate->num_ds == CRTC_DUAL_MIXERS_ONLY)
  2392. max_in_width -= SDE_DS_OVERFETCH_SIZE;
  2393. SDE_DEBUG("max DS width [%d,%d] for num_ds = %d\n",
  2394. max_in_width, max_out_width, cstate->num_ds);
  2395. }
  2396. /* Check LM width and height */
  2397. ret = _sde_crtc_check_dest_scaler_lm(crtc, mode, cfg, hdisplay,
  2398. prev_lm_width, prev_lm_height);
  2399. if (ret)
  2400. return ret;
  2401. /* Check scaler data */
  2402. ret = _sde_crtc_check_dest_scaler_cfg(crtc, sde_crtc, mode,
  2403. hw_ds, cfg, hdisplay,
  2404. max_in_width, max_out_width);
  2405. if (ret)
  2406. return ret;
  2407. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  2408. (*num_ds_enable)++;
  2409. SDE_DEBUG("ds[%d]: flags[0x%X]\n",
  2410. hw_ds->idx - DS_0, cfg->flags);
  2411. SDE_EVT32_VERBOSE(DRMID(crtc), hw_ds->idx - DS_0, cfg->flags);
  2412. }
  2413. return 0;
  2414. }
  2415. static void _sde_crtc_check_dest_scaler_data_disable(struct drm_crtc *crtc,
  2416. struct sde_crtc_state *cstate, struct sde_hw_ds_cfg *cfg,
  2417. u32 num_ds_enable)
  2418. {
  2419. int i;
  2420. SDE_DEBUG("dest scaler status : %d -> %d\n",
  2421. cstate->num_ds_enabled, num_ds_enable);
  2422. SDE_EVT32_VERBOSE(DRMID(crtc), cstate->num_ds_enabled, num_ds_enable,
  2423. cstate->num_ds, cstate->dirty[0]);
  2424. if (cstate->num_ds_enabled != num_ds_enable) {
  2425. /* Disabling destination scaler */
  2426. if (!num_ds_enable) {
  2427. for (i = 0; i < cstate->num_ds; i++) {
  2428. cfg = &cstate->ds_cfg[i];
  2429. cfg->idx = i;
  2430. /* Update scaler settings in disable case */
  2431. cfg->flags = SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2432. cfg->scl3_cfg.enable = 0;
  2433. cfg->scl3_cfg.de.enable = 0;
  2434. }
  2435. }
  2436. cstate->num_ds_enabled = num_ds_enable;
  2437. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2438. } else {
  2439. if (!cstate->num_ds_enabled)
  2440. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2441. }
  2442. }
  2443. /**
  2444. * _sde_crtc_check_dest_scaler_data - validate the dest scaler data
  2445. * @crtc : Pointer to drm crtc
  2446. * @state : Pointer to drm crtc state
  2447. */
  2448. static int _sde_crtc_check_dest_scaler_data(struct drm_crtc *crtc,
  2449. struct drm_crtc_state *state)
  2450. {
  2451. struct sde_crtc *sde_crtc;
  2452. struct sde_crtc_state *cstate;
  2453. struct drm_display_mode *mode;
  2454. struct sde_kms *kms;
  2455. struct sde_hw_ds *hw_ds = NULL;
  2456. struct sde_hw_ds_cfg *cfg = NULL;
  2457. u32 ret = 0;
  2458. u32 num_ds_enable = 0, hdisplay = 0;
  2459. u32 max_in_width = 0, max_out_width = 0;
  2460. u32 prev_lm_width = 0, prev_lm_height = 0;
  2461. if (!crtc || !state)
  2462. return -EINVAL;
  2463. sde_crtc = to_sde_crtc(crtc);
  2464. cstate = to_sde_crtc_state(state);
  2465. kms = _sde_crtc_get_kms(crtc);
  2466. mode = &state->adjusted_mode;
  2467. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2468. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  2469. SDE_DEBUG("dest scaler property not set, skip validation\n");
  2470. return 0;
  2471. }
  2472. if (!kms || !kms->catalog) {
  2473. SDE_ERROR("crtc%d: invalid parameters\n", crtc->base.id);
  2474. return -EINVAL;
  2475. }
  2476. if (!kms->catalog->mdp[0].has_dest_scaler) {
  2477. SDE_DEBUG("dest scaler feature not supported\n");
  2478. return 0;
  2479. }
  2480. if (!sde_crtc->num_mixers) {
  2481. SDE_DEBUG("mixers not allocated\n");
  2482. return 0;
  2483. }
  2484. ret = _sde_validate_hw_resources(sde_crtc);
  2485. if (ret)
  2486. goto err;
  2487. /**
  2488. * No of dest scalers shouldn't exceed hw ds block count and
  2489. * also, match the num of mixers unless it is partial update
  2490. * left only/right only use case - currently PU + DS is not supported
  2491. */
  2492. if (cstate->num_ds > kms->catalog->ds_count ||
  2493. ((cstate->num_ds != sde_crtc->num_mixers) &&
  2494. !(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2495. SDE_ERROR("crtc%d: num_ds(%d), hw_ds_cnt(%d) flags(%d)\n",
  2496. crtc->base.id, cstate->num_ds, kms->catalog->ds_count,
  2497. cstate->ds_cfg[0].flags);
  2498. ret = -EINVAL;
  2499. goto err;
  2500. }
  2501. /**
  2502. * Check if DS needs to be enabled or disabled
  2503. * In case of enable, validate the data
  2504. */
  2505. if (!(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_ENABLE)) {
  2506. SDE_DEBUG("disable dest scaler, num(%d) flags(%d)\n",
  2507. cstate->num_ds, cstate->ds_cfg[0].flags);
  2508. goto disable;
  2509. }
  2510. /* Display resolution */
  2511. hdisplay = mode->hdisplay/sde_crtc->num_mixers;
  2512. /* Validate the DS data */
  2513. ret = _sde_crtc_check_dest_scaler_validate_ds(crtc, sde_crtc, cstate,
  2514. mode, hw_ds, cfg, hdisplay, &num_ds_enable,
  2515. prev_lm_width, prev_lm_height,
  2516. max_in_width, max_out_width);
  2517. if (ret)
  2518. goto err;
  2519. disable:
  2520. _sde_crtc_check_dest_scaler_data_disable(crtc, cstate, cfg,
  2521. num_ds_enable);
  2522. return 0;
  2523. err:
  2524. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2525. return ret;
  2526. }
  2527. /**
  2528. * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences
  2529. * @crtc: Pointer to CRTC object
  2530. */
  2531. static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc)
  2532. {
  2533. struct drm_plane *plane = NULL;
  2534. uint32_t wait_ms = 1;
  2535. ktime_t kt_end, kt_wait;
  2536. int rc = 0;
  2537. SDE_DEBUG("\n");
  2538. if (!crtc || !crtc->state) {
  2539. SDE_ERROR("invalid crtc/state %pK\n", crtc);
  2540. return;
  2541. }
  2542. /* use monotonic timer to limit total fence wait time */
  2543. kt_end = ktime_add_ns(ktime_get(),
  2544. to_sde_crtc_state(crtc->state)->input_fence_timeout_ns);
  2545. /*
  2546. * Wait for fences sequentially, as all of them need to be signalled
  2547. * before we can proceed.
  2548. *
  2549. * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
  2550. * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so
  2551. * that each plane can check its fence status and react appropriately
  2552. * if its fence has timed out. Call input fence wait multiple times if
  2553. * fence wait is interrupted due to interrupt call.
  2554. */
  2555. SDE_ATRACE_BEGIN("plane_wait_input_fence");
  2556. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2557. do {
  2558. kt_wait = ktime_sub(kt_end, ktime_get());
  2559. if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
  2560. wait_ms = ktime_to_ms(kt_wait);
  2561. else
  2562. wait_ms = 0;
  2563. rc = sde_plane_wait_input_fence(plane, wait_ms);
  2564. } while (wait_ms && rc == -ERESTARTSYS);
  2565. }
  2566. SDE_ATRACE_END("plane_wait_input_fence");
  2567. }
  2568. static void _sde_crtc_setup_mixer_for_encoder(
  2569. struct drm_crtc *crtc,
  2570. struct drm_encoder *enc)
  2571. {
  2572. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2573. struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
  2574. struct sde_rm *rm = &sde_kms->rm;
  2575. struct sde_crtc_mixer *mixer;
  2576. struct sde_hw_ctl *last_valid_ctl = NULL;
  2577. int i;
  2578. struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter, ds_iter;
  2579. sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM);
  2580. sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL);
  2581. sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP);
  2582. sde_rm_init_hw_iter(&ds_iter, enc->base.id, SDE_HW_BLK_DS);
  2583. /* Set up all the mixers and ctls reserved by this encoder */
  2584. for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
  2585. mixer = &sde_crtc->mixers[i];
  2586. if (!sde_rm_get_hw(rm, &lm_iter))
  2587. break;
  2588. mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  2589. /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
  2590. if (!sde_rm_get_hw(rm, &ctl_iter)) {
  2591. SDE_DEBUG("no ctl assigned to lm %d, using previous\n",
  2592. mixer->hw_lm->idx - LM_0);
  2593. mixer->hw_ctl = last_valid_ctl;
  2594. } else {
  2595. mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw;
  2596. last_valid_ctl = mixer->hw_ctl;
  2597. sde_crtc->num_ctls++;
  2598. }
  2599. /* Shouldn't happen, mixers are always >= ctls */
  2600. if (!mixer->hw_ctl) {
  2601. SDE_ERROR("no valid ctls found for lm %d\n",
  2602. mixer->hw_lm->idx - LM_0);
  2603. return;
  2604. }
  2605. /* Dspp may be null */
  2606. (void) sde_rm_get_hw(rm, &dspp_iter);
  2607. mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw;
  2608. /* DS may be null */
  2609. (void) sde_rm_get_hw(rm, &ds_iter);
  2610. mixer->hw_ds = (struct sde_hw_ds *)ds_iter.hw;
  2611. mixer->encoder = enc;
  2612. sde_crtc->num_mixers++;
  2613. SDE_DEBUG("setup mixer %d: lm %d\n",
  2614. i, mixer->hw_lm->idx - LM_0);
  2615. SDE_DEBUG("setup mixer %d: ctl %d\n",
  2616. i, mixer->hw_ctl->idx - CTL_0);
  2617. if (mixer->hw_ds)
  2618. SDE_DEBUG("setup mixer %d: ds %d\n",
  2619. i, mixer->hw_ds->idx - DS_0);
  2620. }
  2621. }
  2622. static void _sde_crtc_setup_mixers(struct drm_crtc *crtc)
  2623. {
  2624. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2625. struct drm_encoder *enc;
  2626. sde_crtc->num_ctls = 0;
  2627. sde_crtc->num_mixers = 0;
  2628. sde_crtc->mixers_swapped = false;
  2629. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  2630. mutex_lock(&sde_crtc->crtc_lock);
  2631. /* Check for mixers on all encoders attached to this crtc */
  2632. list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
  2633. if (enc->crtc != crtc)
  2634. continue;
  2635. /* avoid overwriting mixers info from a copy encoder */
  2636. if (sde_encoder_in_clone_mode(enc))
  2637. continue;
  2638. _sde_crtc_setup_mixer_for_encoder(crtc, enc);
  2639. }
  2640. mutex_unlock(&sde_crtc->crtc_lock);
  2641. _sde_crtc_check_dest_scaler_data(crtc, crtc->state);
  2642. }
  2643. static void _sde_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
  2644. {
  2645. int i;
  2646. struct sde_crtc_state *cstate;
  2647. cstate = to_sde_crtc_state(state);
  2648. cstate->is_ppsplit = false;
  2649. for (i = 0; i < cstate->num_connectors; i++) {
  2650. struct drm_connector *conn = cstate->connectors[i];
  2651. if (sde_connector_get_topology_name(conn) ==
  2652. SDE_RM_TOPOLOGY_PPSPLIT)
  2653. cstate->is_ppsplit = true;
  2654. }
  2655. }
  2656. static void _sde_crtc_setup_lm_bounds(struct drm_crtc *crtc,
  2657. struct drm_crtc_state *state)
  2658. {
  2659. struct sde_crtc *sde_crtc;
  2660. struct sde_crtc_state *cstate;
  2661. struct drm_display_mode *adj_mode;
  2662. u32 crtc_split_width;
  2663. int i;
  2664. if (!crtc || !state) {
  2665. SDE_ERROR("invalid args\n");
  2666. return;
  2667. }
  2668. sde_crtc = to_sde_crtc(crtc);
  2669. cstate = to_sde_crtc_state(state);
  2670. adj_mode = &state->adjusted_mode;
  2671. crtc_split_width = sde_crtc_get_mixer_width(sde_crtc, cstate, adj_mode);
  2672. for (i = 0; i < sde_crtc->num_mixers; i++) {
  2673. cstate->lm_bounds[i].x = crtc_split_width * i;
  2674. cstate->lm_bounds[i].y = 0;
  2675. cstate->lm_bounds[i].w = crtc_split_width;
  2676. cstate->lm_bounds[i].h =
  2677. sde_crtc_get_mixer_height(sde_crtc, cstate, adj_mode);
  2678. memcpy(&cstate->lm_roi[i], &cstate->lm_bounds[i],
  2679. sizeof(cstate->lm_roi[i]));
  2680. SDE_EVT32_VERBOSE(DRMID(crtc), i,
  2681. cstate->lm_bounds[i].x, cstate->lm_bounds[i].y,
  2682. cstate->lm_bounds[i].w, cstate->lm_bounds[i].h);
  2683. SDE_DEBUG("%s: lm%d bnd&roi (%d,%d,%d,%d)\n", sde_crtc->name, i,
  2684. cstate->lm_roi[i].x, cstate->lm_roi[i].y,
  2685. cstate->lm_roi[i].w, cstate->lm_roi[i].h);
  2686. }
  2687. drm_mode_debug_printmodeline(adj_mode);
  2688. }
  2689. static void _sde_crtc_clear_all_blend_stages(struct sde_crtc *sde_crtc)
  2690. {
  2691. struct sde_crtc_mixer mixer;
  2692. /*
  2693. * Use mixer[0] to get hw_ctl which will use ops to clear
  2694. * all blendstages. Clear all blendstages will iterate through
  2695. * all mixers.
  2696. */
  2697. if (sde_crtc->num_mixers) {
  2698. mixer = sde_crtc->mixers[0];
  2699. if (mixer.hw_ctl && mixer.hw_ctl->ops.clear_all_blendstages)
  2700. mixer.hw_ctl->ops.clear_all_blendstages(mixer.hw_ctl);
  2701. if (mixer.hw_ctl && mixer.hw_ctl->ops.set_active_pipes)
  2702. mixer.hw_ctl->ops.set_active_pipes(mixer.hw_ctl, NULL);
  2703. }
  2704. }
  2705. static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
  2706. struct drm_crtc_state *old_state)
  2707. {
  2708. struct sde_crtc *sde_crtc;
  2709. struct drm_encoder *encoder;
  2710. struct drm_device *dev;
  2711. struct sde_kms *sde_kms;
  2712. struct drm_plane *plane;
  2713. struct sde_splash_display *splash_display;
  2714. bool cont_splash_enabled = false, apply_cp_prop = false;
  2715. size_t i;
  2716. if (!crtc) {
  2717. SDE_ERROR("invalid crtc\n");
  2718. return;
  2719. }
  2720. if (!crtc->state->enable) {
  2721. SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
  2722. crtc->base.id, crtc->state->enable);
  2723. return;
  2724. }
  2725. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2726. SDE_ERROR("power resource is not enabled\n");
  2727. return;
  2728. }
  2729. sde_kms = _sde_crtc_get_kms(crtc);
  2730. if (!sde_kms)
  2731. return;
  2732. SDE_ATRACE_BEGIN("crtc_atomic_begin");
  2733. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2734. sde_crtc = to_sde_crtc(crtc);
  2735. dev = crtc->dev;
  2736. if (!sde_crtc->num_mixers) {
  2737. _sde_crtc_setup_mixers(crtc);
  2738. _sde_crtc_setup_is_ppsplit(crtc->state);
  2739. _sde_crtc_setup_lm_bounds(crtc, crtc->state);
  2740. _sde_crtc_clear_all_blend_stages(sde_crtc);
  2741. }
  2742. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  2743. if (encoder->crtc != crtc)
  2744. continue;
  2745. /* encoder will trigger pending mask now */
  2746. sde_encoder_trigger_kickoff_pending(encoder);
  2747. }
  2748. /* update performance setting */
  2749. sde_core_perf_crtc_update(crtc, 1, false);
  2750. /*
  2751. * If no mixers have been allocated in sde_crtc_atomic_check(),
  2752. * it means we are trying to flush a CRTC whose state is disabled:
  2753. * nothing else needs to be done.
  2754. */
  2755. if (unlikely(!sde_crtc->num_mixers))
  2756. goto end;
  2757. _sde_crtc_blend_setup(crtc, old_state, true);
  2758. _sde_crtc_dest_scaler_setup(crtc);
  2759. if (old_state->mode_changed) {
  2760. sde_core_perf_crtc_update_uidle(crtc, true);
  2761. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2762. if (plane->state && plane->state->fb)
  2763. _sde_plane_set_qos_lut(plane, crtc,
  2764. plane->state->fb);
  2765. }
  2766. }
  2767. /*
  2768. * Since CP properties use AXI buffer to program the
  2769. * HW, check if context bank is in attached state,
  2770. * apply color processing properties only if
  2771. * smmu state is attached,
  2772. */
  2773. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2774. splash_display = &sde_kms->splash_data.splash_display[i];
  2775. if (splash_display->cont_splash_enabled &&
  2776. splash_display->encoder &&
  2777. crtc == splash_display->encoder->crtc)
  2778. cont_splash_enabled = true;
  2779. }
  2780. apply_cp_prop = sde_kms->catalog->trusted_vm_env ?
  2781. true : sde_crtc->enabled;
  2782. if (sde_kms_is_cp_operation_allowed(sde_kms) &&
  2783. (cont_splash_enabled || apply_cp_prop))
  2784. sde_cp_crtc_apply_properties(crtc);
  2785. /*
  2786. * PP_DONE irq is only used by command mode for now.
  2787. * It is better to request pending before FLUSH and START trigger
  2788. * to make sure no pp_done irq missed.
  2789. * This is safe because no pp_done will happen before SW trigger
  2790. * in command mode.
  2791. */
  2792. end:
  2793. SDE_ATRACE_END("crtc_atomic_begin");
  2794. }
  2795. static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
  2796. struct drm_crtc_state *old_crtc_state)
  2797. {
  2798. struct drm_encoder *encoder;
  2799. struct sde_crtc *sde_crtc;
  2800. struct drm_device *dev;
  2801. struct drm_plane *plane;
  2802. struct msm_drm_private *priv;
  2803. struct sde_crtc_state *cstate;
  2804. struct sde_kms *sde_kms;
  2805. int i;
  2806. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  2807. SDE_ERROR("invalid crtc\n");
  2808. return;
  2809. }
  2810. if (!crtc->state->enable) {
  2811. SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
  2812. crtc->base.id, crtc->state->enable);
  2813. return;
  2814. }
  2815. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2816. SDE_ERROR("power resource is not enabled\n");
  2817. return;
  2818. }
  2819. sde_kms = _sde_crtc_get_kms(crtc);
  2820. if (!sde_kms) {
  2821. SDE_ERROR("invalid kms\n");
  2822. return;
  2823. }
  2824. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2825. sde_crtc = to_sde_crtc(crtc);
  2826. cstate = to_sde_crtc_state(crtc->state);
  2827. dev = crtc->dev;
  2828. priv = dev->dev_private;
  2829. if ((sde_crtc->cache_state == CACHE_STATE_PRE_CACHE) &&
  2830. sde_crtc_get_property(cstate, CRTC_PROP_CACHE_STATE))
  2831. sde_crtc_static_img_control(crtc, CACHE_STATE_FRAME_WRITE,
  2832. false);
  2833. else
  2834. sde_crtc_static_img_control(crtc, CACHE_STATE_NORMAL, false);
  2835. /*
  2836. * If no mixers has been allocated in sde_crtc_atomic_check(),
  2837. * it means we are trying to flush a CRTC whose state is disabled:
  2838. * nothing else needs to be done.
  2839. */
  2840. if (unlikely(!sde_crtc->num_mixers))
  2841. return;
  2842. SDE_ATRACE_BEGIN("sde_crtc_atomic_flush");
  2843. /*
  2844. * For planes without commit update, drm framework will not add
  2845. * those planes to current state since hardware update is not
  2846. * required. However, if those planes were power collapsed since
  2847. * last commit cycle, driver has to restore the hardware state
  2848. * of those planes explicitly here prior to plane flush.
  2849. * Also use this iteration to see if any plane requires cache,
  2850. * so during the perf update driver can activate/deactivate
  2851. * the cache accordingly.
  2852. */
  2853. for (i = 0; i < SDE_SYS_CACHE_MAX; i++)
  2854. sde_crtc->new_perf.llcc_active[i] = false;
  2855. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2856. sde_plane_restore(plane);
  2857. for (i = 0; i < SDE_SYS_CACHE_MAX; i++) {
  2858. if (sde_plane_is_cache_required(plane, i))
  2859. sde_crtc->new_perf.llcc_active[i] = true;
  2860. }
  2861. }
  2862. sde_core_perf_crtc_update_llcc(crtc);
  2863. /* wait for acquire fences before anything else is done */
  2864. _sde_crtc_wait_for_fences(crtc);
  2865. if (!cstate->rsc_update) {
  2866. drm_for_each_encoder_mask(encoder, dev,
  2867. crtc->state->encoder_mask) {
  2868. cstate->rsc_client =
  2869. sde_encoder_get_rsc_client(encoder);
  2870. }
  2871. cstate->rsc_update = true;
  2872. }
  2873. /*
  2874. * Final plane updates: Give each plane a chance to complete all
  2875. * required writes/flushing before crtc's "flush
  2876. * everything" call below.
  2877. */
  2878. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2879. if (sde_kms->smmu_state.transition_error)
  2880. sde_plane_set_error(plane, true);
  2881. sde_plane_flush(plane);
  2882. }
  2883. /* Kickoff will be scheduled by outer layer */
  2884. SDE_ATRACE_END("sde_crtc_atomic_flush");
  2885. }
  2886. /**
  2887. * sde_crtc_destroy_state - state destroy hook
  2888. * @crtc: drm CRTC
  2889. * @state: CRTC state object to release
  2890. */
  2891. static void sde_crtc_destroy_state(struct drm_crtc *crtc,
  2892. struct drm_crtc_state *state)
  2893. {
  2894. struct sde_crtc *sde_crtc;
  2895. struct sde_crtc_state *cstate;
  2896. struct drm_encoder *enc;
  2897. struct sde_kms *sde_kms;
  2898. if (!crtc || !state) {
  2899. SDE_ERROR("invalid argument(s)\n");
  2900. return;
  2901. }
  2902. sde_crtc = to_sde_crtc(crtc);
  2903. cstate = to_sde_crtc_state(state);
  2904. sde_kms = _sde_crtc_get_kms(crtc);
  2905. if (!sde_kms) {
  2906. SDE_ERROR("invalid sde_kms\n");
  2907. return;
  2908. }
  2909. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2910. drm_for_each_encoder_mask(enc, crtc->dev, state->encoder_mask)
  2911. sde_rm_release(&sde_kms->rm, enc, true);
  2912. __drm_atomic_helper_crtc_destroy_state(state);
  2913. /* destroy value helper */
  2914. msm_property_destroy_state(&sde_crtc->property_info, cstate,
  2915. &cstate->property_state);
  2916. }
  2917. static int _sde_crtc_flush_event_thread(struct drm_crtc *crtc)
  2918. {
  2919. struct sde_crtc *sde_crtc;
  2920. int i;
  2921. if (!crtc) {
  2922. SDE_ERROR("invalid argument\n");
  2923. return -EINVAL;
  2924. }
  2925. sde_crtc = to_sde_crtc(crtc);
  2926. if (!atomic_read(&sde_crtc->frame_pending)) {
  2927. SDE_DEBUG("no frames pending\n");
  2928. return 0;
  2929. }
  2930. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY);
  2931. /*
  2932. * flush all the event thread work to make sure all the
  2933. * FRAME_EVENTS from encoder are propagated to crtc
  2934. */
  2935. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  2936. if (list_empty(&sde_crtc->frame_events[i].list))
  2937. kthread_flush_work(&sde_crtc->frame_events[i].work);
  2938. }
  2939. SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  2940. return 0;
  2941. }
  2942. /**
  2943. * _sde_crtc_remove_pipe_flush - remove staged pipes from flush mask
  2944. * @crtc: Pointer to crtc structure
  2945. */
  2946. static void _sde_crtc_remove_pipe_flush(struct drm_crtc *crtc)
  2947. {
  2948. struct drm_plane *plane;
  2949. struct drm_plane_state *state;
  2950. struct sde_crtc *sde_crtc;
  2951. struct sde_crtc_mixer *mixer;
  2952. struct sde_hw_ctl *ctl;
  2953. if (!crtc)
  2954. return;
  2955. sde_crtc = to_sde_crtc(crtc);
  2956. mixer = sde_crtc->mixers;
  2957. if (!mixer)
  2958. return;
  2959. ctl = mixer->hw_ctl;
  2960. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2961. state = plane->state;
  2962. if (!state)
  2963. continue;
  2964. /* clear plane flush bitmask */
  2965. sde_plane_ctl_flush(plane, ctl, false);
  2966. }
  2967. }
  2968. static void _sde_crtc_schedule_idle_notify(struct drm_crtc *crtc,
  2969. struct drm_crtc_state *old_state)
  2970. {
  2971. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2972. struct sde_crtc_state *cstate = to_sde_crtc_state(old_state);
  2973. struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
  2974. struct msm_drm_private *priv;
  2975. struct msm_drm_thread *event_thread;
  2976. int idle_time = 0;
  2977. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  2978. return;
  2979. priv = sde_kms->dev->dev_private;
  2980. idle_time = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_TIMEOUT);
  2981. if (!idle_time ||
  2982. !sde_encoder_check_curr_mode(sde_crtc->mixers[0].encoder,
  2983. MSM_DISPLAY_VIDEO_MODE) ||
  2984. (crtc->index >= ARRAY_SIZE(priv->event_thread)))
  2985. return;
  2986. /* schedule the idle notify delayed work */
  2987. event_thread = &priv->event_thread[crtc->index];
  2988. kthread_mod_delayed_work(&event_thread->worker,
  2989. &sde_crtc->idle_notify_work, msecs_to_jiffies(idle_time));
  2990. SDE_DEBUG("schedule idle notify work in %dms\n", idle_time);
  2991. }
  2992. /**
  2993. * sde_crtc_reset_hw - attempt hardware reset on errors
  2994. * @crtc: Pointer to DRM crtc instance
  2995. * @old_state: Pointer to crtc state for previous commit
  2996. * @recovery_events: Whether or not recovery events are enabled
  2997. * Returns: Zero if current commit should still be attempted
  2998. */
  2999. int sde_crtc_reset_hw(struct drm_crtc *crtc, struct drm_crtc_state *old_state,
  3000. bool recovery_events)
  3001. {
  3002. struct drm_plane *plane_halt[MAX_PLANES];
  3003. struct drm_plane *plane;
  3004. struct drm_encoder *encoder;
  3005. struct sde_crtc *sde_crtc;
  3006. struct sde_crtc_state *cstate;
  3007. struct sde_hw_ctl *ctl;
  3008. signed int i, plane_count;
  3009. int rc;
  3010. if (!crtc || !crtc->dev || !old_state || !crtc->state)
  3011. return -EINVAL;
  3012. sde_crtc = to_sde_crtc(crtc);
  3013. cstate = to_sde_crtc_state(crtc->state);
  3014. SDE_EVT32(DRMID(crtc), recovery_events, SDE_EVTLOG_FUNC_ENTRY);
  3015. /* optionally generate a panic instead of performing a h/w reset */
  3016. SDE_DBG_CTRL("stop_ftrace", "reset_hw_panic");
  3017. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3018. ctl = sde_crtc->mixers[i].hw_ctl;
  3019. if (!ctl || !ctl->ops.reset)
  3020. continue;
  3021. rc = ctl->ops.reset(ctl);
  3022. if (rc) {
  3023. SDE_DEBUG("crtc%d: ctl%d reset failure\n",
  3024. crtc->base.id, ctl->idx - CTL_0);
  3025. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0,
  3026. SDE_EVTLOG_ERROR);
  3027. break;
  3028. }
  3029. }
  3030. /* Early out if simple ctl reset succeeded */
  3031. if (i == sde_crtc->num_ctls)
  3032. return 0;
  3033. SDE_DEBUG("crtc%d: issuing hard reset\n", DRMID(crtc));
  3034. /* force all components in the system into reset at the same time */
  3035. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3036. ctl = sde_crtc->mixers[i].hw_ctl;
  3037. if (!ctl || !ctl->ops.hard_reset)
  3038. continue;
  3039. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0);
  3040. ctl->ops.hard_reset(ctl, true);
  3041. }
  3042. plane_count = 0;
  3043. drm_atomic_crtc_state_for_each_plane(plane, old_state) {
  3044. if (plane_count >= ARRAY_SIZE(plane_halt))
  3045. break;
  3046. plane_halt[plane_count++] = plane;
  3047. sde_plane_halt_requests(plane, true);
  3048. sde_plane_set_revalidate(plane, true);
  3049. }
  3050. /* provide safe "border color only" commit configuration for later */
  3051. _sde_crtc_remove_pipe_flush(crtc);
  3052. _sde_crtc_blend_setup(crtc, old_state, false);
  3053. /* take h/w components out of reset */
  3054. for (i = plane_count - 1; i >= 0; --i)
  3055. sde_plane_halt_requests(plane_halt[i], false);
  3056. /* attempt to poll for start of frame cycle before reset release */
  3057. list_for_each_entry(encoder,
  3058. &crtc->dev->mode_config.encoder_list, head) {
  3059. if (encoder->crtc != crtc)
  3060. continue;
  3061. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3062. sde_encoder_poll_line_counts(encoder);
  3063. }
  3064. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3065. ctl = sde_crtc->mixers[i].hw_ctl;
  3066. if (!ctl || !ctl->ops.hard_reset)
  3067. continue;
  3068. ctl->ops.hard_reset(ctl, false);
  3069. }
  3070. list_for_each_entry(encoder,
  3071. &crtc->dev->mode_config.encoder_list, head) {
  3072. if (encoder->crtc != crtc)
  3073. continue;
  3074. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3075. sde_encoder_kickoff(encoder, false);
  3076. }
  3077. /* panic the device if VBIF is not in good state */
  3078. return !recovery_events ? 0 : -EAGAIN;
  3079. }
  3080. void sde_crtc_commit_kickoff(struct drm_crtc *crtc,
  3081. struct drm_crtc_state *old_state)
  3082. {
  3083. struct drm_encoder *encoder;
  3084. struct drm_device *dev;
  3085. struct sde_crtc *sde_crtc;
  3086. struct sde_kms *sde_kms;
  3087. struct sde_crtc_state *cstate;
  3088. bool is_error = false;
  3089. unsigned long flags;
  3090. enum sde_crtc_idle_pc_state idle_pc_state;
  3091. struct sde_encoder_kickoff_params params = { 0 };
  3092. if (!crtc) {
  3093. SDE_ERROR("invalid argument\n");
  3094. return;
  3095. }
  3096. dev = crtc->dev;
  3097. sde_crtc = to_sde_crtc(crtc);
  3098. sde_kms = _sde_crtc_get_kms(crtc);
  3099. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3100. SDE_ERROR("invalid argument\n");
  3101. return;
  3102. }
  3103. cstate = to_sde_crtc_state(crtc->state);
  3104. /*
  3105. * If no mixers has been allocated in sde_crtc_atomic_check(),
  3106. * it means we are trying to start a CRTC whose state is disabled:
  3107. * nothing else needs to be done.
  3108. */
  3109. if (unlikely(!sde_crtc->num_mixers))
  3110. return;
  3111. SDE_ATRACE_BEGIN("crtc_commit");
  3112. idle_pc_state = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_PC_STATE);
  3113. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3114. if (encoder->crtc != crtc)
  3115. continue;
  3116. /*
  3117. * Encoder will flush/start now, unless it has a tx pending.
  3118. * If so, it may delay and flush at an irq event (e.g. ppdone)
  3119. */
  3120. params.affected_displays = _sde_crtc_get_displays_affected(crtc,
  3121. crtc->state);
  3122. if (sde_encoder_prepare_for_kickoff(encoder, &params))
  3123. sde_crtc->needs_hw_reset = true;
  3124. if (idle_pc_state != IDLE_PC_NONE)
  3125. sde_encoder_control_idle_pc(encoder,
  3126. (idle_pc_state == IDLE_PC_ENABLE) ? true : false);
  3127. }
  3128. /*
  3129. * Optionally attempt h/w recovery if any errors were detected while
  3130. * preparing for the kickoff
  3131. */
  3132. if (sde_crtc->needs_hw_reset) {
  3133. sde_crtc->frame_trigger_mode = params.frame_trigger_mode;
  3134. if (sde_crtc->frame_trigger_mode
  3135. != FRAME_DONE_WAIT_POSTED_START &&
  3136. sde_crtc_reset_hw(crtc, old_state,
  3137. params.recovery_events_enabled))
  3138. is_error = true;
  3139. sde_crtc->needs_hw_reset = false;
  3140. }
  3141. sde_crtc_calc_fps(sde_crtc);
  3142. SDE_ATRACE_BEGIN("flush_event_thread");
  3143. _sde_crtc_flush_event_thread(crtc);
  3144. SDE_ATRACE_END("flush_event_thread");
  3145. sde_crtc->plane_mask_old = crtc->state->plane_mask;
  3146. if (atomic_inc_return(&sde_crtc->frame_pending) == 1) {
  3147. /* acquire bandwidth and other resources */
  3148. SDE_DEBUG("crtc%d first commit\n", crtc->base.id);
  3149. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE1);
  3150. } else {
  3151. SDE_DEBUG("crtc%d commit\n", crtc->base.id);
  3152. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE2);
  3153. }
  3154. sde_crtc->play_count++;
  3155. sde_vbif_clear_errors(sde_kms);
  3156. if (is_error) {
  3157. _sde_crtc_remove_pipe_flush(crtc);
  3158. _sde_crtc_blend_setup(crtc, old_state, false);
  3159. }
  3160. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3161. if (encoder->crtc != crtc)
  3162. continue;
  3163. sde_encoder_kickoff(encoder, false);
  3164. }
  3165. /* store the event after frame trigger */
  3166. if (sde_crtc->event) {
  3167. WARN_ON(sde_crtc->event);
  3168. } else {
  3169. spin_lock_irqsave(&dev->event_lock, flags);
  3170. sde_crtc->event = crtc->state->event;
  3171. spin_unlock_irqrestore(&dev->event_lock, flags);
  3172. }
  3173. _sde_crtc_schedule_idle_notify(crtc, old_state);
  3174. SDE_ATRACE_END("crtc_commit");
  3175. }
  3176. /**
  3177. * _sde_crtc_vblank_enable_no_lock - update power resource and vblank request
  3178. * @sde_crtc: Pointer to sde crtc structure
  3179. * @enable: Whether to enable/disable vblanks
  3180. *
  3181. * @Return: error code
  3182. */
  3183. static int _sde_crtc_vblank_enable_no_lock(
  3184. struct sde_crtc *sde_crtc, bool enable)
  3185. {
  3186. struct drm_crtc *crtc;
  3187. struct drm_encoder *enc;
  3188. if (!sde_crtc) {
  3189. SDE_ERROR("invalid crtc\n");
  3190. return -EINVAL;
  3191. }
  3192. crtc = &sde_crtc->base;
  3193. if (enable) {
  3194. int ret;
  3195. /* drop lock since power crtc cb may try to re-acquire lock */
  3196. mutex_unlock(&sde_crtc->crtc_lock);
  3197. ret = pm_runtime_get_sync(crtc->dev->dev);
  3198. mutex_lock(&sde_crtc->crtc_lock);
  3199. if (ret < 0)
  3200. return ret;
  3201. drm_for_each_encoder_mask(enc, crtc->dev,
  3202. crtc->state->encoder_mask) {
  3203. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3204. sde_crtc->enabled);
  3205. sde_encoder_register_vblank_callback(enc,
  3206. sde_crtc_vblank_cb, (void *)crtc);
  3207. }
  3208. } else {
  3209. drm_for_each_encoder_mask(enc, crtc->dev,
  3210. crtc->state->encoder_mask) {
  3211. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3212. sde_crtc->enabled);
  3213. sde_encoder_register_vblank_callback(enc, NULL, NULL);
  3214. }
  3215. /* drop lock since power crtc cb may try to re-acquire lock */
  3216. mutex_unlock(&sde_crtc->crtc_lock);
  3217. pm_runtime_put_sync(crtc->dev->dev);
  3218. mutex_lock(&sde_crtc->crtc_lock);
  3219. }
  3220. return 0;
  3221. }
  3222. /**
  3223. * sde_crtc_duplicate_state - state duplicate hook
  3224. * @crtc: Pointer to drm crtc structure
  3225. * @Returns: Pointer to new drm_crtc_state structure
  3226. */
  3227. static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc)
  3228. {
  3229. struct sde_crtc *sde_crtc;
  3230. struct sde_crtc_state *cstate, *old_cstate;
  3231. if (!crtc || !crtc->state) {
  3232. SDE_ERROR("invalid argument(s)\n");
  3233. return NULL;
  3234. }
  3235. sde_crtc = to_sde_crtc(crtc);
  3236. old_cstate = to_sde_crtc_state(crtc->state);
  3237. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3238. if (!cstate) {
  3239. SDE_ERROR("failed to allocate state\n");
  3240. return NULL;
  3241. }
  3242. /* duplicate value helper */
  3243. msm_property_duplicate_state(&sde_crtc->property_info,
  3244. old_cstate, cstate,
  3245. &cstate->property_state, cstate->property_values);
  3246. /* duplicate base helper */
  3247. __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
  3248. return &cstate->base;
  3249. }
  3250. /**
  3251. * sde_crtc_reset - reset hook for CRTCs
  3252. * Resets the atomic state for @crtc by freeing the state pointer (which might
  3253. * be NULL, e.g. at driver load time) and allocating a new empty state object.
  3254. * @crtc: Pointer to drm crtc structure
  3255. */
  3256. static void sde_crtc_reset(struct drm_crtc *crtc)
  3257. {
  3258. struct sde_crtc *sde_crtc;
  3259. struct sde_crtc_state *cstate;
  3260. if (!crtc) {
  3261. SDE_ERROR("invalid crtc\n");
  3262. return;
  3263. }
  3264. /* revert suspend actions, if necessary */
  3265. if (!sde_crtc_is_reset_required(crtc)) {
  3266. SDE_DEBUG("avoiding reset for crtc:%d\n", crtc->base.id);
  3267. return;
  3268. }
  3269. /* remove previous state, if present */
  3270. if (crtc->state) {
  3271. sde_crtc_destroy_state(crtc, crtc->state);
  3272. crtc->state = 0;
  3273. }
  3274. sde_crtc = to_sde_crtc(crtc);
  3275. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3276. if (!cstate) {
  3277. SDE_ERROR("failed to allocate state\n");
  3278. return;
  3279. }
  3280. /* reset value helper */
  3281. msm_property_reset_state(&sde_crtc->property_info, cstate,
  3282. &cstate->property_state,
  3283. cstate->property_values);
  3284. _sde_crtc_set_input_fence_timeout(cstate);
  3285. cstate->base.crtc = crtc;
  3286. crtc->state = &cstate->base;
  3287. }
  3288. static void sde_crtc_clear_cached_mixer_cfg(struct drm_crtc *crtc)
  3289. {
  3290. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  3291. struct sde_hw_mixer *hw_lm;
  3292. int lm_idx;
  3293. /* clearing lm cfg marks it dirty to force reprogramming next update */
  3294. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  3295. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  3296. hw_lm->cfg.out_width = 0;
  3297. hw_lm->cfg.out_height = 0;
  3298. }
  3299. SDE_EVT32(DRMID(crtc));
  3300. }
  3301. static void sde_crtc_reset_sw_state_for_ipc(struct drm_crtc *crtc)
  3302. {
  3303. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  3304. struct drm_plane *plane;
  3305. /* mark planes, mixers, and other blocks dirty for next update */
  3306. drm_atomic_crtc_for_each_plane(plane, crtc)
  3307. sde_plane_set_revalidate(plane, true);
  3308. /* mark mixers dirty for next update */
  3309. sde_crtc_clear_cached_mixer_cfg(crtc);
  3310. /* mark other properties which need to be dirty for next update */
  3311. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  3312. if (cstate->num_ds_enabled)
  3313. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  3314. }
  3315. static void sde_crtc_post_ipc(struct drm_crtc *crtc)
  3316. {
  3317. struct sde_crtc *sde_crtc;
  3318. struct sde_crtc_state *cstate;
  3319. struct drm_encoder *encoder;
  3320. sde_crtc = to_sde_crtc(crtc);
  3321. cstate = to_sde_crtc_state(crtc->state);
  3322. /* restore encoder; crtc will be programmed during commit */
  3323. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  3324. sde_encoder_virt_restore(encoder);
  3325. /* restore UIDLE */
  3326. sde_core_perf_crtc_update_uidle(crtc, true);
  3327. sde_cp_crtc_post_ipc(crtc);
  3328. }
  3329. static void sde_crtc_handle_power_event(u32 event_type, void *arg)
  3330. {
  3331. struct drm_crtc *crtc = arg;
  3332. struct sde_crtc *sde_crtc;
  3333. struct drm_encoder *encoder;
  3334. u32 power_on;
  3335. unsigned long flags;
  3336. struct sde_crtc_irq_info *node = NULL;
  3337. int ret = 0;
  3338. struct drm_event event;
  3339. if (!crtc) {
  3340. SDE_ERROR("invalid crtc\n");
  3341. return;
  3342. }
  3343. sde_crtc = to_sde_crtc(crtc);
  3344. mutex_lock(&sde_crtc->crtc_lock);
  3345. SDE_EVT32(DRMID(crtc), event_type);
  3346. switch (event_type) {
  3347. case SDE_POWER_EVENT_POST_ENABLE:
  3348. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3349. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3350. ret = 0;
  3351. if (node->func)
  3352. ret = node->func(crtc, true, &node->irq);
  3353. if (ret)
  3354. SDE_ERROR("%s failed to enable event %x\n",
  3355. sde_crtc->name, node->event);
  3356. }
  3357. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3358. sde_crtc_post_ipc(crtc);
  3359. break;
  3360. case SDE_POWER_EVENT_PRE_DISABLE:
  3361. drm_for_each_encoder_mask(encoder, crtc->dev,
  3362. crtc->state->encoder_mask) {
  3363. /*
  3364. * disable the vsync source after updating the
  3365. * rsc state. rsc state update might have vsync wait
  3366. * and vsync source must be disabled after it.
  3367. * It will avoid generating any vsync from this point
  3368. * till mode-2 entry. It is SW workaround for HW
  3369. * limitation and should not be removed without
  3370. * checking the updated design.
  3371. */
  3372. sde_encoder_control_te(encoder, false);
  3373. }
  3374. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3375. node = NULL;
  3376. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3377. ret = 0;
  3378. if (node->func)
  3379. ret = node->func(crtc, false, &node->irq);
  3380. if (ret)
  3381. SDE_ERROR("%s failed to disable event %x\n",
  3382. sde_crtc->name, node->event);
  3383. }
  3384. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3385. sde_cp_crtc_pre_ipc(crtc);
  3386. break;
  3387. case SDE_POWER_EVENT_POST_DISABLE:
  3388. sde_crtc_reset_sw_state_for_ipc(crtc);
  3389. sde_cp_crtc_suspend(crtc);
  3390. event.type = DRM_EVENT_SDE_POWER;
  3391. event.length = sizeof(power_on);
  3392. power_on = 0;
  3393. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3394. (u8 *)&power_on);
  3395. break;
  3396. default:
  3397. SDE_DEBUG("event:%d not handled\n", event_type);
  3398. break;
  3399. }
  3400. mutex_unlock(&sde_crtc->crtc_lock);
  3401. }
  3402. static void _sde_crtc_reset(struct drm_crtc *crtc)
  3403. {
  3404. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  3405. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  3406. /* mark mixer cfgs dirty before wiping them */
  3407. sde_crtc_clear_cached_mixer_cfg(crtc);
  3408. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  3409. sde_crtc->num_mixers = 0;
  3410. sde_crtc->mixers_swapped = false;
  3411. /* disable clk & bw control until clk & bw properties are set */
  3412. cstate->bw_control = false;
  3413. cstate->bw_split_vote = false;
  3414. sde_crtc_static_img_control(crtc, CACHE_STATE_DISABLED, false);
  3415. }
  3416. static void sde_crtc_disable(struct drm_crtc *crtc)
  3417. {
  3418. struct sde_kms *sde_kms;
  3419. struct sde_crtc *sde_crtc;
  3420. struct sde_crtc_state *cstate;
  3421. struct drm_encoder *encoder;
  3422. struct msm_drm_private *priv;
  3423. unsigned long flags;
  3424. struct sde_crtc_irq_info *node = NULL;
  3425. struct drm_event event;
  3426. u32 power_on;
  3427. bool in_cont_splash = false;
  3428. int ret, i;
  3429. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
  3430. SDE_ERROR("invalid crtc\n");
  3431. return;
  3432. }
  3433. sde_kms = _sde_crtc_get_kms(crtc);
  3434. if (!sde_kms) {
  3435. SDE_ERROR("invalid kms\n");
  3436. return;
  3437. }
  3438. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3439. SDE_ERROR("power resource is not enabled\n");
  3440. return;
  3441. }
  3442. sde_crtc = to_sde_crtc(crtc);
  3443. cstate = to_sde_crtc_state(crtc->state);
  3444. priv = crtc->dev->dev_private;
  3445. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3446. drm_crtc_vblank_off(crtc);
  3447. mutex_lock(&sde_crtc->crtc_lock);
  3448. SDE_EVT32_VERBOSE(DRMID(crtc));
  3449. /* update color processing on suspend */
  3450. event.type = DRM_EVENT_CRTC_POWER;
  3451. event.length = sizeof(u32);
  3452. sde_cp_crtc_suspend(crtc);
  3453. power_on = 0;
  3454. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3455. (u8 *)&power_on);
  3456. _sde_crtc_flush_event_thread(crtc);
  3457. kthread_cancel_delayed_work_sync(&sde_crtc->static_cache_read_work);
  3458. kthread_cancel_delayed_work_sync(&sde_crtc->idle_notify_work);
  3459. SDE_EVT32(DRMID(crtc), sde_crtc->enabled,
  3460. crtc->state->active, crtc->state->enable);
  3461. sde_crtc->enabled = false;
  3462. /* Try to disable uidle */
  3463. sde_core_perf_crtc_update_uidle(crtc, false);
  3464. if (atomic_read(&sde_crtc->frame_pending)) {
  3465. SDE_ERROR("crtc%d frame_pending%d\n", crtc->base.id,
  3466. atomic_read(&sde_crtc->frame_pending));
  3467. SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending),
  3468. SDE_EVTLOG_FUNC_CASE2);
  3469. sde_core_perf_crtc_release_bw(crtc);
  3470. atomic_set(&sde_crtc->frame_pending, 0);
  3471. }
  3472. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3473. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3474. ret = 0;
  3475. if (node->func)
  3476. ret = node->func(crtc, false, &node->irq);
  3477. if (ret)
  3478. SDE_ERROR("%s failed to disable event %x\n",
  3479. sde_crtc->name, node->event);
  3480. }
  3481. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3482. drm_for_each_encoder_mask(encoder, crtc->dev,
  3483. crtc->state->encoder_mask) {
  3484. if (sde_encoder_in_cont_splash(encoder)) {
  3485. in_cont_splash = true;
  3486. break;
  3487. }
  3488. }
  3489. /* avoid clk/bw downvote if cont-splash is enabled */
  3490. if (!in_cont_splash)
  3491. sde_core_perf_crtc_update(crtc, 0, true);
  3492. drm_for_each_encoder_mask(encoder, crtc->dev,
  3493. crtc->state->encoder_mask) {
  3494. sde_encoder_register_frame_event_callback(encoder, NULL, NULL);
  3495. cstate->rsc_client = NULL;
  3496. cstate->rsc_update = false;
  3497. /*
  3498. * reset idle power-collapse to original state during suspend;
  3499. * user-mode will change the state on resume, if required
  3500. */
  3501. if (sde_kms->catalog->has_idle_pc)
  3502. sde_encoder_control_idle_pc(encoder, true);
  3503. }
  3504. if (sde_crtc->power_event) {
  3505. sde_power_handle_unregister_event(&priv->phandle,
  3506. sde_crtc->power_event);
  3507. sde_crtc->power_event = NULL;
  3508. }
  3509. /**
  3510. * All callbacks are unregistered and frame done waits are complete
  3511. * at this point. No buffers are accessed by hardware.
  3512. * reset the fence timeline if crtc will not be enabled for this commit
  3513. */
  3514. if (!crtc->state->active || !crtc->state->enable) {
  3515. sde_fence_signal(sde_crtc->output_fence,
  3516. ktime_get(), SDE_FENCE_RESET_TIMELINE);
  3517. for (i = 0; i < cstate->num_connectors; ++i)
  3518. sde_connector_commit_reset(cstate->connectors[i],
  3519. ktime_get());
  3520. }
  3521. _sde_crtc_reset(crtc);
  3522. mutex_unlock(&sde_crtc->crtc_lock);
  3523. }
  3524. static void sde_crtc_enable(struct drm_crtc *crtc,
  3525. struct drm_crtc_state *old_crtc_state)
  3526. {
  3527. struct sde_crtc *sde_crtc;
  3528. struct drm_encoder *encoder;
  3529. struct msm_drm_private *priv;
  3530. unsigned long flags;
  3531. struct sde_crtc_irq_info *node = NULL;
  3532. struct drm_event event;
  3533. u32 power_on;
  3534. int ret, i;
  3535. struct sde_crtc_state *cstate;
  3536. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  3537. SDE_ERROR("invalid crtc\n");
  3538. return;
  3539. }
  3540. priv = crtc->dev->dev_private;
  3541. cstate = to_sde_crtc_state(crtc->state);
  3542. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3543. SDE_ERROR("power resource is not enabled\n");
  3544. return;
  3545. }
  3546. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3547. SDE_EVT32_VERBOSE(DRMID(crtc));
  3548. sde_crtc = to_sde_crtc(crtc);
  3549. /*
  3550. * Avoid drm_crtc_vblank_on during seamless DMS case
  3551. * when CRTC is already in enabled state
  3552. */
  3553. if (!sde_crtc->enabled)
  3554. drm_crtc_vblank_on(crtc);
  3555. mutex_lock(&sde_crtc->crtc_lock);
  3556. SDE_EVT32(DRMID(crtc), sde_crtc->enabled);
  3557. /*
  3558. * Try to enable uidle (if possible), we do this before the call
  3559. * to return early during seamless dms mode, so any fps
  3560. * change is also consider to enable/disable UIDLE
  3561. */
  3562. sde_core_perf_crtc_update_uidle(crtc, true);
  3563. /* return early if crtc is already enabled, do this after UIDLE check */
  3564. if (sde_crtc->enabled) {
  3565. if (msm_is_mode_seamless_dms(&crtc->state->adjusted_mode) ||
  3566. msm_is_mode_seamless_dyn_clk(&crtc->state->adjusted_mode))
  3567. SDE_DEBUG("%s extra crtc enable expected during DMS\n",
  3568. sde_crtc->name);
  3569. else
  3570. WARN(1, "%s unexpected crtc enable\n", sde_crtc->name);
  3571. mutex_unlock(&sde_crtc->crtc_lock);
  3572. return;
  3573. }
  3574. drm_for_each_encoder_mask(encoder, crtc->dev,
  3575. crtc->state->encoder_mask) {
  3576. sde_encoder_register_frame_event_callback(encoder,
  3577. sde_crtc_frame_event_cb, crtc);
  3578. sde_crtc_static_img_control(crtc, CACHE_STATE_NORMAL,
  3579. sde_encoder_check_curr_mode(encoder,
  3580. MSM_DISPLAY_VIDEO_MODE));
  3581. }
  3582. sde_crtc->enabled = true;
  3583. /* update color processing on resume */
  3584. event.type = DRM_EVENT_CRTC_POWER;
  3585. event.length = sizeof(u32);
  3586. sde_cp_crtc_resume(crtc);
  3587. power_on = 1;
  3588. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3589. (u8 *)&power_on);
  3590. mutex_unlock(&sde_crtc->crtc_lock);
  3591. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3592. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3593. ret = 0;
  3594. if (node->func)
  3595. ret = node->func(crtc, true, &node->irq);
  3596. if (ret)
  3597. SDE_ERROR("%s failed to enable event %x\n",
  3598. sde_crtc->name, node->event);
  3599. }
  3600. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3601. sde_crtc->power_event = sde_power_handle_register_event(
  3602. &priv->phandle,
  3603. SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE |
  3604. SDE_POWER_EVENT_PRE_DISABLE,
  3605. sde_crtc_handle_power_event, crtc, sde_crtc->name);
  3606. /* Enable ESD thread */
  3607. for (i = 0; i < cstate->num_connectors; i++)
  3608. sde_connector_schedule_status_work(cstate->connectors[i], true);
  3609. }
  3610. /* no input validation - caller API has all the checks */
  3611. static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state,
  3612. struct plane_state pstates[], int cnt)
  3613. {
  3614. struct sde_crtc_state *cstate = to_sde_crtc_state(state);
  3615. struct drm_display_mode *mode = &state->adjusted_mode;
  3616. const struct drm_plane_state *pstate;
  3617. struct sde_plane_state *sde_pstate;
  3618. int rc = 0, i;
  3619. /* Check dim layer rect bounds and stage */
  3620. for (i = 0; i < cstate->num_dim_layers; i++) {
  3621. if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y,
  3622. cstate->dim_layer[i].rect.h, mode->vdisplay)) ||
  3623. (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x,
  3624. cstate->dim_layer[i].rect.w, mode->hdisplay)) ||
  3625. (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) ||
  3626. (!cstate->dim_layer[i].rect.w) ||
  3627. (!cstate->dim_layer[i].rect.h)) {
  3628. SDE_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n",
  3629. cstate->dim_layer[i].rect.x,
  3630. cstate->dim_layer[i].rect.y,
  3631. cstate->dim_layer[i].rect.w,
  3632. cstate->dim_layer[i].rect.h,
  3633. cstate->dim_layer[i].stage);
  3634. SDE_ERROR("display: %dx%d\n", mode->hdisplay,
  3635. mode->vdisplay);
  3636. rc = -E2BIG;
  3637. goto end;
  3638. }
  3639. }
  3640. /* log all src and excl_rect, useful for debugging */
  3641. for (i = 0; i < cnt; i++) {
  3642. pstate = pstates[i].drm_pstate;
  3643. sde_pstate = to_sde_plane_state(pstate);
  3644. SDE_DEBUG("p %d z %d src{%d,%d,%d,%d} excl_rect{%d,%d,%d,%d}\n",
  3645. pstate->plane->base.id, pstates[i].stage,
  3646. pstate->crtc_x, pstate->crtc_y,
  3647. pstate->crtc_w, pstate->crtc_h,
  3648. sde_pstate->excl_rect.x, sde_pstate->excl_rect.y,
  3649. sde_pstate->excl_rect.w, sde_pstate->excl_rect.h);
  3650. }
  3651. end:
  3652. return rc;
  3653. }
  3654. static int _sde_crtc_check_secure_blend_config(struct drm_crtc *crtc,
  3655. struct drm_crtc_state *state, struct plane_state pstates[],
  3656. struct sde_crtc_state *cstate, struct sde_kms *sde_kms,
  3657. int cnt, int secure, int fb_ns, int fb_sec, int fb_sec_dir)
  3658. {
  3659. struct drm_plane *plane;
  3660. int i;
  3661. if (secure == SDE_DRM_SEC_ONLY) {
  3662. /*
  3663. * validate planes - only fb_sec_dir is allowed during sec_crtc
  3664. * - fb_sec_dir is for secure camera preview and
  3665. * secure display use case
  3666. * - fb_sec is for secure video playback
  3667. * - fb_ns is for normal non secure use cases
  3668. */
  3669. if (fb_ns || fb_sec) {
  3670. SDE_ERROR(
  3671. "crtc%d: invalid fb_modes Sec:%d, NS:%d, Sec_Dir:%d\n",
  3672. DRMID(crtc), fb_sec, fb_ns, fb_sec_dir);
  3673. return -EINVAL;
  3674. }
  3675. /*
  3676. * - only one blending stage is allowed in sec_crtc
  3677. * - validate if pipe is allowed for sec-ui updates
  3678. */
  3679. for (i = 1; i < cnt; i++) {
  3680. if (!pstates[i].drm_pstate
  3681. || !pstates[i].drm_pstate->plane) {
  3682. SDE_ERROR("crtc%d: invalid pstate at i:%d\n",
  3683. DRMID(crtc), i);
  3684. return -EINVAL;
  3685. }
  3686. plane = pstates[i].drm_pstate->plane;
  3687. if (!sde_plane_is_sec_ui_allowed(plane)) {
  3688. SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n",
  3689. DRMID(crtc), plane->base.id);
  3690. return -EINVAL;
  3691. } else if (pstates[i].stage != pstates[i-1].stage) {
  3692. SDE_ERROR(
  3693. "crtc%d: invalid blend stages %d:%d, %d:%d\n",
  3694. DRMID(crtc), i, pstates[i].stage,
  3695. i-1, pstates[i-1].stage);
  3696. return -EINVAL;
  3697. }
  3698. }
  3699. /* check if all the dim_layers are in the same stage */
  3700. for (i = 1; i < cstate->num_dim_layers; i++) {
  3701. if (cstate->dim_layer[i].stage !=
  3702. cstate->dim_layer[i-1].stage) {
  3703. SDE_ERROR(
  3704. "crtc%d: invalid dimlayer stage %d:%d, %d:%d\n",
  3705. DRMID(crtc),
  3706. i, cstate->dim_layer[i].stage,
  3707. i-1, cstate->dim_layer[i-1].stage);
  3708. return -EINVAL;
  3709. }
  3710. }
  3711. /*
  3712. * if secure-ui supported blendstage is specified,
  3713. * - fail empty commit
  3714. * - validate dim_layer or plane is staged in the supported
  3715. * blendstage
  3716. */
  3717. if (sde_kms->catalog->sui_supported_blendstage) {
  3718. int sec_stage = cnt ? pstates[0].sde_pstate->stage :
  3719. cstate->dim_layer[0].stage;
  3720. if (!sde_kms->catalog->has_base_layer)
  3721. sec_stage -= SDE_STAGE_0;
  3722. if ((!cnt && !cstate->num_dim_layers) ||
  3723. (sde_kms->catalog->sui_supported_blendstage
  3724. != sec_stage)) {
  3725. SDE_ERROR(
  3726. "crtc%d: empty cnt%d/dim%d or bad stage%d\n",
  3727. DRMID(crtc), cnt,
  3728. cstate->num_dim_layers, sec_stage);
  3729. return -EINVAL;
  3730. }
  3731. }
  3732. }
  3733. return 0;
  3734. }
  3735. static int _sde_crtc_check_secure_single_encoder(struct drm_crtc *crtc,
  3736. struct drm_crtc_state *state, int fb_sec_dir)
  3737. {
  3738. struct drm_encoder *encoder;
  3739. int encoder_cnt = 0;
  3740. if (fb_sec_dir) {
  3741. drm_for_each_encoder_mask(encoder, crtc->dev,
  3742. state->encoder_mask)
  3743. encoder_cnt++;
  3744. if (encoder_cnt > MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC) {
  3745. SDE_ERROR("crtc:%d invalid number of encoders:%d\n",
  3746. DRMID(crtc), encoder_cnt);
  3747. return -EINVAL;
  3748. }
  3749. }
  3750. return 0;
  3751. }
  3752. static int _sde_crtc_check_secure_state_smmu_translation(struct drm_crtc *crtc,
  3753. struct drm_crtc_state *state, struct sde_kms *sde_kms, int secure,
  3754. int fb_ns, int fb_sec, int fb_sec_dir)
  3755. {
  3756. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  3757. struct drm_encoder *encoder;
  3758. int is_video_mode = false;
  3759. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  3760. if (sde_encoder_is_dsi_display(encoder))
  3761. is_video_mode |= sde_encoder_check_curr_mode(encoder,
  3762. MSM_DISPLAY_VIDEO_MODE);
  3763. }
  3764. /*
  3765. * Secure display to secure camera needs without direct
  3766. * transition is currently not allowed
  3767. */
  3768. if (fb_sec_dir && secure == SDE_DRM_SEC_NON_SEC &&
  3769. smmu_state->state != ATTACHED &&
  3770. smmu_state->secure_level == SDE_DRM_SEC_ONLY) {
  3771. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  3772. smmu_state->state, smmu_state->secure_level,
  3773. secure);
  3774. goto sec_err;
  3775. }
  3776. /*
  3777. * In video mode check for null commit before transition
  3778. * from secure to non secure and vice versa
  3779. */
  3780. if (is_video_mode && smmu_state &&
  3781. state->plane_mask && crtc->state->plane_mask &&
  3782. ((fb_sec_dir && ((smmu_state->state == ATTACHED) &&
  3783. (secure == SDE_DRM_SEC_ONLY))) ||
  3784. (fb_ns && ((smmu_state->state == DETACHED) ||
  3785. (smmu_state->state == DETACH_ALL_REQ))) ||
  3786. (fb_ns && ((smmu_state->state == DETACHED_SEC) ||
  3787. (smmu_state->state == DETACH_SEC_REQ)) &&
  3788. (smmu_state->secure_level == SDE_DRM_SEC_ONLY)))) {
  3789. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  3790. smmu_state->state, smmu_state->secure_level,
  3791. secure, crtc->state->plane_mask, state->plane_mask);
  3792. goto sec_err;
  3793. }
  3794. return 0;
  3795. sec_err:
  3796. SDE_ERROR(
  3797. "crtc%d Invalid transition;sec%d state%d slvl%d ns%d sdir%d\n",
  3798. DRMID(crtc), secure, smmu_state->state,
  3799. smmu_state->secure_level, fb_ns, fb_sec_dir);
  3800. return -EINVAL;
  3801. }
  3802. static int _sde_crtc_check_secure_conn(struct drm_crtc *crtc,
  3803. struct drm_crtc_state *state, uint32_t fb_sec)
  3804. {
  3805. bool conn_secure = false, is_wb = false;
  3806. struct drm_connector *conn;
  3807. struct drm_connector_state *conn_state;
  3808. int i;
  3809. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  3810. if (conn_state && conn_state->crtc == crtc) {
  3811. if (conn->connector_type ==
  3812. DRM_MODE_CONNECTOR_VIRTUAL)
  3813. is_wb = true;
  3814. if (sde_connector_get_property(conn_state,
  3815. CONNECTOR_PROP_FB_TRANSLATION_MODE) ==
  3816. SDE_DRM_FB_SEC)
  3817. conn_secure = true;
  3818. }
  3819. }
  3820. /*
  3821. * If any input buffers are secure for wb,
  3822. * the output buffer must also be secure.
  3823. */
  3824. if (is_wb && fb_sec && !conn_secure) {
  3825. SDE_ERROR("crtc%d: input fb sec %d, output fb secure %d\n",
  3826. DRMID(crtc), fb_sec, conn_secure);
  3827. return -EINVAL;
  3828. }
  3829. return 0;
  3830. }
  3831. static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
  3832. struct drm_crtc_state *state, struct plane_state pstates[],
  3833. int cnt)
  3834. {
  3835. struct sde_crtc_state *cstate;
  3836. struct sde_kms *sde_kms;
  3837. uint32_t secure;
  3838. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  3839. int rc;
  3840. if (!crtc || !state) {
  3841. SDE_ERROR("invalid arguments\n");
  3842. return -EINVAL;
  3843. }
  3844. sde_kms = _sde_crtc_get_kms(crtc);
  3845. if (!sde_kms || !sde_kms->catalog) {
  3846. SDE_ERROR("invalid kms\n");
  3847. return -EINVAL;
  3848. }
  3849. cstate = to_sde_crtc_state(state);
  3850. secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL);
  3851. rc = sde_crtc_state_find_plane_fb_modes(state, &fb_ns,
  3852. &fb_sec, &fb_sec_dir);
  3853. if (rc)
  3854. return rc;
  3855. rc = _sde_crtc_check_secure_blend_config(crtc, state, pstates, cstate,
  3856. sde_kms, cnt, secure, fb_ns, fb_sec, fb_sec_dir);
  3857. if (rc)
  3858. return rc;
  3859. rc = _sde_crtc_check_secure_conn(crtc, state, fb_sec);
  3860. if (rc)
  3861. return rc;
  3862. /*
  3863. * secure_crtc is not allowed in a shared toppolgy
  3864. * across different encoders.
  3865. */
  3866. rc = _sde_crtc_check_secure_single_encoder(crtc, state, fb_sec_dir);
  3867. if (rc)
  3868. return rc;
  3869. rc = _sde_crtc_check_secure_state_smmu_translation(crtc, state, sde_kms,
  3870. secure, fb_ns, fb_sec, fb_sec_dir);
  3871. if (rc)
  3872. return rc;
  3873. SDE_DEBUG("crtc:%d Secure validation successful\n", DRMID(crtc));
  3874. return 0;
  3875. }
  3876. static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc,
  3877. struct drm_crtc_state *state,
  3878. struct drm_display_mode *mode,
  3879. struct plane_state *pstates,
  3880. struct drm_plane *plane,
  3881. struct sde_multirect_plane_states *multirect_plane,
  3882. int *cnt)
  3883. {
  3884. struct sde_crtc *sde_crtc;
  3885. struct sde_crtc_state *cstate;
  3886. const struct drm_plane_state *pstate;
  3887. const struct drm_plane_state *pipe_staged[SSPP_MAX];
  3888. int rc = 0, multirect_count = 0, i, mixer_width, mixer_height;
  3889. int inc_sde_stage = 0;
  3890. struct sde_kms *kms;
  3891. sde_crtc = to_sde_crtc(crtc);
  3892. cstate = to_sde_crtc_state(state);
  3893. kms = _sde_crtc_get_kms(crtc);
  3894. if (!kms || !kms->catalog) {
  3895. SDE_ERROR("invalid kms\n");
  3896. return -EINVAL;
  3897. }
  3898. memset(pipe_staged, 0, sizeof(pipe_staged));
  3899. mixer_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  3900. mixer_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  3901. if (cstate->num_ds_enabled)
  3902. mixer_width = mixer_width * cstate->num_ds_enabled;
  3903. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  3904. if (IS_ERR_OR_NULL(pstate)) {
  3905. rc = PTR_ERR(pstate);
  3906. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  3907. sde_crtc->name, plane->base.id, rc);
  3908. return rc;
  3909. }
  3910. if (*cnt >= SDE_PSTATES_MAX)
  3911. continue;
  3912. pstates[*cnt].sde_pstate = to_sde_plane_state(pstate);
  3913. pstates[*cnt].drm_pstate = pstate;
  3914. pstates[*cnt].stage = sde_plane_get_property(
  3915. pstates[*cnt].sde_pstate, PLANE_PROP_ZPOS);
  3916. pstates[*cnt].pipe_id = sde_plane_pipe(plane);
  3917. if (!kms->catalog->has_base_layer)
  3918. inc_sde_stage = SDE_STAGE_0;
  3919. /* check dim layer stage with every plane */
  3920. for (i = 0; i < cstate->num_dim_layers; i++) {
  3921. if (cstate->dim_layer[i].stage ==
  3922. (pstates[*cnt].stage + inc_sde_stage)) {
  3923. SDE_ERROR(
  3924. "plane:%d/dim_layer:%i-same stage:%d\n",
  3925. plane->base.id, i,
  3926. cstate->dim_layer[i].stage);
  3927. return -EINVAL;
  3928. }
  3929. }
  3930. if (pipe_staged[pstates[*cnt].pipe_id]) {
  3931. multirect_plane[multirect_count].r0 =
  3932. pipe_staged[pstates[*cnt].pipe_id];
  3933. multirect_plane[multirect_count].r1 = pstate;
  3934. multirect_count++;
  3935. pipe_staged[pstates[*cnt].pipe_id] = NULL;
  3936. } else {
  3937. pipe_staged[pstates[*cnt].pipe_id] = pstate;
  3938. }
  3939. (*cnt)++;
  3940. if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h,
  3941. mode->vdisplay) ||
  3942. CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w,
  3943. mode->hdisplay)) {
  3944. SDE_ERROR("invalid vertical/horizontal destination\n");
  3945. SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n",
  3946. pstate->crtc_y, pstate->crtc_h, mode->vdisplay,
  3947. pstate->crtc_x, pstate->crtc_w, mode->hdisplay);
  3948. return -E2BIG;
  3949. }
  3950. if (cstate->num_ds_enabled &&
  3951. ((pstate->crtc_h > mixer_height) ||
  3952. (pstate->crtc_w > mixer_width))) {
  3953. SDE_ERROR("plane w/h:%x*%x > mixer w/h:%x*%x\n",
  3954. pstate->crtc_w, pstate->crtc_h,
  3955. mixer_width, mixer_height);
  3956. return -E2BIG;
  3957. }
  3958. }
  3959. for (i = 1; i < SSPP_MAX; i++) {
  3960. if (pipe_staged[i]) {
  3961. sde_plane_clear_multirect(pipe_staged[i]);
  3962. if (is_sde_plane_virtual(pipe_staged[i]->plane)) {
  3963. struct sde_plane_state *psde_state;
  3964. SDE_DEBUG("r1 only virt plane:%d staged\n",
  3965. pipe_staged[i]->plane->base.id);
  3966. psde_state = to_sde_plane_state(
  3967. pipe_staged[i]);
  3968. psde_state->multirect_index = SDE_SSPP_RECT_1;
  3969. }
  3970. }
  3971. }
  3972. for (i = 0; i < multirect_count; i++) {
  3973. if (sde_plane_validate_multirect_v2(&multirect_plane[i])) {
  3974. SDE_ERROR(
  3975. "multirect validation failed for planes (%d - %d)\n",
  3976. multirect_plane[i].r0->plane->base.id,
  3977. multirect_plane[i].r1->plane->base.id);
  3978. return -EINVAL;
  3979. }
  3980. }
  3981. return rc;
  3982. }
  3983. static int _sde_crtc_check_zpos(struct drm_crtc_state *state,
  3984. struct sde_crtc *sde_crtc,
  3985. struct plane_state *pstates,
  3986. struct sde_crtc_state *cstate,
  3987. struct drm_display_mode *mode,
  3988. int cnt)
  3989. {
  3990. int rc = 0, i, z_pos;
  3991. u32 zpos_cnt = 0;
  3992. struct drm_crtc *crtc;
  3993. struct sde_kms *kms;
  3994. enum sde_layout layout;
  3995. crtc = &sde_crtc->base;
  3996. kms = _sde_crtc_get_kms(crtc);
  3997. if (!kms || !kms->catalog) {
  3998. SDE_ERROR("Invalid kms\n");
  3999. return -EINVAL;
  4000. }
  4001. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  4002. rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt);
  4003. if (rc)
  4004. return rc;
  4005. if (!sde_is_custom_client()) {
  4006. int stage_old = pstates[0].stage;
  4007. z_pos = 0;
  4008. for (i = 0; i < cnt; i++) {
  4009. if (stage_old != pstates[i].stage)
  4010. ++z_pos;
  4011. stage_old = pstates[i].stage;
  4012. pstates[i].stage = z_pos;
  4013. }
  4014. }
  4015. z_pos = -1;
  4016. layout = SDE_LAYOUT_NONE;
  4017. for (i = 0; i < cnt; i++) {
  4018. /* reset counts at every new blend stage */
  4019. if (pstates[i].stage != z_pos ||
  4020. pstates[i].sde_pstate->layout != layout) {
  4021. zpos_cnt = 0;
  4022. z_pos = pstates[i].stage;
  4023. layout = pstates[i].sde_pstate->layout;
  4024. }
  4025. /* verify z_pos setting before using it */
  4026. if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) {
  4027. SDE_ERROR("> %d plane stages assigned\n",
  4028. SDE_STAGE_MAX - SDE_STAGE_0);
  4029. return -EINVAL;
  4030. } else if (zpos_cnt == 2) {
  4031. SDE_ERROR("> 2 planes @ stage %d\n", z_pos);
  4032. return -EINVAL;
  4033. } else {
  4034. zpos_cnt++;
  4035. }
  4036. if (!kms->catalog->has_base_layer)
  4037. pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
  4038. else
  4039. pstates[i].sde_pstate->stage = z_pos;
  4040. SDE_DEBUG("%s: layout %d, zpos %d", sde_crtc->name, layout,
  4041. z_pos);
  4042. }
  4043. return rc;
  4044. }
  4045. static int _sde_crtc_atomic_check_pstates(struct drm_crtc *crtc,
  4046. struct drm_crtc_state *state,
  4047. struct plane_state *pstates,
  4048. struct sde_multirect_plane_states *multirect_plane)
  4049. {
  4050. struct sde_crtc *sde_crtc;
  4051. struct sde_crtc_state *cstate;
  4052. struct sde_kms *kms;
  4053. struct drm_plane *plane = NULL;
  4054. struct drm_display_mode *mode;
  4055. int rc = 0, cnt = 0;
  4056. kms = _sde_crtc_get_kms(crtc);
  4057. if (!kms || !kms->catalog) {
  4058. SDE_ERROR("invalid parameters\n");
  4059. return -EINVAL;
  4060. }
  4061. sde_crtc = to_sde_crtc(crtc);
  4062. cstate = to_sde_crtc_state(state);
  4063. mode = &state->adjusted_mode;
  4064. /* get plane state for all drm planes associated with crtc state */
  4065. rc = _sde_crtc_check_get_pstates(crtc, state, mode, pstates,
  4066. plane, multirect_plane, &cnt);
  4067. if (rc)
  4068. return rc;
  4069. /* assign mixer stages based on sorted zpos property */
  4070. rc = _sde_crtc_check_zpos(state, sde_crtc, pstates, cstate, mode, cnt);
  4071. if (rc)
  4072. return rc;
  4073. rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);
  4074. if (rc)
  4075. return rc;
  4076. /*
  4077. * validate and set source split:
  4078. * use pstates sorted by stage to check planes on same stage
  4079. * we assume that all pipes are in source split so its valid to compare
  4080. * without taking into account left/right mixer placement
  4081. */
  4082. rc = _sde_crtc_validate_src_split_order(crtc, pstates, cnt);
  4083. if (rc)
  4084. return rc;
  4085. return 0;
  4086. }
  4087. static int _sde_crtc_check_plane_layout(struct drm_crtc *crtc,
  4088. struct drm_crtc_state *crtc_state)
  4089. {
  4090. struct sde_kms *kms;
  4091. struct drm_plane *plane;
  4092. struct drm_plane_state *plane_state;
  4093. struct sde_plane_state *pstate;
  4094. int layout_split;
  4095. kms = _sde_crtc_get_kms(crtc);
  4096. if (!kms || !kms->catalog) {
  4097. SDE_ERROR("invalid parameters\n");
  4098. return -EINVAL;
  4099. }
  4100. if (!sde_rm_topology_is_group(&kms->rm, crtc_state,
  4101. SDE_RM_TOPOLOGY_GROUP_QUADPIPE))
  4102. return 0;
  4103. drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
  4104. plane_state = drm_atomic_get_existing_plane_state(
  4105. crtc_state->state, plane);
  4106. if (!plane_state)
  4107. continue;
  4108. pstate = to_sde_plane_state(plane_state);
  4109. layout_split = crtc_state->mode.hdisplay >> 1;
  4110. if (plane_state->crtc_x >= layout_split) {
  4111. plane_state->crtc_x -= layout_split;
  4112. pstate->layout_offset = layout_split;
  4113. pstate->layout = SDE_LAYOUT_RIGHT;
  4114. } else {
  4115. pstate->layout_offset = -1;
  4116. pstate->layout = SDE_LAYOUT_LEFT;
  4117. }
  4118. SDE_DEBUG("plane%d updated: crtc_x=%d layout=%d\n",
  4119. DRMID(plane), plane_state->crtc_x,
  4120. pstate->layout);
  4121. /* check layout boundary */
  4122. if (CHECK_LAYER_BOUNDS(plane_state->crtc_x,
  4123. plane_state->crtc_w, layout_split)) {
  4124. SDE_ERROR("invalid horizontal destination\n");
  4125. SDE_ERROR("x:%d w:%d hdisp:%d layout:%d\n",
  4126. plane_state->crtc_x,
  4127. plane_state->crtc_w,
  4128. layout_split, pstate->layout);
  4129. return -E2BIG;
  4130. }
  4131. }
  4132. return 0;
  4133. }
  4134. static int sde_crtc_atomic_check(struct drm_crtc *crtc,
  4135. struct drm_crtc_state *state)
  4136. {
  4137. struct drm_device *dev;
  4138. struct sde_crtc *sde_crtc;
  4139. struct plane_state *pstates = NULL;
  4140. struct sde_crtc_state *cstate;
  4141. struct drm_display_mode *mode;
  4142. int rc = 0;
  4143. struct sde_multirect_plane_states *multirect_plane = NULL;
  4144. struct drm_connector *conn;
  4145. struct drm_connector_list_iter conn_iter;
  4146. if (!crtc) {
  4147. SDE_ERROR("invalid crtc\n");
  4148. return -EINVAL;
  4149. }
  4150. dev = crtc->dev;
  4151. sde_crtc = to_sde_crtc(crtc);
  4152. cstate = to_sde_crtc_state(state);
  4153. if (!state->enable || !state->active) {
  4154. SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
  4155. crtc->base.id, state->enable, state->active);
  4156. goto end;
  4157. }
  4158. pstates = kcalloc(SDE_PSTATES_MAX,
  4159. sizeof(struct plane_state), GFP_KERNEL);
  4160. multirect_plane = kcalloc(SDE_MULTIRECT_PLANE_MAX,
  4161. sizeof(struct sde_multirect_plane_states),
  4162. GFP_KERNEL);
  4163. if (!pstates || !multirect_plane) {
  4164. rc = -ENOMEM;
  4165. goto end;
  4166. }
  4167. mode = &state->adjusted_mode;
  4168. SDE_DEBUG("%s: check", sde_crtc->name);
  4169. /* force a full mode set if active state changed */
  4170. if (state->active_changed)
  4171. state->mode_changed = true;
  4172. /* identify connectors attached to this crtc */
  4173. cstate->num_connectors = 0;
  4174. drm_connector_list_iter_begin(dev, &conn_iter);
  4175. drm_for_each_connector_iter(conn, &conn_iter)
  4176. if ((state->connector_mask & (1 << drm_connector_index(conn)))
  4177. && cstate->num_connectors < MAX_CONNECTORS) {
  4178. cstate->connectors[cstate->num_connectors++] = conn;
  4179. }
  4180. drm_connector_list_iter_end(&conn_iter);
  4181. rc = _sde_crtc_check_dest_scaler_data(crtc, state);
  4182. if (rc) {
  4183. SDE_ERROR("crtc%d failed dest scaler check %d\n",
  4184. crtc->base.id, rc);
  4185. goto end;
  4186. }
  4187. rc = _sde_crtc_check_plane_layout(crtc, state);
  4188. if (rc) {
  4189. SDE_ERROR("crtc%d failed plane layout check %d\n",
  4190. crtc->base.id, rc);
  4191. goto end;
  4192. }
  4193. _sde_crtc_setup_is_ppsplit(state);
  4194. _sde_crtc_setup_lm_bounds(crtc, state);
  4195. rc = _sde_crtc_atomic_check_pstates(crtc, state, pstates,
  4196. multirect_plane);
  4197. if (rc) {
  4198. SDE_ERROR("crtc%d failed pstate check %d\n", crtc->base.id, rc);
  4199. goto end;
  4200. }
  4201. rc = sde_core_perf_crtc_check(crtc, state);
  4202. if (rc) {
  4203. SDE_ERROR("crtc%d failed performance check %d\n",
  4204. crtc->base.id, rc);
  4205. goto end;
  4206. }
  4207. rc = _sde_crtc_check_rois(crtc, state);
  4208. if (rc) {
  4209. SDE_ERROR("crtc%d failed roi check %d\n", crtc->base.id, rc);
  4210. goto end;
  4211. }
  4212. rc = sde_cp_crtc_check_properties(crtc, state);
  4213. if (rc) {
  4214. SDE_ERROR("crtc%d failed cp properties check %d\n",
  4215. crtc->base.id, rc);
  4216. goto end;
  4217. }
  4218. end:
  4219. kfree(pstates);
  4220. kfree(multirect_plane);
  4221. return rc;
  4222. }
  4223. /**
  4224. * sde_crtc_get_num_datapath - get the number of datapath active
  4225. * of primary connector
  4226. * @crtc: Pointer to DRM crtc object
  4227. * @connector: Pointer to DRM connector object of WB in CWB case
  4228. */
  4229. int sde_crtc_get_num_datapath(struct drm_crtc *crtc,
  4230. struct drm_connector *connector)
  4231. {
  4232. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  4233. struct sde_connector_state *sde_conn_state = NULL;
  4234. struct drm_connector *conn;
  4235. struct drm_connector_list_iter conn_iter;
  4236. if (!sde_crtc || !connector) {
  4237. SDE_DEBUG("Invalid argument\n");
  4238. return 0;
  4239. }
  4240. if (sde_crtc->num_mixers)
  4241. return sde_crtc->num_mixers;
  4242. drm_connector_list_iter_begin(crtc->dev, &conn_iter);
  4243. drm_for_each_connector_iter(conn, &conn_iter) {
  4244. if (conn->state && conn->state->crtc == crtc &&
  4245. conn != connector)
  4246. sde_conn_state = to_sde_connector_state(conn->state);
  4247. }
  4248. drm_connector_list_iter_end(&conn_iter);
  4249. if (sde_conn_state)
  4250. return sde_conn_state->mode_info.topology.num_lm;
  4251. return 0;
  4252. }
  4253. int sde_crtc_vblank(struct drm_crtc *crtc, bool en)
  4254. {
  4255. struct sde_crtc *sde_crtc;
  4256. int ret;
  4257. if (!crtc) {
  4258. SDE_ERROR("invalid crtc\n");
  4259. return -EINVAL;
  4260. }
  4261. sde_crtc = to_sde_crtc(crtc);
  4262. mutex_lock(&sde_crtc->crtc_lock);
  4263. SDE_EVT32(DRMID(&sde_crtc->base), en, sde_crtc->enabled);
  4264. ret = _sde_crtc_vblank_enable_no_lock(sde_crtc, en);
  4265. if (ret)
  4266. SDE_ERROR("%s vblank enable failed: %d\n",
  4267. sde_crtc->name, ret);
  4268. mutex_unlock(&sde_crtc->crtc_lock);
  4269. return 0;
  4270. }
  4271. static void sde_crtc_install_dest_scale_properties(struct sde_crtc *sde_crtc,
  4272. struct sde_mdss_cfg *catalog, struct sde_kms_info *info)
  4273. {
  4274. sde_kms_info_add_keyint(info, "has_dest_scaler",
  4275. catalog->mdp[0].has_dest_scaler);
  4276. sde_kms_info_add_keyint(info, "dest_scaler_count",
  4277. catalog->ds_count);
  4278. if (catalog->ds[0].top) {
  4279. sde_kms_info_add_keyint(info,
  4280. "max_dest_scaler_input_width",
  4281. catalog->ds[0].top->maxinputwidth);
  4282. sde_kms_info_add_keyint(info,
  4283. "max_dest_scaler_output_width",
  4284. catalog->ds[0].top->maxoutputwidth);
  4285. sde_kms_info_add_keyint(info, "max_dest_scale_up",
  4286. catalog->ds[0].top->maxupscale);
  4287. }
  4288. if (catalog->ds[0].features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  4289. msm_property_install_volatile_range(
  4290. &sde_crtc->property_info, "dest_scaler",
  4291. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4292. msm_property_install_blob(&sde_crtc->property_info,
  4293. "ds_lut_ed", 0,
  4294. CRTC_PROP_DEST_SCALER_LUT_ED);
  4295. msm_property_install_blob(&sde_crtc->property_info,
  4296. "ds_lut_cir", 0,
  4297. CRTC_PROP_DEST_SCALER_LUT_CIR);
  4298. msm_property_install_blob(&sde_crtc->property_info,
  4299. "ds_lut_sep", 0,
  4300. CRTC_PROP_DEST_SCALER_LUT_SEP);
  4301. } else if (catalog->ds[0].features
  4302. & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  4303. msm_property_install_volatile_range(
  4304. &sde_crtc->property_info, "dest_scaler",
  4305. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4306. }
  4307. }
  4308. static void sde_crtc_install_perf_properties(struct sde_crtc *sde_crtc,
  4309. struct sde_kms *sde_kms, struct sde_mdss_cfg *catalog,
  4310. struct sde_kms_info *info)
  4311. {
  4312. msm_property_install_range(&sde_crtc->property_info,
  4313. "core_clk", 0x0, 0, U64_MAX,
  4314. sde_kms->perf.max_core_clk_rate,
  4315. CRTC_PROP_CORE_CLK);
  4316. msm_property_install_range(&sde_crtc->property_info,
  4317. "core_ab", 0x0, 0, U64_MAX,
  4318. catalog->perf.max_bw_high * 1000ULL,
  4319. CRTC_PROP_CORE_AB);
  4320. msm_property_install_range(&sde_crtc->property_info,
  4321. "core_ib", 0x0, 0, U64_MAX,
  4322. catalog->perf.max_bw_high * 1000ULL,
  4323. CRTC_PROP_CORE_IB);
  4324. msm_property_install_range(&sde_crtc->property_info,
  4325. "llcc_ab", 0x0, 0, U64_MAX,
  4326. catalog->perf.max_bw_high * 1000ULL,
  4327. CRTC_PROP_LLCC_AB);
  4328. msm_property_install_range(&sde_crtc->property_info,
  4329. "llcc_ib", 0x0, 0, U64_MAX,
  4330. catalog->perf.max_bw_high * 1000ULL,
  4331. CRTC_PROP_LLCC_IB);
  4332. msm_property_install_range(&sde_crtc->property_info,
  4333. "dram_ab", 0x0, 0, U64_MAX,
  4334. catalog->perf.max_bw_high * 1000ULL,
  4335. CRTC_PROP_DRAM_AB);
  4336. msm_property_install_range(&sde_crtc->property_info,
  4337. "dram_ib", 0x0, 0, U64_MAX,
  4338. catalog->perf.max_bw_high * 1000ULL,
  4339. CRTC_PROP_DRAM_IB);
  4340. msm_property_install_range(&sde_crtc->property_info,
  4341. "rot_prefill_bw", 0, 0, U64_MAX,
  4342. catalog->perf.max_bw_high * 1000ULL,
  4343. CRTC_PROP_ROT_PREFILL_BW);
  4344. msm_property_install_range(&sde_crtc->property_info,
  4345. "rot_clk", 0, 0, U64_MAX,
  4346. sde_kms->perf.max_core_clk_rate,
  4347. CRTC_PROP_ROT_CLK);
  4348. if (catalog->perf.max_bw_low)
  4349. sde_kms_info_add_keyint(info, "max_bandwidth_low",
  4350. catalog->perf.max_bw_low * 1000LL);
  4351. if (catalog->perf.max_bw_high)
  4352. sde_kms_info_add_keyint(info, "max_bandwidth_high",
  4353. catalog->perf.max_bw_high * 1000LL);
  4354. if (catalog->perf.min_core_ib)
  4355. sde_kms_info_add_keyint(info, "min_core_ib",
  4356. catalog->perf.min_core_ib * 1000LL);
  4357. if (catalog->perf.min_llcc_ib)
  4358. sde_kms_info_add_keyint(info, "min_llcc_ib",
  4359. catalog->perf.min_llcc_ib * 1000LL);
  4360. if (catalog->perf.min_dram_ib)
  4361. sde_kms_info_add_keyint(info, "min_dram_ib",
  4362. catalog->perf.min_dram_ib * 1000LL);
  4363. if (sde_kms->perf.max_core_clk_rate)
  4364. sde_kms_info_add_keyint(info, "max_mdp_clk",
  4365. sde_kms->perf.max_core_clk_rate);
  4366. }
  4367. static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
  4368. struct sde_mdss_cfg *catalog)
  4369. {
  4370. sde_kms_info_reset(info);
  4371. sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
  4372. sde_kms_info_add_keyint(info, "max_linewidth",
  4373. catalog->max_mixer_width);
  4374. sde_kms_info_add_keyint(info, "max_blendstages",
  4375. catalog->max_mixer_blendstages);
  4376. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED2)
  4377. sde_kms_info_add_keystr(info, "qseed_type", "qseed2");
  4378. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3)
  4379. sde_kms_info_add_keystr(info, "qseed_type", "qseed3");
  4380. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3LITE)
  4381. sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");
  4382. if (catalog->ubwc_version) {
  4383. sde_kms_info_add_keyint(info, "UBWC version",
  4384. catalog->ubwc_version);
  4385. sde_kms_info_add_keyint(info, "UBWC macrotile_mode",
  4386. catalog->macrotile_mode);
  4387. sde_kms_info_add_keyint(info, "UBWC highest banking bit",
  4388. catalog->mdp[0].highest_bank_bit);
  4389. sde_kms_info_add_keyint(info, "UBWC swizzle",
  4390. catalog->mdp[0].ubwc_swizzle);
  4391. }
  4392. if (of_fdt_get_ddrtype() == LP_DDR4_TYPE)
  4393. sde_kms_info_add_keystr(info, "DDR version", "DDR4");
  4394. else
  4395. sde_kms_info_add_keystr(info, "DDR version", "DDR5");
  4396. if (sde_is_custom_client()) {
  4397. /* No support for SMART_DMA_V1 yet */
  4398. if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2)
  4399. sde_kms_info_add_keystr(info,
  4400. "smart_dma_rev", "smart_dma_v2");
  4401. else if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2p5)
  4402. sde_kms_info_add_keystr(info,
  4403. "smart_dma_rev", "smart_dma_v2p5");
  4404. }
  4405. sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split);
  4406. sde_kms_info_add_keyint(info, "has_hdr", catalog->has_hdr);
  4407. sde_kms_info_add_keyint(info, "has_hdr_plus", catalog->has_hdr_plus);
  4408. if (catalog->uidle_cfg.uidle_rev)
  4409. sde_kms_info_add_keyint(info, "has_uidle",
  4410. true);
  4411. sde_kms_info_add_keystr(info, "core_ib_ff",
  4412. catalog->perf.core_ib_ff);
  4413. sde_kms_info_add_keystr(info, "core_clk_ff",
  4414. catalog->perf.core_clk_ff);
  4415. sde_kms_info_add_keystr(info, "comp_ratio_rt",
  4416. catalog->perf.comp_ratio_rt);
  4417. sde_kms_info_add_keystr(info, "comp_ratio_nrt",
  4418. catalog->perf.comp_ratio_nrt);
  4419. sde_kms_info_add_keyint(info, "dest_scale_prefill_lines",
  4420. catalog->perf.dest_scale_prefill_lines);
  4421. sde_kms_info_add_keyint(info, "undersized_prefill_lines",
  4422. catalog->perf.undersized_prefill_lines);
  4423. sde_kms_info_add_keyint(info, "macrotile_prefill_lines",
  4424. catalog->perf.macrotile_prefill_lines);
  4425. sde_kms_info_add_keyint(info, "yuv_nv12_prefill_lines",
  4426. catalog->perf.yuv_nv12_prefill_lines);
  4427. sde_kms_info_add_keyint(info, "linear_prefill_lines",
  4428. catalog->perf.linear_prefill_lines);
  4429. sde_kms_info_add_keyint(info, "downscaling_prefill_lines",
  4430. catalog->perf.downscaling_prefill_lines);
  4431. sde_kms_info_add_keyint(info, "xtra_prefill_lines",
  4432. catalog->perf.xtra_prefill_lines);
  4433. sde_kms_info_add_keyint(info, "amortizable_threshold",
  4434. catalog->perf.amortizable_threshold);
  4435. sde_kms_info_add_keyint(info, "min_prefill_lines",
  4436. catalog->perf.min_prefill_lines);
  4437. sde_kms_info_add_keyint(info, "num_mnoc_ports",
  4438. catalog->perf.num_mnoc_ports);
  4439. sde_kms_info_add_keyint(info, "axi_bus_width",
  4440. catalog->perf.axi_bus_width);
  4441. sde_kms_info_add_keyint(info, "sec_ui_blendstage",
  4442. catalog->sui_supported_blendstage);
  4443. if (catalog->ubwc_bw_calc_version)
  4444. sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver",
  4445. catalog->ubwc_bw_calc_version);
  4446. }
  4447. /**
  4448. * sde_crtc_install_properties - install all drm properties for crtc
  4449. * @crtc: Pointer to drm crtc structure
  4450. */
  4451. static void sde_crtc_install_properties(struct drm_crtc *crtc,
  4452. struct sde_mdss_cfg *catalog)
  4453. {
  4454. struct sde_crtc *sde_crtc;
  4455. struct sde_kms_info *info;
  4456. struct sde_kms *sde_kms;
  4457. static const struct drm_prop_enum_list e_secure_level[] = {
  4458. {SDE_DRM_SEC_NON_SEC, "sec_and_non_sec"},
  4459. {SDE_DRM_SEC_ONLY, "sec_only"},
  4460. };
  4461. static const struct drm_prop_enum_list e_cwb_data_points[] = {
  4462. {CAPTURE_MIXER_OUT, "capture_mixer_out"},
  4463. {CAPTURE_DSPP_OUT, "capture_pp_out"},
  4464. };
  4465. static const struct drm_prop_enum_list e_idle_pc_state[] = {
  4466. {IDLE_PC_NONE, "idle_pc_none"},
  4467. {IDLE_PC_ENABLE, "idle_pc_enable"},
  4468. {IDLE_PC_DISABLE, "idle_pc_disable"},
  4469. };
  4470. static const struct drm_prop_enum_list e_cache_state[] = {
  4471. {CACHE_STATE_DISABLED, "cache_state_disabled"},
  4472. {CACHE_STATE_ENABLED, "cache_state_enabled"},
  4473. };
  4474. static const struct drm_prop_enum_list e_vm_req_state[] = {
  4475. {VM_REQ_NONE, "vm_req_none"},
  4476. {VM_REQ_RELEASE, "vm_req_release"},
  4477. {VM_REQ_ACQUIRE, "vm_req_acquire"},
  4478. };
  4479. SDE_DEBUG("\n");
  4480. if (!crtc || !catalog) {
  4481. SDE_ERROR("invalid crtc or catalog\n");
  4482. return;
  4483. }
  4484. sde_crtc = to_sde_crtc(crtc);
  4485. sde_kms = _sde_crtc_get_kms(crtc);
  4486. if (!sde_kms) {
  4487. SDE_ERROR("invalid argument\n");
  4488. return;
  4489. }
  4490. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  4491. if (!info) {
  4492. SDE_ERROR("failed to allocate info memory\n");
  4493. return;
  4494. }
  4495. sde_crtc_setup_capabilities_blob(info, catalog);
  4496. msm_property_install_range(&sde_crtc->property_info,
  4497. "input_fence_timeout", 0x0, 0,
  4498. SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT, SDE_CRTC_INPUT_FENCE_TIMEOUT,
  4499. CRTC_PROP_INPUT_FENCE_TIMEOUT);
  4500. msm_property_install_volatile_range(&sde_crtc->property_info,
  4501. "output_fence", 0x0, 0, ~0, 0, CRTC_PROP_OUTPUT_FENCE);
  4502. msm_property_install_range(&sde_crtc->property_info,
  4503. "output_fence_offset", 0x0, 0, 1, 0,
  4504. CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4505. sde_crtc_install_perf_properties(sde_crtc, sde_kms, catalog, info);
  4506. msm_property_install_range(&sde_crtc->property_info,
  4507. "idle_time", 0, 0, U64_MAX, 0,
  4508. CRTC_PROP_IDLE_TIMEOUT);
  4509. if (catalog->has_trusted_vm_support) {
  4510. int init_idx = sde_in_trusted_vm(sde_kms) ? 1 : 0;
  4511. msm_property_install_enum(&sde_crtc->property_info,
  4512. "vm_request_state", 0x0, 0, e_vm_req_state,
  4513. ARRAY_SIZE(e_vm_req_state), init_idx,
  4514. CRTC_PROP_VM_REQ_STATE);
  4515. }
  4516. if (catalog->has_idle_pc)
  4517. msm_property_install_enum(&sde_crtc->property_info,
  4518. "idle_pc_state", 0x0, 0, e_idle_pc_state,
  4519. ARRAY_SIZE(e_idle_pc_state), 0,
  4520. CRTC_PROP_IDLE_PC_STATE);
  4521. if (catalog->has_cwb_support)
  4522. msm_property_install_enum(&sde_crtc->property_info,
  4523. "capture_mode", 0, 0, e_cwb_data_points,
  4524. ARRAY_SIZE(e_cwb_data_points), 0,
  4525. CRTC_PROP_CAPTURE_OUTPUT);
  4526. msm_property_install_volatile_range(&sde_crtc->property_info,
  4527. "sde_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1);
  4528. msm_property_install_enum(&sde_crtc->property_info, "security_level",
  4529. 0x0, 0, e_secure_level,
  4530. ARRAY_SIZE(e_secure_level), 0,
  4531. CRTC_PROP_SECURITY_LEVEL);
  4532. msm_property_install_enum(&sde_crtc->property_info, "cache_state",
  4533. 0x0, 0, e_cache_state,
  4534. ARRAY_SIZE(e_cache_state), 0,
  4535. CRTC_PROP_CACHE_STATE);
  4536. if (catalog->has_dim_layer) {
  4537. msm_property_install_volatile_range(&sde_crtc->property_info,
  4538. "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1);
  4539. sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers",
  4540. SDE_MAX_DIM_LAYERS);
  4541. }
  4542. if (catalog->mdp[0].has_dest_scaler)
  4543. sde_crtc_install_dest_scale_properties(sde_crtc, catalog,
  4544. info);
  4545. if (catalog->dspp_count && catalog->rc_count)
  4546. sde_kms_info_add_keyint(info, "rc_mem_size",
  4547. catalog->dspp[0].sblk->rc.mem_total_size);
  4548. msm_property_install_blob(&sde_crtc->property_info, "capabilities",
  4549. DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
  4550. sde_kms_info_add_keyint(info, "use_baselayer_for_stage",
  4551. catalog->has_base_layer);
  4552. msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
  4553. info->data, SDE_KMS_INFO_DATALEN(info),
  4554. CRTC_PROP_INFO);
  4555. kfree(info);
  4556. }
  4557. static int _sde_crtc_get_output_fence(struct drm_crtc *crtc,
  4558. const struct drm_crtc_state *state, uint64_t *val)
  4559. {
  4560. struct sde_crtc *sde_crtc;
  4561. struct sde_crtc_state *cstate;
  4562. uint32_t offset;
  4563. bool is_vid = false;
  4564. struct drm_encoder *encoder;
  4565. sde_crtc = to_sde_crtc(crtc);
  4566. cstate = to_sde_crtc_state(state);
  4567. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  4568. if (sde_encoder_check_curr_mode(encoder,
  4569. MSM_DISPLAY_VIDEO_MODE))
  4570. is_vid = true;
  4571. if (is_vid)
  4572. break;
  4573. }
  4574. offset = sde_crtc_get_property(cstate, CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4575. /*
  4576. * Increment trigger offset for vidoe mode alone as its release fence
  4577. * can be triggered only after the next frame-update. For cmd mode &
  4578. * virtual displays the release fence for the current frame can be
  4579. * triggered right after PP_DONE/WB_DONE interrupt
  4580. */
  4581. if (is_vid)
  4582. offset++;
  4583. /*
  4584. * Hwcomposer now queries the fences using the commit list in atomic
  4585. * commit ioctl. The offset should be set to next timeline
  4586. * which will be incremented during the prepare commit phase
  4587. */
  4588. offset++;
  4589. return sde_fence_create(sde_crtc->output_fence, val, offset);
  4590. }
  4591. /**
  4592. * sde_crtc_atomic_set_property - atomically set a crtc drm property
  4593. * @crtc: Pointer to drm crtc structure
  4594. * @state: Pointer to drm crtc state structure
  4595. * @property: Pointer to targeted drm property
  4596. * @val: Updated property value
  4597. * @Returns: Zero on success
  4598. */
  4599. static int sde_crtc_atomic_set_property(struct drm_crtc *crtc,
  4600. struct drm_crtc_state *state,
  4601. struct drm_property *property,
  4602. uint64_t val)
  4603. {
  4604. struct sde_crtc *sde_crtc;
  4605. struct sde_crtc_state *cstate;
  4606. int idx, ret;
  4607. uint64_t fence_user_fd;
  4608. uint64_t __user prev_user_fd;
  4609. if (!crtc || !state || !property) {
  4610. SDE_ERROR("invalid argument(s)\n");
  4611. return -EINVAL;
  4612. }
  4613. sde_crtc = to_sde_crtc(crtc);
  4614. cstate = to_sde_crtc_state(state);
  4615. SDE_ATRACE_BEGIN("sde_crtc_atomic_set_property");
  4616. /* check with cp property system first */
  4617. ret = sde_cp_crtc_set_property(crtc, property, val);
  4618. if (ret != -ENOENT)
  4619. goto exit;
  4620. /* if not handled by cp, check msm_property system */
  4621. ret = msm_property_atomic_set(&sde_crtc->property_info,
  4622. &cstate->property_state, property, val);
  4623. if (ret)
  4624. goto exit;
  4625. idx = msm_property_index(&sde_crtc->property_info, property);
  4626. switch (idx) {
  4627. case CRTC_PROP_INPUT_FENCE_TIMEOUT:
  4628. _sde_crtc_set_input_fence_timeout(cstate);
  4629. break;
  4630. case CRTC_PROP_DIM_LAYER_V1:
  4631. _sde_crtc_set_dim_layer_v1(crtc, cstate,
  4632. (void __user *)(uintptr_t)val);
  4633. break;
  4634. case CRTC_PROP_ROI_V1:
  4635. ret = _sde_crtc_set_roi_v1(state,
  4636. (void __user *)(uintptr_t)val);
  4637. break;
  4638. case CRTC_PROP_DEST_SCALER:
  4639. ret = _sde_crtc_set_dest_scaler(sde_crtc, cstate,
  4640. (void __user *)(uintptr_t)val);
  4641. break;
  4642. case CRTC_PROP_DEST_SCALER_LUT_ED:
  4643. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  4644. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  4645. ret = _sde_crtc_set_dest_scaler_lut(sde_crtc, cstate, idx);
  4646. break;
  4647. case CRTC_PROP_CORE_CLK:
  4648. case CRTC_PROP_CORE_AB:
  4649. case CRTC_PROP_CORE_IB:
  4650. cstate->bw_control = true;
  4651. break;
  4652. case CRTC_PROP_LLCC_AB:
  4653. case CRTC_PROP_LLCC_IB:
  4654. case CRTC_PROP_DRAM_AB:
  4655. case CRTC_PROP_DRAM_IB:
  4656. cstate->bw_control = true;
  4657. cstate->bw_split_vote = true;
  4658. break;
  4659. case CRTC_PROP_OUTPUT_FENCE:
  4660. if (!val)
  4661. goto exit;
  4662. ret = copy_from_user(&prev_user_fd, (void __user *)val,
  4663. sizeof(uint64_t));
  4664. if (ret) {
  4665. SDE_ERROR("copy from user failed rc:%d\n", ret);
  4666. ret = -EFAULT;
  4667. goto exit;
  4668. }
  4669. /*
  4670. * client is expected to reset the property to -1 before
  4671. * requesting for the release fence
  4672. */
  4673. if (prev_user_fd == -1) {
  4674. ret = _sde_crtc_get_output_fence(crtc, state,
  4675. &fence_user_fd);
  4676. if (ret) {
  4677. SDE_ERROR("fence create failed rc:%d\n", ret);
  4678. goto exit;
  4679. }
  4680. ret = copy_to_user((uint64_t __user *)(uintptr_t)val,
  4681. &fence_user_fd, sizeof(uint64_t));
  4682. if (ret) {
  4683. SDE_ERROR("copy to user failed rc:%d\n", ret);
  4684. put_unused_fd(fence_user_fd);
  4685. ret = -EFAULT;
  4686. goto exit;
  4687. }
  4688. }
  4689. break;
  4690. default:
  4691. /* nothing to do */
  4692. break;
  4693. }
  4694. exit:
  4695. if (ret) {
  4696. if (ret != -EPERM)
  4697. SDE_ERROR("%s: failed to set property%d %s: %d\n",
  4698. crtc->name, DRMID(property),
  4699. property->name, ret);
  4700. else
  4701. SDE_DEBUG("%s: failed to set property%d %s: %d\n",
  4702. crtc->name, DRMID(property),
  4703. property->name, ret);
  4704. } else {
  4705. SDE_DEBUG("%s: %s[%d] <= 0x%llx\n", crtc->name, property->name,
  4706. property->base.id, val);
  4707. }
  4708. SDE_ATRACE_END("sde_crtc_atomic_set_property");
  4709. return ret;
  4710. }
  4711. void sde_crtc_set_qos_dirty(struct drm_crtc *crtc)
  4712. {
  4713. struct drm_plane *plane;
  4714. struct drm_plane_state *state;
  4715. struct sde_plane_state *pstate;
  4716. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4717. state = plane->state;
  4718. if (!state)
  4719. continue;
  4720. pstate = to_sde_plane_state(state);
  4721. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  4722. }
  4723. }
  4724. /**
  4725. * sde_crtc_atomic_get_property - retrieve a crtc drm property
  4726. * @crtc: Pointer to drm crtc structure
  4727. * @state: Pointer to drm crtc state structure
  4728. * @property: Pointer to targeted drm property
  4729. * @val: Pointer to variable for receiving property value
  4730. * @Returns: Zero on success
  4731. */
  4732. static int sde_crtc_atomic_get_property(struct drm_crtc *crtc,
  4733. const struct drm_crtc_state *state,
  4734. struct drm_property *property,
  4735. uint64_t *val)
  4736. {
  4737. struct sde_crtc *sde_crtc;
  4738. struct sde_crtc_state *cstate;
  4739. int ret = -EINVAL, i;
  4740. if (!crtc || !state) {
  4741. SDE_ERROR("invalid argument(s)\n");
  4742. goto end;
  4743. }
  4744. sde_crtc = to_sde_crtc(crtc);
  4745. cstate = to_sde_crtc_state(state);
  4746. i = msm_property_index(&sde_crtc->property_info, property);
  4747. if (i == CRTC_PROP_OUTPUT_FENCE) {
  4748. *val = ~0;
  4749. ret = 0;
  4750. } else {
  4751. ret = msm_property_atomic_get(&sde_crtc->property_info,
  4752. &cstate->property_state, property, val);
  4753. if (ret)
  4754. ret = sde_cp_crtc_get_property(crtc, property, val);
  4755. }
  4756. if (ret)
  4757. DRM_ERROR("get property failed\n");
  4758. end:
  4759. return ret;
  4760. }
  4761. int sde_crtc_helper_reset_custom_properties(struct drm_crtc *crtc,
  4762. struct drm_crtc_state *crtc_state)
  4763. {
  4764. struct sde_crtc *sde_crtc;
  4765. struct sde_crtc_state *cstate;
  4766. struct drm_property *drm_prop;
  4767. enum msm_mdp_crtc_property prop_idx;
  4768. if (!crtc || !crtc_state) {
  4769. SDE_ERROR("invalid params\n");
  4770. return -EINVAL;
  4771. }
  4772. sde_crtc = to_sde_crtc(crtc);
  4773. cstate = to_sde_crtc_state(crtc_state);
  4774. sde_cp_crtc_clear(crtc);
  4775. for (prop_idx = 0; prop_idx < CRTC_PROP_COUNT; prop_idx++) {
  4776. uint64_t val = cstate->property_values[prop_idx].value;
  4777. uint64_t def;
  4778. int ret;
  4779. drm_prop = msm_property_index_to_drm_property(
  4780. &sde_crtc->property_info, prop_idx);
  4781. if (!drm_prop) {
  4782. /* not all props will be installed, based on caps */
  4783. SDE_DEBUG("%s: invalid property index %d\n",
  4784. sde_crtc->name, prop_idx);
  4785. continue;
  4786. }
  4787. def = msm_property_get_default(&sde_crtc->property_info,
  4788. prop_idx);
  4789. if (val == def)
  4790. continue;
  4791. SDE_DEBUG("%s: set prop %s idx %d from %llu to %llu\n",
  4792. sde_crtc->name, drm_prop->name, prop_idx, val,
  4793. def);
  4794. ret = sde_crtc_atomic_set_property(crtc, crtc_state, drm_prop,
  4795. def);
  4796. if (ret) {
  4797. SDE_ERROR("%s: set property failed, idx %d ret %d\n",
  4798. sde_crtc->name, prop_idx, ret);
  4799. continue;
  4800. }
  4801. }
  4802. /* disable clk and bw control until clk & bw properties are set */
  4803. cstate->bw_control = false;
  4804. cstate->bw_split_vote = false;
  4805. return 0;
  4806. }
  4807. void sde_crtc_misr_setup(struct drm_crtc *crtc, bool enable, u32 frame_count)
  4808. {
  4809. struct sde_crtc *sde_crtc;
  4810. struct sde_crtc_mixer *m;
  4811. int i;
  4812. if (!crtc) {
  4813. SDE_ERROR("invalid argument\n");
  4814. return;
  4815. }
  4816. sde_crtc = to_sde_crtc(crtc);
  4817. if (!sde_crtc->misr_reconfigure)
  4818. return;
  4819. sde_crtc->misr_enable_sui = enable;
  4820. sde_crtc->misr_frame_count = frame_count;
  4821. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4822. m = &sde_crtc->mixers[i];
  4823. if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
  4824. continue;
  4825. m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
  4826. }
  4827. sde_crtc->misr_reconfigure = false;
  4828. }
  4829. void sde_crtc_get_misr_info(struct drm_crtc *crtc,
  4830. struct sde_crtc_misr_info *crtc_misr_info)
  4831. {
  4832. struct sde_crtc *sde_crtc;
  4833. struct sde_kms *sde_kms;
  4834. if (!crtc_misr_info) {
  4835. SDE_ERROR("invalid misr info\n");
  4836. return;
  4837. }
  4838. crtc_misr_info->misr_enable = false;
  4839. crtc_misr_info->misr_frame_count = 0;
  4840. if (!crtc) {
  4841. SDE_ERROR("invalid crtc\n");
  4842. return;
  4843. }
  4844. sde_kms = _sde_crtc_get_kms(crtc);
  4845. if (!sde_kms) {
  4846. SDE_ERROR("invalid sde_kms\n");
  4847. return;
  4848. }
  4849. if (sde_kms_is_secure_session_inprogress(sde_kms))
  4850. return;
  4851. sde_crtc = to_sde_crtc(crtc);
  4852. crtc_misr_info->misr_enable =
  4853. sde_crtc->misr_enable_debugfs ? true : false;
  4854. crtc_misr_info->misr_frame_count = sde_crtc->misr_frame_count;
  4855. }
  4856. #ifdef CONFIG_DEBUG_FS
  4857. static int _sde_debugfs_status_show(struct seq_file *s, void *data)
  4858. {
  4859. struct sde_crtc *sde_crtc;
  4860. struct sde_plane_state *pstate = NULL;
  4861. struct sde_crtc_mixer *m;
  4862. struct drm_crtc *crtc;
  4863. struct drm_plane *plane;
  4864. struct drm_display_mode *mode;
  4865. struct drm_framebuffer *fb;
  4866. struct drm_plane_state *state;
  4867. struct sde_crtc_state *cstate;
  4868. int i, out_width, out_height;
  4869. if (!s || !s->private)
  4870. return -EINVAL;
  4871. sde_crtc = s->private;
  4872. crtc = &sde_crtc->base;
  4873. cstate = to_sde_crtc_state(crtc->state);
  4874. mutex_lock(&sde_crtc->crtc_lock);
  4875. mode = &crtc->state->adjusted_mode;
  4876. out_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  4877. out_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  4878. seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
  4879. mode->hdisplay, mode->vdisplay);
  4880. seq_puts(s, "\n");
  4881. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4882. m = &sde_crtc->mixers[i];
  4883. if (!m->hw_lm)
  4884. seq_printf(s, "\tmixer[%d] has no lm\n", i);
  4885. else if (!m->hw_ctl)
  4886. seq_printf(s, "\tmixer[%d] has no ctl\n", i);
  4887. else
  4888. seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
  4889. m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
  4890. out_width, out_height);
  4891. }
  4892. seq_puts(s, "\n");
  4893. for (i = 0; i < cstate->num_dim_layers; i++) {
  4894. struct sde_hw_dim_layer *dim_layer = &cstate->dim_layer[i];
  4895. seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n",
  4896. i, dim_layer->stage, dim_layer->flags);
  4897. seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n",
  4898. dim_layer->rect.x, dim_layer->rect.y,
  4899. dim_layer->rect.w, dim_layer->rect.h);
  4900. seq_printf(s,
  4901. "\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n",
  4902. dim_layer->color_fill.color_0,
  4903. dim_layer->color_fill.color_1,
  4904. dim_layer->color_fill.color_2,
  4905. dim_layer->color_fill.color_3);
  4906. seq_puts(s, "\n");
  4907. }
  4908. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4909. pstate = to_sde_plane_state(plane->state);
  4910. state = plane->state;
  4911. if (!pstate || !state)
  4912. continue;
  4913. seq_printf(s, "\tplane:%u stage:%d rotation:%d\n",
  4914. plane->base.id, pstate->stage, pstate->rotation);
  4915. if (plane->state->fb) {
  4916. fb = plane->state->fb;
  4917. seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
  4918. fb->base.id, (char *) &fb->format->format,
  4919. fb->width, fb->height);
  4920. for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
  4921. seq_printf(s, "cpp[%d]:%u ",
  4922. i, fb->format->cpp[i]);
  4923. seq_puts(s, "\n\t");
  4924. seq_printf(s, "modifier:%8llu ", fb->modifier);
  4925. seq_puts(s, "\n");
  4926. seq_puts(s, "\t");
  4927. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
  4928. seq_printf(s, "pitches[%d]:%8u ", i,
  4929. fb->pitches[i]);
  4930. seq_puts(s, "\n");
  4931. seq_puts(s, "\t");
  4932. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
  4933. seq_printf(s, "offsets[%d]:%8u ", i,
  4934. fb->offsets[i]);
  4935. seq_puts(s, "\n");
  4936. }
  4937. seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
  4938. state->src_x >> 16, state->src_y >> 16,
  4939. state->src_w >> 16, state->src_h >> 16);
  4940. seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
  4941. state->crtc_x, state->crtc_y, state->crtc_w,
  4942. state->crtc_h);
  4943. seq_printf(s, "\tmultirect: mode: %d index: %d\n",
  4944. pstate->multirect_mode, pstate->multirect_index);
  4945. seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n",
  4946. pstate->excl_rect.x, pstate->excl_rect.y,
  4947. pstate->excl_rect.w, pstate->excl_rect.h);
  4948. seq_puts(s, "\n");
  4949. }
  4950. if (sde_crtc->vblank_cb_count) {
  4951. ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time);
  4952. u32 diff_ms = ktime_to_ms(diff);
  4953. u64 fps = diff_ms ? DIV_ROUND_CLOSEST(
  4954. sde_crtc->vblank_cb_count * 1000, diff_ms) : 0;
  4955. seq_printf(s,
  4956. "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
  4957. fps, sde_crtc->vblank_cb_count,
  4958. ktime_to_ms(diff), sde_crtc->play_count);
  4959. /* reset time & count for next measurement */
  4960. sde_crtc->vblank_cb_count = 0;
  4961. sde_crtc->vblank_cb_time = ktime_set(0, 0);
  4962. }
  4963. mutex_unlock(&sde_crtc->crtc_lock);
  4964. return 0;
  4965. }
  4966. static int _sde_debugfs_status_open(struct inode *inode, struct file *file)
  4967. {
  4968. return single_open(file, _sde_debugfs_status_show, inode->i_private);
  4969. }
  4970. static ssize_t _sde_crtc_misr_setup(struct file *file,
  4971. const char __user *user_buf, size_t count, loff_t *ppos)
  4972. {
  4973. struct drm_crtc *crtc;
  4974. struct sde_crtc *sde_crtc;
  4975. char buf[MISR_BUFF_SIZE + 1];
  4976. u32 frame_count, enable;
  4977. size_t buff_copy;
  4978. struct sde_kms *sde_kms;
  4979. if (!file || !file->private_data)
  4980. return -EINVAL;
  4981. sde_crtc = file->private_data;
  4982. crtc = &sde_crtc->base;
  4983. sde_kms = _sde_crtc_get_kms(crtc);
  4984. if (!sde_kms) {
  4985. SDE_ERROR("invalid sde_kms\n");
  4986. return -EINVAL;
  4987. }
  4988. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  4989. if (copy_from_user(buf, user_buf, buff_copy)) {
  4990. SDE_ERROR("buffer copy failed\n");
  4991. return -EINVAL;
  4992. }
  4993. buf[buff_copy] = 0; /* end of string */
  4994. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  4995. return -EINVAL;
  4996. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4997. SDE_DEBUG("crtc:%d misr enable/disable not allowed\n",
  4998. DRMID(crtc));
  4999. return -EINVAL;
  5000. }
  5001. sde_crtc->misr_enable_debugfs = enable;
  5002. sde_crtc->misr_frame_count = frame_count;
  5003. sde_crtc->misr_reconfigure = true;
  5004. return count;
  5005. }
  5006. static ssize_t _sde_crtc_misr_read(struct file *file,
  5007. char __user *user_buff, size_t count, loff_t *ppos)
  5008. {
  5009. struct drm_crtc *crtc;
  5010. struct sde_crtc *sde_crtc;
  5011. struct sde_kms *sde_kms;
  5012. struct sde_crtc_mixer *m;
  5013. int i = 0, rc;
  5014. ssize_t len = 0;
  5015. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  5016. if (*ppos)
  5017. return 0;
  5018. if (!file || !file->private_data)
  5019. return -EINVAL;
  5020. sde_crtc = file->private_data;
  5021. crtc = &sde_crtc->base;
  5022. sde_kms = _sde_crtc_get_kms(crtc);
  5023. if (!sde_kms)
  5024. return -EINVAL;
  5025. rc = pm_runtime_get_sync(crtc->dev->dev);
  5026. if (rc < 0)
  5027. return rc;
  5028. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  5029. SDE_DEBUG("crtc:%d misr read not allowed\n", DRMID(crtc));
  5030. goto end;
  5031. }
  5032. if (!sde_crtc->misr_enable_debugfs) {
  5033. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5034. "disabled\n");
  5035. goto buff_check;
  5036. }
  5037. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  5038. u32 misr_value = 0;
  5039. m = &sde_crtc->mixers[i];
  5040. if (!m->hw_lm || !m->hw_lm->ops.collect_misr) {
  5041. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5042. "invalid\n");
  5043. SDE_ERROR("crtc:%d invalid misr ops\n", DRMID(crtc));
  5044. continue;
  5045. }
  5046. rc = m->hw_lm->ops.collect_misr(m->hw_lm, false, &misr_value);
  5047. if (rc) {
  5048. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5049. "invalid\n");
  5050. SDE_ERROR("crtc:%d failed to collect misr %d\n",
  5051. DRMID(crtc), rc);
  5052. continue;
  5053. } else {
  5054. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5055. "lm idx:%d\n", m->hw_lm->idx - LM_0);
  5056. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5057. "0x%x\n", misr_value);
  5058. }
  5059. }
  5060. buff_check:
  5061. if (count <= len) {
  5062. len = 0;
  5063. goto end;
  5064. }
  5065. if (copy_to_user(user_buff, buf, len)) {
  5066. len = -EFAULT;
  5067. goto end;
  5068. }
  5069. *ppos += len; /* increase offset */
  5070. end:
  5071. pm_runtime_put_sync(crtc->dev->dev);
  5072. return len;
  5073. }
  5074. #define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \
  5075. static int __prefix ## _open(struct inode *inode, struct file *file) \
  5076. { \
  5077. return single_open(file, __prefix ## _show, inode->i_private); \
  5078. } \
  5079. static const struct file_operations __prefix ## _fops = { \
  5080. .owner = THIS_MODULE, \
  5081. .open = __prefix ## _open, \
  5082. .release = single_release, \
  5083. .read = seq_read, \
  5084. .llseek = seq_lseek, \
  5085. }
  5086. static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
  5087. {
  5088. struct drm_crtc *crtc = (struct drm_crtc *) s->private;
  5089. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  5090. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  5091. int i;
  5092. seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
  5093. seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc));
  5094. seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc,
  5095. crtc->state));
  5096. seq_printf(s, "core_clk_rate: %llu\n",
  5097. sde_crtc->cur_perf.core_clk_rate);
  5098. for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC;
  5099. i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
  5100. seq_printf(s, "bw_ctl[%s]: %llu\n",
  5101. sde_power_handle_get_dbus_name(i),
  5102. sde_crtc->cur_perf.bw_ctl[i]);
  5103. seq_printf(s, "max_per_pipe_ib[%s]: %llu\n",
  5104. sde_power_handle_get_dbus_name(i),
  5105. sde_crtc->cur_perf.max_per_pipe_ib[i]);
  5106. }
  5107. return 0;
  5108. }
  5109. DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state);
  5110. static int _sde_debugfs_fence_status_show(struct seq_file *s, void *data)
  5111. {
  5112. struct drm_crtc *crtc;
  5113. struct drm_plane *plane;
  5114. struct drm_connector *conn;
  5115. struct drm_mode_object *drm_obj;
  5116. struct sde_crtc *sde_crtc;
  5117. struct sde_crtc_state *cstate;
  5118. struct sde_fence_context *ctx;
  5119. struct drm_connector_list_iter conn_iter;
  5120. struct drm_device *dev;
  5121. if (!s || !s->private)
  5122. return -EINVAL;
  5123. sde_crtc = s->private;
  5124. crtc = &sde_crtc->base;
  5125. dev = crtc->dev;
  5126. cstate = to_sde_crtc_state(crtc->state);
  5127. /* Dump input fence info */
  5128. seq_puts(s, "===Input fence===\n");
  5129. drm_atomic_crtc_for_each_plane(plane, crtc) {
  5130. struct sde_plane_state *pstate;
  5131. struct dma_fence *fence;
  5132. pstate = to_sde_plane_state(plane->state);
  5133. if (!pstate)
  5134. continue;
  5135. seq_printf(s, "plane:%u stage:%d\n", plane->base.id,
  5136. pstate->stage);
  5137. fence = pstate->input_fence;
  5138. if (fence)
  5139. sde_fence_list_dump(fence, &s);
  5140. }
  5141. /* Dump release fence info */
  5142. seq_puts(s, "\n");
  5143. seq_puts(s, "===Release fence===\n");
  5144. ctx = sde_crtc->output_fence;
  5145. drm_obj = &crtc->base;
  5146. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  5147. seq_puts(s, "\n");
  5148. /* Dump retire fence info */
  5149. seq_puts(s, "===Retire fence===\n");
  5150. drm_connector_list_iter_begin(dev, &conn_iter);
  5151. drm_for_each_connector_iter(conn, &conn_iter)
  5152. if (conn->state && conn->state->crtc == crtc &&
  5153. cstate->num_connectors < MAX_CONNECTORS) {
  5154. struct sde_connector *c_conn;
  5155. c_conn = to_sde_connector(conn);
  5156. ctx = c_conn->retire_fence;
  5157. drm_obj = &conn->base;
  5158. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  5159. }
  5160. drm_connector_list_iter_end(&conn_iter);
  5161. seq_puts(s, "\n");
  5162. return 0;
  5163. }
  5164. static int _sde_debugfs_fence_status(struct inode *inode, struct file *file)
  5165. {
  5166. return single_open(file, _sde_debugfs_fence_status_show,
  5167. inode->i_private);
  5168. }
  5169. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  5170. {
  5171. struct sde_crtc *sde_crtc;
  5172. struct sde_kms *sde_kms;
  5173. static const struct file_operations debugfs_status_fops = {
  5174. .open = _sde_debugfs_status_open,
  5175. .read = seq_read,
  5176. .llseek = seq_lseek,
  5177. .release = single_release,
  5178. };
  5179. static const struct file_operations debugfs_misr_fops = {
  5180. .open = simple_open,
  5181. .read = _sde_crtc_misr_read,
  5182. .write = _sde_crtc_misr_setup,
  5183. };
  5184. static const struct file_operations debugfs_fps_fops = {
  5185. .open = _sde_debugfs_fps_status,
  5186. .read = seq_read,
  5187. };
  5188. static const struct file_operations debugfs_fence_fops = {
  5189. .open = _sde_debugfs_fence_status,
  5190. .read = seq_read,
  5191. };
  5192. if (!crtc)
  5193. return -EINVAL;
  5194. sde_crtc = to_sde_crtc(crtc);
  5195. sde_kms = _sde_crtc_get_kms(crtc);
  5196. if (!sde_kms)
  5197. return -EINVAL;
  5198. sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name,
  5199. crtc->dev->primary->debugfs_root);
  5200. if (!sde_crtc->debugfs_root)
  5201. return -ENOMEM;
  5202. /* don't error check these */
  5203. debugfs_create_file("status", 0400,
  5204. sde_crtc->debugfs_root,
  5205. sde_crtc, &debugfs_status_fops);
  5206. debugfs_create_file("state", 0400,
  5207. sde_crtc->debugfs_root,
  5208. &sde_crtc->base,
  5209. &sde_crtc_debugfs_state_fops);
  5210. debugfs_create_file("misr_data", 0600, sde_crtc->debugfs_root,
  5211. sde_crtc, &debugfs_misr_fops);
  5212. debugfs_create_file("fps", 0400, sde_crtc->debugfs_root,
  5213. sde_crtc, &debugfs_fps_fops);
  5214. debugfs_create_file("fence_status", 0400, sde_crtc->debugfs_root,
  5215. sde_crtc, &debugfs_fence_fops);
  5216. return 0;
  5217. }
  5218. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5219. {
  5220. struct sde_crtc *sde_crtc;
  5221. if (!crtc)
  5222. return;
  5223. sde_crtc = to_sde_crtc(crtc);
  5224. debugfs_remove_recursive(sde_crtc->debugfs_root);
  5225. }
  5226. #else
  5227. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  5228. {
  5229. return 0;
  5230. }
  5231. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5232. {
  5233. }
  5234. #endif /* CONFIG_DEBUG_FS */
  5235. static int sde_crtc_late_register(struct drm_crtc *crtc)
  5236. {
  5237. return _sde_crtc_init_debugfs(crtc);
  5238. }
  5239. static void sde_crtc_early_unregister(struct drm_crtc *crtc)
  5240. {
  5241. _sde_crtc_destroy_debugfs(crtc);
  5242. }
  5243. static const struct drm_crtc_funcs sde_crtc_funcs = {
  5244. .set_config = drm_atomic_helper_set_config,
  5245. .destroy = sde_crtc_destroy,
  5246. .page_flip = drm_atomic_helper_page_flip,
  5247. .atomic_set_property = sde_crtc_atomic_set_property,
  5248. .atomic_get_property = sde_crtc_atomic_get_property,
  5249. .reset = sde_crtc_reset,
  5250. .atomic_duplicate_state = sde_crtc_duplicate_state,
  5251. .atomic_destroy_state = sde_crtc_destroy_state,
  5252. .late_register = sde_crtc_late_register,
  5253. .early_unregister = sde_crtc_early_unregister,
  5254. };
  5255. static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = {
  5256. .mode_fixup = sde_crtc_mode_fixup,
  5257. .disable = sde_crtc_disable,
  5258. .atomic_enable = sde_crtc_enable,
  5259. .atomic_check = sde_crtc_atomic_check,
  5260. .atomic_begin = sde_crtc_atomic_begin,
  5261. .atomic_flush = sde_crtc_atomic_flush,
  5262. };
  5263. static void _sde_crtc_event_cb(struct kthread_work *work)
  5264. {
  5265. struct sde_crtc_event *event;
  5266. struct sde_crtc *sde_crtc;
  5267. unsigned long irq_flags;
  5268. if (!work) {
  5269. SDE_ERROR("invalid work item\n");
  5270. return;
  5271. }
  5272. event = container_of(work, struct sde_crtc_event, kt_work);
  5273. /* set sde_crtc to NULL for static work structures */
  5274. sde_crtc = event->sde_crtc;
  5275. if (!sde_crtc)
  5276. return;
  5277. if (event->cb_func)
  5278. event->cb_func(&sde_crtc->base, event->usr);
  5279. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5280. list_add_tail(&event->list, &sde_crtc->event_free_list);
  5281. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5282. }
  5283. int sde_crtc_event_queue(struct drm_crtc *crtc,
  5284. void (*func)(struct drm_crtc *crtc, void *usr),
  5285. void *usr, bool color_processing_event)
  5286. {
  5287. unsigned long irq_flags;
  5288. struct sde_crtc *sde_crtc;
  5289. struct msm_drm_private *priv;
  5290. struct sde_crtc_event *event = NULL;
  5291. u32 crtc_id;
  5292. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !func) {
  5293. SDE_ERROR("invalid parameters\n");
  5294. return -EINVAL;
  5295. }
  5296. sde_crtc = to_sde_crtc(crtc);
  5297. priv = crtc->dev->dev_private;
  5298. crtc_id = drm_crtc_index(crtc);
  5299. /*
  5300. * Obtain an event struct from the private cache. This event
  5301. * queue may be called from ISR contexts, so use a private
  5302. * cache to avoid calling any memory allocation functions.
  5303. */
  5304. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5305. if (!list_empty(&sde_crtc->event_free_list)) {
  5306. event = list_first_entry(&sde_crtc->event_free_list,
  5307. struct sde_crtc_event, list);
  5308. list_del_init(&event->list);
  5309. }
  5310. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5311. if (!event)
  5312. return -ENOMEM;
  5313. /* populate event node */
  5314. event->sde_crtc = sde_crtc;
  5315. event->cb_func = func;
  5316. event->usr = usr;
  5317. /* queue new event request */
  5318. kthread_init_work(&event->kt_work, _sde_crtc_event_cb);
  5319. if (color_processing_event)
  5320. kthread_queue_work(&priv->pp_event_worker,
  5321. &event->kt_work);
  5322. else
  5323. kthread_queue_work(&priv->event_thread[crtc_id].worker,
  5324. &event->kt_work);
  5325. return 0;
  5326. }
  5327. static int _sde_crtc_init_events(struct sde_crtc *sde_crtc)
  5328. {
  5329. int i, rc = 0;
  5330. if (!sde_crtc) {
  5331. SDE_ERROR("invalid crtc\n");
  5332. return -EINVAL;
  5333. }
  5334. spin_lock_init(&sde_crtc->event_lock);
  5335. INIT_LIST_HEAD(&sde_crtc->event_free_list);
  5336. for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i)
  5337. list_add_tail(&sde_crtc->event_cache[i].list,
  5338. &sde_crtc->event_free_list);
  5339. return rc;
  5340. }
  5341. void sde_crtc_static_img_control(struct drm_crtc *crtc,
  5342. enum sde_crtc_cache_state state,
  5343. bool is_vidmode)
  5344. {
  5345. struct drm_plane *plane;
  5346. struct sde_crtc *sde_crtc;
  5347. if (!crtc || !crtc->dev)
  5348. return;
  5349. sde_crtc = to_sde_crtc(crtc);
  5350. if (sde_crtc->cache_state == state)
  5351. return;
  5352. switch (state) {
  5353. case CACHE_STATE_NORMAL:
  5354. if (sde_crtc->cache_state == CACHE_STATE_DISABLED
  5355. && !is_vidmode)
  5356. return;
  5357. kthread_cancel_delayed_work_sync(
  5358. &sde_crtc->static_cache_read_work);
  5359. break;
  5360. case CACHE_STATE_PRE_CACHE:
  5361. if (sde_crtc->cache_state != CACHE_STATE_NORMAL)
  5362. return;
  5363. break;
  5364. case CACHE_STATE_FRAME_WRITE:
  5365. if (sde_crtc->cache_state != CACHE_STATE_PRE_CACHE)
  5366. return;
  5367. break;
  5368. case CACHE_STATE_FRAME_READ:
  5369. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  5370. return;
  5371. break;
  5372. case CACHE_STATE_DISABLED:
  5373. break;
  5374. default:
  5375. return;
  5376. }
  5377. sde_crtc->cache_state = state;
  5378. drm_atomic_crtc_for_each_plane(plane, crtc)
  5379. sde_plane_static_img_control(plane, state);
  5380. }
  5381. /*
  5382. * __sde_crtc_static_cache_read_work - transition to cache read
  5383. */
  5384. void __sde_crtc_static_cache_read_work(struct kthread_work *work)
  5385. {
  5386. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  5387. static_cache_read_work.work);
  5388. struct drm_crtc *crtc;
  5389. struct msm_kms *kms;
  5390. struct msm_drm_private *priv = NULL;
  5391. struct sde_crtc_mixer *mixer;
  5392. struct sde_hw_ctl *ctl;
  5393. if (!sde_crtc)
  5394. return;
  5395. crtc = &sde_crtc->base;
  5396. priv = crtc->dev->dev_private;
  5397. kms = priv->kms;
  5398. mixer = sde_crtc->mixers;
  5399. if (!mixer)
  5400. return;
  5401. ctl = mixer->hw_ctl;
  5402. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY);
  5403. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE ||
  5404. !ctl->ops.trigger_flush)
  5405. return;
  5406. sde_crtc_static_img_control(crtc, CACHE_STATE_FRAME_READ, false);
  5407. /* flush with previous commit flush bits & wait till frame done */
  5408. ctl->ops.trigger_flush(ctl);
  5409. if (kms->funcs->wait_for_crtc_commit_done)
  5410. kms->funcs->wait_for_crtc_commit_done(kms, crtc);
  5411. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  5412. }
  5413. void sde_crtc_static_cache_read_kickoff(struct drm_crtc *crtc)
  5414. {
  5415. struct drm_device *dev;
  5416. struct msm_drm_private *priv;
  5417. struct msm_drm_thread *disp_thread;
  5418. struct sde_crtc *sde_crtc;
  5419. struct sde_crtc_state *cstate;
  5420. u32 msecs_fps = 0;
  5421. if (!crtc)
  5422. return;
  5423. dev = crtc->dev;
  5424. sde_crtc = to_sde_crtc(crtc);
  5425. cstate = to_sde_crtc_state(crtc->state);
  5426. if (!dev || !dev->dev_private || !sde_crtc)
  5427. return;
  5428. priv = dev->dev_private;
  5429. disp_thread = &priv->disp_thread[crtc->index];
  5430. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  5431. return;
  5432. msecs_fps = DIV_ROUND_UP((1 * 1000), sde_crtc_get_fps_mode(crtc));
  5433. /* Kickoff transition to read state after next vblank */
  5434. kthread_queue_delayed_work(&disp_thread->worker,
  5435. &sde_crtc->static_cache_read_work,
  5436. msecs_to_jiffies(msecs_fps));
  5437. }
  5438. /*
  5439. * __sde_crtc_idle_notify_work - signal idle timeout to user space
  5440. */
  5441. static void __sde_crtc_idle_notify_work(struct kthread_work *work)
  5442. {
  5443. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  5444. idle_notify_work.work);
  5445. struct drm_crtc *crtc;
  5446. struct drm_event event;
  5447. int ret = 0;
  5448. if (!sde_crtc) {
  5449. SDE_ERROR("invalid sde crtc\n");
  5450. } else {
  5451. crtc = &sde_crtc->base;
  5452. event.type = DRM_EVENT_IDLE_NOTIFY;
  5453. event.length = sizeof(u32);
  5454. msm_mode_object_event_notify(&crtc->base, crtc->dev,
  5455. &event, (u8 *)&ret);
  5456. SDE_EVT32(DRMID(crtc));
  5457. SDE_DEBUG("crtc[%d]: idle timeout notified\n", crtc->base.id);
  5458. sde_crtc_static_img_control(crtc, CACHE_STATE_PRE_CACHE, false);
  5459. }
  5460. }
  5461. /* initialize crtc */
  5462. struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
  5463. {
  5464. struct drm_crtc *crtc = NULL;
  5465. struct sde_crtc *sde_crtc = NULL;
  5466. struct msm_drm_private *priv = NULL;
  5467. struct sde_kms *kms = NULL;
  5468. int i, rc;
  5469. priv = dev->dev_private;
  5470. kms = to_sde_kms(priv->kms);
  5471. sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL);
  5472. if (!sde_crtc)
  5473. return ERR_PTR(-ENOMEM);
  5474. crtc = &sde_crtc->base;
  5475. crtc->dev = dev;
  5476. mutex_init(&sde_crtc->crtc_lock);
  5477. spin_lock_init(&sde_crtc->spin_lock);
  5478. atomic_set(&sde_crtc->frame_pending, 0);
  5479. sde_crtc->enabled = false;
  5480. /* Below parameters are for fps calculation for sysfs node */
  5481. sde_crtc->fps_info.fps_periodic_duration = DEFAULT_FPS_PERIOD_1_SEC;
  5482. sde_crtc->fps_info.time_buf = kmalloc_array(MAX_FRAME_COUNT,
  5483. sizeof(ktime_t), GFP_KERNEL);
  5484. if (!sde_crtc->fps_info.time_buf)
  5485. SDE_ERROR("invalid buffer\n");
  5486. else
  5487. memset(sde_crtc->fps_info.time_buf, 0,
  5488. sizeof(*(sde_crtc->fps_info.time_buf)));
  5489. INIT_LIST_HEAD(&sde_crtc->frame_event_list);
  5490. INIT_LIST_HEAD(&sde_crtc->user_event_list);
  5491. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  5492. INIT_LIST_HEAD(&sde_crtc->frame_events[i].list);
  5493. list_add(&sde_crtc->frame_events[i].list,
  5494. &sde_crtc->frame_event_list);
  5495. kthread_init_work(&sde_crtc->frame_events[i].work,
  5496. sde_crtc_frame_event_work);
  5497. }
  5498. drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs,
  5499. NULL);
  5500. drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs);
  5501. /* save user friendly CRTC name for later */
  5502. snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
  5503. /* initialize event handling */
  5504. rc = _sde_crtc_init_events(sde_crtc);
  5505. if (rc) {
  5506. drm_crtc_cleanup(crtc);
  5507. kfree(sde_crtc);
  5508. return ERR_PTR(rc);
  5509. }
  5510. /* initialize output fence support */
  5511. sde_crtc->output_fence = sde_fence_init(sde_crtc->name, crtc->base.id);
  5512. if (IS_ERR(sde_crtc->output_fence)) {
  5513. rc = PTR_ERR(sde_crtc->output_fence);
  5514. SDE_ERROR("failed to init fence, %d\n", rc);
  5515. drm_crtc_cleanup(crtc);
  5516. kfree(sde_crtc);
  5517. return ERR_PTR(rc);
  5518. }
  5519. /* create CRTC properties */
  5520. msm_property_init(&sde_crtc->property_info, &crtc->base, dev,
  5521. priv->crtc_property, sde_crtc->property_data,
  5522. CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT,
  5523. sizeof(struct sde_crtc_state));
  5524. sde_crtc_install_properties(crtc, kms->catalog);
  5525. /* Install color processing properties */
  5526. sde_cp_crtc_init(crtc);
  5527. sde_cp_crtc_install_properties(crtc);
  5528. for (i = 0; i < SDE_SYS_CACHE_MAX; i++) {
  5529. sde_crtc->cur_perf.llcc_active[i] = false;
  5530. sde_crtc->new_perf.llcc_active[i] = false;
  5531. }
  5532. kthread_init_delayed_work(&sde_crtc->idle_notify_work,
  5533. __sde_crtc_idle_notify_work);
  5534. kthread_init_delayed_work(&sde_crtc->static_cache_read_work,
  5535. __sde_crtc_static_cache_read_work);
  5536. SDE_DEBUG("crtc=%d new_llcc=%d, old_llcc=%d\n",
  5537. crtc->base.id,
  5538. sde_crtc->new_perf.llcc_active,
  5539. sde_crtc->cur_perf.llcc_active);
  5540. SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name);
  5541. return crtc;
  5542. }
  5543. int sde_crtc_post_init(struct drm_device *dev, struct drm_crtc *crtc)
  5544. {
  5545. struct sde_crtc *sde_crtc;
  5546. int rc = 0;
  5547. if (!dev || !dev->primary || !dev->primary->kdev || !crtc) {
  5548. SDE_ERROR("invalid input param(s)\n");
  5549. rc = -EINVAL;
  5550. goto end;
  5551. }
  5552. sde_crtc = to_sde_crtc(crtc);
  5553. sde_crtc->sysfs_dev = device_create_with_groups(
  5554. dev->primary->kdev->class, dev->primary->kdev, 0, crtc,
  5555. sde_crtc_attr_groups, "sde-crtc-%d", crtc->index);
  5556. if (IS_ERR_OR_NULL(sde_crtc->sysfs_dev)) {
  5557. SDE_ERROR("crtc:%d sysfs create failed rc:%ld\n", crtc->index,
  5558. PTR_ERR(sde_crtc->sysfs_dev));
  5559. if (!sde_crtc->sysfs_dev)
  5560. rc = -EINVAL;
  5561. else
  5562. rc = PTR_ERR(sde_crtc->sysfs_dev);
  5563. goto end;
  5564. }
  5565. sde_crtc->vsync_event_sf = sysfs_get_dirent(
  5566. sde_crtc->sysfs_dev->kobj.sd, "vsync_event");
  5567. if (!sde_crtc->vsync_event_sf)
  5568. SDE_ERROR("crtc:%d vsync_event sysfs create failed\n",
  5569. crtc->base.id);
  5570. end:
  5571. return rc;
  5572. }
  5573. static int _sde_crtc_event_enable(struct sde_kms *kms,
  5574. struct drm_crtc *crtc_drm, u32 event)
  5575. {
  5576. struct sde_crtc *crtc = NULL;
  5577. struct sde_crtc_irq_info *node;
  5578. unsigned long flags;
  5579. bool found = false;
  5580. int ret, i = 0;
  5581. bool add_event = false;
  5582. crtc = to_sde_crtc(crtc_drm);
  5583. spin_lock_irqsave(&crtc->spin_lock, flags);
  5584. list_for_each_entry(node, &crtc->user_event_list, list) {
  5585. if (node->event == event) {
  5586. found = true;
  5587. break;
  5588. }
  5589. }
  5590. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5591. /* event already enabled */
  5592. if (found)
  5593. return 0;
  5594. node = NULL;
  5595. for (i = 0; i < ARRAY_SIZE(custom_events); i++) {
  5596. if (custom_events[i].event == event &&
  5597. custom_events[i].func) {
  5598. node = kzalloc(sizeof(*node), GFP_KERNEL);
  5599. if (!node)
  5600. return -ENOMEM;
  5601. INIT_LIST_HEAD(&node->list);
  5602. INIT_LIST_HEAD(&node->irq.list);
  5603. node->func = custom_events[i].func;
  5604. node->event = event;
  5605. node->state = IRQ_NOINIT;
  5606. spin_lock_init(&node->state_lock);
  5607. break;
  5608. }
  5609. }
  5610. if (!node) {
  5611. SDE_ERROR("unsupported event %x\n", event);
  5612. return -EINVAL;
  5613. }
  5614. ret = 0;
  5615. if (crtc_drm->enabled) {
  5616. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5617. if (ret < 0) {
  5618. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5619. kfree(node);
  5620. return ret;
  5621. }
  5622. INIT_LIST_HEAD(&node->irq.list);
  5623. mutex_lock(&crtc->crtc_lock);
  5624. ret = node->func(crtc_drm, true, &node->irq);
  5625. if (!ret) {
  5626. spin_lock_irqsave(&crtc->spin_lock, flags);
  5627. list_add_tail(&node->list, &crtc->user_event_list);
  5628. add_event = true;
  5629. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5630. }
  5631. mutex_unlock(&crtc->crtc_lock);
  5632. pm_runtime_put_sync(crtc_drm->dev->dev);
  5633. }
  5634. if (add_event)
  5635. return 0;
  5636. if (!ret) {
  5637. spin_lock_irqsave(&crtc->spin_lock, flags);
  5638. list_add_tail(&node->list, &crtc->user_event_list);
  5639. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5640. } else {
  5641. kfree(node);
  5642. }
  5643. return ret;
  5644. }
  5645. static int _sde_crtc_event_disable(struct sde_kms *kms,
  5646. struct drm_crtc *crtc_drm, u32 event)
  5647. {
  5648. struct sde_crtc *crtc = NULL;
  5649. struct sde_crtc_irq_info *node = NULL;
  5650. unsigned long flags;
  5651. bool found = false;
  5652. int ret;
  5653. crtc = to_sde_crtc(crtc_drm);
  5654. spin_lock_irqsave(&crtc->spin_lock, flags);
  5655. list_for_each_entry(node, &crtc->user_event_list, list) {
  5656. if (node->event == event) {
  5657. list_del_init(&node->list);
  5658. found = true;
  5659. break;
  5660. }
  5661. }
  5662. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5663. /* event already disabled */
  5664. if (!found)
  5665. return 0;
  5666. /**
  5667. * crtc is disabled interrupts are cleared remove from the list,
  5668. * no need to disable/de-register.
  5669. */
  5670. if (!crtc_drm->enabled) {
  5671. kfree(node);
  5672. return 0;
  5673. }
  5674. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5675. if (ret < 0) {
  5676. SDE_ERROR("failed to enable power resource %d\n", ret);
  5677. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5678. kfree(node);
  5679. return ret;
  5680. }
  5681. ret = node->func(crtc_drm, false, &node->irq);
  5682. if (ret) {
  5683. spin_lock_irqsave(&crtc->spin_lock, flags);
  5684. list_add_tail(&node->list, &crtc->user_event_list);
  5685. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5686. } else {
  5687. kfree(node);
  5688. }
  5689. pm_runtime_put_sync(crtc_drm->dev->dev);
  5690. return ret;
  5691. }
  5692. int sde_crtc_register_custom_event(struct sde_kms *kms,
  5693. struct drm_crtc *crtc_drm, u32 event, bool en)
  5694. {
  5695. struct sde_crtc *crtc = NULL;
  5696. int ret;
  5697. crtc = to_sde_crtc(crtc_drm);
  5698. if (!crtc || !kms || !kms->dev) {
  5699. DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc,
  5700. kms, ((kms) ? (kms->dev) : NULL));
  5701. return -EINVAL;
  5702. }
  5703. if (en)
  5704. ret = _sde_crtc_event_enable(kms, crtc_drm, event);
  5705. else
  5706. ret = _sde_crtc_event_disable(kms, crtc_drm, event);
  5707. return ret;
  5708. }
  5709. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  5710. bool en, struct sde_irq_callback *irq)
  5711. {
  5712. return 0;
  5713. }
  5714. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  5715. struct sde_irq_callback *noirq)
  5716. {
  5717. /*
  5718. * IRQ object noirq is not being used here since there is
  5719. * no crtc irq from pm event.
  5720. */
  5721. return 0;
  5722. }
  5723. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  5724. bool en, struct sde_irq_callback *irq)
  5725. {
  5726. return 0;
  5727. }
  5728. /**
  5729. * sde_crtc_update_cont_splash_settings - update mixer settings
  5730. * and initial clk during device bootup for cont_splash use case
  5731. * @crtc: Pointer to drm crtc structure
  5732. */
  5733. void sde_crtc_update_cont_splash_settings(struct drm_crtc *crtc)
  5734. {
  5735. struct sde_kms *kms = NULL;
  5736. struct msm_drm_private *priv;
  5737. struct sde_crtc *sde_crtc;
  5738. u64 rate;
  5739. if (!crtc || !crtc->state || !crtc->dev || !crtc->dev->dev_private) {
  5740. SDE_ERROR("invalid crtc\n");
  5741. return;
  5742. }
  5743. priv = crtc->dev->dev_private;
  5744. kms = to_sde_kms(priv->kms);
  5745. if (!kms || !kms->catalog) {
  5746. SDE_ERROR("invalid parameters\n");
  5747. return;
  5748. }
  5749. _sde_crtc_setup_mixers(crtc);
  5750. crtc->enabled = true;
  5751. /* update core clk value for initial state with cont-splash */
  5752. sde_crtc = to_sde_crtc(crtc);
  5753. rate = sde_power_clk_get_rate(&priv->phandle, kms->perf.clk_name);
  5754. sde_crtc->cur_perf.core_clk_rate = (rate > 0) ?
  5755. rate : kms->perf.max_core_clk_rate;
  5756. sde_crtc->cur_perf.core_clk_rate = kms->perf.max_core_clk_rate;
  5757. }