qcs405.c 210 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/input.h>
  21. #include <linux/of_device.h>
  22. #include <linux/pm_qos.h>
  23. #include <sound/core.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/info.h>
  29. #include <dsp/audio_notifier.h>
  30. #include <dsp/q6afe-v2.h>
  31. #include <dsp/q6core.h>
  32. #include "device_event.h"
  33. #include "msm-pcm-routing-v2.h"
  34. #include "codecs/msm-cdc-pinctrl.h"
  35. #include "codecs/wcd9335.h"
  36. #include "codecs/wsa881x.h"
  37. #include "codecs/csra66x0/csra66x0.h"
  38. #include <dt-bindings/sound/audio-codec-port-types.h>
  39. #define DRV_NAME "qcs405-asoc-snd"
  40. #define __CHIPSET__ "QCS405 "
  41. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  42. #define DEV_NAME_STR_LEN 32
  43. #define SAMPLING_RATE_8KHZ 8000
  44. #define SAMPLING_RATE_11P025KHZ 11025
  45. #define SAMPLING_RATE_16KHZ 16000
  46. #define SAMPLING_RATE_22P05KHZ 22050
  47. #define SAMPLING_RATE_32KHZ 32000
  48. #define SAMPLING_RATE_44P1KHZ 44100
  49. #define SAMPLING_RATE_48KHZ 48000
  50. #define SAMPLING_RATE_88P2KHZ 88200
  51. #define SAMPLING_RATE_96KHZ 96000
  52. #define SAMPLING_RATE_176P4KHZ 176400
  53. #define SAMPLING_RATE_192KHZ 192000
  54. #define SAMPLING_RATE_352P8KHZ 352800
  55. #define SAMPLING_RATE_384KHZ 384000
  56. #define WSA8810_NAME_1 "wsa881x.20170211"
  57. #define WSA8810_NAME_2 "wsa881x.20170212"
  58. #define WCN_CDC_SLIM_RX_CH_MAX 2
  59. #define WCN_CDC_SLIM_TX_CH_MAX 3
  60. #define TDM_CHANNEL_MAX 8
  61. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  62. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  63. enum {
  64. SLIM_RX_0 = 0,
  65. SLIM_RX_1,
  66. SLIM_RX_2,
  67. SLIM_RX_3,
  68. SLIM_RX_4,
  69. SLIM_RX_5,
  70. SLIM_RX_6,
  71. SLIM_RX_7,
  72. SLIM_RX_MAX,
  73. };
  74. enum {
  75. SLIM_TX_0 = 0,
  76. SLIM_TX_1,
  77. SLIM_TX_2,
  78. SLIM_TX_3,
  79. SLIM_TX_4,
  80. SLIM_TX_5,
  81. SLIM_TX_6,
  82. SLIM_TX_7,
  83. SLIM_TX_8,
  84. SLIM_TX_MAX,
  85. };
  86. enum {
  87. PRIM_MI2S = 0,
  88. SEC_MI2S,
  89. TERT_MI2S,
  90. QUAT_MI2S,
  91. QUIN_MI2S,
  92. MI2S_MAX,
  93. };
  94. enum {
  95. PRIM_AUX_PCM = 0,
  96. SEC_AUX_PCM,
  97. TERT_AUX_PCM,
  98. QUAT_AUX_PCM,
  99. QUIN_AUX_PCM,
  100. AUX_PCM_MAX,
  101. };
  102. enum {
  103. WSA_CDC_DMA_RX_0 = 0,
  104. WSA_CDC_DMA_RX_1,
  105. CDC_DMA_RX_MAX,
  106. };
  107. enum {
  108. WSA_CDC_DMA_TX_0 = 0,
  109. WSA_CDC_DMA_TX_1,
  110. WSA_CDC_DMA_TX_2,
  111. VA_CDC_DMA_TX_0,
  112. VA_CDC_DMA_TX_1,
  113. CDC_DMA_TX_MAX,
  114. };
  115. struct mi2s_conf {
  116. struct mutex lock;
  117. u32 ref_cnt;
  118. u32 msm_is_mi2s_master;
  119. };
  120. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  121. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  122. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  123. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  124. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  125. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  126. };
  127. struct dev_config {
  128. u32 sample_rate;
  129. u32 bit_format;
  130. u32 channels;
  131. };
  132. struct msm_wsa881x_dev_info {
  133. struct device_node *of_node;
  134. u32 index;
  135. };
  136. struct msm_csra66x0_dev_info {
  137. struct device_node *of_node;
  138. u32 index;
  139. };
  140. enum pinctrl_pin_state {
  141. STATE_DISABLE = 0, /* All pins are in sleep state */
  142. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  143. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  144. };
  145. struct msm_pinctrl_info {
  146. struct pinctrl *pinctrl;
  147. struct pinctrl_state *mi2s_disable;
  148. struct pinctrl_state *tdm_disable;
  149. struct pinctrl_state *mi2s_active;
  150. struct pinctrl_state *tdm_active;
  151. enum pinctrl_pin_state curr_state;
  152. };
  153. struct msm_asoc_mach_data {
  154. struct snd_info_entry *codec_root;
  155. struct msm_pinctrl_info pinctrl_info;
  156. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  157. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  158. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  159. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  160. int dmic_01_gpio_cnt;
  161. int dmic_23_gpio_cnt;
  162. int dmic_45_gpio_cnt;
  163. int dmic_67_gpio_cnt;
  164. };
  165. struct msm_asoc_wcd93xx_codec {
  166. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  167. enum afe_config_type config_type);
  168. };
  169. static const char *const pin_states[] = {"sleep", "i2s-active",
  170. "tdm-active"};
  171. enum {
  172. TDM_0 = 0,
  173. TDM_1,
  174. TDM_2,
  175. TDM_3,
  176. TDM_4,
  177. TDM_5,
  178. TDM_6,
  179. TDM_7,
  180. TDM_PORT_MAX,
  181. };
  182. enum {
  183. TDM_PRI = 0,
  184. TDM_SEC,
  185. TDM_TERT,
  186. TDM_QUAT,
  187. TDM_QUIN,
  188. TDM_INTERFACE_MAX,
  189. };
  190. struct tdm_port {
  191. u32 mode;
  192. u32 channel;
  193. };
  194. /* TDM default config */
  195. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  196. { /* PRI TDM */
  197. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  198. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  199. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  200. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  201. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  202. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  203. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  205. },
  206. { /* SEC TDM */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  215. },
  216. { /* TERT TDM */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  225. },
  226. { /* QUAT TDM */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  235. },
  236. { /* QUIN TDM */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  245. }
  246. };
  247. /* TDM default config */
  248. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  249. { /* PRI TDM */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  258. },
  259. { /* SEC TDM */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  268. },
  269. { /* TERT TDM */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  278. },
  279. { /* QUAT TDM */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  288. },
  289. { /* QUIN TDM */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  298. }
  299. };
  300. /* Default configuration of slimbus channels */
  301. static struct dev_config slim_rx_cfg[] = {
  302. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  303. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  304. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  305. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  306. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  307. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  308. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  309. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. };
  311. static struct dev_config slim_tx_cfg[] = {
  312. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  318. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  319. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  321. };
  322. /* Default configuration of Codec DMA Interface Tx */
  323. static struct dev_config cdc_dma_rx_cfg[] = {
  324. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  325. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  326. };
  327. /* Default configuration of Codec DMA Interface Rx */
  328. static struct dev_config cdc_dma_tx_cfg[] = {
  329. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  330. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  331. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  332. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  333. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  334. };
  335. static struct dev_config usb_rx_cfg = {
  336. .sample_rate = SAMPLING_RATE_48KHZ,
  337. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  338. .channels = 2,
  339. };
  340. static struct dev_config usb_tx_cfg = {
  341. .sample_rate = SAMPLING_RATE_48KHZ,
  342. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  343. .channels = 1,
  344. };
  345. static struct dev_config proxy_rx_cfg = {
  346. .sample_rate = SAMPLING_RATE_48KHZ,
  347. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  348. .channels = 2,
  349. };
  350. /* Default configuration of MI2S channels */
  351. static struct dev_config mi2s_rx_cfg[] = {
  352. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  353. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  354. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  355. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  356. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  357. };
  358. static struct dev_config mi2s_tx_cfg[] = {
  359. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  360. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  361. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  362. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  363. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  364. };
  365. static struct dev_config aux_pcm_rx_cfg[] = {
  366. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  367. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  368. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  369. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  370. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  371. };
  372. static struct dev_config aux_pcm_tx_cfg[] = {
  373. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  374. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  375. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  376. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  377. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. };
  379. static int msm_vi_feed_tx_ch = 2;
  380. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  381. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  382. "Five", "Six", "Seven",
  383. "Eight"};
  384. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  385. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  386. "S32_LE"};
  387. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  388. "KHZ_32", "KHZ_44P1", "KHZ_48",
  389. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  390. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  391. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  392. "KHZ_44P1", "KHZ_48",
  393. "KHZ_88P2", "KHZ_96"};
  394. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  395. "Five", "Six", "Seven",
  396. "Eight"};
  397. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  398. "Six", "Seven", "Eight"};
  399. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  400. "KHZ_16", "KHZ_22P05",
  401. "KHZ_32", "KHZ_44P1", "KHZ_48",
  402. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  403. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  404. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  405. "Five", "Six", "Seven", "Eight"};
  406. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  407. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  408. "KHZ_48", "KHZ_176P4",
  409. "KHZ_352P8"};
  410. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  411. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  412. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  413. "KHZ_48", "KHZ_96", "KHZ_192"};
  414. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  415. "Five", "Six", "Seven",
  416. "Eight"};
  417. static const char *const qos_text[] = {"Disable", "Enable"};
  418. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  419. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  420. "Five", "Six", "Seven",
  421. "Eight"};
  422. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  423. "KHZ_16", "KHZ_22P05",
  424. "KHZ_32", "KHZ_44P1", "KHZ_48",
  425. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  426. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  427. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  428. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  429. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  430. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  505. cdc_dma_sample_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  507. cdc_dma_sample_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  509. cdc_dma_sample_rate_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  511. cdc_dma_sample_rate_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  513. cdc_dma_sample_rate_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  515. cdc_dma_sample_rate_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  517. cdc_dma_sample_rate_text);
  518. static struct platform_device *spdev;
  519. static bool is_initial_boot;
  520. static bool codec_reg_done;
  521. static struct snd_soc_aux_dev *msm_aux_dev;
  522. static struct snd_soc_codec_conf *msm_codec_conf;
  523. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  524. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  525. int enable, bool dapm);
  526. static int msm_wsa881x_init(struct snd_soc_component *component);
  527. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  528. struct snd_ctl_elem_value *ucontrol);
  529. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  530. {"MIC BIAS1", NULL, "MCLK TX"},
  531. {"MIC BIAS2", NULL, "MCLK TX"},
  532. {"MIC BIAS3", NULL, "MCLK TX"},
  533. {"MIC BIAS4", NULL, "MCLK TX"},
  534. };
  535. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  536. {
  537. AFE_API_VERSION_I2S_CONFIG,
  538. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  539. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  540. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  541. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  542. 0,
  543. },
  544. {
  545. AFE_API_VERSION_I2S_CONFIG,
  546. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  547. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  548. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  549. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  550. 0,
  551. },
  552. {
  553. AFE_API_VERSION_I2S_CONFIG,
  554. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  555. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  556. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  557. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  558. 0,
  559. },
  560. {
  561. AFE_API_VERSION_I2S_CONFIG,
  562. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  563. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  564. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  565. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  566. 0,
  567. },
  568. {
  569. AFE_API_VERSION_I2S_CONFIG,
  570. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  571. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  572. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  573. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  574. 0,
  575. }
  576. };
  577. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  578. static int slim_get_sample_rate_val(int sample_rate)
  579. {
  580. int sample_rate_val = 0;
  581. switch (sample_rate) {
  582. case SAMPLING_RATE_8KHZ:
  583. sample_rate_val = 0;
  584. break;
  585. case SAMPLING_RATE_16KHZ:
  586. sample_rate_val = 1;
  587. break;
  588. case SAMPLING_RATE_32KHZ:
  589. sample_rate_val = 2;
  590. break;
  591. case SAMPLING_RATE_44P1KHZ:
  592. sample_rate_val = 3;
  593. break;
  594. case SAMPLING_RATE_48KHZ:
  595. sample_rate_val = 4;
  596. break;
  597. case SAMPLING_RATE_88P2KHZ:
  598. sample_rate_val = 5;
  599. break;
  600. case SAMPLING_RATE_96KHZ:
  601. sample_rate_val = 6;
  602. break;
  603. case SAMPLING_RATE_176P4KHZ:
  604. sample_rate_val = 7;
  605. break;
  606. case SAMPLING_RATE_192KHZ:
  607. sample_rate_val = 8;
  608. break;
  609. case SAMPLING_RATE_352P8KHZ:
  610. sample_rate_val = 9;
  611. break;
  612. case SAMPLING_RATE_384KHZ:
  613. sample_rate_val = 10;
  614. break;
  615. default:
  616. sample_rate_val = 4;
  617. break;
  618. }
  619. return sample_rate_val;
  620. }
  621. static int slim_get_sample_rate(int value)
  622. {
  623. int sample_rate = 0;
  624. switch (value) {
  625. case 0:
  626. sample_rate = SAMPLING_RATE_8KHZ;
  627. break;
  628. case 1:
  629. sample_rate = SAMPLING_RATE_16KHZ;
  630. break;
  631. case 2:
  632. sample_rate = SAMPLING_RATE_32KHZ;
  633. break;
  634. case 3:
  635. sample_rate = SAMPLING_RATE_44P1KHZ;
  636. break;
  637. case 4:
  638. sample_rate = SAMPLING_RATE_48KHZ;
  639. break;
  640. case 5:
  641. sample_rate = SAMPLING_RATE_88P2KHZ;
  642. break;
  643. case 6:
  644. sample_rate = SAMPLING_RATE_96KHZ;
  645. break;
  646. case 7:
  647. sample_rate = SAMPLING_RATE_176P4KHZ;
  648. break;
  649. case 8:
  650. sample_rate = SAMPLING_RATE_192KHZ;
  651. break;
  652. case 9:
  653. sample_rate = SAMPLING_RATE_352P8KHZ;
  654. break;
  655. case 10:
  656. sample_rate = SAMPLING_RATE_384KHZ;
  657. break;
  658. default:
  659. sample_rate = SAMPLING_RATE_48KHZ;
  660. break;
  661. }
  662. return sample_rate;
  663. }
  664. static int slim_get_bit_format_val(int bit_format)
  665. {
  666. int val = 0;
  667. switch (bit_format) {
  668. case SNDRV_PCM_FORMAT_S32_LE:
  669. val = 3;
  670. break;
  671. case SNDRV_PCM_FORMAT_S24_3LE:
  672. val = 2;
  673. break;
  674. case SNDRV_PCM_FORMAT_S24_LE:
  675. val = 1;
  676. break;
  677. case SNDRV_PCM_FORMAT_S16_LE:
  678. default:
  679. val = 0;
  680. break;
  681. }
  682. return val;
  683. }
  684. static int slim_get_bit_format(int val)
  685. {
  686. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  687. switch (val) {
  688. case 0:
  689. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  690. break;
  691. case 1:
  692. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  693. break;
  694. case 2:
  695. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  696. break;
  697. case 3:
  698. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  699. break;
  700. default:
  701. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  702. break;
  703. }
  704. return bit_fmt;
  705. }
  706. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  707. {
  708. int port_id = 0;
  709. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  710. port_id = SLIM_RX_0;
  711. } else if (strnstr(kcontrol->id.name,
  712. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  713. port_id = SLIM_RX_2;
  714. } else if (strnstr(kcontrol->id.name,
  715. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  716. port_id = SLIM_RX_5;
  717. } else if (strnstr(kcontrol->id.name,
  718. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  719. port_id = SLIM_RX_6;
  720. } else if (strnstr(kcontrol->id.name,
  721. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  722. port_id = SLIM_TX_0;
  723. } else if (strnstr(kcontrol->id.name,
  724. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  725. port_id = SLIM_TX_1;
  726. } else {
  727. pr_err("%s: unsupported channel: %s",
  728. __func__, kcontrol->id.name);
  729. return -EINVAL;
  730. }
  731. return port_id;
  732. }
  733. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  734. struct snd_ctl_elem_value *ucontrol)
  735. {
  736. int ch_num = slim_get_port_idx(kcontrol);
  737. if (ch_num < 0)
  738. return ch_num;
  739. ucontrol->value.enumerated.item[0] =
  740. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  741. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  742. ch_num, slim_rx_cfg[ch_num].sample_rate,
  743. ucontrol->value.enumerated.item[0]);
  744. return 0;
  745. }
  746. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  747. struct snd_ctl_elem_value *ucontrol)
  748. {
  749. int ch_num = slim_get_port_idx(kcontrol);
  750. if (ch_num < 0)
  751. return ch_num;
  752. slim_rx_cfg[ch_num].sample_rate =
  753. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  754. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  755. ch_num, slim_rx_cfg[ch_num].sample_rate,
  756. ucontrol->value.enumerated.item[0]);
  757. return 0;
  758. }
  759. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  760. struct snd_ctl_elem_value *ucontrol)
  761. {
  762. int ch_num = slim_get_port_idx(kcontrol);
  763. if (ch_num < 0)
  764. return ch_num;
  765. ucontrol->value.enumerated.item[0] =
  766. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  767. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  768. ch_num, slim_tx_cfg[ch_num].sample_rate,
  769. ucontrol->value.enumerated.item[0]);
  770. return 0;
  771. }
  772. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  773. struct snd_ctl_elem_value *ucontrol)
  774. {
  775. int sample_rate = 0;
  776. int ch_num = slim_get_port_idx(kcontrol);
  777. if (ch_num < 0)
  778. return ch_num;
  779. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  780. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  781. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  782. __func__, sample_rate);
  783. return -EINVAL;
  784. }
  785. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  786. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  787. ch_num, slim_tx_cfg[ch_num].sample_rate,
  788. ucontrol->value.enumerated.item[0]);
  789. return 0;
  790. }
  791. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  792. struct snd_ctl_elem_value *ucontrol)
  793. {
  794. int ch_num = slim_get_port_idx(kcontrol);
  795. if (ch_num < 0)
  796. return ch_num;
  797. ucontrol->value.enumerated.item[0] =
  798. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  799. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  800. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  801. ucontrol->value.enumerated.item[0]);
  802. return 0;
  803. }
  804. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  805. struct snd_ctl_elem_value *ucontrol)
  806. {
  807. int ch_num = slim_get_port_idx(kcontrol);
  808. if (ch_num < 0)
  809. return ch_num;
  810. slim_rx_cfg[ch_num].bit_format =
  811. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  812. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  813. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  814. ucontrol->value.enumerated.item[0]);
  815. return 0;
  816. }
  817. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  818. struct snd_ctl_elem_value *ucontrol)
  819. {
  820. int ch_num = slim_get_port_idx(kcontrol);
  821. if (ch_num < 0)
  822. return ch_num;
  823. ucontrol->value.enumerated.item[0] =
  824. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  825. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  826. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  827. ucontrol->value.enumerated.item[0]);
  828. return 0;
  829. }
  830. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  831. struct snd_ctl_elem_value *ucontrol)
  832. {
  833. int ch_num = slim_get_port_idx(kcontrol);
  834. if (ch_num < 0)
  835. return ch_num;
  836. slim_tx_cfg[ch_num].bit_format =
  837. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  838. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  839. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  840. ucontrol->value.enumerated.item[0]);
  841. return 0;
  842. }
  843. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  844. struct snd_ctl_elem_value *ucontrol)
  845. {
  846. int ch_num = slim_get_port_idx(kcontrol);
  847. if (ch_num < 0)
  848. return ch_num;
  849. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  850. ch_num, slim_rx_cfg[ch_num].channels);
  851. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  852. return 0;
  853. }
  854. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  855. struct snd_ctl_elem_value *ucontrol)
  856. {
  857. int ch_num = slim_get_port_idx(kcontrol);
  858. if (ch_num < 0)
  859. return ch_num;
  860. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  861. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  862. ch_num, slim_rx_cfg[ch_num].channels);
  863. return 1;
  864. }
  865. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  866. struct snd_ctl_elem_value *ucontrol)
  867. {
  868. int ch_num = slim_get_port_idx(kcontrol);
  869. if (ch_num < 0)
  870. return ch_num;
  871. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  872. ch_num, slim_tx_cfg[ch_num].channels);
  873. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  874. return 0;
  875. }
  876. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  877. struct snd_ctl_elem_value *ucontrol)
  878. {
  879. int ch_num = slim_get_port_idx(kcontrol);
  880. if (ch_num < 0)
  881. return ch_num;
  882. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  883. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  884. ch_num, slim_tx_cfg[ch_num].channels);
  885. return 1;
  886. }
  887. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  888. struct snd_ctl_elem_value *ucontrol)
  889. {
  890. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  891. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  892. ucontrol->value.integer.value[0]);
  893. return 0;
  894. }
  895. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  896. struct snd_ctl_elem_value *ucontrol)
  897. {
  898. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  899. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  900. return 1;
  901. }
  902. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  903. struct snd_ctl_elem_value *ucontrol)
  904. {
  905. /*
  906. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  907. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  908. * value.
  909. */
  910. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  911. case SAMPLING_RATE_96KHZ:
  912. ucontrol->value.integer.value[0] = 5;
  913. break;
  914. case SAMPLING_RATE_88P2KHZ:
  915. ucontrol->value.integer.value[0] = 4;
  916. break;
  917. case SAMPLING_RATE_48KHZ:
  918. ucontrol->value.integer.value[0] = 3;
  919. break;
  920. case SAMPLING_RATE_44P1KHZ:
  921. ucontrol->value.integer.value[0] = 2;
  922. break;
  923. case SAMPLING_RATE_16KHZ:
  924. ucontrol->value.integer.value[0] = 1;
  925. break;
  926. case SAMPLING_RATE_8KHZ:
  927. default:
  928. ucontrol->value.integer.value[0] = 0;
  929. break;
  930. }
  931. pr_debug("%s: sample rate = %d", __func__,
  932. slim_rx_cfg[SLIM_RX_7].sample_rate);
  933. return 0;
  934. }
  935. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  936. struct snd_ctl_elem_value *ucontrol)
  937. {
  938. switch (ucontrol->value.integer.value[0]) {
  939. case 1:
  940. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  941. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  942. break;
  943. case 2:
  944. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  945. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  946. break;
  947. case 3:
  948. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  949. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  950. break;
  951. case 4:
  952. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  953. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  954. break;
  955. case 5:
  956. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  957. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  958. break;
  959. case 0:
  960. default:
  961. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  962. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  963. break;
  964. }
  965. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  966. __func__,
  967. slim_rx_cfg[SLIM_RX_7].sample_rate,
  968. slim_tx_cfg[SLIM_TX_7].sample_rate,
  969. ucontrol->value.enumerated.item[0]);
  970. return 0;
  971. }
  972. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  973. {
  974. int idx = 0;
  975. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  976. sizeof("WSA_CDC_DMA_RX_0")))
  977. idx = WSA_CDC_DMA_RX_0;
  978. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  979. sizeof("WSA_CDC_DMA_RX_0")))
  980. idx = WSA_CDC_DMA_RX_1;
  981. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  982. sizeof("WSA_CDC_DMA_TX_0")))
  983. idx = WSA_CDC_DMA_TX_0;
  984. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  985. sizeof("WSA_CDC_DMA_TX_1")))
  986. idx = WSA_CDC_DMA_TX_1;
  987. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  988. sizeof("WSA_CDC_DMA_TX_2")))
  989. idx = WSA_CDC_DMA_TX_2;
  990. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  991. sizeof("VA_CDC_DMA_TX_0")))
  992. idx = VA_CDC_DMA_TX_0;
  993. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  994. sizeof("VA_CDC_DMA_TX_1")))
  995. idx = VA_CDC_DMA_TX_1;
  996. else {
  997. pr_err("%s: unsupported port: %s\n",
  998. __func__, kcontrol->id.name);
  999. return -EINVAL;
  1000. }
  1001. return idx;
  1002. }
  1003. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1004. struct snd_ctl_elem_value *ucontrol)
  1005. {
  1006. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1007. if (ch_num < 0)
  1008. return ch_num;
  1009. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1010. cdc_dma_rx_cfg[ch_num].channels - 1);
  1011. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1012. return 0;
  1013. }
  1014. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1015. struct snd_ctl_elem_value *ucontrol)
  1016. {
  1017. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1018. if (ch_num < 0)
  1019. return ch_num;
  1020. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1021. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1022. cdc_dma_rx_cfg[ch_num].channels);
  1023. return 1;
  1024. }
  1025. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1026. struct snd_ctl_elem_value *ucontrol)
  1027. {
  1028. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1029. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1030. case SNDRV_PCM_FORMAT_S32_LE:
  1031. ucontrol->value.integer.value[0] = 3;
  1032. break;
  1033. case SNDRV_PCM_FORMAT_S24_3LE:
  1034. ucontrol->value.integer.value[0] = 2;
  1035. break;
  1036. case SNDRV_PCM_FORMAT_S24_LE:
  1037. ucontrol->value.integer.value[0] = 1;
  1038. break;
  1039. case SNDRV_PCM_FORMAT_S16_LE:
  1040. default:
  1041. ucontrol->value.integer.value[0] = 0;
  1042. break;
  1043. }
  1044. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1045. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1046. ucontrol->value.integer.value[0]);
  1047. return 0;
  1048. }
  1049. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1050. struct snd_ctl_elem_value *ucontrol)
  1051. {
  1052. int rc = 0;
  1053. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1054. switch (ucontrol->value.integer.value[0]) {
  1055. case 3:
  1056. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1057. break;
  1058. case 2:
  1059. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1060. break;
  1061. case 1:
  1062. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1063. break;
  1064. case 0:
  1065. default:
  1066. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1067. break;
  1068. }
  1069. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1070. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1071. ucontrol->value.integer.value[0]);
  1072. return rc;
  1073. }
  1074. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1075. {
  1076. int sample_rate_val = 0;
  1077. switch (sample_rate) {
  1078. case SAMPLING_RATE_8KHZ:
  1079. sample_rate_val = 0;
  1080. break;
  1081. case SAMPLING_RATE_16KHZ:
  1082. sample_rate_val = 1;
  1083. break;
  1084. case SAMPLING_RATE_32KHZ:
  1085. sample_rate_val = 2;
  1086. break;
  1087. case SAMPLING_RATE_44P1KHZ:
  1088. sample_rate_val = 3;
  1089. break;
  1090. case SAMPLING_RATE_48KHZ:
  1091. sample_rate_val = 4;
  1092. break;
  1093. case SAMPLING_RATE_88P2KHZ:
  1094. sample_rate_val = 5;
  1095. break;
  1096. case SAMPLING_RATE_96KHZ:
  1097. sample_rate_val = 6;
  1098. break;
  1099. case SAMPLING_RATE_176P4KHZ:
  1100. sample_rate_val = 7;
  1101. break;
  1102. case SAMPLING_RATE_192KHZ:
  1103. sample_rate_val = 8;
  1104. break;
  1105. case SAMPLING_RATE_352P8KHZ:
  1106. sample_rate_val = 9;
  1107. break;
  1108. case SAMPLING_RATE_384KHZ:
  1109. sample_rate_val = 10;
  1110. break;
  1111. default:
  1112. sample_rate_val = 4;
  1113. break;
  1114. }
  1115. return sample_rate_val;
  1116. }
  1117. static int cdc_dma_get_sample_rate(int value)
  1118. {
  1119. int sample_rate = 0;
  1120. switch (value) {
  1121. case 0:
  1122. sample_rate = SAMPLING_RATE_8KHZ;
  1123. break;
  1124. case 1:
  1125. sample_rate = SAMPLING_RATE_16KHZ;
  1126. break;
  1127. case 2:
  1128. sample_rate = SAMPLING_RATE_32KHZ;
  1129. break;
  1130. case 3:
  1131. sample_rate = SAMPLING_RATE_44P1KHZ;
  1132. break;
  1133. case 4:
  1134. sample_rate = SAMPLING_RATE_48KHZ;
  1135. break;
  1136. case 5:
  1137. sample_rate = SAMPLING_RATE_88P2KHZ;
  1138. break;
  1139. case 6:
  1140. sample_rate = SAMPLING_RATE_96KHZ;
  1141. break;
  1142. case 7:
  1143. sample_rate = SAMPLING_RATE_176P4KHZ;
  1144. break;
  1145. case 8:
  1146. sample_rate = SAMPLING_RATE_192KHZ;
  1147. break;
  1148. case 9:
  1149. sample_rate = SAMPLING_RATE_352P8KHZ;
  1150. break;
  1151. case 10:
  1152. sample_rate = SAMPLING_RATE_384KHZ;
  1153. break;
  1154. default:
  1155. sample_rate = SAMPLING_RATE_48KHZ;
  1156. break;
  1157. }
  1158. return sample_rate;
  1159. }
  1160. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1161. struct snd_ctl_elem_value *ucontrol)
  1162. {
  1163. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1164. if (ch_num < 0)
  1165. return ch_num;
  1166. ucontrol->value.enumerated.item[0] =
  1167. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1168. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1169. cdc_dma_rx_cfg[ch_num].sample_rate);
  1170. return 0;
  1171. }
  1172. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1173. struct snd_ctl_elem_value *ucontrol)
  1174. {
  1175. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1176. if (ch_num < 0)
  1177. return ch_num;
  1178. cdc_dma_rx_cfg[ch_num].sample_rate =
  1179. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1180. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1181. __func__, ucontrol->value.enumerated.item[0],
  1182. cdc_dma_rx_cfg[ch_num].sample_rate);
  1183. return 0;
  1184. }
  1185. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1186. struct snd_ctl_elem_value *ucontrol)
  1187. {
  1188. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1189. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1190. cdc_dma_tx_cfg[ch_num].channels);
  1191. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1192. return 0;
  1193. }
  1194. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1195. struct snd_ctl_elem_value *ucontrol)
  1196. {
  1197. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1198. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1199. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1200. cdc_dma_tx_cfg[ch_num].channels);
  1201. return 1;
  1202. }
  1203. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1204. struct snd_ctl_elem_value *ucontrol)
  1205. {
  1206. int sample_rate_val;
  1207. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1208. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1209. case SAMPLING_RATE_384KHZ:
  1210. sample_rate_val = 12;
  1211. break;
  1212. case SAMPLING_RATE_352P8KHZ:
  1213. sample_rate_val = 11;
  1214. break;
  1215. case SAMPLING_RATE_192KHZ:
  1216. sample_rate_val = 10;
  1217. break;
  1218. case SAMPLING_RATE_176P4KHZ:
  1219. sample_rate_val = 9;
  1220. break;
  1221. case SAMPLING_RATE_96KHZ:
  1222. sample_rate_val = 8;
  1223. break;
  1224. case SAMPLING_RATE_88P2KHZ:
  1225. sample_rate_val = 7;
  1226. break;
  1227. case SAMPLING_RATE_48KHZ:
  1228. sample_rate_val = 6;
  1229. break;
  1230. case SAMPLING_RATE_44P1KHZ:
  1231. sample_rate_val = 5;
  1232. break;
  1233. case SAMPLING_RATE_32KHZ:
  1234. sample_rate_val = 4;
  1235. break;
  1236. case SAMPLING_RATE_22P05KHZ:
  1237. sample_rate_val = 3;
  1238. break;
  1239. case SAMPLING_RATE_16KHZ:
  1240. sample_rate_val = 2;
  1241. break;
  1242. case SAMPLING_RATE_11P025KHZ:
  1243. sample_rate_val = 1;
  1244. break;
  1245. case SAMPLING_RATE_8KHZ:
  1246. sample_rate_val = 0;
  1247. break;
  1248. default:
  1249. sample_rate_val = 6;
  1250. break;
  1251. }
  1252. ucontrol->value.integer.value[0] = sample_rate_val;
  1253. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1254. cdc_dma_tx_cfg[ch_num].sample_rate);
  1255. return 0;
  1256. }
  1257. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1258. struct snd_ctl_elem_value *ucontrol)
  1259. {
  1260. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1261. switch (ucontrol->value.integer.value[0]) {
  1262. case 12:
  1263. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1264. break;
  1265. case 11:
  1266. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1267. break;
  1268. case 10:
  1269. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1270. break;
  1271. case 9:
  1272. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1273. break;
  1274. case 8:
  1275. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1276. break;
  1277. case 7:
  1278. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1279. break;
  1280. case 6:
  1281. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1282. break;
  1283. case 5:
  1284. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1285. break;
  1286. case 4:
  1287. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1288. break;
  1289. case 3:
  1290. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1291. break;
  1292. case 2:
  1293. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1294. break;
  1295. case 1:
  1296. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1297. break;
  1298. case 0:
  1299. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1300. break;
  1301. default:
  1302. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1303. break;
  1304. }
  1305. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1306. __func__, ucontrol->value.integer.value[0],
  1307. cdc_dma_tx_cfg[ch_num].sample_rate);
  1308. return 0;
  1309. }
  1310. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1311. struct snd_ctl_elem_value *ucontrol)
  1312. {
  1313. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1314. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1315. case SNDRV_PCM_FORMAT_S32_LE:
  1316. ucontrol->value.integer.value[0] = 3;
  1317. break;
  1318. case SNDRV_PCM_FORMAT_S24_3LE:
  1319. ucontrol->value.integer.value[0] = 2;
  1320. break;
  1321. case SNDRV_PCM_FORMAT_S24_LE:
  1322. ucontrol->value.integer.value[0] = 1;
  1323. break;
  1324. case SNDRV_PCM_FORMAT_S16_LE:
  1325. default:
  1326. ucontrol->value.integer.value[0] = 0;
  1327. break;
  1328. }
  1329. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1330. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1331. ucontrol->value.integer.value[0]);
  1332. return 0;
  1333. }
  1334. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1335. struct snd_ctl_elem_value *ucontrol)
  1336. {
  1337. int rc = 0;
  1338. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1339. switch (ucontrol->value.integer.value[0]) {
  1340. case 3:
  1341. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1342. break;
  1343. case 2:
  1344. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1345. break;
  1346. case 1:
  1347. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1348. break;
  1349. case 0:
  1350. default:
  1351. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1352. break;
  1353. }
  1354. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1355. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1356. ucontrol->value.integer.value[0]);
  1357. return rc;
  1358. }
  1359. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1360. struct snd_ctl_elem_value *ucontrol)
  1361. {
  1362. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1363. usb_rx_cfg.channels);
  1364. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1365. return 0;
  1366. }
  1367. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1368. struct snd_ctl_elem_value *ucontrol)
  1369. {
  1370. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1371. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1372. return 1;
  1373. }
  1374. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1375. struct snd_ctl_elem_value *ucontrol)
  1376. {
  1377. int sample_rate_val;
  1378. switch (usb_rx_cfg.sample_rate) {
  1379. case SAMPLING_RATE_384KHZ:
  1380. sample_rate_val = 12;
  1381. break;
  1382. case SAMPLING_RATE_352P8KHZ:
  1383. sample_rate_val = 11;
  1384. break;
  1385. case SAMPLING_RATE_192KHZ:
  1386. sample_rate_val = 10;
  1387. break;
  1388. case SAMPLING_RATE_176P4KHZ:
  1389. sample_rate_val = 9;
  1390. break;
  1391. case SAMPLING_RATE_96KHZ:
  1392. sample_rate_val = 8;
  1393. break;
  1394. case SAMPLING_RATE_88P2KHZ:
  1395. sample_rate_val = 7;
  1396. break;
  1397. case SAMPLING_RATE_48KHZ:
  1398. sample_rate_val = 6;
  1399. break;
  1400. case SAMPLING_RATE_44P1KHZ:
  1401. sample_rate_val = 5;
  1402. break;
  1403. case SAMPLING_RATE_32KHZ:
  1404. sample_rate_val = 4;
  1405. break;
  1406. case SAMPLING_RATE_22P05KHZ:
  1407. sample_rate_val = 3;
  1408. break;
  1409. case SAMPLING_RATE_16KHZ:
  1410. sample_rate_val = 2;
  1411. break;
  1412. case SAMPLING_RATE_11P025KHZ:
  1413. sample_rate_val = 1;
  1414. break;
  1415. case SAMPLING_RATE_8KHZ:
  1416. default:
  1417. sample_rate_val = 0;
  1418. break;
  1419. }
  1420. ucontrol->value.integer.value[0] = sample_rate_val;
  1421. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1422. usb_rx_cfg.sample_rate);
  1423. return 0;
  1424. }
  1425. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1426. struct snd_ctl_elem_value *ucontrol)
  1427. {
  1428. switch (ucontrol->value.integer.value[0]) {
  1429. case 12:
  1430. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1431. break;
  1432. case 11:
  1433. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1434. break;
  1435. case 10:
  1436. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1437. break;
  1438. case 9:
  1439. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1440. break;
  1441. case 8:
  1442. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1443. break;
  1444. case 7:
  1445. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1446. break;
  1447. case 6:
  1448. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1449. break;
  1450. case 5:
  1451. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1452. break;
  1453. case 4:
  1454. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1455. break;
  1456. case 3:
  1457. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1458. break;
  1459. case 2:
  1460. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1461. break;
  1462. case 1:
  1463. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1464. break;
  1465. case 0:
  1466. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1467. break;
  1468. default:
  1469. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1470. break;
  1471. }
  1472. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1473. __func__, ucontrol->value.integer.value[0],
  1474. usb_rx_cfg.sample_rate);
  1475. return 0;
  1476. }
  1477. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1478. struct snd_ctl_elem_value *ucontrol)
  1479. {
  1480. switch (usb_rx_cfg.bit_format) {
  1481. case SNDRV_PCM_FORMAT_S32_LE:
  1482. ucontrol->value.integer.value[0] = 3;
  1483. break;
  1484. case SNDRV_PCM_FORMAT_S24_3LE:
  1485. ucontrol->value.integer.value[0] = 2;
  1486. break;
  1487. case SNDRV_PCM_FORMAT_S24_LE:
  1488. ucontrol->value.integer.value[0] = 1;
  1489. break;
  1490. case SNDRV_PCM_FORMAT_S16_LE:
  1491. default:
  1492. ucontrol->value.integer.value[0] = 0;
  1493. break;
  1494. }
  1495. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1496. __func__, usb_rx_cfg.bit_format,
  1497. ucontrol->value.integer.value[0]);
  1498. return 0;
  1499. }
  1500. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1501. struct snd_ctl_elem_value *ucontrol)
  1502. {
  1503. int rc = 0;
  1504. switch (ucontrol->value.integer.value[0]) {
  1505. case 3:
  1506. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1507. break;
  1508. case 2:
  1509. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1510. break;
  1511. case 1:
  1512. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1513. break;
  1514. case 0:
  1515. default:
  1516. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1517. break;
  1518. }
  1519. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1520. __func__, usb_rx_cfg.bit_format,
  1521. ucontrol->value.integer.value[0]);
  1522. return rc;
  1523. }
  1524. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1525. struct snd_ctl_elem_value *ucontrol)
  1526. {
  1527. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1528. usb_tx_cfg.channels);
  1529. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1530. return 0;
  1531. }
  1532. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1533. struct snd_ctl_elem_value *ucontrol)
  1534. {
  1535. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1536. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1537. return 1;
  1538. }
  1539. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1540. struct snd_ctl_elem_value *ucontrol)
  1541. {
  1542. int sample_rate_val;
  1543. switch (usb_tx_cfg.sample_rate) {
  1544. case SAMPLING_RATE_384KHZ:
  1545. sample_rate_val = 12;
  1546. break;
  1547. case SAMPLING_RATE_352P8KHZ:
  1548. sample_rate_val = 11;
  1549. break;
  1550. case SAMPLING_RATE_192KHZ:
  1551. sample_rate_val = 10;
  1552. break;
  1553. case SAMPLING_RATE_176P4KHZ:
  1554. sample_rate_val = 9;
  1555. break;
  1556. case SAMPLING_RATE_96KHZ:
  1557. sample_rate_val = 8;
  1558. break;
  1559. case SAMPLING_RATE_88P2KHZ:
  1560. sample_rate_val = 7;
  1561. break;
  1562. case SAMPLING_RATE_48KHZ:
  1563. sample_rate_val = 6;
  1564. break;
  1565. case SAMPLING_RATE_44P1KHZ:
  1566. sample_rate_val = 5;
  1567. break;
  1568. case SAMPLING_RATE_32KHZ:
  1569. sample_rate_val = 4;
  1570. break;
  1571. case SAMPLING_RATE_22P05KHZ:
  1572. sample_rate_val = 3;
  1573. break;
  1574. case SAMPLING_RATE_16KHZ:
  1575. sample_rate_val = 2;
  1576. break;
  1577. case SAMPLING_RATE_11P025KHZ:
  1578. sample_rate_val = 1;
  1579. break;
  1580. case SAMPLING_RATE_8KHZ:
  1581. sample_rate_val = 0;
  1582. break;
  1583. default:
  1584. sample_rate_val = 6;
  1585. break;
  1586. }
  1587. ucontrol->value.integer.value[0] = sample_rate_val;
  1588. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1589. usb_tx_cfg.sample_rate);
  1590. return 0;
  1591. }
  1592. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1593. struct snd_ctl_elem_value *ucontrol)
  1594. {
  1595. switch (ucontrol->value.integer.value[0]) {
  1596. case 12:
  1597. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1598. break;
  1599. case 11:
  1600. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1601. break;
  1602. case 10:
  1603. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1604. break;
  1605. case 9:
  1606. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1607. break;
  1608. case 8:
  1609. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1610. break;
  1611. case 7:
  1612. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1613. break;
  1614. case 6:
  1615. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1616. break;
  1617. case 5:
  1618. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1619. break;
  1620. case 4:
  1621. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1622. break;
  1623. case 3:
  1624. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1625. break;
  1626. case 2:
  1627. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1628. break;
  1629. case 1:
  1630. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1631. break;
  1632. case 0:
  1633. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1634. break;
  1635. default:
  1636. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1637. break;
  1638. }
  1639. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1640. __func__, ucontrol->value.integer.value[0],
  1641. usb_tx_cfg.sample_rate);
  1642. return 0;
  1643. }
  1644. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1645. struct snd_ctl_elem_value *ucontrol)
  1646. {
  1647. switch (usb_tx_cfg.bit_format) {
  1648. case SNDRV_PCM_FORMAT_S32_LE:
  1649. ucontrol->value.integer.value[0] = 3;
  1650. break;
  1651. case SNDRV_PCM_FORMAT_S24_3LE:
  1652. ucontrol->value.integer.value[0] = 2;
  1653. break;
  1654. case SNDRV_PCM_FORMAT_S24_LE:
  1655. ucontrol->value.integer.value[0] = 1;
  1656. break;
  1657. case SNDRV_PCM_FORMAT_S16_LE:
  1658. default:
  1659. ucontrol->value.integer.value[0] = 0;
  1660. break;
  1661. }
  1662. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1663. __func__, usb_tx_cfg.bit_format,
  1664. ucontrol->value.integer.value[0]);
  1665. return 0;
  1666. }
  1667. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1668. struct snd_ctl_elem_value *ucontrol)
  1669. {
  1670. int rc = 0;
  1671. switch (ucontrol->value.integer.value[0]) {
  1672. case 3:
  1673. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1674. break;
  1675. case 2:
  1676. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1677. break;
  1678. case 1:
  1679. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1680. break;
  1681. case 0:
  1682. default:
  1683. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1684. break;
  1685. }
  1686. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1687. __func__, usb_tx_cfg.bit_format,
  1688. ucontrol->value.integer.value[0]);
  1689. return rc;
  1690. }
  1691. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1692. struct snd_ctl_elem_value *ucontrol)
  1693. {
  1694. pr_debug("%s: proxy_rx channels = %d\n",
  1695. __func__, proxy_rx_cfg.channels);
  1696. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1697. return 0;
  1698. }
  1699. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1700. struct snd_ctl_elem_value *ucontrol)
  1701. {
  1702. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1703. pr_debug("%s: proxy_rx channels = %d\n",
  1704. __func__, proxy_rx_cfg.channels);
  1705. return 1;
  1706. }
  1707. static int tdm_get_sample_rate(int value)
  1708. {
  1709. int sample_rate = 0;
  1710. switch (value) {
  1711. case 0:
  1712. sample_rate = SAMPLING_RATE_8KHZ;
  1713. break;
  1714. case 1:
  1715. sample_rate = SAMPLING_RATE_16KHZ;
  1716. break;
  1717. case 2:
  1718. sample_rate = SAMPLING_RATE_32KHZ;
  1719. break;
  1720. case 3:
  1721. sample_rate = SAMPLING_RATE_48KHZ;
  1722. break;
  1723. case 4:
  1724. sample_rate = SAMPLING_RATE_176P4KHZ;
  1725. break;
  1726. case 5:
  1727. sample_rate = SAMPLING_RATE_352P8KHZ;
  1728. break;
  1729. default:
  1730. sample_rate = SAMPLING_RATE_48KHZ;
  1731. break;
  1732. }
  1733. return sample_rate;
  1734. }
  1735. static int aux_pcm_get_sample_rate(int value)
  1736. {
  1737. int sample_rate;
  1738. switch (value) {
  1739. case 1:
  1740. sample_rate = SAMPLING_RATE_16KHZ;
  1741. break;
  1742. case 0:
  1743. default:
  1744. sample_rate = SAMPLING_RATE_8KHZ;
  1745. break;
  1746. }
  1747. return sample_rate;
  1748. }
  1749. static int tdm_get_sample_rate_val(int sample_rate)
  1750. {
  1751. int sample_rate_val = 0;
  1752. switch (sample_rate) {
  1753. case SAMPLING_RATE_8KHZ:
  1754. sample_rate_val = 0;
  1755. break;
  1756. case SAMPLING_RATE_16KHZ:
  1757. sample_rate_val = 1;
  1758. break;
  1759. case SAMPLING_RATE_32KHZ:
  1760. sample_rate_val = 2;
  1761. break;
  1762. case SAMPLING_RATE_48KHZ:
  1763. sample_rate_val = 3;
  1764. break;
  1765. case SAMPLING_RATE_176P4KHZ:
  1766. sample_rate_val = 4;
  1767. break;
  1768. case SAMPLING_RATE_352P8KHZ:
  1769. sample_rate_val = 5;
  1770. break;
  1771. default:
  1772. sample_rate_val = 3;
  1773. break;
  1774. }
  1775. return sample_rate_val;
  1776. }
  1777. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1778. {
  1779. int sample_rate_val;
  1780. switch (sample_rate) {
  1781. case SAMPLING_RATE_16KHZ:
  1782. sample_rate_val = 1;
  1783. break;
  1784. case SAMPLING_RATE_8KHZ:
  1785. default:
  1786. sample_rate_val = 0;
  1787. break;
  1788. }
  1789. return sample_rate_val;
  1790. }
  1791. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1792. struct tdm_port *port)
  1793. {
  1794. if (port) {
  1795. if (strnstr(kcontrol->id.name, "PRI",
  1796. sizeof(kcontrol->id.name))) {
  1797. port->mode = TDM_PRI;
  1798. } else if (strnstr(kcontrol->id.name, "SEC",
  1799. sizeof(kcontrol->id.name))) {
  1800. port->mode = TDM_SEC;
  1801. } else if (strnstr(kcontrol->id.name, "TERT",
  1802. sizeof(kcontrol->id.name))) {
  1803. port->mode = TDM_TERT;
  1804. } else if (strnstr(kcontrol->id.name, "QUAT",
  1805. sizeof(kcontrol->id.name))) {
  1806. port->mode = TDM_QUAT;
  1807. } else if (strnstr(kcontrol->id.name, "QUIN",
  1808. sizeof(kcontrol->id.name))) {
  1809. port->mode = TDM_QUIN;
  1810. } else {
  1811. pr_err("%s: unsupported mode in: %s",
  1812. __func__, kcontrol->id.name);
  1813. return -EINVAL;
  1814. }
  1815. if (strnstr(kcontrol->id.name, "RX_0",
  1816. sizeof(kcontrol->id.name)) ||
  1817. strnstr(kcontrol->id.name, "TX_0",
  1818. sizeof(kcontrol->id.name))) {
  1819. port->channel = TDM_0;
  1820. } else if (strnstr(kcontrol->id.name, "RX_1",
  1821. sizeof(kcontrol->id.name)) ||
  1822. strnstr(kcontrol->id.name, "TX_1",
  1823. sizeof(kcontrol->id.name))) {
  1824. port->channel = TDM_1;
  1825. } else if (strnstr(kcontrol->id.name, "RX_2",
  1826. sizeof(kcontrol->id.name)) ||
  1827. strnstr(kcontrol->id.name, "TX_2",
  1828. sizeof(kcontrol->id.name))) {
  1829. port->channel = TDM_2;
  1830. } else if (strnstr(kcontrol->id.name, "RX_3",
  1831. sizeof(kcontrol->id.name)) ||
  1832. strnstr(kcontrol->id.name, "TX_3",
  1833. sizeof(kcontrol->id.name))) {
  1834. port->channel = TDM_3;
  1835. } else if (strnstr(kcontrol->id.name, "RX_4",
  1836. sizeof(kcontrol->id.name)) ||
  1837. strnstr(kcontrol->id.name, "TX_4",
  1838. sizeof(kcontrol->id.name))) {
  1839. port->channel = TDM_4;
  1840. } else if (strnstr(kcontrol->id.name, "RX_5",
  1841. sizeof(kcontrol->id.name)) ||
  1842. strnstr(kcontrol->id.name, "TX_5",
  1843. sizeof(kcontrol->id.name))) {
  1844. port->channel = TDM_5;
  1845. } else if (strnstr(kcontrol->id.name, "RX_6",
  1846. sizeof(kcontrol->id.name)) ||
  1847. strnstr(kcontrol->id.name, "TX_6",
  1848. sizeof(kcontrol->id.name))) {
  1849. port->channel = TDM_6;
  1850. } else if (strnstr(kcontrol->id.name, "RX_7",
  1851. sizeof(kcontrol->id.name)) ||
  1852. strnstr(kcontrol->id.name, "TX_7",
  1853. sizeof(kcontrol->id.name))) {
  1854. port->channel = TDM_7;
  1855. } else {
  1856. pr_err("%s: unsupported channel in: %s",
  1857. __func__, kcontrol->id.name);
  1858. return -EINVAL;
  1859. }
  1860. } else
  1861. return -EINVAL;
  1862. return 0;
  1863. }
  1864. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1865. struct snd_ctl_elem_value *ucontrol)
  1866. {
  1867. struct tdm_port port;
  1868. int ret = tdm_get_port_idx(kcontrol, &port);
  1869. if (ret) {
  1870. pr_err("%s: unsupported control: %s",
  1871. __func__, kcontrol->id.name);
  1872. } else {
  1873. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1874. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1875. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1876. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1877. ucontrol->value.enumerated.item[0]);
  1878. }
  1879. return ret;
  1880. }
  1881. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1882. struct snd_ctl_elem_value *ucontrol)
  1883. {
  1884. struct tdm_port port;
  1885. int ret = tdm_get_port_idx(kcontrol, &port);
  1886. if (ret) {
  1887. pr_err("%s: unsupported control: %s",
  1888. __func__, kcontrol->id.name);
  1889. } else {
  1890. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1891. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1892. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1893. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1894. ucontrol->value.enumerated.item[0]);
  1895. }
  1896. return ret;
  1897. }
  1898. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1899. struct snd_ctl_elem_value *ucontrol)
  1900. {
  1901. struct tdm_port port;
  1902. int ret = tdm_get_port_idx(kcontrol, &port);
  1903. if (ret) {
  1904. pr_err("%s: unsupported control: %s",
  1905. __func__, kcontrol->id.name);
  1906. } else {
  1907. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1908. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1909. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1910. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1911. ucontrol->value.enumerated.item[0]);
  1912. }
  1913. return ret;
  1914. }
  1915. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1916. struct snd_ctl_elem_value *ucontrol)
  1917. {
  1918. struct tdm_port port;
  1919. int ret = tdm_get_port_idx(kcontrol, &port);
  1920. if (ret) {
  1921. pr_err("%s: unsupported control: %s",
  1922. __func__, kcontrol->id.name);
  1923. } else {
  1924. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1925. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1926. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1927. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1928. ucontrol->value.enumerated.item[0]);
  1929. }
  1930. return ret;
  1931. }
  1932. static int tdm_get_format(int value)
  1933. {
  1934. int format = 0;
  1935. switch (value) {
  1936. case 0:
  1937. format = SNDRV_PCM_FORMAT_S16_LE;
  1938. break;
  1939. case 1:
  1940. format = SNDRV_PCM_FORMAT_S24_LE;
  1941. break;
  1942. case 2:
  1943. format = SNDRV_PCM_FORMAT_S32_LE;
  1944. break;
  1945. default:
  1946. format = SNDRV_PCM_FORMAT_S16_LE;
  1947. break;
  1948. }
  1949. return format;
  1950. }
  1951. static int tdm_get_format_val(int format)
  1952. {
  1953. int value = 0;
  1954. switch (format) {
  1955. case SNDRV_PCM_FORMAT_S16_LE:
  1956. value = 0;
  1957. break;
  1958. case SNDRV_PCM_FORMAT_S24_LE:
  1959. value = 1;
  1960. break;
  1961. case SNDRV_PCM_FORMAT_S32_LE:
  1962. value = 2;
  1963. break;
  1964. default:
  1965. value = 0;
  1966. break;
  1967. }
  1968. return value;
  1969. }
  1970. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1971. struct snd_ctl_elem_value *ucontrol)
  1972. {
  1973. struct tdm_port port;
  1974. int ret = tdm_get_port_idx(kcontrol, &port);
  1975. if (ret) {
  1976. pr_err("%s: unsupported control: %s",
  1977. __func__, kcontrol->id.name);
  1978. } else {
  1979. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1980. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1981. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1982. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1983. ucontrol->value.enumerated.item[0]);
  1984. }
  1985. return ret;
  1986. }
  1987. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1988. struct snd_ctl_elem_value *ucontrol)
  1989. {
  1990. struct tdm_port port;
  1991. int ret = tdm_get_port_idx(kcontrol, &port);
  1992. if (ret) {
  1993. pr_err("%s: unsupported control: %s",
  1994. __func__, kcontrol->id.name);
  1995. } else {
  1996. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1997. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1998. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1999. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2000. ucontrol->value.enumerated.item[0]);
  2001. }
  2002. return ret;
  2003. }
  2004. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2005. struct snd_ctl_elem_value *ucontrol)
  2006. {
  2007. struct tdm_port port;
  2008. int ret = tdm_get_port_idx(kcontrol, &port);
  2009. if (ret) {
  2010. pr_err("%s: unsupported control: %s",
  2011. __func__, kcontrol->id.name);
  2012. } else {
  2013. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2014. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2015. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2016. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2017. ucontrol->value.enumerated.item[0]);
  2018. }
  2019. return ret;
  2020. }
  2021. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2022. struct snd_ctl_elem_value *ucontrol)
  2023. {
  2024. struct tdm_port port;
  2025. int ret = tdm_get_port_idx(kcontrol, &port);
  2026. if (ret) {
  2027. pr_err("%s: unsupported control: %s",
  2028. __func__, kcontrol->id.name);
  2029. } else {
  2030. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2031. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2032. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2033. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2034. ucontrol->value.enumerated.item[0]);
  2035. }
  2036. return ret;
  2037. }
  2038. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2039. struct snd_ctl_elem_value *ucontrol)
  2040. {
  2041. struct tdm_port port;
  2042. int ret = tdm_get_port_idx(kcontrol, &port);
  2043. if (ret) {
  2044. pr_err("%s: unsupported control: %s",
  2045. __func__, kcontrol->id.name);
  2046. } else {
  2047. ucontrol->value.enumerated.item[0] =
  2048. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2049. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2050. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2051. ucontrol->value.enumerated.item[0]);
  2052. }
  2053. return ret;
  2054. }
  2055. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2056. struct snd_ctl_elem_value *ucontrol)
  2057. {
  2058. struct tdm_port port;
  2059. int ret = tdm_get_port_idx(kcontrol, &port);
  2060. if (ret) {
  2061. pr_err("%s: unsupported control: %s",
  2062. __func__, kcontrol->id.name);
  2063. } else {
  2064. tdm_rx_cfg[port.mode][port.channel].channels =
  2065. ucontrol->value.enumerated.item[0] + 1;
  2066. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2067. tdm_rx_cfg[port.mode][port.channel].channels,
  2068. ucontrol->value.enumerated.item[0] + 1);
  2069. }
  2070. return ret;
  2071. }
  2072. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2073. struct snd_ctl_elem_value *ucontrol)
  2074. {
  2075. struct tdm_port port;
  2076. int ret = tdm_get_port_idx(kcontrol, &port);
  2077. if (ret) {
  2078. pr_err("%s: unsupported control: %s",
  2079. __func__, kcontrol->id.name);
  2080. } else {
  2081. ucontrol->value.enumerated.item[0] =
  2082. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2083. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2084. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2085. ucontrol->value.enumerated.item[0]);
  2086. }
  2087. return ret;
  2088. }
  2089. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2090. struct snd_ctl_elem_value *ucontrol)
  2091. {
  2092. struct tdm_port port;
  2093. int ret = tdm_get_port_idx(kcontrol, &port);
  2094. if (ret) {
  2095. pr_err("%s: unsupported control: %s",
  2096. __func__, kcontrol->id.name);
  2097. } else {
  2098. tdm_tx_cfg[port.mode][port.channel].channels =
  2099. ucontrol->value.enumerated.item[0] + 1;
  2100. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2101. tdm_tx_cfg[port.mode][port.channel].channels,
  2102. ucontrol->value.enumerated.item[0] + 1);
  2103. }
  2104. return ret;
  2105. }
  2106. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2107. {
  2108. int idx;
  2109. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2110. sizeof("PRIM_AUX_PCM")))
  2111. idx = PRIM_AUX_PCM;
  2112. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2113. sizeof("SEC_AUX_PCM")))
  2114. idx = SEC_AUX_PCM;
  2115. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2116. sizeof("TERT_AUX_PCM")))
  2117. idx = TERT_AUX_PCM;
  2118. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2119. sizeof("QUAT_AUX_PCM")))
  2120. idx = QUAT_AUX_PCM;
  2121. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2122. sizeof("QUIN_AUX_PCM")))
  2123. idx = QUIN_AUX_PCM;
  2124. else {
  2125. pr_err("%s: unsupported port: %s",
  2126. __func__, kcontrol->id.name);
  2127. idx = -EINVAL;
  2128. }
  2129. return idx;
  2130. }
  2131. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2132. struct snd_ctl_elem_value *ucontrol)
  2133. {
  2134. int idx = aux_pcm_get_port_idx(kcontrol);
  2135. if (idx < 0)
  2136. return idx;
  2137. aux_pcm_rx_cfg[idx].sample_rate =
  2138. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2139. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2140. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2141. ucontrol->value.enumerated.item[0]);
  2142. return 0;
  2143. }
  2144. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2145. struct snd_ctl_elem_value *ucontrol)
  2146. {
  2147. int idx = aux_pcm_get_port_idx(kcontrol);
  2148. if (idx < 0)
  2149. return idx;
  2150. ucontrol->value.enumerated.item[0] =
  2151. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2152. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2153. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2154. ucontrol->value.enumerated.item[0]);
  2155. return 0;
  2156. }
  2157. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2158. struct snd_ctl_elem_value *ucontrol)
  2159. {
  2160. int idx = aux_pcm_get_port_idx(kcontrol);
  2161. if (idx < 0)
  2162. return idx;
  2163. aux_pcm_tx_cfg[idx].sample_rate =
  2164. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2165. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2166. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2167. ucontrol->value.enumerated.item[0]);
  2168. return 0;
  2169. }
  2170. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2171. struct snd_ctl_elem_value *ucontrol)
  2172. {
  2173. int idx = aux_pcm_get_port_idx(kcontrol);
  2174. if (idx < 0)
  2175. return idx;
  2176. ucontrol->value.enumerated.item[0] =
  2177. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2178. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2179. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2180. ucontrol->value.enumerated.item[0]);
  2181. return 0;
  2182. }
  2183. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2184. {
  2185. int idx;
  2186. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2187. sizeof("PRIM_MI2S_RX")))
  2188. idx = PRIM_MI2S;
  2189. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2190. sizeof("SEC_MI2S_RX")))
  2191. idx = SEC_MI2S;
  2192. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2193. sizeof("TERT_MI2S_RX")))
  2194. idx = TERT_MI2S;
  2195. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2196. sizeof("QUAT_MI2S_RX")))
  2197. idx = QUAT_MI2S;
  2198. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2199. sizeof("QUIN_MI2S_RX")))
  2200. idx = QUIN_MI2S;
  2201. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2202. sizeof("PRIM_MI2S_TX")))
  2203. idx = PRIM_MI2S;
  2204. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2205. sizeof("SEC_MI2S_TX")))
  2206. idx = SEC_MI2S;
  2207. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2208. sizeof("TERT_MI2S_TX")))
  2209. idx = TERT_MI2S;
  2210. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2211. sizeof("QUAT_MI2S_TX")))
  2212. idx = QUAT_MI2S;
  2213. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2214. sizeof("QUIN_MI2S_TX")))
  2215. idx = QUIN_MI2S;
  2216. else {
  2217. pr_err("%s: unsupported channel: %s",
  2218. __func__, kcontrol->id.name);
  2219. idx = -EINVAL;
  2220. }
  2221. return idx;
  2222. }
  2223. static int mi2s_get_sample_rate_val(int sample_rate)
  2224. {
  2225. int sample_rate_val;
  2226. switch (sample_rate) {
  2227. case SAMPLING_RATE_8KHZ:
  2228. sample_rate_val = 0;
  2229. break;
  2230. case SAMPLING_RATE_11P025KHZ:
  2231. sample_rate_val = 1;
  2232. break;
  2233. case SAMPLING_RATE_16KHZ:
  2234. sample_rate_val = 2;
  2235. break;
  2236. case SAMPLING_RATE_22P05KHZ:
  2237. sample_rate_val = 3;
  2238. break;
  2239. case SAMPLING_RATE_32KHZ:
  2240. sample_rate_val = 4;
  2241. break;
  2242. case SAMPLING_RATE_44P1KHZ:
  2243. sample_rate_val = 5;
  2244. break;
  2245. case SAMPLING_RATE_48KHZ:
  2246. sample_rate_val = 6;
  2247. break;
  2248. case SAMPLING_RATE_96KHZ:
  2249. sample_rate_val = 7;
  2250. break;
  2251. case SAMPLING_RATE_192KHZ:
  2252. sample_rate_val = 8;
  2253. break;
  2254. default:
  2255. sample_rate_val = 6;
  2256. break;
  2257. }
  2258. return sample_rate_val;
  2259. }
  2260. static int mi2s_get_sample_rate(int value)
  2261. {
  2262. int sample_rate;
  2263. switch (value) {
  2264. case 0:
  2265. sample_rate = SAMPLING_RATE_8KHZ;
  2266. break;
  2267. case 1:
  2268. sample_rate = SAMPLING_RATE_11P025KHZ;
  2269. break;
  2270. case 2:
  2271. sample_rate = SAMPLING_RATE_16KHZ;
  2272. break;
  2273. case 3:
  2274. sample_rate = SAMPLING_RATE_22P05KHZ;
  2275. break;
  2276. case 4:
  2277. sample_rate = SAMPLING_RATE_32KHZ;
  2278. break;
  2279. case 5:
  2280. sample_rate = SAMPLING_RATE_44P1KHZ;
  2281. break;
  2282. case 6:
  2283. sample_rate = SAMPLING_RATE_48KHZ;
  2284. break;
  2285. case 7:
  2286. sample_rate = SAMPLING_RATE_96KHZ;
  2287. break;
  2288. case 8:
  2289. sample_rate = SAMPLING_RATE_192KHZ;
  2290. break;
  2291. default:
  2292. sample_rate = SAMPLING_RATE_48KHZ;
  2293. break;
  2294. }
  2295. return sample_rate;
  2296. }
  2297. static int mi2s_auxpcm_get_format(int value)
  2298. {
  2299. int format;
  2300. switch (value) {
  2301. case 0:
  2302. format = SNDRV_PCM_FORMAT_S16_LE;
  2303. break;
  2304. case 1:
  2305. format = SNDRV_PCM_FORMAT_S24_LE;
  2306. break;
  2307. case 2:
  2308. format = SNDRV_PCM_FORMAT_S24_3LE;
  2309. break;
  2310. case 3:
  2311. format = SNDRV_PCM_FORMAT_S32_LE;
  2312. break;
  2313. default:
  2314. format = SNDRV_PCM_FORMAT_S16_LE;
  2315. break;
  2316. }
  2317. return format;
  2318. }
  2319. static int mi2s_auxpcm_get_format_value(int format)
  2320. {
  2321. int value;
  2322. switch (format) {
  2323. case SNDRV_PCM_FORMAT_S16_LE:
  2324. value = 0;
  2325. break;
  2326. case SNDRV_PCM_FORMAT_S24_LE:
  2327. value = 1;
  2328. break;
  2329. case SNDRV_PCM_FORMAT_S24_3LE:
  2330. value = 2;
  2331. break;
  2332. case SNDRV_PCM_FORMAT_S32_LE:
  2333. value = 3;
  2334. break;
  2335. default:
  2336. value = 0;
  2337. break;
  2338. }
  2339. return value;
  2340. }
  2341. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2342. struct snd_ctl_elem_value *ucontrol)
  2343. {
  2344. int idx = mi2s_get_port_idx(kcontrol);
  2345. if (idx < 0)
  2346. return idx;
  2347. mi2s_rx_cfg[idx].sample_rate =
  2348. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2349. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2350. idx, mi2s_rx_cfg[idx].sample_rate,
  2351. ucontrol->value.enumerated.item[0]);
  2352. return 0;
  2353. }
  2354. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2355. struct snd_ctl_elem_value *ucontrol)
  2356. {
  2357. int idx = mi2s_get_port_idx(kcontrol);
  2358. if (idx < 0)
  2359. return idx;
  2360. ucontrol->value.enumerated.item[0] =
  2361. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2362. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2363. idx, mi2s_rx_cfg[idx].sample_rate,
  2364. ucontrol->value.enumerated.item[0]);
  2365. return 0;
  2366. }
  2367. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2368. struct snd_ctl_elem_value *ucontrol)
  2369. {
  2370. int idx = mi2s_get_port_idx(kcontrol);
  2371. if (idx < 0)
  2372. return idx;
  2373. mi2s_tx_cfg[idx].sample_rate =
  2374. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2375. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2376. idx, mi2s_tx_cfg[idx].sample_rate,
  2377. ucontrol->value.enumerated.item[0]);
  2378. return 0;
  2379. }
  2380. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2381. struct snd_ctl_elem_value *ucontrol)
  2382. {
  2383. int idx = mi2s_get_port_idx(kcontrol);
  2384. if (idx < 0)
  2385. return idx;
  2386. ucontrol->value.enumerated.item[0] =
  2387. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2388. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2389. idx, mi2s_tx_cfg[idx].sample_rate,
  2390. ucontrol->value.enumerated.item[0]);
  2391. return 0;
  2392. }
  2393. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2394. struct snd_ctl_elem_value *ucontrol)
  2395. {
  2396. int idx = mi2s_get_port_idx(kcontrol);
  2397. if (idx < 0)
  2398. return idx;
  2399. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2400. idx, mi2s_rx_cfg[idx].channels);
  2401. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2402. return 0;
  2403. }
  2404. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2405. struct snd_ctl_elem_value *ucontrol)
  2406. {
  2407. int idx = mi2s_get_port_idx(kcontrol);
  2408. if (idx < 0)
  2409. return idx;
  2410. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2411. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2412. idx, mi2s_rx_cfg[idx].channels);
  2413. return 1;
  2414. }
  2415. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2416. struct snd_ctl_elem_value *ucontrol)
  2417. {
  2418. int idx = mi2s_get_port_idx(kcontrol);
  2419. if (idx < 0)
  2420. return idx;
  2421. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2422. idx, mi2s_tx_cfg[idx].channels);
  2423. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2424. return 0;
  2425. }
  2426. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2427. struct snd_ctl_elem_value *ucontrol)
  2428. {
  2429. int idx = mi2s_get_port_idx(kcontrol);
  2430. if (idx < 0)
  2431. return idx;
  2432. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2433. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2434. idx, mi2s_tx_cfg[idx].channels);
  2435. return 1;
  2436. }
  2437. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2438. struct snd_ctl_elem_value *ucontrol)
  2439. {
  2440. int idx = mi2s_get_port_idx(kcontrol);
  2441. if (idx < 0)
  2442. return idx;
  2443. ucontrol->value.enumerated.item[0] =
  2444. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2445. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2446. idx, mi2s_rx_cfg[idx].bit_format,
  2447. ucontrol->value.enumerated.item[0]);
  2448. return 0;
  2449. }
  2450. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2451. struct snd_ctl_elem_value *ucontrol)
  2452. {
  2453. int idx = mi2s_get_port_idx(kcontrol);
  2454. if (idx < 0)
  2455. return idx;
  2456. mi2s_rx_cfg[idx].bit_format =
  2457. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2458. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2459. idx, mi2s_rx_cfg[idx].bit_format,
  2460. ucontrol->value.enumerated.item[0]);
  2461. return 0;
  2462. }
  2463. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2464. struct snd_ctl_elem_value *ucontrol)
  2465. {
  2466. int idx = mi2s_get_port_idx(kcontrol);
  2467. if (idx < 0)
  2468. return idx;
  2469. ucontrol->value.enumerated.item[0] =
  2470. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2471. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2472. idx, mi2s_tx_cfg[idx].bit_format,
  2473. ucontrol->value.enumerated.item[0]);
  2474. return 0;
  2475. }
  2476. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2477. struct snd_ctl_elem_value *ucontrol)
  2478. {
  2479. int idx = mi2s_get_port_idx(kcontrol);
  2480. if (idx < 0)
  2481. return idx;
  2482. mi2s_tx_cfg[idx].bit_format =
  2483. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2484. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2485. idx, mi2s_tx_cfg[idx].bit_format,
  2486. ucontrol->value.enumerated.item[0]);
  2487. return 0;
  2488. }
  2489. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2490. struct snd_ctl_elem_value *ucontrol)
  2491. {
  2492. int idx = aux_pcm_get_port_idx(kcontrol);
  2493. if (idx < 0)
  2494. return idx;
  2495. ucontrol->value.enumerated.item[0] =
  2496. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2497. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2498. idx, aux_pcm_rx_cfg[idx].bit_format,
  2499. ucontrol->value.enumerated.item[0]);
  2500. return 0;
  2501. }
  2502. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2503. struct snd_ctl_elem_value *ucontrol)
  2504. {
  2505. int idx = aux_pcm_get_port_idx(kcontrol);
  2506. if (idx < 0)
  2507. return idx;
  2508. aux_pcm_rx_cfg[idx].bit_format =
  2509. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2510. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2511. idx, aux_pcm_rx_cfg[idx].bit_format,
  2512. ucontrol->value.enumerated.item[0]);
  2513. return 0;
  2514. }
  2515. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2516. struct snd_ctl_elem_value *ucontrol)
  2517. {
  2518. int idx = aux_pcm_get_port_idx(kcontrol);
  2519. if (idx < 0)
  2520. return idx;
  2521. ucontrol->value.enumerated.item[0] =
  2522. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2523. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2524. idx, aux_pcm_tx_cfg[idx].bit_format,
  2525. ucontrol->value.enumerated.item[0]);
  2526. return 0;
  2527. }
  2528. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2529. struct snd_ctl_elem_value *ucontrol)
  2530. {
  2531. int idx = aux_pcm_get_port_idx(kcontrol);
  2532. if (idx < 0)
  2533. return idx;
  2534. aux_pcm_tx_cfg[idx].bit_format =
  2535. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2536. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2537. idx, aux_pcm_tx_cfg[idx].bit_format,
  2538. ucontrol->value.enumerated.item[0]);
  2539. return 0;
  2540. }
  2541. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2542. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2543. slim_rx_ch_get, slim_rx_ch_put),
  2544. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2545. slim_rx_ch_get, slim_rx_ch_put),
  2546. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2547. slim_tx_ch_get, slim_tx_ch_put),
  2548. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2549. slim_tx_ch_get, slim_tx_ch_put),
  2550. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2551. slim_rx_ch_get, slim_rx_ch_put),
  2552. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2553. slim_rx_ch_get, slim_rx_ch_put),
  2554. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2555. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2556. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2557. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2558. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2559. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2560. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2561. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2562. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2563. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2564. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2565. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2566. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2567. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2568. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2569. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2570. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2571. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2572. };
  2573. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2574. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2575. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2576. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2577. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2578. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2579. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2580. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2581. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2582. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2583. va_cdc_dma_tx_0_sample_rate,
  2584. cdc_dma_tx_sample_rate_get,
  2585. cdc_dma_tx_sample_rate_put),
  2586. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2587. va_cdc_dma_tx_1_sample_rate,
  2588. cdc_dma_tx_sample_rate_get,
  2589. cdc_dma_tx_sample_rate_put),
  2590. };
  2591. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2592. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2593. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2594. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2595. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2596. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2597. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2598. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2599. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2600. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2601. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2602. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2603. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2604. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2605. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2606. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2607. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2608. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2609. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2610. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2611. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2612. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2613. wsa_cdc_dma_rx_0_sample_rate,
  2614. cdc_dma_rx_sample_rate_get,
  2615. cdc_dma_rx_sample_rate_put),
  2616. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2617. wsa_cdc_dma_rx_1_sample_rate,
  2618. cdc_dma_rx_sample_rate_get,
  2619. cdc_dma_rx_sample_rate_put),
  2620. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2621. wsa_cdc_dma_tx_0_sample_rate,
  2622. cdc_dma_tx_sample_rate_get,
  2623. cdc_dma_tx_sample_rate_put),
  2624. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2625. wsa_cdc_dma_tx_1_sample_rate,
  2626. cdc_dma_tx_sample_rate_get,
  2627. cdc_dma_tx_sample_rate_put),
  2628. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2629. wsa_cdc_dma_tx_2_sample_rate,
  2630. cdc_dma_tx_sample_rate_get,
  2631. cdc_dma_tx_sample_rate_put),
  2632. };
  2633. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2634. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2635. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2636. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2637. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2638. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2639. proxy_rx_ch_get, proxy_rx_ch_put),
  2640. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2641. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2642. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2643. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2644. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2645. msm_bt_sample_rate_get,
  2646. msm_bt_sample_rate_put),
  2647. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2648. usb_audio_rx_sample_rate_get,
  2649. usb_audio_rx_sample_rate_put),
  2650. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2651. usb_audio_tx_sample_rate_get,
  2652. usb_audio_tx_sample_rate_put),
  2653. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2654. tdm_rx_sample_rate_get,
  2655. tdm_rx_sample_rate_put),
  2656. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2657. tdm_tx_sample_rate_get,
  2658. tdm_tx_sample_rate_put),
  2659. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2660. tdm_rx_format_get,
  2661. tdm_rx_format_put),
  2662. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2663. tdm_tx_format_get,
  2664. tdm_tx_format_put),
  2665. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2666. tdm_rx_ch_get,
  2667. tdm_rx_ch_put),
  2668. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2669. tdm_tx_ch_get,
  2670. tdm_tx_ch_put),
  2671. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2672. tdm_rx_sample_rate_get,
  2673. tdm_rx_sample_rate_put),
  2674. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2675. tdm_tx_sample_rate_get,
  2676. tdm_tx_sample_rate_put),
  2677. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2678. tdm_rx_format_get,
  2679. tdm_rx_format_put),
  2680. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2681. tdm_tx_format_get,
  2682. tdm_tx_format_put),
  2683. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2684. tdm_rx_ch_get,
  2685. tdm_rx_ch_put),
  2686. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2687. tdm_tx_ch_get,
  2688. tdm_tx_ch_put),
  2689. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2690. tdm_rx_sample_rate_get,
  2691. tdm_rx_sample_rate_put),
  2692. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2693. tdm_tx_sample_rate_get,
  2694. tdm_tx_sample_rate_put),
  2695. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2696. tdm_rx_format_get,
  2697. tdm_rx_format_put),
  2698. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2699. tdm_tx_format_get,
  2700. tdm_tx_format_put),
  2701. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2702. tdm_rx_ch_get,
  2703. tdm_rx_ch_put),
  2704. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2705. tdm_tx_ch_get,
  2706. tdm_tx_ch_put),
  2707. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2708. tdm_rx_sample_rate_get,
  2709. tdm_rx_sample_rate_put),
  2710. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2711. tdm_tx_sample_rate_get,
  2712. tdm_tx_sample_rate_put),
  2713. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  2714. tdm_rx_format_get,
  2715. tdm_rx_format_put),
  2716. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  2717. tdm_tx_format_get,
  2718. tdm_tx_format_put),
  2719. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  2720. tdm_rx_ch_get,
  2721. tdm_rx_ch_put),
  2722. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  2723. tdm_tx_ch_get,
  2724. tdm_tx_ch_put),
  2725. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2726. tdm_rx_sample_rate_get,
  2727. tdm_rx_sample_rate_put),
  2728. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2729. tdm_tx_sample_rate_get,
  2730. tdm_tx_sample_rate_put),
  2731. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  2732. tdm_rx_format_get,
  2733. tdm_rx_format_put),
  2734. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  2735. tdm_tx_format_get,
  2736. tdm_tx_format_put),
  2737. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  2738. tdm_rx_ch_get,
  2739. tdm_rx_ch_put),
  2740. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  2741. tdm_tx_ch_get,
  2742. tdm_tx_ch_put),
  2743. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2744. aux_pcm_rx_sample_rate_get,
  2745. aux_pcm_rx_sample_rate_put),
  2746. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2747. aux_pcm_rx_sample_rate_get,
  2748. aux_pcm_rx_sample_rate_put),
  2749. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2750. aux_pcm_rx_sample_rate_get,
  2751. aux_pcm_rx_sample_rate_put),
  2752. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  2753. aux_pcm_rx_sample_rate_get,
  2754. aux_pcm_rx_sample_rate_put),
  2755. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  2756. aux_pcm_rx_sample_rate_get,
  2757. aux_pcm_rx_sample_rate_put),
  2758. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2759. aux_pcm_tx_sample_rate_get,
  2760. aux_pcm_tx_sample_rate_put),
  2761. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2762. aux_pcm_tx_sample_rate_get,
  2763. aux_pcm_tx_sample_rate_put),
  2764. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2765. aux_pcm_tx_sample_rate_get,
  2766. aux_pcm_tx_sample_rate_put),
  2767. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  2768. aux_pcm_tx_sample_rate_get,
  2769. aux_pcm_tx_sample_rate_put),
  2770. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  2771. aux_pcm_tx_sample_rate_get,
  2772. aux_pcm_tx_sample_rate_put),
  2773. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2774. mi2s_rx_sample_rate_get,
  2775. mi2s_rx_sample_rate_put),
  2776. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2777. mi2s_rx_sample_rate_get,
  2778. mi2s_rx_sample_rate_put),
  2779. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2780. mi2s_rx_sample_rate_get,
  2781. mi2s_rx_sample_rate_put),
  2782. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  2783. mi2s_rx_sample_rate_get,
  2784. mi2s_rx_sample_rate_put),
  2785. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  2786. mi2s_rx_sample_rate_get,
  2787. mi2s_rx_sample_rate_put),
  2788. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  2789. mi2s_tx_sample_rate_get,
  2790. mi2s_tx_sample_rate_put),
  2791. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2792. mi2s_tx_sample_rate_get,
  2793. mi2s_tx_sample_rate_put),
  2794. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2795. mi2s_tx_sample_rate_get,
  2796. mi2s_tx_sample_rate_put),
  2797. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  2798. mi2s_tx_sample_rate_get,
  2799. mi2s_tx_sample_rate_put),
  2800. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  2801. mi2s_tx_sample_rate_get,
  2802. mi2s_tx_sample_rate_put),
  2803. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2804. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2805. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2806. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2807. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2808. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2809. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2810. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2811. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2812. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2813. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2814. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2815. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  2816. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2817. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  2818. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2819. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  2820. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2821. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  2822. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2823. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2824. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2825. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2826. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2827. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2828. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2829. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2830. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2831. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2832. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2833. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2834. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2835. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  2836. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2837. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  2838. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2839. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  2840. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2841. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  2842. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2843. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2844. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2845. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2846. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2847. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2848. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2849. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2850. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2851. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2852. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2853. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2854. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2855. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2856. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2857. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2858. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2859. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  2860. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2861. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  2862. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2863. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  2864. msm_snd_vad_cfg_put),
  2865. };
  2866. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  2867. int enable, bool dapm)
  2868. {
  2869. int ret = 0;
  2870. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2871. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  2872. } else {
  2873. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  2874. __func__);
  2875. ret = -EINVAL;
  2876. }
  2877. return ret;
  2878. }
  2879. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  2880. int enable, bool dapm)
  2881. {
  2882. int ret = 0;
  2883. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2884. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  2885. } else {
  2886. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  2887. __func__);
  2888. ret = -EINVAL;
  2889. }
  2890. return ret;
  2891. }
  2892. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  2893. struct snd_kcontrol *kcontrol, int event)
  2894. {
  2895. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2896. pr_debug("%s: event = %d\n", __func__, event);
  2897. switch (event) {
  2898. case SND_SOC_DAPM_PRE_PMU:
  2899. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  2900. case SND_SOC_DAPM_POST_PMD:
  2901. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  2902. }
  2903. return 0;
  2904. }
  2905. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  2906. struct snd_kcontrol *kcontrol, int event)
  2907. {
  2908. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2909. pr_debug("%s: event = %d\n", __func__, event);
  2910. switch (event) {
  2911. case SND_SOC_DAPM_PRE_PMU:
  2912. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  2913. case SND_SOC_DAPM_POST_PMD:
  2914. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  2915. }
  2916. return 0;
  2917. }
  2918. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  2919. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  2920. msm_mclk_event,
  2921. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2922. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  2923. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2924. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  2925. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  2926. };
  2927. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  2928. struct snd_kcontrol *kcontrol, int event)
  2929. {
  2930. struct msm_asoc_mach_data *pdata = NULL;
  2931. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2932. int ret = 0;
  2933. uint32_t dmic_idx;
  2934. int *dmic_gpio_cnt;
  2935. struct device_node *dmic_gpio;
  2936. char *wname;
  2937. wname = strpbrk(w->name, "01234567");
  2938. if (!wname) {
  2939. dev_err(codec->dev, "%s: widget not found\n", __func__);
  2940. return -EINVAL;
  2941. }
  2942. ret = kstrtouint(wname, 10, &dmic_idx);
  2943. if (ret < 0) {
  2944. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  2945. __func__);
  2946. return -EINVAL;
  2947. }
  2948. pdata = snd_soc_card_get_drvdata(codec->component.card);
  2949. switch (dmic_idx) {
  2950. case 0:
  2951. case 1:
  2952. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  2953. dmic_gpio = pdata->dmic_01_gpio_p;
  2954. break;
  2955. case 2:
  2956. case 3:
  2957. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  2958. dmic_gpio = pdata->dmic_23_gpio_p;
  2959. break;
  2960. case 4:
  2961. case 5:
  2962. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  2963. dmic_gpio = pdata->dmic_45_gpio_p;
  2964. break;
  2965. case 6:
  2966. case 7:
  2967. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  2968. dmic_gpio = pdata->dmic_67_gpio_p;
  2969. break;
  2970. default:
  2971. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  2972. __func__);
  2973. return -EINVAL;
  2974. }
  2975. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  2976. __func__, event, dmic_idx, *dmic_gpio_cnt);
  2977. switch (event) {
  2978. case SND_SOC_DAPM_PRE_PMU:
  2979. (*dmic_gpio_cnt)++;
  2980. if (*dmic_gpio_cnt == 1) {
  2981. ret = msm_cdc_pinctrl_select_active_state(
  2982. dmic_gpio);
  2983. if (ret < 0) {
  2984. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  2985. __func__, "dmic_gpio");
  2986. return ret;
  2987. }
  2988. }
  2989. break;
  2990. case SND_SOC_DAPM_POST_PMD:
  2991. (*dmic_gpio_cnt)--;
  2992. if (*dmic_gpio_cnt == 0) {
  2993. ret = msm_cdc_pinctrl_select_sleep_state(
  2994. dmic_gpio);
  2995. if (ret < 0) {
  2996. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  2997. __func__, "dmic_gpio");
  2998. return ret;
  2999. }
  3000. }
  3001. break;
  3002. default:
  3003. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3004. __func__, event);
  3005. return -EINVAL;
  3006. }
  3007. return 0;
  3008. }
  3009. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3010. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3011. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3012. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3013. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3014. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3015. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3016. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3017. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3018. };
  3019. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3020. };
  3021. static inline int param_is_mask(int p)
  3022. {
  3023. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3024. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3025. }
  3026. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3027. int n)
  3028. {
  3029. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3030. }
  3031. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3032. unsigned int bit)
  3033. {
  3034. if (bit >= SNDRV_MASK_MAX)
  3035. return;
  3036. if (param_is_mask(n)) {
  3037. struct snd_mask *m = param_to_mask(p, n);
  3038. m->bits[0] = 0;
  3039. m->bits[1] = 0;
  3040. m->bits[bit >> 5] |= (1 << (bit & 31));
  3041. }
  3042. }
  3043. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3044. {
  3045. int ch_id = 0;
  3046. switch (be_id) {
  3047. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3048. ch_id = SLIM_RX_0;
  3049. break;
  3050. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3051. ch_id = SLIM_RX_1;
  3052. break;
  3053. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3054. ch_id = SLIM_RX_2;
  3055. break;
  3056. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3057. ch_id = SLIM_RX_3;
  3058. break;
  3059. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3060. ch_id = SLIM_RX_4;
  3061. break;
  3062. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3063. ch_id = SLIM_RX_6;
  3064. break;
  3065. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3066. ch_id = SLIM_TX_0;
  3067. break;
  3068. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3069. ch_id = SLIM_TX_3;
  3070. break;
  3071. default:
  3072. ch_id = SLIM_RX_0;
  3073. break;
  3074. }
  3075. return ch_id;
  3076. }
  3077. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3078. {
  3079. *port_id = 0xFFFF;
  3080. switch (be_id) {
  3081. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3082. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3083. break;
  3084. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3085. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3086. break;
  3087. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3088. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3089. break;
  3090. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3091. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3092. break;
  3093. default:
  3094. return -EINVAL;
  3095. }
  3096. return 0;
  3097. }
  3098. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3099. {
  3100. int idx = 0;
  3101. switch (be_id) {
  3102. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3103. idx = WSA_CDC_DMA_RX_0;
  3104. break;
  3105. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3106. idx = WSA_CDC_DMA_TX_0;
  3107. break;
  3108. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3109. idx = WSA_CDC_DMA_RX_1;
  3110. break;
  3111. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3112. idx = WSA_CDC_DMA_TX_1;
  3113. break;
  3114. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3115. idx = WSA_CDC_DMA_TX_2;
  3116. break;
  3117. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3118. idx = VA_CDC_DMA_TX_0;
  3119. break;
  3120. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3121. idx = VA_CDC_DMA_TX_1;
  3122. break;
  3123. default:
  3124. idx = VA_CDC_DMA_TX_0;
  3125. break;
  3126. }
  3127. return idx;
  3128. }
  3129. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3130. struct snd_pcm_hw_params *params)
  3131. {
  3132. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3133. struct snd_interval *rate = hw_param_interval(params,
  3134. SNDRV_PCM_HW_PARAM_RATE);
  3135. struct snd_interval *channels = hw_param_interval(params,
  3136. SNDRV_PCM_HW_PARAM_CHANNELS);
  3137. int rc = 0;
  3138. int idx;
  3139. void *config = NULL;
  3140. struct snd_soc_codec *codec = NULL;
  3141. pr_debug("%s: format = %d, rate = %d\n",
  3142. __func__, params_format(params), params_rate(params));
  3143. switch (dai_link->id) {
  3144. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3145. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3146. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3147. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3148. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3149. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3150. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3151. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3152. slim_rx_cfg[idx].bit_format);
  3153. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3154. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3155. break;
  3156. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3157. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3158. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3159. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3160. slim_tx_cfg[idx].bit_format);
  3161. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3162. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3163. break;
  3164. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3165. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3166. slim_tx_cfg[1].bit_format);
  3167. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3168. channels->min = channels->max = slim_tx_cfg[1].channels;
  3169. break;
  3170. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3171. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3172. SNDRV_PCM_FORMAT_S32_LE);
  3173. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3174. channels->min = channels->max = msm_vi_feed_tx_ch;
  3175. break;
  3176. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3177. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3178. slim_rx_cfg[5].bit_format);
  3179. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3180. channels->min = channels->max = slim_rx_cfg[5].channels;
  3181. break;
  3182. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3183. codec = rtd->codec;
  3184. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3185. channels->min = channels->max = 1;
  3186. config = msm_codec_fn.get_afe_config_fn(codec,
  3187. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3188. if (config) {
  3189. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3190. config, SLIMBUS_5_TX);
  3191. if (rc)
  3192. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3193. __func__, rc);
  3194. }
  3195. break;
  3196. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3197. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3198. slim_rx_cfg[SLIM_RX_7].bit_format);
  3199. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3200. channels->min = channels->max =
  3201. slim_rx_cfg[SLIM_RX_7].channels;
  3202. break;
  3203. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3204. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3205. channels->min = channels->max =
  3206. slim_tx_cfg[SLIM_TX_7].channels;
  3207. break;
  3208. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3209. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3210. channels->min = channels->max =
  3211. slim_tx_cfg[SLIM_TX_8].channels;
  3212. break;
  3213. case MSM_BACKEND_DAI_USB_RX:
  3214. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3215. usb_rx_cfg.bit_format);
  3216. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3217. channels->min = channels->max = usb_rx_cfg.channels;
  3218. break;
  3219. case MSM_BACKEND_DAI_USB_TX:
  3220. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3221. usb_tx_cfg.bit_format);
  3222. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3223. channels->min = channels->max = usb_tx_cfg.channels;
  3224. break;
  3225. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3226. channels->min = channels->max = proxy_rx_cfg.channels;
  3227. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3228. break;
  3229. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3230. channels->min = channels->max =
  3231. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3232. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3233. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3234. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3235. break;
  3236. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3237. channels->min = channels->max =
  3238. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3239. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3240. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3241. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3242. break;
  3243. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3244. channels->min = channels->max =
  3245. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3246. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3247. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3248. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3249. break;
  3250. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3251. channels->min = channels->max =
  3252. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3253. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3254. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3255. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3256. break;
  3257. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3258. channels->min = channels->max =
  3259. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3260. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3261. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3262. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3263. break;
  3264. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3265. channels->min = channels->max =
  3266. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3267. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3268. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3269. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3270. break;
  3271. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3272. channels->min = channels->max =
  3273. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3274. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3275. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3276. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3277. break;
  3278. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3279. channels->min = channels->max =
  3280. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3281. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3282. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3283. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3284. break;
  3285. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3286. channels->min = channels->max =
  3287. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3288. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3289. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3290. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3291. break;
  3292. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3293. channels->min = channels->max =
  3294. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3295. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3296. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3297. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3298. break;
  3299. case MSM_BACKEND_DAI_AUXPCM_RX:
  3300. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3301. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3302. rate->min = rate->max =
  3303. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3304. channels->min = channels->max =
  3305. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3306. break;
  3307. case MSM_BACKEND_DAI_AUXPCM_TX:
  3308. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3309. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3310. rate->min = rate->max =
  3311. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3312. channels->min = channels->max =
  3313. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3314. break;
  3315. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3316. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3317. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3318. rate->min = rate->max =
  3319. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3320. channels->min = channels->max =
  3321. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3322. break;
  3323. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3324. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3325. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3326. rate->min = rate->max =
  3327. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3328. channels->min = channels->max =
  3329. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3330. break;
  3331. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3332. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3333. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3334. rate->min = rate->max =
  3335. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3336. channels->min = channels->max =
  3337. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3338. break;
  3339. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3340. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3341. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3342. rate->min = rate->max =
  3343. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3344. channels->min = channels->max =
  3345. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3346. break;
  3347. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3348. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3349. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3350. rate->min = rate->max =
  3351. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3352. channels->min = channels->max =
  3353. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3354. break;
  3355. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3356. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3357. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3358. rate->min = rate->max =
  3359. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3360. channels->min = channels->max =
  3361. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3362. break;
  3363. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3364. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3365. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3366. rate->min = rate->max =
  3367. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3368. channels->min = channels->max =
  3369. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3370. break;
  3371. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3372. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3373. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3374. rate->min = rate->max =
  3375. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3376. channels->min = channels->max =
  3377. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3378. break;
  3379. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3380. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3381. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3382. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3383. channels->min = channels->max =
  3384. mi2s_rx_cfg[PRIM_MI2S].channels;
  3385. break;
  3386. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3387. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3388. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3389. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3390. channels->min = channels->max =
  3391. mi2s_tx_cfg[PRIM_MI2S].channels;
  3392. break;
  3393. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3394. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3395. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3396. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3397. channels->min = channels->max =
  3398. mi2s_rx_cfg[SEC_MI2S].channels;
  3399. break;
  3400. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3401. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3402. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3403. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3404. channels->min = channels->max =
  3405. mi2s_tx_cfg[SEC_MI2S].channels;
  3406. break;
  3407. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3408. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3409. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3410. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3411. channels->min = channels->max =
  3412. mi2s_rx_cfg[TERT_MI2S].channels;
  3413. break;
  3414. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3415. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3416. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3417. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3418. channels->min = channels->max =
  3419. mi2s_tx_cfg[TERT_MI2S].channels;
  3420. break;
  3421. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3422. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3423. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3424. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3425. channels->min = channels->max =
  3426. mi2s_rx_cfg[QUAT_MI2S].channels;
  3427. break;
  3428. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3429. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3430. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3431. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3432. channels->min = channels->max =
  3433. mi2s_tx_cfg[QUAT_MI2S].channels;
  3434. break;
  3435. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3436. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3437. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3438. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3439. channels->min = channels->max =
  3440. mi2s_rx_cfg[QUIN_MI2S].channels;
  3441. break;
  3442. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3443. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3444. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3445. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3446. channels->min = channels->max =
  3447. mi2s_tx_cfg[QUIN_MI2S].channels;
  3448. break;
  3449. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3450. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3451. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3452. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3453. cdc_dma_rx_cfg[idx].bit_format);
  3454. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3455. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3456. break;
  3457. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3458. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3459. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3460. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3461. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3462. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3463. cdc_dma_tx_cfg[idx].bit_format);
  3464. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3465. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3466. break;
  3467. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3468. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3469. SNDRV_PCM_FORMAT_S32_LE);
  3470. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3471. channels->min = channels->max = msm_vi_feed_tx_ch;
  3472. break;
  3473. default:
  3474. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3475. break;
  3476. }
  3477. return rc;
  3478. }
  3479. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3480. {
  3481. int ret = 0;
  3482. void *config_data = NULL;
  3483. if (!msm_codec_fn.get_afe_config_fn) {
  3484. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3485. __func__);
  3486. return -EINVAL;
  3487. }
  3488. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3489. AFE_CDC_REGISTERS_CONFIG);
  3490. if (config_data) {
  3491. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3492. if (ret) {
  3493. dev_err(codec->dev,
  3494. "%s: Failed to set codec registers config %d\n",
  3495. __func__, ret);
  3496. return ret;
  3497. }
  3498. }
  3499. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3500. AFE_CDC_REGISTER_PAGE_CONFIG);
  3501. if (config_data) {
  3502. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3503. 0);
  3504. if (ret)
  3505. dev_err(codec->dev,
  3506. "%s: Failed to set cdc register page config\n",
  3507. __func__);
  3508. }
  3509. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3510. AFE_SLIMBUS_SLAVE_CONFIG);
  3511. if (config_data) {
  3512. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3513. if (ret) {
  3514. dev_err(codec->dev,
  3515. "%s: Failed to set slimbus slave config %d\n",
  3516. __func__, ret);
  3517. return ret;
  3518. }
  3519. }
  3520. return 0;
  3521. }
  3522. static void msm_afe_clear_config(void)
  3523. {
  3524. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3525. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3526. }
  3527. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3528. struct snd_card *card)
  3529. {
  3530. int ret = 0;
  3531. unsigned long timeout;
  3532. int adsp_ready = 0;
  3533. bool snd_card_online = 0;
  3534. timeout = jiffies +
  3535. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3536. do {
  3537. if (!snd_card_online) {
  3538. snd_card_online = snd_card_is_online_state(card);
  3539. pr_debug("%s: Sound card is %s\n", __func__,
  3540. snd_card_online ? "Online" : "Offline");
  3541. }
  3542. if (!adsp_ready) {
  3543. adsp_ready = q6core_is_adsp_ready();
  3544. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3545. adsp_ready ? "ready" : "not ready");
  3546. }
  3547. if (snd_card_online && adsp_ready)
  3548. break;
  3549. /*
  3550. * Sound card/ADSP will be coming up after subsystem restart and
  3551. * it might not be fully up when the control reaches
  3552. * here. So, wait for 50msec before checking ADSP state
  3553. */
  3554. msleep(50);
  3555. } while (time_after(timeout, jiffies));
  3556. if (!snd_card_online || !adsp_ready) {
  3557. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3558. __func__,
  3559. snd_card_online ? "Online" : "Offline",
  3560. adsp_ready ? "ready" : "not ready");
  3561. ret = -ETIMEDOUT;
  3562. goto err;
  3563. }
  3564. ret = msm_afe_set_config(codec);
  3565. if (ret)
  3566. pr_err("%s: Failed to set AFE config. err %d\n",
  3567. __func__, ret);
  3568. return 0;
  3569. err:
  3570. return ret;
  3571. }
  3572. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3573. unsigned long opcode, void *ptr)
  3574. {
  3575. int ret;
  3576. struct snd_soc_card *card = NULL;
  3577. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3578. struct snd_soc_pcm_runtime *rtd;
  3579. struct snd_soc_codec *codec;
  3580. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3581. switch (opcode) {
  3582. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3583. /*
  3584. * Use flag to ignore initial boot notifications
  3585. * On initial boot msm_adsp_power_up_config is
  3586. * called on init. There is no need to clear
  3587. * and set the config again on initial boot.
  3588. */
  3589. if (is_initial_boot)
  3590. break;
  3591. msm_afe_clear_config();
  3592. break;
  3593. case AUDIO_NOTIFIER_SERVICE_UP:
  3594. if (is_initial_boot) {
  3595. is_initial_boot = false;
  3596. break;
  3597. }
  3598. if (!spdev)
  3599. return -EINVAL;
  3600. card = platform_get_drvdata(spdev);
  3601. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3602. if (!rtd) {
  3603. dev_err(card->dev,
  3604. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3605. __func__, be_dl_name);
  3606. ret = -EINVAL;
  3607. goto err;
  3608. }
  3609. codec = rtd->codec;
  3610. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3611. if (ret < 0) {
  3612. dev_err(card->dev,
  3613. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3614. __func__, ret);
  3615. goto err;
  3616. }
  3617. break;
  3618. default:
  3619. break;
  3620. }
  3621. err:
  3622. return NOTIFY_OK;
  3623. }
  3624. static struct notifier_block service_nb = {
  3625. .notifier_call = qcs405_notifier_service_cb,
  3626. .priority = -INT_MAX,
  3627. };
  3628. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3629. {
  3630. int ret = 0;
  3631. void *config_data;
  3632. struct snd_soc_codec *codec = rtd->codec;
  3633. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3634. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3635. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3636. struct snd_card *card;
  3637. struct snd_info_entry *entry;
  3638. struct msm_asoc_mach_data *pdata =
  3639. snd_soc_card_get_drvdata(rtd->card);
  3640. /*
  3641. * Codec SLIMBUS configuration
  3642. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  3643. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  3644. * TX14, TX15, TX16
  3645. */
  3646. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  3647. 151, 152, 153, 154, 155, 156};
  3648. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  3649. 134, 135, 136, 137, 138, 139,
  3650. 140, 141, 142, 143};
  3651. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  3652. rtd->pmdown_time = 0;
  3653. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  3654. ARRAY_SIZE(msm_snd_sb_controls));
  3655. if (ret < 0) {
  3656. pr_err("%s: add_codec_controls failed, err %d\n",
  3657. __func__, ret);
  3658. return ret;
  3659. }
  3660. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  3661. ARRAY_SIZE(msm_dapm_widgets));
  3662. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  3663. ARRAY_SIZE(wcd_audio_paths));
  3664. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  3665. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  3666. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3667. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3668. snd_soc_dapm_sync(dapm);
  3669. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3670. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3671. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  3672. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  3673. if (ret) {
  3674. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  3675. __func__, ret);
  3676. goto err;
  3677. }
  3678. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3679. AFE_AANC_VERSION);
  3680. if (config_data) {
  3681. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  3682. if (ret) {
  3683. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  3684. __func__, ret);
  3685. goto err;
  3686. }
  3687. }
  3688. card = rtd->card->snd_card;
  3689. entry = snd_info_create_subdir(card->module, "codecs",
  3690. card->proc_root);
  3691. if (!entry) {
  3692. pr_debug("%s: Cannot create codecs module entry\n",
  3693. __func__);
  3694. ret = 0;
  3695. goto err;
  3696. }
  3697. pdata->codec_root = entry;
  3698. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  3699. codec_reg_done = true;
  3700. return 0;
  3701. err:
  3702. return ret;
  3703. }
  3704. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3705. {
  3706. int ret = 0;
  3707. struct snd_soc_codec *codec = rtd->codec;
  3708. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3709. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  3710. ARRAY_SIZE(msm_snd_va_controls));
  3711. if (ret < 0) {
  3712. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3713. __func__, ret);
  3714. return ret;
  3715. }
  3716. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  3717. ARRAY_SIZE(msm_va_dapm_widgets));
  3718. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3719. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3720. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3721. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3722. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  3723. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  3724. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  3725. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  3726. snd_soc_dapm_sync(dapm);
  3727. return ret;
  3728. }
  3729. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3730. {
  3731. int ret = 0;
  3732. struct snd_soc_codec *codec = rtd->codec;
  3733. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3734. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  3735. ARRAY_SIZE(msm_snd_wsa_controls));
  3736. if (ret < 0) {
  3737. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3738. __func__, ret);
  3739. return ret;
  3740. }
  3741. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  3742. ARRAY_SIZE(msm_wsa_dapm_widgets));
  3743. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  3744. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  3745. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  3746. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  3747. snd_soc_dapm_sync(dapm);
  3748. return ret;
  3749. }
  3750. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3751. {
  3752. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3753. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  3754. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3755. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3756. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3757. }
  3758. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  3759. struct snd_pcm_hw_params *params)
  3760. {
  3761. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3762. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3763. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3764. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3765. int ret = 0;
  3766. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3767. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3768. u32 user_set_tx_ch = 0;
  3769. u32 rx_ch_count;
  3770. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3771. ret = snd_soc_dai_get_channel_map(codec_dai,
  3772. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3773. if (ret < 0) {
  3774. pr_err("%s: failed to get codec chan map, err:%d\n",
  3775. __func__, ret);
  3776. goto err;
  3777. }
  3778. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  3779. pr_debug("%s: rx_5_ch=%d\n", __func__,
  3780. slim_rx_cfg[5].channels);
  3781. rx_ch_count = slim_rx_cfg[5].channels;
  3782. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  3783. pr_debug("%s: rx_2_ch=%d\n", __func__,
  3784. slim_rx_cfg[2].channels);
  3785. rx_ch_count = slim_rx_cfg[2].channels;
  3786. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  3787. pr_debug("%s: rx_6_ch=%d\n", __func__,
  3788. slim_rx_cfg[6].channels);
  3789. rx_ch_count = slim_rx_cfg[6].channels;
  3790. } else {
  3791. pr_debug("%s: rx_0_ch=%d\n", __func__,
  3792. slim_rx_cfg[0].channels);
  3793. rx_ch_count = slim_rx_cfg[0].channels;
  3794. }
  3795. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3796. rx_ch_count, rx_ch);
  3797. if (ret < 0) {
  3798. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3799. __func__, ret);
  3800. goto err;
  3801. }
  3802. } else {
  3803. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  3804. codec_dai->name, codec_dai->id, user_set_tx_ch);
  3805. ret = snd_soc_dai_get_channel_map(codec_dai,
  3806. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3807. if (ret < 0) {
  3808. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3809. __func__, ret);
  3810. goto err;
  3811. }
  3812. /* For <codec>_tx1 case */
  3813. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  3814. user_set_tx_ch = slim_tx_cfg[0].channels;
  3815. /* For <codec>_tx3 case */
  3816. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  3817. user_set_tx_ch = slim_tx_cfg[1].channels;
  3818. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  3819. user_set_tx_ch = msm_vi_feed_tx_ch;
  3820. else
  3821. user_set_tx_ch = tx_ch_cnt;
  3822. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  3823. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  3824. tx_ch_cnt, dai_link->id);
  3825. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3826. user_set_tx_ch, tx_ch, 0, 0);
  3827. if (ret < 0)
  3828. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3829. __func__, ret);
  3830. }
  3831. err:
  3832. return ret;
  3833. }
  3834. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3835. struct snd_pcm_hw_params *params)
  3836. {
  3837. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3838. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3839. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3840. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3841. int ret = 0;
  3842. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3843. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3844. u32 user_set_tx_ch = 0;
  3845. u32 user_set_rx_ch = 0;
  3846. u32 ch_id;
  3847. ret = snd_soc_dai_get_channel_map(codec_dai,
  3848. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3849. &rx_ch_cdc_dma);
  3850. if (ret < 0) {
  3851. pr_err("%s: failed to get codec chan map, err:%d\n",
  3852. __func__, ret);
  3853. goto err;
  3854. }
  3855. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3856. switch (dai_link->id) {
  3857. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3858. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3859. {
  3860. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3861. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3862. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3863. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3864. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3865. user_set_rx_ch, &rx_ch_cdc_dma);
  3866. if (ret < 0) {
  3867. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3868. __func__, ret);
  3869. goto err;
  3870. }
  3871. }
  3872. break;
  3873. }
  3874. } else {
  3875. switch (dai_link->id) {
  3876. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3877. {
  3878. user_set_tx_ch = msm_vi_feed_tx_ch;
  3879. }
  3880. break;
  3881. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3882. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3883. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3884. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3885. {
  3886. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3887. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3888. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3889. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3890. }
  3891. break;
  3892. }
  3893. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3894. &tx_ch_cdc_dma, 0, 0);
  3895. if (ret < 0) {
  3896. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3897. __func__, ret);
  3898. goto err;
  3899. }
  3900. }
  3901. err:
  3902. return ret;
  3903. }
  3904. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3905. struct snd_pcm_hw_params *params)
  3906. {
  3907. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3908. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3909. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3910. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3911. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3912. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3913. int ret;
  3914. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3915. codec_dai->name, codec_dai->id);
  3916. ret = snd_soc_dai_get_channel_map(codec_dai,
  3917. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3918. if (ret) {
  3919. dev_err(rtd->dev,
  3920. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3921. __func__, ret);
  3922. goto err;
  3923. }
  3924. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3925. __func__, tx_ch_cnt, dai_link->id);
  3926. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3927. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3928. if (ret)
  3929. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3930. __func__, ret);
  3931. err:
  3932. return ret;
  3933. }
  3934. static int msm_get_port_id(int be_id)
  3935. {
  3936. int afe_port_id;
  3937. switch (be_id) {
  3938. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3939. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  3940. break;
  3941. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3942. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  3943. break;
  3944. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3945. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  3946. break;
  3947. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3948. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  3949. break;
  3950. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3951. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  3952. break;
  3953. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3954. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  3955. break;
  3956. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3957. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  3958. break;
  3959. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3960. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  3961. break;
  3962. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3963. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  3964. break;
  3965. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3966. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3967. break;
  3968. default:
  3969. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  3970. afe_port_id = -EINVAL;
  3971. }
  3972. return afe_port_id;
  3973. }
  3974. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  3975. {
  3976. u32 bit_per_sample;
  3977. switch (bit_format) {
  3978. case SNDRV_PCM_FORMAT_S32_LE:
  3979. case SNDRV_PCM_FORMAT_S24_3LE:
  3980. case SNDRV_PCM_FORMAT_S24_LE:
  3981. bit_per_sample = 32;
  3982. break;
  3983. case SNDRV_PCM_FORMAT_S16_LE:
  3984. default:
  3985. bit_per_sample = 16;
  3986. break;
  3987. }
  3988. return bit_per_sample;
  3989. }
  3990. static void update_mi2s_clk_val(int dai_id, int stream)
  3991. {
  3992. u32 bit_per_sample;
  3993. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3994. bit_per_sample =
  3995. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  3996. mi2s_clk[dai_id].clk_freq_in_hz =
  3997. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  3998. } else {
  3999. bit_per_sample =
  4000. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4001. mi2s_clk[dai_id].clk_freq_in_hz =
  4002. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4003. }
  4004. }
  4005. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4006. {
  4007. int ret = 0;
  4008. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4009. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4010. int port_id = 0;
  4011. int index = cpu_dai->id;
  4012. port_id = msm_get_port_id(rtd->dai_link->id);
  4013. if (port_id < 0) {
  4014. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4015. ret = port_id;
  4016. goto err;
  4017. }
  4018. if (enable) {
  4019. update_mi2s_clk_val(index, substream->stream);
  4020. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4021. mi2s_clk[index].clk_freq_in_hz);
  4022. }
  4023. mi2s_clk[index].enable = enable;
  4024. ret = afe_set_lpass_clock_v2(port_id,
  4025. &mi2s_clk[index]);
  4026. if (ret < 0) {
  4027. dev_err(rtd->card->dev,
  4028. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4029. __func__, port_id, ret);
  4030. goto err;
  4031. }
  4032. err:
  4033. return ret;
  4034. }
  4035. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4036. enum pinctrl_pin_state new_state)
  4037. {
  4038. int ret = 0;
  4039. int curr_state = 0;
  4040. if (pinctrl_info == NULL) {
  4041. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4042. ret = -EINVAL;
  4043. goto err;
  4044. }
  4045. if (pinctrl_info->pinctrl == NULL) {
  4046. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4047. ret = -EINVAL;
  4048. goto err;
  4049. }
  4050. curr_state = pinctrl_info->curr_state;
  4051. pinctrl_info->curr_state = new_state;
  4052. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4053. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4054. if (curr_state == pinctrl_info->curr_state) {
  4055. pr_debug("%s: Already in same state\n", __func__);
  4056. goto err;
  4057. }
  4058. if (curr_state != STATE_DISABLE &&
  4059. pinctrl_info->curr_state != STATE_DISABLE) {
  4060. pr_debug("%s: state already active cannot switch\n", __func__);
  4061. ret = -EIO;
  4062. goto err;
  4063. }
  4064. switch (pinctrl_info->curr_state) {
  4065. case STATE_MI2S_ACTIVE:
  4066. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4067. pinctrl_info->mi2s_active);
  4068. if (ret) {
  4069. pr_err("%s: MI2S state select failed with %d\n",
  4070. __func__, ret);
  4071. ret = -EIO;
  4072. goto err;
  4073. }
  4074. break;
  4075. case STATE_TDM_ACTIVE:
  4076. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4077. pinctrl_info->tdm_active);
  4078. if (ret) {
  4079. pr_err("%s: TDM state select failed with %d\n",
  4080. __func__, ret);
  4081. ret = -EIO;
  4082. goto err;
  4083. }
  4084. break;
  4085. case STATE_DISABLE:
  4086. if (curr_state == STATE_MI2S_ACTIVE) {
  4087. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4088. pinctrl_info->mi2s_disable);
  4089. } else {
  4090. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4091. pinctrl_info->tdm_disable);
  4092. }
  4093. if (ret) {
  4094. pr_err("%s: state disable failed with %d\n",
  4095. __func__, ret);
  4096. ret = -EIO;
  4097. goto err;
  4098. }
  4099. break;
  4100. default:
  4101. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4102. return -EINVAL;
  4103. }
  4104. err:
  4105. return ret;
  4106. }
  4107. static void msm_release_pinctrl(struct platform_device *pdev)
  4108. {
  4109. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4110. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4111. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4112. if (pinctrl_info->pinctrl) {
  4113. devm_pinctrl_put(pinctrl_info->pinctrl);
  4114. pinctrl_info->pinctrl = NULL;
  4115. }
  4116. }
  4117. static int msm_get_pinctrl(struct platform_device *pdev)
  4118. {
  4119. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4120. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4121. struct msm_pinctrl_info *pinctrl_info = NULL;
  4122. struct pinctrl *pinctrl;
  4123. int ret;
  4124. pinctrl_info = &pdata->pinctrl_info;
  4125. if (pinctrl_info == NULL) {
  4126. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4127. return -EINVAL;
  4128. }
  4129. pinctrl = devm_pinctrl_get(&pdev->dev);
  4130. if (IS_ERR_OR_NULL(pinctrl)) {
  4131. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4132. return -EINVAL;
  4133. }
  4134. pinctrl_info->pinctrl = pinctrl;
  4135. /* get all the states handles from Device Tree */
  4136. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4137. "quat-mi2s-sleep");
  4138. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4139. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4140. goto err;
  4141. }
  4142. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4143. "quat-mi2s-active");
  4144. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4145. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4146. goto err;
  4147. }
  4148. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4149. "quat-tdm-sleep");
  4150. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4151. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4152. goto err;
  4153. }
  4154. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4155. "quat-tdm-active");
  4156. if (IS_ERR(pinctrl_info->tdm_active)) {
  4157. pr_err("%s: could not get tdm_active pinstate\n",
  4158. __func__);
  4159. goto err;
  4160. }
  4161. /* Reset the TLMM pins to a default state */
  4162. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4163. pinctrl_info->mi2s_disable);
  4164. if (ret != 0) {
  4165. pr_err("%s: Disable TLMM pins failed with %d\n",
  4166. __func__, ret);
  4167. ret = -EIO;
  4168. goto err;
  4169. }
  4170. pinctrl_info->curr_state = STATE_DISABLE;
  4171. return 0;
  4172. err:
  4173. devm_pinctrl_put(pinctrl);
  4174. pinctrl_info->pinctrl = NULL;
  4175. return -EINVAL;
  4176. }
  4177. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4178. struct snd_pcm_hw_params *params)
  4179. {
  4180. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4181. struct snd_interval *rate = hw_param_interval(params,
  4182. SNDRV_PCM_HW_PARAM_RATE);
  4183. struct snd_interval *channels = hw_param_interval(params,
  4184. SNDRV_PCM_HW_PARAM_CHANNELS);
  4185. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4186. channels->min = channels->max =
  4187. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4188. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4189. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4190. rate->min = rate->max =
  4191. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4192. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4193. channels->min = channels->max =
  4194. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4195. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4196. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4197. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4198. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4199. channels->min = channels->max =
  4200. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4201. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4202. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4203. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4204. } else {
  4205. pr_err("%s: dai id 0x%x not supported\n",
  4206. __func__, cpu_dai->id);
  4207. return -EINVAL;
  4208. }
  4209. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4210. __func__, cpu_dai->id, channels->max, rate->max,
  4211. params_format(params));
  4212. return 0;
  4213. }
  4214. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4215. struct snd_pcm_hw_params *params)
  4216. {
  4217. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4218. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4219. int ret = 0;
  4220. int slot_width = 32;
  4221. int channels, slots;
  4222. unsigned int slot_mask, rate, clk_freq;
  4223. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4224. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4225. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4226. switch (cpu_dai->id) {
  4227. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4228. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4229. break;
  4230. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4231. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4232. break;
  4233. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4234. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4235. break;
  4236. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4237. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4238. break;
  4239. case AFE_PORT_ID_QUINARY_TDM_RX:
  4240. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4241. break;
  4242. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4243. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4244. break;
  4245. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4246. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4247. break;
  4248. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4249. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4250. break;
  4251. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4252. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4253. break;
  4254. case AFE_PORT_ID_QUINARY_TDM_TX:
  4255. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4256. break;
  4257. default:
  4258. pr_err("%s: dai id 0x%x not supported\n",
  4259. __func__, cpu_dai->id);
  4260. return -EINVAL;
  4261. }
  4262. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4263. /*2 slot config - bits 0 and 1 set for the first two slots */
  4264. slot_mask = 0x0000FFFF >> (16-slots);
  4265. channels = slots;
  4266. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4267. __func__, slot_width, slots);
  4268. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4269. slots, slot_width);
  4270. if (ret < 0) {
  4271. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4272. __func__, ret);
  4273. goto end;
  4274. }
  4275. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4276. 0, NULL, channels, slot_offset);
  4277. if (ret < 0) {
  4278. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4279. __func__, ret);
  4280. goto end;
  4281. }
  4282. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4283. /*2 slot config - bits 0 and 1 set for the first two slots */
  4284. slot_mask = 0x0000FFFF >> (16-slots);
  4285. channels = slots;
  4286. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4287. __func__, slot_width, slots);
  4288. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4289. slots, slot_width);
  4290. if (ret < 0) {
  4291. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4292. __func__, ret);
  4293. goto end;
  4294. }
  4295. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4296. channels, slot_offset, 0, NULL);
  4297. if (ret < 0) {
  4298. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4299. __func__, ret);
  4300. goto end;
  4301. }
  4302. } else {
  4303. ret = -EINVAL;
  4304. pr_err("%s: invalid use case, err:%d\n",
  4305. __func__, ret);
  4306. goto end;
  4307. }
  4308. rate = params_rate(params);
  4309. clk_freq = rate * slot_width * slots;
  4310. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4311. if (ret < 0)
  4312. pr_err("%s: failed to set tdm clk, err:%d\n",
  4313. __func__, ret);
  4314. end:
  4315. return ret;
  4316. }
  4317. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4318. {
  4319. int ret = 0;
  4320. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4321. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4322. struct snd_soc_card *card = rtd->card;
  4323. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4324. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4325. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4326. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4327. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4328. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4329. if (ret)
  4330. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4331. __func__, ret);
  4332. }
  4333. return ret;
  4334. }
  4335. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4336. {
  4337. int ret = 0;
  4338. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4339. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4340. struct snd_soc_card *card = rtd->card;
  4341. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4342. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4343. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4344. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4345. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4346. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4347. if (ret)
  4348. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4349. __func__, ret);
  4350. }
  4351. }
  4352. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4353. .hw_params = qcs405_tdm_snd_hw_params,
  4354. .startup = qcs405_tdm_snd_startup,
  4355. .shutdown = qcs405_tdm_snd_shutdown
  4356. };
  4357. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4358. {
  4359. cpumask_t mask;
  4360. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4361. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4362. cpumask_clear(&mask);
  4363. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4364. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4365. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4366. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4367. pm_qos_add_request(&substream->latency_pm_qos_req,
  4368. PM_QOS_CPU_DMA_LATENCY,
  4369. MSM_LL_QOS_VALUE);
  4370. return 0;
  4371. }
  4372. static struct snd_soc_ops msm_fe_qos_ops = {
  4373. .prepare = msm_fe_qos_prepare,
  4374. };
  4375. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4376. {
  4377. int ret = 0;
  4378. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4379. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4380. int index = cpu_dai->id;
  4381. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4382. struct snd_soc_card *card = rtd->card;
  4383. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4384. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4385. int ret_pinctrl = 0;
  4386. dev_dbg(rtd->card->dev,
  4387. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4388. __func__, substream->name, substream->stream,
  4389. cpu_dai->name, cpu_dai->id);
  4390. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4391. ret = -EINVAL;
  4392. dev_err(rtd->card->dev,
  4393. "%s: CPU DAI id (%d) out of range\n",
  4394. __func__, cpu_dai->id);
  4395. goto err;
  4396. }
  4397. /*
  4398. * Mutex protection in case the same MI2S
  4399. * interface using for both TX and RX so
  4400. * that the same clock won't be enable twice.
  4401. */
  4402. mutex_lock(&mi2s_intf_conf[index].lock);
  4403. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4404. /* Check if msm needs to provide the clock to the interface */
  4405. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4406. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4407. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4408. }
  4409. ret = msm_mi2s_set_sclk(substream, true);
  4410. if (ret < 0) {
  4411. dev_err(rtd->card->dev,
  4412. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4413. __func__, ret);
  4414. goto clean_up;
  4415. }
  4416. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4417. if (ret < 0) {
  4418. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4419. __func__, index, ret);
  4420. goto clk_off;
  4421. }
  4422. if (index == QUAT_MI2S) {
  4423. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4424. STATE_MI2S_ACTIVE);
  4425. if (ret_pinctrl)
  4426. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4427. __func__, ret_pinctrl);
  4428. }
  4429. }
  4430. clk_off:
  4431. if (ret < 0)
  4432. msm_mi2s_set_sclk(substream, false);
  4433. clean_up:
  4434. if (ret < 0)
  4435. mi2s_intf_conf[index].ref_cnt--;
  4436. mutex_unlock(&mi2s_intf_conf[index].lock);
  4437. err:
  4438. return ret;
  4439. }
  4440. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4441. {
  4442. int ret;
  4443. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4444. int index = rtd->cpu_dai->id;
  4445. struct snd_soc_card *card = rtd->card;
  4446. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4447. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4448. int ret_pinctrl = 0;
  4449. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4450. substream->name, substream->stream);
  4451. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4452. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4453. return;
  4454. }
  4455. mutex_lock(&mi2s_intf_conf[index].lock);
  4456. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4457. ret = msm_mi2s_set_sclk(substream, false);
  4458. if (ret < 0)
  4459. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4460. __func__, index, ret);
  4461. if (index == QUAT_MI2S) {
  4462. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4463. STATE_DISABLE);
  4464. if (ret_pinctrl)
  4465. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4466. __func__, ret_pinctrl);
  4467. }
  4468. }
  4469. mutex_unlock(&mi2s_intf_conf[index].lock);
  4470. }
  4471. static struct snd_soc_ops msm_mi2s_be_ops = {
  4472. .startup = msm_mi2s_snd_startup,
  4473. .shutdown = msm_mi2s_snd_shutdown,
  4474. };
  4475. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4476. .hw_params = msm_snd_cdc_dma_hw_params,
  4477. };
  4478. static struct snd_soc_ops msm_be_ops = {
  4479. .hw_params = msm_snd_hw_params,
  4480. };
  4481. static struct snd_soc_ops msm_wcn_ops = {
  4482. .hw_params = msm_wcn_hw_params,
  4483. };
  4484. /* Digital audio interface glue - connects codec <---> CPU */
  4485. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4486. /* FrontEnd DAI Links */
  4487. {
  4488. .name = MSM_DAILINK_NAME(Media1),
  4489. .stream_name = "MultiMedia1",
  4490. .cpu_dai_name = "MultiMedia1",
  4491. .platform_name = "msm-pcm-dsp.0",
  4492. .dynamic = 1,
  4493. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4494. .dpcm_playback = 1,
  4495. .dpcm_capture = 1,
  4496. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4497. SND_SOC_DPCM_TRIGGER_POST},
  4498. .codec_dai_name = "snd-soc-dummy-dai",
  4499. .codec_name = "snd-soc-dummy",
  4500. .ignore_suspend = 1,
  4501. /* this dainlink has playback support */
  4502. .ignore_pmdown_time = 1,
  4503. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4504. },
  4505. {
  4506. .name = MSM_DAILINK_NAME(Media2),
  4507. .stream_name = "MultiMedia2",
  4508. .cpu_dai_name = "MultiMedia2",
  4509. .platform_name = "msm-pcm-dsp.0",
  4510. .dynamic = 1,
  4511. .dpcm_playback = 1,
  4512. .dpcm_capture = 1,
  4513. .codec_dai_name = "snd-soc-dummy-dai",
  4514. .codec_name = "snd-soc-dummy",
  4515. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4516. SND_SOC_DPCM_TRIGGER_POST},
  4517. .ignore_suspend = 1,
  4518. /* this dainlink has playback support */
  4519. .ignore_pmdown_time = 1,
  4520. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4521. },
  4522. {
  4523. .name = "VoiceMMode1",
  4524. .stream_name = "VoiceMMode1",
  4525. .cpu_dai_name = "VoiceMMode1",
  4526. .platform_name = "msm-pcm-voice",
  4527. .dynamic = 1,
  4528. .dpcm_playback = 1,
  4529. .dpcm_capture = 1,
  4530. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4531. SND_SOC_DPCM_TRIGGER_POST},
  4532. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4533. .ignore_suspend = 1,
  4534. .ignore_pmdown_time = 1,
  4535. .codec_dai_name = "snd-soc-dummy-dai",
  4536. .codec_name = "snd-soc-dummy",
  4537. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4538. },
  4539. {
  4540. .name = "MSM VoIP",
  4541. .stream_name = "VoIP",
  4542. .cpu_dai_name = "VoIP",
  4543. .platform_name = "msm-voip-dsp",
  4544. .dynamic = 1,
  4545. .dpcm_playback = 1,
  4546. .dpcm_capture = 1,
  4547. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4548. SND_SOC_DPCM_TRIGGER_POST},
  4549. .codec_dai_name = "snd-soc-dummy-dai",
  4550. .codec_name = "snd-soc-dummy",
  4551. .ignore_suspend = 1,
  4552. /* this dainlink has playback support */
  4553. .ignore_pmdown_time = 1,
  4554. .id = MSM_FRONTEND_DAI_VOIP,
  4555. },
  4556. {
  4557. .name = MSM_DAILINK_NAME(ULL),
  4558. .stream_name = "MultiMedia3",
  4559. .cpu_dai_name = "MultiMedia3",
  4560. .platform_name = "msm-pcm-dsp.2",
  4561. .dynamic = 1,
  4562. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4563. .dpcm_playback = 1,
  4564. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4565. SND_SOC_DPCM_TRIGGER_POST},
  4566. .codec_dai_name = "snd-soc-dummy-dai",
  4567. .codec_name = "snd-soc-dummy",
  4568. .ignore_suspend = 1,
  4569. /* this dainlink has playback support */
  4570. .ignore_pmdown_time = 1,
  4571. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4572. },
  4573. /* Hostless PCM purpose */
  4574. {
  4575. .name = "SLIMBUS_0 Hostless",
  4576. .stream_name = "SLIMBUS_0 Hostless",
  4577. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  4578. .platform_name = "msm-pcm-hostless",
  4579. .dynamic = 1,
  4580. .dpcm_playback = 1,
  4581. .dpcm_capture = 1,
  4582. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4583. SND_SOC_DPCM_TRIGGER_POST},
  4584. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4585. .ignore_suspend = 1,
  4586. /* this dailink has playback support */
  4587. .ignore_pmdown_time = 1,
  4588. .codec_dai_name = "snd-soc-dummy-dai",
  4589. .codec_name = "snd-soc-dummy",
  4590. },
  4591. {
  4592. .name = "MSM AFE-PCM RX",
  4593. .stream_name = "AFE-PROXY RX",
  4594. .cpu_dai_name = "msm-dai-q6-dev.241",
  4595. .codec_name = "msm-stub-codec.1",
  4596. .codec_dai_name = "msm-stub-rx",
  4597. .platform_name = "msm-pcm-afe",
  4598. .dpcm_playback = 1,
  4599. .ignore_suspend = 1,
  4600. /* this dainlink has playback support */
  4601. .ignore_pmdown_time = 1,
  4602. },
  4603. {
  4604. .name = "MSM AFE-PCM TX",
  4605. .stream_name = "AFE-PROXY TX",
  4606. .cpu_dai_name = "msm-dai-q6-dev.240",
  4607. .codec_name = "msm-stub-codec.1",
  4608. .codec_dai_name = "msm-stub-tx",
  4609. .platform_name = "msm-pcm-afe",
  4610. .dpcm_capture = 1,
  4611. .ignore_suspend = 1,
  4612. },
  4613. {
  4614. .name = MSM_DAILINK_NAME(Compress1),
  4615. .stream_name = "Compress1",
  4616. .cpu_dai_name = "MultiMedia4",
  4617. .platform_name = "msm-compress-dsp",
  4618. .dynamic = 1,
  4619. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4620. .dpcm_playback = 1,
  4621. .dpcm_capture = 1,
  4622. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4623. SND_SOC_DPCM_TRIGGER_POST},
  4624. .codec_dai_name = "snd-soc-dummy-dai",
  4625. .codec_name = "snd-soc-dummy",
  4626. .ignore_suspend = 1,
  4627. .ignore_pmdown_time = 1,
  4628. /* this dainlink has playback support */
  4629. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4630. },
  4631. {
  4632. .name = "AUXPCM Hostless",
  4633. .stream_name = "AUXPCM Hostless",
  4634. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4635. .platform_name = "msm-pcm-hostless",
  4636. .dynamic = 1,
  4637. .dpcm_playback = 1,
  4638. .dpcm_capture = 1,
  4639. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4640. SND_SOC_DPCM_TRIGGER_POST},
  4641. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4642. .ignore_suspend = 1,
  4643. /* this dainlink has playback support */
  4644. .ignore_pmdown_time = 1,
  4645. .codec_dai_name = "snd-soc-dummy-dai",
  4646. .codec_name = "snd-soc-dummy",
  4647. },
  4648. {
  4649. .name = "SLIMBUS_1 Hostless",
  4650. .stream_name = "SLIMBUS_1 Hostless",
  4651. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  4652. .platform_name = "msm-pcm-hostless",
  4653. .dynamic = 1,
  4654. .dpcm_playback = 1,
  4655. .dpcm_capture = 1,
  4656. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4657. SND_SOC_DPCM_TRIGGER_POST},
  4658. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4659. .ignore_suspend = 1,
  4660. /* this dailink has playback support */
  4661. .ignore_pmdown_time = 1,
  4662. .codec_dai_name = "snd-soc-dummy-dai",
  4663. .codec_name = "snd-soc-dummy",
  4664. },
  4665. {
  4666. .name = "SLIMBUS_3 Hostless",
  4667. .stream_name = "SLIMBUS_3 Hostless",
  4668. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  4669. .platform_name = "msm-pcm-hostless",
  4670. .dynamic = 1,
  4671. .dpcm_playback = 1,
  4672. .dpcm_capture = 1,
  4673. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4674. SND_SOC_DPCM_TRIGGER_POST},
  4675. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4676. .ignore_suspend = 1,
  4677. /* this dailink has playback support */
  4678. .ignore_pmdown_time = 1,
  4679. .codec_dai_name = "snd-soc-dummy-dai",
  4680. .codec_name = "snd-soc-dummy",
  4681. },
  4682. {
  4683. .name = "SLIMBUS_4 Hostless",
  4684. .stream_name = "SLIMBUS_4 Hostless",
  4685. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  4686. .platform_name = "msm-pcm-hostless",
  4687. .dynamic = 1,
  4688. .dpcm_playback = 1,
  4689. .dpcm_capture = 1,
  4690. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4691. SND_SOC_DPCM_TRIGGER_POST},
  4692. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4693. .ignore_suspend = 1,
  4694. /* this dailink has playback support */
  4695. .ignore_pmdown_time = 1,
  4696. .codec_dai_name = "snd-soc-dummy-dai",
  4697. .codec_name = "snd-soc-dummy",
  4698. },
  4699. {
  4700. .name = MSM_DAILINK_NAME(LowLatency),
  4701. .stream_name = "MultiMedia5",
  4702. .cpu_dai_name = "MultiMedia5",
  4703. .platform_name = "msm-pcm-dsp.1",
  4704. .dynamic = 1,
  4705. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4706. .dpcm_playback = 1,
  4707. .dpcm_capture = 1,
  4708. .codec_dai_name = "snd-soc-dummy-dai",
  4709. .codec_name = "snd-soc-dummy",
  4710. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4711. SND_SOC_DPCM_TRIGGER_POST},
  4712. .ignore_suspend = 1,
  4713. /* this dainlink has playback support */
  4714. .ignore_pmdown_time = 1,
  4715. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4716. .ops = &msm_fe_qos_ops,
  4717. },
  4718. {
  4719. .name = "Listen 1 Audio Service",
  4720. .stream_name = "Listen 1 Audio Service",
  4721. .cpu_dai_name = "LSM1",
  4722. .platform_name = "msm-lsm-client",
  4723. .dynamic = 1,
  4724. .dpcm_capture = 1,
  4725. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4726. SND_SOC_DPCM_TRIGGER_POST },
  4727. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4728. .ignore_suspend = 1,
  4729. .codec_dai_name = "snd-soc-dummy-dai",
  4730. .codec_name = "snd-soc-dummy",
  4731. .id = MSM_FRONTEND_DAI_LSM1,
  4732. },
  4733. /* Multiple Tunnel instances */
  4734. {
  4735. .name = MSM_DAILINK_NAME(Compress2),
  4736. .stream_name = "Compress2",
  4737. .cpu_dai_name = "MultiMedia7",
  4738. .platform_name = "msm-compress-dsp",
  4739. .dynamic = 1,
  4740. .dpcm_playback = 1,
  4741. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4742. SND_SOC_DPCM_TRIGGER_POST},
  4743. .codec_dai_name = "snd-soc-dummy-dai",
  4744. .codec_name = "snd-soc-dummy",
  4745. .ignore_suspend = 1,
  4746. .ignore_pmdown_time = 1,
  4747. /* this dainlink has playback support */
  4748. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4749. },
  4750. {
  4751. .name = MSM_DAILINK_NAME(MultiMedia10),
  4752. .stream_name = "MultiMedia10",
  4753. .cpu_dai_name = "MultiMedia10",
  4754. .platform_name = "msm-pcm-dsp.1",
  4755. .dynamic = 1,
  4756. .dpcm_playback = 1,
  4757. .dpcm_capture = 1,
  4758. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4759. SND_SOC_DPCM_TRIGGER_POST},
  4760. .codec_dai_name = "snd-soc-dummy-dai",
  4761. .codec_name = "snd-soc-dummy",
  4762. .ignore_suspend = 1,
  4763. .ignore_pmdown_time = 1,
  4764. /* this dainlink has playback support */
  4765. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4766. },
  4767. {
  4768. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4769. .stream_name = "MM_NOIRQ",
  4770. .cpu_dai_name = "MultiMedia8",
  4771. .platform_name = "msm-pcm-dsp-noirq",
  4772. .dynamic = 1,
  4773. .dpcm_playback = 1,
  4774. .dpcm_capture = 1,
  4775. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4776. SND_SOC_DPCM_TRIGGER_POST},
  4777. .codec_dai_name = "snd-soc-dummy-dai",
  4778. .codec_name = "snd-soc-dummy",
  4779. .ignore_suspend = 1,
  4780. .ignore_pmdown_time = 1,
  4781. /* this dainlink has playback support */
  4782. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4783. .ops = &msm_fe_qos_ops,
  4784. },
  4785. /* HDMI Hostless */
  4786. {
  4787. .name = "HDMI_RX_HOSTLESS",
  4788. .stream_name = "HDMI_RX_HOSTLESS",
  4789. .cpu_dai_name = "HDMI_HOSTLESS",
  4790. .platform_name = "msm-pcm-hostless",
  4791. .dynamic = 1,
  4792. .dpcm_playback = 1,
  4793. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4794. SND_SOC_DPCM_TRIGGER_POST},
  4795. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4796. .ignore_suspend = 1,
  4797. .ignore_pmdown_time = 1,
  4798. .codec_dai_name = "snd-soc-dummy-dai",
  4799. .codec_name = "snd-soc-dummy",
  4800. },
  4801. {
  4802. .name = "VoiceMMode2",
  4803. .stream_name = "VoiceMMode2",
  4804. .cpu_dai_name = "VoiceMMode2",
  4805. .platform_name = "msm-pcm-voice",
  4806. .dynamic = 1,
  4807. .dpcm_playback = 1,
  4808. .dpcm_capture = 1,
  4809. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4810. SND_SOC_DPCM_TRIGGER_POST},
  4811. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4812. .ignore_suspend = 1,
  4813. .ignore_pmdown_time = 1,
  4814. .codec_dai_name = "snd-soc-dummy-dai",
  4815. .codec_name = "snd-soc-dummy",
  4816. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4817. },
  4818. /* LSM FE */
  4819. {
  4820. .name = "Listen 2 Audio Service",
  4821. .stream_name = "Listen 2 Audio Service",
  4822. .cpu_dai_name = "LSM2",
  4823. .platform_name = "msm-lsm-client",
  4824. .dynamic = 1,
  4825. .dpcm_capture = 1,
  4826. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4827. SND_SOC_DPCM_TRIGGER_POST },
  4828. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4829. .ignore_suspend = 1,
  4830. .codec_dai_name = "snd-soc-dummy-dai",
  4831. .codec_name = "snd-soc-dummy",
  4832. .id = MSM_FRONTEND_DAI_LSM2,
  4833. },
  4834. {
  4835. .name = "Listen 3 Audio Service",
  4836. .stream_name = "Listen 3 Audio Service",
  4837. .cpu_dai_name = "LSM3",
  4838. .platform_name = "msm-lsm-client",
  4839. .dynamic = 1,
  4840. .dpcm_capture = 1,
  4841. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4842. SND_SOC_DPCM_TRIGGER_POST },
  4843. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4844. .ignore_suspend = 1,
  4845. .codec_dai_name = "snd-soc-dummy-dai",
  4846. .codec_name = "snd-soc-dummy",
  4847. .id = MSM_FRONTEND_DAI_LSM3,
  4848. },
  4849. {
  4850. .name = "Listen 4 Audio Service",
  4851. .stream_name = "Listen 4 Audio Service",
  4852. .cpu_dai_name = "LSM4",
  4853. .platform_name = "msm-lsm-client",
  4854. .dynamic = 1,
  4855. .dpcm_capture = 1,
  4856. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4857. SND_SOC_DPCM_TRIGGER_POST },
  4858. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4859. .ignore_suspend = 1,
  4860. .codec_dai_name = "snd-soc-dummy-dai",
  4861. .codec_name = "snd-soc-dummy",
  4862. .id = MSM_FRONTEND_DAI_LSM4,
  4863. },
  4864. {
  4865. .name = "Listen 5 Audio Service",
  4866. .stream_name = "Listen 5 Audio Service",
  4867. .cpu_dai_name = "LSM5",
  4868. .platform_name = "msm-lsm-client",
  4869. .dynamic = 1,
  4870. .dpcm_capture = 1,
  4871. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4872. SND_SOC_DPCM_TRIGGER_POST },
  4873. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4874. .ignore_suspend = 1,
  4875. .codec_dai_name = "snd-soc-dummy-dai",
  4876. .codec_name = "snd-soc-dummy",
  4877. .id = MSM_FRONTEND_DAI_LSM5,
  4878. },
  4879. {
  4880. .name = "Listen 6 Audio Service",
  4881. .stream_name = "Listen 6 Audio Service",
  4882. .cpu_dai_name = "LSM6",
  4883. .platform_name = "msm-lsm-client",
  4884. .dynamic = 1,
  4885. .dpcm_capture = 1,
  4886. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4887. SND_SOC_DPCM_TRIGGER_POST },
  4888. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4889. .ignore_suspend = 1,
  4890. .codec_dai_name = "snd-soc-dummy-dai",
  4891. .codec_name = "snd-soc-dummy",
  4892. .id = MSM_FRONTEND_DAI_LSM6,
  4893. },
  4894. {
  4895. .name = "Listen 7 Audio Service",
  4896. .stream_name = "Listen 7 Audio Service",
  4897. .cpu_dai_name = "LSM7",
  4898. .platform_name = "msm-lsm-client",
  4899. .dynamic = 1,
  4900. .dpcm_capture = 1,
  4901. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4902. SND_SOC_DPCM_TRIGGER_POST },
  4903. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4904. .ignore_suspend = 1,
  4905. .codec_dai_name = "snd-soc-dummy-dai",
  4906. .codec_name = "snd-soc-dummy",
  4907. .id = MSM_FRONTEND_DAI_LSM7,
  4908. },
  4909. {
  4910. .name = "Listen 8 Audio Service",
  4911. .stream_name = "Listen 8 Audio Service",
  4912. .cpu_dai_name = "LSM8",
  4913. .platform_name = "msm-lsm-client",
  4914. .dynamic = 1,
  4915. .dpcm_capture = 1,
  4916. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4917. SND_SOC_DPCM_TRIGGER_POST },
  4918. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4919. .ignore_suspend = 1,
  4920. .codec_dai_name = "snd-soc-dummy-dai",
  4921. .codec_name = "snd-soc-dummy",
  4922. .id = MSM_FRONTEND_DAI_LSM8,
  4923. },
  4924. {
  4925. .name = MSM_DAILINK_NAME(Media9),
  4926. .stream_name = "MultiMedia9",
  4927. .cpu_dai_name = "MultiMedia9",
  4928. .platform_name = "msm-pcm-dsp.0",
  4929. .dynamic = 1,
  4930. .dpcm_playback = 1,
  4931. .dpcm_capture = 1,
  4932. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4933. SND_SOC_DPCM_TRIGGER_POST},
  4934. .codec_dai_name = "snd-soc-dummy-dai",
  4935. .codec_name = "snd-soc-dummy",
  4936. .ignore_suspend = 1,
  4937. /* this dainlink has playback support */
  4938. .ignore_pmdown_time = 1,
  4939. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4940. },
  4941. {
  4942. .name = MSM_DAILINK_NAME(Compress4),
  4943. .stream_name = "Compress4",
  4944. .cpu_dai_name = "MultiMedia11",
  4945. .platform_name = "msm-compress-dsp",
  4946. .dynamic = 1,
  4947. .dpcm_playback = 1,
  4948. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4949. SND_SOC_DPCM_TRIGGER_POST},
  4950. .codec_dai_name = "snd-soc-dummy-dai",
  4951. .codec_name = "snd-soc-dummy",
  4952. .ignore_suspend = 1,
  4953. .ignore_pmdown_time = 1,
  4954. /* this dainlink has playback support */
  4955. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4956. },
  4957. {
  4958. .name = MSM_DAILINK_NAME(Compress5),
  4959. .stream_name = "Compress5",
  4960. .cpu_dai_name = "MultiMedia12",
  4961. .platform_name = "msm-compress-dsp",
  4962. .dynamic = 1,
  4963. .dpcm_playback = 1,
  4964. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4965. SND_SOC_DPCM_TRIGGER_POST},
  4966. .codec_dai_name = "snd-soc-dummy-dai",
  4967. .codec_name = "snd-soc-dummy",
  4968. .ignore_suspend = 1,
  4969. .ignore_pmdown_time = 1,
  4970. /* this dainlink has playback support */
  4971. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4972. },
  4973. {
  4974. .name = MSM_DAILINK_NAME(Compress6),
  4975. .stream_name = "Compress6",
  4976. .cpu_dai_name = "MultiMedia13",
  4977. .platform_name = "msm-compress-dsp",
  4978. .dynamic = 1,
  4979. .dpcm_playback = 1,
  4980. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4981. SND_SOC_DPCM_TRIGGER_POST},
  4982. .codec_dai_name = "snd-soc-dummy-dai",
  4983. .codec_name = "snd-soc-dummy",
  4984. .ignore_suspend = 1,
  4985. .ignore_pmdown_time = 1,
  4986. /* this dainlink has playback support */
  4987. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  4988. },
  4989. {
  4990. .name = MSM_DAILINK_NAME(Compress7),
  4991. .stream_name = "Compress7",
  4992. .cpu_dai_name = "MultiMedia14",
  4993. .platform_name = "msm-compress-dsp",
  4994. .dynamic = 1,
  4995. .dpcm_playback = 1,
  4996. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4997. SND_SOC_DPCM_TRIGGER_POST},
  4998. .codec_dai_name = "snd-soc-dummy-dai",
  4999. .codec_name = "snd-soc-dummy",
  5000. .ignore_suspend = 1,
  5001. .ignore_pmdown_time = 1,
  5002. /* this dainlink has playback support */
  5003. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5004. },
  5005. {
  5006. .name = MSM_DAILINK_NAME(Compress8),
  5007. .stream_name = "Compress8",
  5008. .cpu_dai_name = "MultiMedia15",
  5009. .platform_name = "msm-compress-dsp",
  5010. .dynamic = 1,
  5011. .dpcm_playback = 1,
  5012. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5013. SND_SOC_DPCM_TRIGGER_POST},
  5014. .codec_dai_name = "snd-soc-dummy-dai",
  5015. .codec_name = "snd-soc-dummy",
  5016. .ignore_suspend = 1,
  5017. .ignore_pmdown_time = 1,
  5018. /* this dainlink has playback support */
  5019. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5020. },
  5021. {
  5022. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5023. .stream_name = "MM_NOIRQ_2",
  5024. .cpu_dai_name = "MultiMedia16",
  5025. .platform_name = "msm-pcm-dsp-noirq",
  5026. .dynamic = 1,
  5027. .dpcm_playback = 1,
  5028. .dpcm_capture = 1,
  5029. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5030. SND_SOC_DPCM_TRIGGER_POST},
  5031. .codec_dai_name = "snd-soc-dummy-dai",
  5032. .codec_name = "snd-soc-dummy",
  5033. .ignore_suspend = 1,
  5034. .ignore_pmdown_time = 1,
  5035. /* this dainlink has playback support */
  5036. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5037. },
  5038. {
  5039. .name = "SLIMBUS_8 Hostless",
  5040. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5041. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5042. .platform_name = "msm-pcm-hostless",
  5043. .dynamic = 1,
  5044. .dpcm_capture = 1,
  5045. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5046. SND_SOC_DPCM_TRIGGER_POST},
  5047. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5048. .ignore_suspend = 1,
  5049. .codec_dai_name = "snd-soc-dummy-dai",
  5050. .codec_name = "snd-soc-dummy",
  5051. },
  5052. /* Hostless PCM purpose */
  5053. {
  5054. .name = "CDC_DMA Hostless",
  5055. .stream_name = "CDC_DMA Hostless",
  5056. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5057. .platform_name = "msm-pcm-hostless",
  5058. .dynamic = 1,
  5059. .dpcm_playback = 1,
  5060. .dpcm_capture = 1,
  5061. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5062. SND_SOC_DPCM_TRIGGER_POST},
  5063. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5064. .ignore_suspend = 1,
  5065. /* this dailink has playback support */
  5066. .ignore_pmdown_time = 1,
  5067. .codec_dai_name = "snd-soc-dummy-dai",
  5068. .codec_name = "snd-soc-dummy",
  5069. },
  5070. };
  5071. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5072. {
  5073. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5074. .stream_name = "WSA CDC DMA0 Capture",
  5075. .cpu_dai_name = "msm-dai-cdc-dma.45057",
  5076. .platform_name = "msm-pcm-hostless",
  5077. .codec_name = "bolero_codec",
  5078. .codec_dai_name = "wsa_macro_vifeedback",
  5079. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5080. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5081. .ignore_suspend = 1,
  5082. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5083. .ops = &msm_cdc_dma_be_ops,
  5084. },
  5085. };
  5086. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5087. {
  5088. .name = MSM_DAILINK_NAME(ASM Loopback),
  5089. .stream_name = "MultiMedia6",
  5090. .cpu_dai_name = "MultiMedia6",
  5091. .platform_name = "msm-pcm-loopback",
  5092. .dynamic = 1,
  5093. .dpcm_playback = 1,
  5094. .dpcm_capture = 1,
  5095. .codec_dai_name = "snd-soc-dummy-dai",
  5096. .codec_name = "snd-soc-dummy",
  5097. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5098. SND_SOC_DPCM_TRIGGER_POST},
  5099. .ignore_suspend = 1,
  5100. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5101. .ignore_pmdown_time = 1,
  5102. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5103. },
  5104. {
  5105. .name = "USB Audio Hostless",
  5106. .stream_name = "USB Audio Hostless",
  5107. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5108. .platform_name = "msm-pcm-hostless",
  5109. .dynamic = 1,
  5110. .dpcm_playback = 1,
  5111. .dpcm_capture = 1,
  5112. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5113. SND_SOC_DPCM_TRIGGER_POST},
  5114. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5115. .ignore_suspend = 1,
  5116. .ignore_pmdown_time = 1,
  5117. .codec_dai_name = "snd-soc-dummy-dai",
  5118. .codec_name = "snd-soc-dummy",
  5119. },
  5120. {
  5121. .name = "SLIMBUS_7 Hostless",
  5122. .stream_name = "SLIMBUS_7 Hostless",
  5123. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5124. .platform_name = "msm-pcm-hostless",
  5125. .dynamic = 1,
  5126. .dpcm_capture = 1,
  5127. .dpcm_playback = 1,
  5128. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5129. SND_SOC_DPCM_TRIGGER_POST},
  5130. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5131. .ignore_suspend = 1,
  5132. .ignore_pmdown_time = 1,
  5133. .codec_dai_name = "snd-soc-dummy-dai",
  5134. .codec_name = "snd-soc-dummy",
  5135. },
  5136. };
  5137. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5138. /* Backend AFE DAI Links */
  5139. {
  5140. .name = LPASS_BE_AFE_PCM_RX,
  5141. .stream_name = "AFE Playback",
  5142. .cpu_dai_name = "msm-dai-q6-dev.224",
  5143. .platform_name = "msm-pcm-routing",
  5144. .codec_name = "msm-stub-codec.1",
  5145. .codec_dai_name = "msm-stub-rx",
  5146. .no_pcm = 1,
  5147. .dpcm_playback = 1,
  5148. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5149. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5150. /* this dainlink has playback support */
  5151. .ignore_pmdown_time = 1,
  5152. .ignore_suspend = 1,
  5153. },
  5154. {
  5155. .name = LPASS_BE_AFE_PCM_TX,
  5156. .stream_name = "AFE Capture",
  5157. .cpu_dai_name = "msm-dai-q6-dev.225",
  5158. .platform_name = "msm-pcm-routing",
  5159. .codec_name = "msm-stub-codec.1",
  5160. .codec_dai_name = "msm-stub-tx",
  5161. .no_pcm = 1,
  5162. .dpcm_capture = 1,
  5163. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5164. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5165. .ignore_suspend = 1,
  5166. },
  5167. /* Incall Record Uplink BACK END DAI Link */
  5168. {
  5169. .name = LPASS_BE_INCALL_RECORD_TX,
  5170. .stream_name = "Voice Uplink Capture",
  5171. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5172. .platform_name = "msm-pcm-routing",
  5173. .codec_name = "msm-stub-codec.1",
  5174. .codec_dai_name = "msm-stub-tx",
  5175. .no_pcm = 1,
  5176. .dpcm_capture = 1,
  5177. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5178. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5179. .ignore_suspend = 1,
  5180. },
  5181. /* Incall Record Downlink BACK END DAI Link */
  5182. {
  5183. .name = LPASS_BE_INCALL_RECORD_RX,
  5184. .stream_name = "Voice Downlink Capture",
  5185. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5186. .platform_name = "msm-pcm-routing",
  5187. .codec_name = "msm-stub-codec.1",
  5188. .codec_dai_name = "msm-stub-tx",
  5189. .no_pcm = 1,
  5190. .dpcm_capture = 1,
  5191. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5192. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5193. .ignore_suspend = 1,
  5194. },
  5195. /* Incall Music BACK END DAI Link */
  5196. {
  5197. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5198. .stream_name = "Voice Farend Playback",
  5199. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5200. .platform_name = "msm-pcm-routing",
  5201. .codec_name = "msm-stub-codec.1",
  5202. .codec_dai_name = "msm-stub-rx",
  5203. .no_pcm = 1,
  5204. .dpcm_playback = 1,
  5205. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5206. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5207. .ignore_suspend = 1,
  5208. .ignore_pmdown_time = 1,
  5209. },
  5210. /* Incall Music 2 BACK END DAI Link */
  5211. {
  5212. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5213. .stream_name = "Voice2 Farend Playback",
  5214. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5215. .platform_name = "msm-pcm-routing",
  5216. .codec_name = "msm-stub-codec.1",
  5217. .codec_dai_name = "msm-stub-rx",
  5218. .no_pcm = 1,
  5219. .dpcm_playback = 1,
  5220. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5221. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5222. .ignore_suspend = 1,
  5223. .ignore_pmdown_time = 1,
  5224. },
  5225. {
  5226. .name = LPASS_BE_USB_AUDIO_RX,
  5227. .stream_name = "USB Audio Playback",
  5228. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5229. .platform_name = "msm-pcm-routing",
  5230. .codec_name = "msm-stub-codec.1",
  5231. .codec_dai_name = "msm-stub-rx",
  5232. .no_pcm = 1,
  5233. .dpcm_playback = 1,
  5234. .id = MSM_BACKEND_DAI_USB_RX,
  5235. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5236. .ignore_pmdown_time = 1,
  5237. .ignore_suspend = 1,
  5238. },
  5239. {
  5240. .name = LPASS_BE_USB_AUDIO_TX,
  5241. .stream_name = "USB Audio Capture",
  5242. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5243. .platform_name = "msm-pcm-routing",
  5244. .codec_name = "msm-stub-codec.1",
  5245. .codec_dai_name = "msm-stub-tx",
  5246. .no_pcm = 1,
  5247. .dpcm_capture = 1,
  5248. .id = MSM_BACKEND_DAI_USB_TX,
  5249. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5250. .ignore_suspend = 1,
  5251. },
  5252. {
  5253. .name = LPASS_BE_PRI_TDM_RX_0,
  5254. .stream_name = "Primary TDM0 Playback",
  5255. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5256. .platform_name = "msm-pcm-routing",
  5257. .codec_name = "msm-stub-codec.1",
  5258. .codec_dai_name = "msm-stub-rx",
  5259. .no_pcm = 1,
  5260. .dpcm_playback = 1,
  5261. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5262. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5263. .ops = &qcs405_tdm_be_ops,
  5264. .ignore_suspend = 1,
  5265. .ignore_pmdown_time = 1,
  5266. },
  5267. {
  5268. .name = LPASS_BE_PRI_TDM_TX_0,
  5269. .stream_name = "Primary TDM0 Capture",
  5270. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5271. .platform_name = "msm-pcm-routing",
  5272. .codec_name = "msm-stub-codec.1",
  5273. .codec_dai_name = "msm-stub-tx",
  5274. .no_pcm = 1,
  5275. .dpcm_capture = 1,
  5276. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5277. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5278. .ops = &qcs405_tdm_be_ops,
  5279. .ignore_suspend = 1,
  5280. },
  5281. {
  5282. .name = LPASS_BE_SEC_TDM_RX_0,
  5283. .stream_name = "Secondary TDM0 Playback",
  5284. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5285. .platform_name = "msm-pcm-routing",
  5286. .codec_name = "msm-stub-codec.1",
  5287. .codec_dai_name = "msm-stub-rx",
  5288. .no_pcm = 1,
  5289. .dpcm_playback = 1,
  5290. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5291. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5292. .ops = &qcs405_tdm_be_ops,
  5293. .ignore_suspend = 1,
  5294. .ignore_pmdown_time = 1,
  5295. },
  5296. {
  5297. .name = LPASS_BE_SEC_TDM_TX_0,
  5298. .stream_name = "Secondary TDM0 Capture",
  5299. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5300. .platform_name = "msm-pcm-routing",
  5301. .codec_name = "msm-stub-codec.1",
  5302. .codec_dai_name = "msm-stub-tx",
  5303. .no_pcm = 1,
  5304. .dpcm_capture = 1,
  5305. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5306. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5307. .ops = &qcs405_tdm_be_ops,
  5308. .ignore_suspend = 1,
  5309. },
  5310. {
  5311. .name = LPASS_BE_TERT_TDM_RX_0,
  5312. .stream_name = "Tertiary TDM0 Playback",
  5313. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5314. .platform_name = "msm-pcm-routing",
  5315. .codec_name = "msm-stub-codec.1",
  5316. .codec_dai_name = "msm-stub-rx",
  5317. .no_pcm = 1,
  5318. .dpcm_playback = 1,
  5319. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5320. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5321. .ops = &qcs405_tdm_be_ops,
  5322. .ignore_suspend = 1,
  5323. .ignore_pmdown_time = 1,
  5324. },
  5325. {
  5326. .name = LPASS_BE_TERT_TDM_TX_0,
  5327. .stream_name = "Tertiary TDM0 Capture",
  5328. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5329. .platform_name = "msm-pcm-routing",
  5330. .codec_name = "msm-stub-codec.1",
  5331. .codec_dai_name = "msm-stub-tx",
  5332. .no_pcm = 1,
  5333. .dpcm_capture = 1,
  5334. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5335. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5336. .ops = &qcs405_tdm_be_ops,
  5337. .ignore_suspend = 1,
  5338. },
  5339. {
  5340. .name = LPASS_BE_QUAT_TDM_RX_0,
  5341. .stream_name = "Quaternary TDM0 Playback",
  5342. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5343. .platform_name = "msm-pcm-routing",
  5344. .codec_name = "msm-stub-codec.1",
  5345. .codec_dai_name = "msm-stub-rx",
  5346. .no_pcm = 1,
  5347. .dpcm_playback = 1,
  5348. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5349. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5350. .ops = &qcs405_tdm_be_ops,
  5351. .ignore_suspend = 1,
  5352. .ignore_pmdown_time = 1,
  5353. },
  5354. {
  5355. .name = LPASS_BE_QUAT_TDM_TX_0,
  5356. .stream_name = "Quaternary TDM0 Capture",
  5357. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5358. .platform_name = "msm-pcm-routing",
  5359. .codec_name = "msm-stub-codec.1",
  5360. .codec_dai_name = "msm-stub-tx",
  5361. .no_pcm = 1,
  5362. .dpcm_capture = 1,
  5363. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5364. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5365. .ops = &qcs405_tdm_be_ops,
  5366. .ignore_suspend = 1,
  5367. },
  5368. {
  5369. .name = LPASS_BE_QUIN_TDM_RX_0,
  5370. .stream_name = "Quinary TDM0 Playback",
  5371. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5372. .platform_name = "msm-pcm-routing",
  5373. .codec_name = "msm-stub-codec.1",
  5374. .codec_dai_name = "msm-stub-rx",
  5375. .no_pcm = 1,
  5376. .dpcm_playback = 1,
  5377. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5378. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5379. .ops = &qcs405_tdm_be_ops,
  5380. .ignore_suspend = 1,
  5381. .ignore_pmdown_time = 1,
  5382. },
  5383. {
  5384. .name = LPASS_BE_QUIN_TDM_TX_0,
  5385. .stream_name = "Quinary TDM0 Capture",
  5386. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5387. .platform_name = "msm-pcm-routing",
  5388. .codec_name = "msm-stub-codec.1",
  5389. .codec_dai_name = "msm-stub-tx",
  5390. .no_pcm = 1,
  5391. .dpcm_capture = 1,
  5392. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5393. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5394. .ops = &qcs405_tdm_be_ops,
  5395. .ignore_suspend = 1,
  5396. },
  5397. };
  5398. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5399. {
  5400. .name = LPASS_BE_SLIMBUS_0_RX,
  5401. .stream_name = "Slimbus Playback",
  5402. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5403. .platform_name = "msm-pcm-routing",
  5404. .codec_name = "tasha_codec",
  5405. .codec_dai_name = "tasha_mix_rx1",
  5406. .no_pcm = 1,
  5407. .dpcm_playback = 1,
  5408. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5409. .init = &msm_audrx_init,
  5410. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5411. /* this dainlink has playback support */
  5412. .ignore_pmdown_time = 1,
  5413. .ignore_suspend = 1,
  5414. .ops = &msm_be_ops,
  5415. },
  5416. {
  5417. .name = LPASS_BE_SLIMBUS_0_TX,
  5418. .stream_name = "Slimbus Capture",
  5419. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5420. .platform_name = "msm-pcm-routing",
  5421. .codec_name = "tasha_codec",
  5422. .codec_dai_name = "tasha_tx1",
  5423. .no_pcm = 1,
  5424. .dpcm_capture = 1,
  5425. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5426. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5427. .ignore_suspend = 1,
  5428. .ops = &msm_be_ops,
  5429. },
  5430. {
  5431. .name = LPASS_BE_SLIMBUS_1_RX,
  5432. .stream_name = "Slimbus1 Playback",
  5433. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5434. .platform_name = "msm-pcm-routing",
  5435. .codec_name = "tasha_codec",
  5436. .codec_dai_name = "tasha_mix_rx1",
  5437. .no_pcm = 1,
  5438. .dpcm_playback = 1,
  5439. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5440. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5441. .ops = &msm_be_ops,
  5442. /* dai link has playback support */
  5443. .ignore_pmdown_time = 1,
  5444. .ignore_suspend = 1,
  5445. },
  5446. {
  5447. .name = LPASS_BE_SLIMBUS_1_TX,
  5448. .stream_name = "Slimbus1 Capture",
  5449. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5450. .platform_name = "msm-pcm-routing",
  5451. .codec_name = "tasha_codec",
  5452. .codec_dai_name = "tasha_tx3",
  5453. .no_pcm = 1,
  5454. .dpcm_capture = 1,
  5455. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5456. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5457. .ops = &msm_be_ops,
  5458. .ignore_suspend = 1,
  5459. },
  5460. {
  5461. .name = LPASS_BE_SLIMBUS_2_RX,
  5462. .stream_name = "Slimbus2 Playback",
  5463. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5464. .platform_name = "msm-pcm-routing",
  5465. .codec_name = "tasha_codec",
  5466. .codec_dai_name = "tasha_rx2",
  5467. .no_pcm = 1,
  5468. .dpcm_playback = 1,
  5469. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  5470. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5471. .ops = &msm_be_ops,
  5472. .ignore_pmdown_time = 1,
  5473. .ignore_suspend = 1,
  5474. },
  5475. {
  5476. .name = LPASS_BE_SLIMBUS_3_RX,
  5477. .stream_name = "Slimbus3 Playback",
  5478. .cpu_dai_name = "msm-dai-q6-dev.16390",
  5479. .platform_name = "msm-pcm-routing",
  5480. .codec_name = "tasha_codec",
  5481. .codec_dai_name = "tasha_mix_rx1",
  5482. .no_pcm = 1,
  5483. .dpcm_playback = 1,
  5484. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  5485. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5486. .ops = &msm_be_ops,
  5487. /* dai link has playback support */
  5488. .ignore_pmdown_time = 1,
  5489. .ignore_suspend = 1,
  5490. },
  5491. {
  5492. .name = LPASS_BE_SLIMBUS_3_TX,
  5493. .stream_name = "Slimbus3 Capture",
  5494. .cpu_dai_name = "msm-dai-q6-dev.16391",
  5495. .platform_name = "msm-pcm-routing",
  5496. .codec_name = "tasha_codec",
  5497. .codec_dai_name = "tasha_tx1",
  5498. .no_pcm = 1,
  5499. .dpcm_capture = 1,
  5500. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  5501. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5502. .ops = &msm_be_ops,
  5503. .ignore_suspend = 1,
  5504. },
  5505. {
  5506. .name = LPASS_BE_SLIMBUS_4_RX,
  5507. .stream_name = "Slimbus4 Playback",
  5508. .cpu_dai_name = "msm-dai-q6-dev.16392",
  5509. .platform_name = "msm-pcm-routing",
  5510. .codec_name = "tasha_codec",
  5511. .codec_dai_name = "tasha_mix_rx1",
  5512. .no_pcm = 1,
  5513. .dpcm_playback = 1,
  5514. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  5515. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5516. .ops = &msm_be_ops,
  5517. /* dai link has playback support */
  5518. .ignore_pmdown_time = 1,
  5519. .ignore_suspend = 1,
  5520. },
  5521. {
  5522. .name = LPASS_BE_SLIMBUS_5_RX,
  5523. .stream_name = "Slimbus5 Playback",
  5524. .cpu_dai_name = "msm-dai-q6-dev.16394",
  5525. .platform_name = "msm-pcm-routing",
  5526. .codec_name = "tasha_codec",
  5527. .codec_dai_name = "tasha_rx3",
  5528. .no_pcm = 1,
  5529. .dpcm_playback = 1,
  5530. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  5531. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5532. .ops = &msm_be_ops,
  5533. /* dai link has playback support */
  5534. .ignore_pmdown_time = 1,
  5535. .ignore_suspend = 1,
  5536. },
  5537. {
  5538. .name = LPASS_BE_SLIMBUS_6_RX,
  5539. .stream_name = "Slimbus6 Playback",
  5540. .cpu_dai_name = "msm-dai-q6-dev.16396",
  5541. .platform_name = "msm-pcm-routing",
  5542. .codec_name = "tasha_codec",
  5543. .codec_dai_name = "tasha_rx4",
  5544. .no_pcm = 1,
  5545. .dpcm_playback = 1,
  5546. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  5547. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5548. .ops = &msm_be_ops,
  5549. /* dai link has playback support */
  5550. .ignore_pmdown_time = 1,
  5551. .ignore_suspend = 1,
  5552. },
  5553. /* Slimbus VI Recording */
  5554. {
  5555. .name = LPASS_BE_SLIMBUS_TX_VI,
  5556. .stream_name = "Slimbus4 Capture",
  5557. .cpu_dai_name = "msm-dai-q6-dev.16393",
  5558. .platform_name = "msm-pcm-routing",
  5559. .codec_name = "tasha_codec",
  5560. .codec_dai_name = "tasha_vifeedback",
  5561. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  5562. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5563. .ops = &msm_be_ops,
  5564. .ignore_suspend = 1,
  5565. .no_pcm = 1,
  5566. .dpcm_capture = 1,
  5567. .ignore_pmdown_time = 1,
  5568. },
  5569. };
  5570. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5571. {
  5572. .name = LPASS_BE_SLIMBUS_7_RX,
  5573. .stream_name = "Slimbus7 Playback",
  5574. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5575. .platform_name = "msm-pcm-routing",
  5576. .codec_name = "btfmslim_slave",
  5577. /* BT codec driver determines capabilities based on
  5578. * dai name, bt codecdai name should always contains
  5579. * supported usecase information
  5580. */
  5581. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5582. .no_pcm = 1,
  5583. .dpcm_playback = 1,
  5584. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5585. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5586. .ops = &msm_wcn_ops,
  5587. /* dai link has playback support */
  5588. .ignore_pmdown_time = 1,
  5589. .ignore_suspend = 1,
  5590. },
  5591. {
  5592. .name = LPASS_BE_SLIMBUS_7_TX,
  5593. .stream_name = "Slimbus7 Capture",
  5594. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5595. .platform_name = "msm-pcm-routing",
  5596. .codec_name = "btfmslim_slave",
  5597. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5598. .no_pcm = 1,
  5599. .dpcm_capture = 1,
  5600. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5601. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5602. .ops = &msm_wcn_ops,
  5603. .ignore_suspend = 1,
  5604. },
  5605. {
  5606. .name = LPASS_BE_SLIMBUS_8_TX,
  5607. .stream_name = "Slimbus8 Capture",
  5608. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5609. .platform_name = "msm-pcm-routing",
  5610. .codec_name = "btfmslim_slave",
  5611. .codec_dai_name = "btfm_fm_slim_tx",
  5612. .no_pcm = 1,
  5613. .dpcm_capture = 1,
  5614. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5615. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5616. .init = &msm_wcn_init,
  5617. .ops = &msm_wcn_ops,
  5618. .ignore_suspend = 1,
  5619. },
  5620. };
  5621. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5622. {
  5623. .name = LPASS_BE_PRI_MI2S_RX,
  5624. .stream_name = "Primary MI2S Playback",
  5625. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5626. .platform_name = "msm-pcm-routing",
  5627. .codec_name = "msm-stub-codec.1",
  5628. .codec_dai_name = "msm-stub-rx",
  5629. .no_pcm = 1,
  5630. .dpcm_playback = 1,
  5631. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5632. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5633. .ops = &msm_mi2s_be_ops,
  5634. .ignore_suspend = 1,
  5635. .ignore_pmdown_time = 1,
  5636. },
  5637. {
  5638. .name = LPASS_BE_PRI_MI2S_TX,
  5639. .stream_name = "Primary MI2S Capture",
  5640. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5641. .platform_name = "msm-pcm-routing",
  5642. .codec_name = "msm-stub-codec.1",
  5643. .codec_dai_name = "msm-stub-tx",
  5644. .no_pcm = 1,
  5645. .dpcm_capture = 1,
  5646. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5647. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5648. .ops = &msm_mi2s_be_ops,
  5649. .ignore_suspend = 1,
  5650. },
  5651. {
  5652. .name = LPASS_BE_SEC_MI2S_RX,
  5653. .stream_name = "Secondary MI2S Playback",
  5654. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5655. .platform_name = "msm-pcm-routing",
  5656. .codec_name = "msm-stub-codec.1",
  5657. .codec_dai_name = "msm-stub-rx",
  5658. .no_pcm = 1,
  5659. .dpcm_playback = 1,
  5660. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5661. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5662. .ops = &msm_mi2s_be_ops,
  5663. .ignore_suspend = 1,
  5664. .ignore_pmdown_time = 1,
  5665. },
  5666. {
  5667. .name = LPASS_BE_SEC_MI2S_TX,
  5668. .stream_name = "Secondary MI2S Capture",
  5669. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5670. .platform_name = "msm-pcm-routing",
  5671. .codec_name = "msm-stub-codec.1",
  5672. .codec_dai_name = "msm-stub-tx",
  5673. .no_pcm = 1,
  5674. .dpcm_capture = 1,
  5675. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5676. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5677. .ops = &msm_mi2s_be_ops,
  5678. .ignore_suspend = 1,
  5679. },
  5680. {
  5681. .name = LPASS_BE_TERT_MI2S_RX,
  5682. .stream_name = "Tertiary MI2S Playback",
  5683. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5684. .platform_name = "msm-pcm-routing",
  5685. .codec_name = "msm-stub-codec.1",
  5686. .codec_dai_name = "msm-stub-rx",
  5687. .no_pcm = 1,
  5688. .dpcm_playback = 1,
  5689. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5690. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5691. .ops = &msm_mi2s_be_ops,
  5692. .ignore_suspend = 1,
  5693. .ignore_pmdown_time = 1,
  5694. },
  5695. {
  5696. .name = LPASS_BE_TERT_MI2S_TX,
  5697. .stream_name = "Tertiary MI2S Capture",
  5698. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5699. .platform_name = "msm-pcm-routing",
  5700. .codec_name = "msm-stub-codec.1",
  5701. .codec_dai_name = "msm-stub-tx",
  5702. .no_pcm = 1,
  5703. .dpcm_capture = 1,
  5704. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5705. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5706. .ops = &msm_mi2s_be_ops,
  5707. .ignore_suspend = 1,
  5708. },
  5709. {
  5710. .name = LPASS_BE_QUAT_MI2S_RX,
  5711. .stream_name = "Quaternary MI2S Playback",
  5712. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5713. .platform_name = "msm-pcm-routing",
  5714. .codec_name = "msm-stub-codec.1",
  5715. .codec_dai_name = "msm-stub-rx",
  5716. .no_pcm = 1,
  5717. .dpcm_playback = 1,
  5718. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5719. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5720. .ops = &msm_mi2s_be_ops,
  5721. .ignore_suspend = 1,
  5722. .ignore_pmdown_time = 1,
  5723. },
  5724. {
  5725. .name = LPASS_BE_QUAT_MI2S_TX,
  5726. .stream_name = "Quaternary MI2S Capture",
  5727. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5728. .platform_name = "msm-pcm-routing",
  5729. .codec_name = "msm-stub-codec.1",
  5730. .codec_dai_name = "msm-stub-tx",
  5731. .no_pcm = 1,
  5732. .dpcm_capture = 1,
  5733. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5734. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5735. .ops = &msm_mi2s_be_ops,
  5736. .ignore_suspend = 1,
  5737. },
  5738. {
  5739. .name = LPASS_BE_QUIN_MI2S_RX,
  5740. .stream_name = "Quinary MI2S Playback",
  5741. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5742. .platform_name = "msm-pcm-routing",
  5743. .codec_name = "msm-stub-codec.1",
  5744. .codec_dai_name = "msm-stub-rx",
  5745. .no_pcm = 1,
  5746. .dpcm_playback = 1,
  5747. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5748. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5749. .ops = &msm_mi2s_be_ops,
  5750. .ignore_suspend = 1,
  5751. .ignore_pmdown_time = 1,
  5752. },
  5753. {
  5754. .name = LPASS_BE_QUIN_MI2S_TX,
  5755. .stream_name = "Quinary MI2S Capture",
  5756. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5757. .platform_name = "msm-pcm-routing",
  5758. .codec_name = "msm-stub-codec.1",
  5759. .codec_dai_name = "msm-stub-tx",
  5760. .no_pcm = 1,
  5761. .dpcm_capture = 1,
  5762. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5763. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5764. .ops = &msm_mi2s_be_ops,
  5765. .ignore_suspend = 1,
  5766. },
  5767. };
  5768. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5769. /* Primary AUX PCM Backend DAI Links */
  5770. {
  5771. .name = LPASS_BE_AUXPCM_RX,
  5772. .stream_name = "AUX PCM Playback",
  5773. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5774. .platform_name = "msm-pcm-routing",
  5775. .codec_name = "msm-stub-codec.1",
  5776. .codec_dai_name = "msm-stub-rx",
  5777. .no_pcm = 1,
  5778. .dpcm_playback = 1,
  5779. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5780. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5781. .ignore_pmdown_time = 1,
  5782. .ignore_suspend = 1,
  5783. },
  5784. {
  5785. .name = LPASS_BE_AUXPCM_TX,
  5786. .stream_name = "AUX PCM Capture",
  5787. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5788. .platform_name = "msm-pcm-routing",
  5789. .codec_name = "msm-stub-codec.1",
  5790. .codec_dai_name = "msm-stub-tx",
  5791. .no_pcm = 1,
  5792. .dpcm_capture = 1,
  5793. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5794. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5795. .ignore_suspend = 1,
  5796. },
  5797. /* Secondary AUX PCM Backend DAI Links */
  5798. {
  5799. .name = LPASS_BE_SEC_AUXPCM_RX,
  5800. .stream_name = "Sec AUX PCM Playback",
  5801. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5802. .platform_name = "msm-pcm-routing",
  5803. .codec_name = "msm-stub-codec.1",
  5804. .codec_dai_name = "msm-stub-rx",
  5805. .no_pcm = 1,
  5806. .dpcm_playback = 1,
  5807. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5808. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5809. .ignore_pmdown_time = 1,
  5810. .ignore_suspend = 1,
  5811. },
  5812. {
  5813. .name = LPASS_BE_SEC_AUXPCM_TX,
  5814. .stream_name = "Sec AUX PCM Capture",
  5815. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5816. .platform_name = "msm-pcm-routing",
  5817. .codec_name = "msm-stub-codec.1",
  5818. .codec_dai_name = "msm-stub-tx",
  5819. .no_pcm = 1,
  5820. .dpcm_capture = 1,
  5821. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5822. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5823. .ignore_suspend = 1,
  5824. },
  5825. /* Tertiary AUX PCM Backend DAI Links */
  5826. {
  5827. .name = LPASS_BE_TERT_AUXPCM_RX,
  5828. .stream_name = "Tert AUX PCM Playback",
  5829. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5830. .platform_name = "msm-pcm-routing",
  5831. .codec_name = "msm-stub-codec.1",
  5832. .codec_dai_name = "msm-stub-rx",
  5833. .no_pcm = 1,
  5834. .dpcm_playback = 1,
  5835. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5836. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5837. .ignore_suspend = 1,
  5838. },
  5839. {
  5840. .name = LPASS_BE_TERT_AUXPCM_TX,
  5841. .stream_name = "Tert AUX PCM Capture",
  5842. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5843. .platform_name = "msm-pcm-routing",
  5844. .codec_name = "msm-stub-codec.1",
  5845. .codec_dai_name = "msm-stub-tx",
  5846. .no_pcm = 1,
  5847. .dpcm_capture = 1,
  5848. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5849. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5850. .ignore_suspend = 1,
  5851. },
  5852. /* Quaternary AUX PCM Backend DAI Links */
  5853. {
  5854. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5855. .stream_name = "Quat AUX PCM Playback",
  5856. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5857. .platform_name = "msm-pcm-routing",
  5858. .codec_name = "msm-stub-codec.1",
  5859. .codec_dai_name = "msm-stub-rx",
  5860. .no_pcm = 1,
  5861. .dpcm_playback = 1,
  5862. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5863. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5864. .ignore_pmdown_time = 1,
  5865. .ignore_suspend = 1,
  5866. },
  5867. {
  5868. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5869. .stream_name = "Quat AUX PCM Capture",
  5870. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5871. .platform_name = "msm-pcm-routing",
  5872. .codec_name = "msm-stub-codec.1",
  5873. .codec_dai_name = "msm-stub-tx",
  5874. .no_pcm = 1,
  5875. .dpcm_capture = 1,
  5876. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5877. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5878. .ignore_suspend = 1,
  5879. },
  5880. /* Quinary AUX PCM Backend DAI Links */
  5881. {
  5882. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5883. .stream_name = "Quin AUX PCM Playback",
  5884. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5885. .platform_name = "msm-pcm-routing",
  5886. .codec_name = "msm-stub-codec.1",
  5887. .codec_dai_name = "msm-stub-rx",
  5888. .no_pcm = 1,
  5889. .dpcm_playback = 1,
  5890. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5891. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5892. .ignore_pmdown_time = 1,
  5893. .ignore_suspend = 1,
  5894. },
  5895. {
  5896. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5897. .stream_name = "Quin AUX PCM Capture",
  5898. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5899. .platform_name = "msm-pcm-routing",
  5900. .codec_name = "msm-stub-codec.1",
  5901. .codec_dai_name = "msm-stub-tx",
  5902. .no_pcm = 1,
  5903. .dpcm_capture = 1,
  5904. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5905. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5906. .ignore_suspend = 1,
  5907. },
  5908. };
  5909. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  5910. /* WSA CDC DMA Backend DAI Links */
  5911. {
  5912. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  5913. .stream_name = "WSA CDC DMA0 Playback",
  5914. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  5915. .platform_name = "msm-pcm-routing",
  5916. .codec_name = "bolero_codec",
  5917. .codec_dai_name = "wsa_macro_rx1",
  5918. .no_pcm = 1,
  5919. .dpcm_playback = 1,
  5920. .init = &msm_wsa_cdc_dma_init,
  5921. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  5922. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5923. .ignore_pmdown_time = 1,
  5924. .ignore_suspend = 1,
  5925. .ops = &msm_cdc_dma_be_ops,
  5926. },
  5927. {
  5928. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  5929. .stream_name = "WSA CDC DMA1 Playback",
  5930. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  5931. .platform_name = "msm-pcm-routing",
  5932. .codec_name = "bolero_codec",
  5933. .codec_dai_name = "wsa_macro_rx_mix",
  5934. .no_pcm = 1,
  5935. .dpcm_playback = 1,
  5936. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  5937. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5938. .ignore_pmdown_time = 1,
  5939. .ignore_suspend = 1,
  5940. .ops = &msm_cdc_dma_be_ops,
  5941. },
  5942. {
  5943. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  5944. .stream_name = "WSA CDC DMA1 Capture",
  5945. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  5946. .platform_name = "msm-pcm-routing",
  5947. .codec_name = "bolero_codec",
  5948. .codec_dai_name = "wsa_macro_echo",
  5949. .no_pcm = 1,
  5950. .dpcm_capture = 1,
  5951. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  5952. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5953. .ignore_suspend = 1,
  5954. .ops = &msm_cdc_dma_be_ops,
  5955. },
  5956. };
  5957. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  5958. {
  5959. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  5960. .stream_name = "VA CDC DMA0 Capture",
  5961. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  5962. .platform_name = "msm-pcm-routing",
  5963. .codec_name = "bolero_codec",
  5964. .codec_dai_name = "va_macro_tx1",
  5965. .no_pcm = 1,
  5966. .dpcm_capture = 1,
  5967. .init = &msm_va_cdc_dma_init,
  5968. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  5969. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5970. .ignore_suspend = 1,
  5971. .ops = &msm_cdc_dma_be_ops,
  5972. },
  5973. {
  5974. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  5975. .stream_name = "VA CDC DMA1 Capture",
  5976. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  5977. .platform_name = "msm-pcm-routing",
  5978. .codec_name = "bolero_codec",
  5979. .codec_dai_name = "va_macro_tx2",
  5980. .no_pcm = 1,
  5981. .dpcm_capture = 1,
  5982. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  5983. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5984. .ignore_suspend = 1,
  5985. .ops = &msm_cdc_dma_be_ops,
  5986. },
  5987. };
  5988. static struct snd_soc_dai_link msm_qcs405_dai_links[
  5989. ARRAY_SIZE(msm_common_dai_links) +
  5990. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  5991. ARRAY_SIZE(msm_common_be_dai_links) +
  5992. ARRAY_SIZE(msm_tasha_be_dai_links) +
  5993. ARRAY_SIZE(msm_wcn_be_dai_links) +
  5994. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  5995. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  5996. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  5997. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  5998. ARRAY_SIZE(msm_bolero_fe_dai_links)];
  5999. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6000. {
  6001. int ret = 0;
  6002. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6003. &service_nb);
  6004. if (ret < 0)
  6005. pr_err("%s: Audio notifier register failed ret = %d\n",
  6006. __func__, ret);
  6007. return ret;
  6008. }
  6009. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6010. struct snd_ctl_elem_value *ucontrol)
  6011. {
  6012. int ret = 0;
  6013. int port_id;
  6014. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6015. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6016. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6017. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6018. (vad_enable < 0) || (vad_enable > 1) ||
  6019. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6020. pr_err("%s: Invalid arguments\n", __func__);
  6021. ret = -EINVAL;
  6022. goto done;
  6023. }
  6024. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6025. vad_enable, preroll_config, vad_intf);
  6026. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6027. if (ret) {
  6028. pr_err("%s: Invalid vad interface\n", __func__);
  6029. goto done;
  6030. }
  6031. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6032. done:
  6033. return ret;
  6034. }
  6035. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6036. {
  6037. int ret = 0;
  6038. uint32_t tasha_codec = 0;
  6039. ret = afe_cal_init_hwdep(card);
  6040. if (ret) {
  6041. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6042. ret = 0;
  6043. }
  6044. /* tasha late probe when it is present */
  6045. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6046. &tasha_codec);
  6047. if (ret) {
  6048. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6049. ret = 0;
  6050. } else {
  6051. if (tasha_codec) {
  6052. ret = msm_snd_card_tasha_late_probe(card);
  6053. if (ret)
  6054. dev_err(card->dev, "%s: tasha late probe err\n",
  6055. __func__);
  6056. }
  6057. }
  6058. return ret;
  6059. }
  6060. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6061. .name = "qcs405-snd-card",
  6062. .controls = msm_snd_controls,
  6063. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6064. .late_probe = msm_snd_card_codec_late_probe,
  6065. };
  6066. static int msm_populate_dai_link_component_of_node(
  6067. struct snd_soc_card *card)
  6068. {
  6069. int i, index, ret = 0;
  6070. struct device *cdev = card->dev;
  6071. struct snd_soc_dai_link *dai_link = card->dai_link;
  6072. struct device_node *np;
  6073. if (!cdev) {
  6074. pr_err("%s: Sound card device memory NULL\n", __func__);
  6075. return -ENODEV;
  6076. }
  6077. for (i = 0; i < card->num_links; i++) {
  6078. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6079. continue;
  6080. /* populate platform_of_node for snd card dai links */
  6081. if (dai_link[i].platform_name &&
  6082. !dai_link[i].platform_of_node) {
  6083. index = of_property_match_string(cdev->of_node,
  6084. "asoc-platform-names",
  6085. dai_link[i].platform_name);
  6086. if (index < 0) {
  6087. pr_err("%s: No match found for platform name: %s\n",
  6088. __func__, dai_link[i].platform_name);
  6089. ret = index;
  6090. goto err;
  6091. }
  6092. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6093. index);
  6094. if (!np) {
  6095. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6096. __func__, dai_link[i].platform_name,
  6097. index);
  6098. ret = -ENODEV;
  6099. goto err;
  6100. }
  6101. dai_link[i].platform_of_node = np;
  6102. dai_link[i].platform_name = NULL;
  6103. }
  6104. /* populate cpu_of_node for snd card dai links */
  6105. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6106. index = of_property_match_string(cdev->of_node,
  6107. "asoc-cpu-names",
  6108. dai_link[i].cpu_dai_name);
  6109. if (index >= 0) {
  6110. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6111. index);
  6112. if (!np) {
  6113. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6114. __func__,
  6115. dai_link[i].cpu_dai_name);
  6116. ret = -ENODEV;
  6117. goto err;
  6118. }
  6119. dai_link[i].cpu_of_node = np;
  6120. dai_link[i].cpu_dai_name = NULL;
  6121. }
  6122. }
  6123. /* populate codec_of_node for snd card dai links */
  6124. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6125. index = of_property_match_string(cdev->of_node,
  6126. "asoc-codec-names",
  6127. dai_link[i].codec_name);
  6128. if (index < 0)
  6129. continue;
  6130. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6131. index);
  6132. if (!np) {
  6133. pr_err("%s: retrieving phandle for codec %s failed\n",
  6134. __func__, dai_link[i].codec_name);
  6135. ret = -ENODEV;
  6136. goto err;
  6137. }
  6138. dai_link[i].codec_of_node = np;
  6139. dai_link[i].codec_name = NULL;
  6140. }
  6141. }
  6142. err:
  6143. return ret;
  6144. }
  6145. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6146. /* FrontEnd DAI Links */
  6147. {
  6148. .name = "MSMSTUB Media1",
  6149. .stream_name = "MultiMedia1",
  6150. .cpu_dai_name = "MultiMedia1",
  6151. .platform_name = "msm-pcm-dsp.0",
  6152. .dynamic = 1,
  6153. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6154. .dpcm_playback = 1,
  6155. .dpcm_capture = 1,
  6156. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6157. SND_SOC_DPCM_TRIGGER_POST},
  6158. .codec_dai_name = "snd-soc-dummy-dai",
  6159. .codec_name = "snd-soc-dummy",
  6160. .ignore_suspend = 1,
  6161. /* this dainlink has playback support */
  6162. .ignore_pmdown_time = 1,
  6163. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6164. },
  6165. };
  6166. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6167. /* Backend DAI Links */
  6168. {
  6169. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6170. .stream_name = "VA CDC DMA0 Capture",
  6171. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6172. .platform_name = "msm-pcm-routing",
  6173. .codec_name = "bolero_codec",
  6174. .codec_dai_name = "va_macro_tx1",
  6175. .no_pcm = 1,
  6176. .dpcm_capture = 1,
  6177. .init = &msm_va_cdc_dma_init,
  6178. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6179. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6180. .ignore_suspend = 1,
  6181. .ops = &msm_cdc_dma_be_ops,
  6182. },
  6183. {
  6184. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6185. .stream_name = "VA CDC DMA1 Capture",
  6186. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6187. .platform_name = "msm-pcm-routing",
  6188. .codec_name = "bolero_codec",
  6189. .codec_dai_name = "va_macro_tx2",
  6190. .no_pcm = 1,
  6191. .dpcm_capture = 1,
  6192. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6193. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6194. .ignore_suspend = 1,
  6195. .ops = &msm_cdc_dma_be_ops,
  6196. },
  6197. };
  6198. static struct snd_soc_dai_link msm_stub_dai_links[
  6199. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6200. ARRAY_SIZE(msm_stub_be_dai_links)];
  6201. struct snd_soc_card snd_soc_card_stub_msm = {
  6202. .name = "qcs405-stub-snd-card",
  6203. };
  6204. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6205. { .compatible = "qcom,qcs405-asoc-snd",
  6206. .data = "codec"},
  6207. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6208. .data = "stub_codec"},
  6209. {},
  6210. };
  6211. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6212. {
  6213. struct snd_soc_card *card = NULL;
  6214. struct snd_soc_dai_link *dailink;
  6215. int total_links = 0;
  6216. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6217. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6218. const struct of_device_id *match;
  6219. int rc = 0;
  6220. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6221. if (!match) {
  6222. dev_err(dev, "%s: No DT match found for sound card\n",
  6223. __func__);
  6224. return NULL;
  6225. }
  6226. if (!strcmp(match->data, "codec")) {
  6227. card = &snd_soc_card_qcs405_msm;
  6228. memcpy(msm_qcs405_dai_links + total_links,
  6229. msm_common_dai_links,
  6230. sizeof(msm_common_dai_links));
  6231. total_links += ARRAY_SIZE(msm_common_dai_links);
  6232. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6233. &wsa_bolero_codec);
  6234. if (rc) {
  6235. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6236. __func__);
  6237. } else {
  6238. if (wsa_bolero_codec) {
  6239. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  6240. __func__);
  6241. memcpy(msm_qcs405_dai_links + total_links,
  6242. msm_bolero_fe_dai_links,
  6243. sizeof(msm_bolero_fe_dai_links));
  6244. total_links +=
  6245. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6246. }
  6247. }
  6248. memcpy(msm_qcs405_dai_links + total_links,
  6249. msm_common_misc_fe_dai_links,
  6250. sizeof(msm_common_misc_fe_dai_links));
  6251. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6252. memcpy(msm_qcs405_dai_links + total_links,
  6253. msm_common_be_dai_links,
  6254. sizeof(msm_common_be_dai_links));
  6255. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6256. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6257. &tasha_codec);
  6258. if (rc) {
  6259. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6260. __func__);
  6261. } else {
  6262. if (tasha_codec) {
  6263. memcpy(msm_qcs405_dai_links + total_links,
  6264. msm_tasha_be_dai_links,
  6265. sizeof(msm_tasha_be_dai_links));
  6266. total_links +=
  6267. ARRAY_SIZE(msm_tasha_be_dai_links);
  6268. }
  6269. }
  6270. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6271. &va_bolero_codec);
  6272. if (rc) {
  6273. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6274. __func__);
  6275. } else {
  6276. if (va_bolero_codec) {
  6277. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6278. __func__);
  6279. memcpy(msm_qcs405_dai_links + total_links,
  6280. msm_va_cdc_dma_be_dai_links,
  6281. sizeof(msm_va_cdc_dma_be_dai_links));
  6282. total_links +=
  6283. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6284. }
  6285. }
  6286. if (wsa_bolero_codec) {
  6287. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6288. __func__);
  6289. memcpy(msm_qcs405_dai_links + total_links,
  6290. msm_wsa_cdc_dma_be_dai_links,
  6291. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6292. total_links +=
  6293. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6294. }
  6295. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6296. &mi2s_audio_intf);
  6297. if (rc) {
  6298. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6299. __func__);
  6300. } else {
  6301. if (mi2s_audio_intf) {
  6302. memcpy(msm_qcs405_dai_links + total_links,
  6303. msm_mi2s_be_dai_links,
  6304. sizeof(msm_mi2s_be_dai_links));
  6305. total_links +=
  6306. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6307. }
  6308. }
  6309. rc = of_property_read_u32(dev->of_node,
  6310. "qcom,auxpcm-audio-intf",
  6311. &auxpcm_audio_intf);
  6312. if (rc) {
  6313. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6314. __func__);
  6315. } else {
  6316. if (auxpcm_audio_intf) {
  6317. memcpy(msm_qcs405_dai_links + total_links,
  6318. msm_auxpcm_be_dai_links,
  6319. sizeof(msm_auxpcm_be_dai_links));
  6320. total_links +=
  6321. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6322. }
  6323. }
  6324. dailink = msm_qcs405_dai_links;
  6325. } else if (!strcmp(match->data, "stub_codec")) {
  6326. card = &snd_soc_card_stub_msm;
  6327. memcpy(msm_stub_dai_links + total_links,
  6328. msm_stub_fe_dai_links,
  6329. sizeof(msm_stub_fe_dai_links));
  6330. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6331. memcpy(msm_stub_dai_links + total_links,
  6332. msm_stub_be_dai_links,
  6333. sizeof(msm_stub_be_dai_links));
  6334. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6335. dailink = msm_stub_dai_links;
  6336. }
  6337. if (card) {
  6338. card->dai_link = dailink;
  6339. card->num_links = total_links;
  6340. }
  6341. return card;
  6342. }
  6343. static int msm_wsa881x_init(struct snd_soc_component *component)
  6344. {
  6345. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6346. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6347. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6348. SPKR_L_BOOST, SPKR_L_VI};
  6349. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6350. SPKR_R_BOOST, SPKR_R_VI};
  6351. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6352. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6353. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6354. struct msm_asoc_mach_data *pdata;
  6355. struct snd_soc_dapm_context *dapm;
  6356. int ret = 0;
  6357. if (!codec) {
  6358. pr_err("%s codec is NULL\n", __func__);
  6359. return -EINVAL;
  6360. }
  6361. dapm = snd_soc_codec_get_dapm(codec);
  6362. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6363. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6364. __func__, codec->component.name);
  6365. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6366. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6367. &ch_rate[0], &spkleft_port_types[0]);
  6368. if (dapm->component) {
  6369. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6370. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6371. }
  6372. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6373. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  6374. __func__, codec->component.name);
  6375. wsa881x_set_channel_map(codec, &spkright_ports[0],
  6376. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6377. &ch_rate[0], &spkright_port_types[0]);
  6378. if (dapm->component) {
  6379. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6380. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6381. }
  6382. } else {
  6383. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  6384. codec->component.name);
  6385. ret = -EINVAL;
  6386. goto err;
  6387. }
  6388. pdata = snd_soc_card_get_drvdata(component->card);
  6389. if (pdata && pdata->codec_root)
  6390. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6391. codec);
  6392. err:
  6393. return ret;
  6394. }
  6395. static int msm_init_wsa_dev(struct platform_device *pdev,
  6396. struct snd_soc_card *card)
  6397. {
  6398. struct device_node *wsa_of_node;
  6399. u32 wsa_max_devs;
  6400. u32 wsa_dev_cnt;
  6401. int i;
  6402. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6403. const char *wsa_auxdev_name_prefix[1];
  6404. char *dev_name_str = NULL;
  6405. int found = 0;
  6406. int ret = 0;
  6407. /* Get maximum WSA device count for this platform */
  6408. ret = of_property_read_u32(pdev->dev.of_node,
  6409. "qcom,wsa-max-devs", &wsa_max_devs);
  6410. if (ret) {
  6411. dev_info(&pdev->dev,
  6412. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6413. __func__, pdev->dev.of_node->full_name, ret);
  6414. card->num_aux_devs = 0;
  6415. return 0;
  6416. }
  6417. if (wsa_max_devs == 0) {
  6418. dev_warn(&pdev->dev,
  6419. "%s: Max WSA devices is 0 for this target?\n",
  6420. __func__);
  6421. card->num_aux_devs = 0;
  6422. return 0;
  6423. }
  6424. /* Get count of WSA device phandles for this platform */
  6425. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6426. "qcom,wsa-devs", NULL);
  6427. if (wsa_dev_cnt == -ENOENT) {
  6428. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6429. __func__);
  6430. goto err;
  6431. } else if (wsa_dev_cnt <= 0) {
  6432. dev_err(&pdev->dev,
  6433. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6434. __func__, wsa_dev_cnt);
  6435. ret = -EINVAL;
  6436. goto err;
  6437. }
  6438. /*
  6439. * Expect total phandles count to be NOT less than maximum possible
  6440. * WSA count. However, if it is less, then assign same value to
  6441. * max count as well.
  6442. */
  6443. if (wsa_dev_cnt < wsa_max_devs) {
  6444. dev_dbg(&pdev->dev,
  6445. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6446. __func__, wsa_max_devs, wsa_dev_cnt);
  6447. wsa_max_devs = wsa_dev_cnt;
  6448. }
  6449. /* Make sure prefix string passed for each WSA device */
  6450. ret = of_property_count_strings(pdev->dev.of_node,
  6451. "qcom,wsa-aux-dev-prefix");
  6452. if (ret != wsa_dev_cnt) {
  6453. dev_err(&pdev->dev,
  6454. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6455. __func__, wsa_dev_cnt, ret);
  6456. ret = -EINVAL;
  6457. goto err;
  6458. }
  6459. /*
  6460. * Alloc mem to store phandle and index info of WSA device, if already
  6461. * registered with ALSA core
  6462. */
  6463. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6464. sizeof(struct msm_wsa881x_dev_info),
  6465. GFP_KERNEL);
  6466. if (!wsa881x_dev_info) {
  6467. ret = -ENOMEM;
  6468. goto err;
  6469. }
  6470. /*
  6471. * search and check whether all WSA devices are already
  6472. * registered with ALSA core or not. If found a node, store
  6473. * the node and the index in a local array of struct for later
  6474. * use.
  6475. */
  6476. for (i = 0; i < wsa_dev_cnt; i++) {
  6477. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6478. "qcom,wsa-devs", i);
  6479. if (unlikely(!wsa_of_node)) {
  6480. /* we should not be here */
  6481. dev_err(&pdev->dev,
  6482. "%s: wsa dev node is not present\n",
  6483. __func__);
  6484. ret = -EINVAL;
  6485. goto err_free_dev_info;
  6486. }
  6487. if (soc_find_component(wsa_of_node, NULL)) {
  6488. /* WSA device registered with ALSA core */
  6489. wsa881x_dev_info[found].of_node = wsa_of_node;
  6490. wsa881x_dev_info[found].index = i;
  6491. found++;
  6492. if (found == wsa_max_devs)
  6493. break;
  6494. }
  6495. }
  6496. if (found < wsa_max_devs) {
  6497. dev_err(&pdev->dev,
  6498. "%s: failed to find %d components. Found only %d\n",
  6499. __func__, wsa_max_devs, found);
  6500. return -EPROBE_DEFER;
  6501. }
  6502. dev_info(&pdev->dev,
  6503. "%s: found %d wsa881x devices registered with ALSA core\n",
  6504. __func__, found);
  6505. card->num_aux_devs = wsa_max_devs;
  6506. card->num_configs = wsa_max_devs;
  6507. /* Alloc array of AUX devs struct */
  6508. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6509. sizeof(struct snd_soc_aux_dev),
  6510. GFP_KERNEL);
  6511. if (!msm_aux_dev) {
  6512. ret = -ENOMEM;
  6513. goto err_free_dev_info;
  6514. }
  6515. /* Alloc array of codec conf struct */
  6516. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6517. sizeof(struct snd_soc_codec_conf),
  6518. GFP_KERNEL);
  6519. if (!msm_codec_conf) {
  6520. ret = -ENOMEM;
  6521. goto err_free_aux_dev;
  6522. }
  6523. for (i = 0; i < card->num_aux_devs; i++) {
  6524. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6525. GFP_KERNEL);
  6526. if (!dev_name_str) {
  6527. ret = -ENOMEM;
  6528. goto err_free_cdc_conf;
  6529. }
  6530. ret = of_property_read_string_index(pdev->dev.of_node,
  6531. "qcom,wsa-aux-dev-prefix",
  6532. wsa881x_dev_info[i].index,
  6533. wsa_auxdev_name_prefix);
  6534. if (ret) {
  6535. dev_err(&pdev->dev,
  6536. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6537. __func__, ret);
  6538. ret = -EINVAL;
  6539. goto err_free_dev_name_str;
  6540. }
  6541. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6542. msm_aux_dev[i].name = dev_name_str;
  6543. msm_aux_dev[i].codec_name = NULL;
  6544. msm_aux_dev[i].codec_of_node =
  6545. wsa881x_dev_info[i].of_node;
  6546. msm_aux_dev[i].init = msm_wsa881x_init;
  6547. msm_codec_conf[i].dev_name = NULL;
  6548. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  6549. msm_codec_conf[i].of_node =
  6550. wsa881x_dev_info[i].of_node;
  6551. }
  6552. card->codec_conf = msm_codec_conf;
  6553. card->aux_dev = msm_aux_dev;
  6554. return 0;
  6555. err_free_dev_name_str:
  6556. devm_kfree(&pdev->dev, dev_name_str);
  6557. err_free_cdc_conf:
  6558. devm_kfree(&pdev->dev, msm_codec_conf);
  6559. err_free_aux_dev:
  6560. devm_kfree(&pdev->dev, msm_aux_dev);
  6561. err_free_dev_info:
  6562. devm_kfree(&pdev->dev, wsa881x_dev_info);
  6563. err:
  6564. return ret;
  6565. }
  6566. static int msm_csra66x0_init(struct snd_soc_component *component)
  6567. {
  6568. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6569. if (!codec) {
  6570. pr_err("%s codec is NULL\n", __func__);
  6571. return -EINVAL;
  6572. }
  6573. return 0;
  6574. }
  6575. static int msm_init_csra_dev(struct platform_device *pdev,
  6576. struct snd_soc_card *card)
  6577. {
  6578. struct device_node *csra_of_node;
  6579. u32 csra_max_devs;
  6580. u32 csra_dev_cnt;
  6581. char *dev_name_str = NULL;
  6582. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  6583. const char *csra_auxdev_name_prefix[1];
  6584. int i;
  6585. int found = 0;
  6586. int ret = 0;
  6587. /* Get maximum CSRA device count for this platform */
  6588. ret = of_property_read_u32(pdev->dev.of_node,
  6589. "qcom,csra-max-devs", &csra_max_devs);
  6590. if (ret) {
  6591. dev_info(&pdev->dev,
  6592. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  6593. __func__, pdev->dev.of_node->full_name, ret);
  6594. card->num_aux_devs = 0;
  6595. return 0;
  6596. }
  6597. if (csra_max_devs == 0) {
  6598. dev_warn(&pdev->dev,
  6599. "%s: Max CSRA devices is 0 for this target?\n",
  6600. __func__);
  6601. return 0;
  6602. }
  6603. /* Get count of CSRA device phandles for this platform */
  6604. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6605. "qcom,csra-devs", NULL);
  6606. if (csra_dev_cnt == -ENOENT) {
  6607. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  6608. __func__);
  6609. goto err;
  6610. } else if (csra_dev_cnt <= 0) {
  6611. dev_err(&pdev->dev,
  6612. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  6613. __func__, csra_dev_cnt);
  6614. ret = -EINVAL;
  6615. goto err;
  6616. }
  6617. /*
  6618. * Expect total phandles count to be NOT less than maximum possible
  6619. * CSRA count. However, if it is less, then assign same value to
  6620. * max count as well.
  6621. */
  6622. if (csra_dev_cnt < csra_max_devs) {
  6623. dev_dbg(&pdev->dev,
  6624. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  6625. __func__, csra_max_devs, csra_dev_cnt);
  6626. csra_max_devs = csra_dev_cnt;
  6627. }
  6628. /* Make sure prefix string passed for each CSRA device */
  6629. ret = of_property_count_strings(pdev->dev.of_node,
  6630. "qcom,csra-aux-dev-prefix");
  6631. if (ret != csra_dev_cnt) {
  6632. dev_err(&pdev->dev,
  6633. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  6634. __func__, csra_dev_cnt, ret);
  6635. ret = -EINVAL;
  6636. goto err;
  6637. }
  6638. /*
  6639. * Alloc mem to store phandle and index info of CSRA device, if already
  6640. * registered with ALSA core
  6641. */
  6642. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  6643. sizeof(struct msm_csra66x0_dev_info),
  6644. GFP_KERNEL);
  6645. if (!csra66x0_dev_info) {
  6646. ret = -ENOMEM;
  6647. goto err;
  6648. }
  6649. /*
  6650. * search and check whether all CSRA devices are already
  6651. * registered with ALSA core or not. If found a node, store
  6652. * the node and the index in a local array of struct for later
  6653. * use.
  6654. */
  6655. for (i = 0; i < csra_dev_cnt; i++) {
  6656. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  6657. "qcom,csra-devs", i);
  6658. if (unlikely(!csra_of_node)) {
  6659. /* we should not be here */
  6660. dev_err(&pdev->dev,
  6661. "%s: csra dev node is not present\n",
  6662. __func__);
  6663. ret = -EINVAL;
  6664. goto err_free_dev_info;
  6665. }
  6666. if (soc_find_component(csra_of_node, NULL)) {
  6667. /* CSRA device registered with ALSA core */
  6668. csra66x0_dev_info[found].of_node = csra_of_node;
  6669. csra66x0_dev_info[found].index = i;
  6670. found++;
  6671. if (found == csra_max_devs)
  6672. break;
  6673. }
  6674. }
  6675. if (found < csra_max_devs) {
  6676. dev_dbg(&pdev->dev,
  6677. "%s: failed to find %d components. Found only %d\n",
  6678. __func__, csra_max_devs, found);
  6679. return -EPROBE_DEFER;
  6680. }
  6681. dev_info(&pdev->dev,
  6682. "%s: found %d csra66x0 devices registered with ALSA core\n",
  6683. __func__, found);
  6684. card->num_aux_devs = csra_max_devs;
  6685. card->num_configs = csra_max_devs;
  6686. /* Alloc array of AUX devs struct */
  6687. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6688. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  6689. if (!msm_aux_dev) {
  6690. ret = -ENOMEM;
  6691. goto err_free_dev_info;
  6692. }
  6693. /* Alloc array of codec conf struct */
  6694. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6695. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  6696. if (!msm_codec_conf) {
  6697. ret = -ENOMEM;
  6698. goto err_free_aux_dev;
  6699. }
  6700. for (i = 0; i < card->num_aux_devs; i++) {
  6701. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6702. GFP_KERNEL);
  6703. if (!dev_name_str) {
  6704. ret = -ENOMEM;
  6705. goto err_free_cdc_conf;
  6706. }
  6707. ret = of_property_read_string_index(pdev->dev.of_node,
  6708. "qcom,csra-aux-dev-prefix",
  6709. csra66x0_dev_info[i].index,
  6710. csra_auxdev_name_prefix);
  6711. if (ret) {
  6712. dev_err(&pdev->dev,
  6713. "%s: failed to read csra aux dev prefix, ret = %d\n",
  6714. __func__, ret);
  6715. ret = -EINVAL;
  6716. goto err_free_dev_name_str;
  6717. }
  6718. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  6719. msm_aux_dev[i].name = dev_name_str;
  6720. msm_aux_dev[i].codec_name = NULL;
  6721. msm_aux_dev[i].codec_of_node =
  6722. csra66x0_dev_info[i].of_node;
  6723. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  6724. msm_codec_conf[i].dev_name = NULL;
  6725. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  6726. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  6727. }
  6728. card->codec_conf = msm_codec_conf;
  6729. card->aux_dev = msm_aux_dev;
  6730. return 0;
  6731. err_free_dev_name_str:
  6732. devm_kfree(&pdev->dev, dev_name_str);
  6733. err_free_cdc_conf:
  6734. devm_kfree(&pdev->dev, msm_codec_conf);
  6735. err_free_aux_dev:
  6736. devm_kfree(&pdev->dev, msm_aux_dev);
  6737. err_free_dev_info:
  6738. devm_kfree(&pdev->dev, csra66x0_dev_info);
  6739. err:
  6740. return ret;
  6741. }
  6742. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6743. {
  6744. int count;
  6745. u32 mi2s_master_slave[MI2S_MAX];
  6746. int ret;
  6747. for (count = 0; count < MI2S_MAX; count++) {
  6748. mutex_init(&mi2s_intf_conf[count].lock);
  6749. mi2s_intf_conf[count].ref_cnt = 0;
  6750. }
  6751. ret = of_property_read_u32_array(pdev->dev.of_node,
  6752. "qcom,msm-mi2s-master",
  6753. mi2s_master_slave, MI2S_MAX);
  6754. if (ret) {
  6755. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6756. __func__);
  6757. } else {
  6758. for (count = 0; count < MI2S_MAX; count++) {
  6759. mi2s_intf_conf[count].msm_is_mi2s_master =
  6760. mi2s_master_slave[count];
  6761. }
  6762. }
  6763. }
  6764. static void msm_i2s_auxpcm_deinit(void)
  6765. {
  6766. int count;
  6767. for (count = 0; count < MI2S_MAX; count++) {
  6768. mutex_destroy(&mi2s_intf_conf[count].lock);
  6769. mi2s_intf_conf[count].ref_cnt = 0;
  6770. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6771. }
  6772. }
  6773. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6774. {
  6775. struct snd_soc_card *card;
  6776. struct msm_asoc_mach_data *pdata;
  6777. int ret;
  6778. u32 val;
  6779. if (!pdev->dev.of_node) {
  6780. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  6781. return -EINVAL;
  6782. }
  6783. pdata = devm_kzalloc(&pdev->dev,
  6784. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6785. if (!pdata)
  6786. return -ENOMEM;
  6787. card = populate_snd_card_dailinks(&pdev->dev);
  6788. if (!card) {
  6789. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6790. ret = -EINVAL;
  6791. goto err;
  6792. }
  6793. card->dev = &pdev->dev;
  6794. platform_set_drvdata(pdev, card);
  6795. snd_soc_card_set_drvdata(card, pdata);
  6796. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6797. if (ret) {
  6798. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  6799. ret);
  6800. goto err;
  6801. }
  6802. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6803. if (ret) {
  6804. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  6805. ret);
  6806. goto err;
  6807. }
  6808. ret = msm_populate_dai_link_component_of_node(card);
  6809. if (ret) {
  6810. ret = -EPROBE_DEFER;
  6811. goto err;
  6812. }
  6813. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  6814. if (ret) {
  6815. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  6816. val = 0;
  6817. }
  6818. if (val) {
  6819. ret = msm_init_csra_dev(pdev, card);
  6820. if (ret)
  6821. goto err;
  6822. } else {
  6823. ret = msm_init_wsa_dev(pdev, card);
  6824. if (ret)
  6825. goto err;
  6826. }
  6827. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6828. "qcom,cdc-dmic01-gpios",
  6829. 0);
  6830. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6831. "qcom,cdc-dmic23-gpios",
  6832. 0);
  6833. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6834. "qcom,cdc-dmic45-gpios",
  6835. 0);
  6836. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6837. "qcom,cdc-dmic67-gpios",
  6838. 0);
  6839. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6840. if (ret == -EPROBE_DEFER) {
  6841. if (codec_reg_done)
  6842. ret = -EINVAL;
  6843. goto err;
  6844. } else if (ret) {
  6845. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  6846. ret);
  6847. goto err;
  6848. }
  6849. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  6850. spdev = pdev;
  6851. /* Parse pinctrl info from devicetree */
  6852. ret = msm_get_pinctrl(pdev);
  6853. if (!ret) {
  6854. pr_debug("%s: pinctrl parsing successful\n", __func__);
  6855. } else {
  6856. dev_dbg(&pdev->dev,
  6857. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  6858. __func__, ret);
  6859. ret = 0;
  6860. }
  6861. msm_i2s_auxpcm_init(pdev);
  6862. is_initial_boot = true;
  6863. return 0;
  6864. err:
  6865. msm_release_pinctrl(pdev);
  6866. return ret;
  6867. }
  6868. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6869. {
  6870. audio_notifier_deregister("qcs405");
  6871. msm_i2s_auxpcm_deinit();
  6872. msm_release_pinctrl(pdev);
  6873. return 0;
  6874. }
  6875. static struct platform_driver qcs405_asoc_machine_driver = {
  6876. .driver = {
  6877. .name = DRV_NAME,
  6878. .owner = THIS_MODULE,
  6879. .pm = &snd_soc_pm_ops,
  6880. .of_match_table = qcs405_asoc_machine_of_match,
  6881. },
  6882. .probe = msm_asoc_machine_probe,
  6883. .remove = msm_asoc_machine_remove,
  6884. };
  6885. module_platform_driver(qcs405_asoc_machine_driver);
  6886. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  6887. MODULE_LICENSE("GPL v2");
  6888. MODULE_ALIAS("platform:" DRV_NAME);
  6889. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);