pci_platform.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */
  3. #ifndef _CNSS_PCI_PLATFORM_H
  4. #define _CNSS_PCI_PLATFORM_H
  5. #include "pci.h"
  6. #if IS_ENABLED(CONFIG_PCI_MSM)
  7. /**
  8. * _cnss_pci_enumerate() - Enumerate PCIe endpoints
  9. * @plat_priv: driver platform context pointer
  10. * @rc_num: root complex index that an endpoint connects to
  11. *
  12. * This function shall call corresponding PCIe root complex driver APIs
  13. * to power on root complex and enumerate the endpoint connected to it.
  14. *
  15. * Return: 0 for success, negative value for error
  16. */
  17. int _cnss_pci_enumerate(struct cnss_plat_data *plat_priv, u32 rc_num);
  18. /**
  19. * cnss_pci_assert_perst() - Assert PCIe PERST GPIO
  20. * @pci_priv: driver PCI bus context pointer
  21. *
  22. * This function shall call corresponding PCIe root complex driver APIs
  23. * to assert PCIe PERST GPIO.
  24. *
  25. * Return: 0 for success, negative value for error
  26. */
  27. int cnss_pci_assert_perst(struct cnss_pci_data *pci_priv);
  28. /**
  29. * cnss_pci_disable_pc() - Disable PCIe link power collapse from RC driver
  30. * @pci_priv: driver PCI bus context pointer
  31. * @vote: value to indicate disable (true) or enable (false)
  32. *
  33. * This function shall call corresponding PCIe root complex driver APIs
  34. * to disable PCIe power collapse. The purpose of this API is to avoid
  35. * root complex driver still controlling PCIe link from callbacks of
  36. * system suspend/resume. Device driver itself should take full control
  37. * of the link in such cases.
  38. *
  39. * Return: 0 for success, negative value for error
  40. */
  41. int cnss_pci_disable_pc(struct cnss_pci_data *pci_priv, bool vote);
  42. /**
  43. * cnss_pci_set_link_bandwidth() - Update number of lanes and speed of
  44. * PCIe link
  45. * @pci_priv: driver PCI bus context pointer
  46. * @link_speed: PCIe link gen speed
  47. * @link_width: number of lanes for PCIe link
  48. *
  49. * This function shall call corresponding PCIe root complex driver APIs
  50. * to update number of lanes and speed of the link.
  51. *
  52. * Return: 0 for success, negative value for error
  53. */
  54. int cnss_pci_set_link_bandwidth(struct cnss_pci_data *pci_priv,
  55. u16 link_speed, u16 link_width);
  56. /**
  57. * cnss_pci_set_max_link_speed() - Set the maximum speed PCIe can link up with
  58. * @pci_priv: driver PCI bus context pointer
  59. * @rc_num: root complex index that an endpoint connects to
  60. * @link_speed: PCIe link gen speed
  61. *
  62. * This function shall call corresponding PCIe root complex driver APIs
  63. * to update the maximum speed that PCIe can link up with.
  64. *
  65. * Return: 0 for success, negative value for error
  66. */
  67. int cnss_pci_set_max_link_speed(struct cnss_pci_data *pci_priv,
  68. u32 rc_num, u16 link_speed);
  69. /**
  70. * cnss_reg_pci_event() - Register for PCIe events
  71. * @pci_priv: driver PCI bus context pointer
  72. *
  73. * This function shall call corresponding PCIe root complex driver APIs
  74. * to register for PCIe events like link down or WAKE GPIO toggling etc.
  75. * The events should be based on PCIe root complex driver's capability.
  76. *
  77. * Return: 0 for success, negative value for error
  78. */
  79. int cnss_reg_pci_event(struct cnss_pci_data *pci_priv);
  80. void cnss_dereg_pci_event(struct cnss_pci_data *pci_priv);
  81. /**
  82. * cnss_wlan_adsp_pc_enable: Control ADSP power collapse setup
  83. * @dev: Platform driver pci private data structure
  84. * @control: Power collapse enable / disable
  85. *
  86. * This function controls ADSP power collapse (PC). It must be called
  87. * based on wlan state. ADSP power collapse during wlan RTPM suspend state
  88. * results in delay during periodic QMI stats PCI link up/down. This delay
  89. * causes additional power consumption.
  90. *
  91. * Result: 0 Success. negative error codes.
  92. */
  93. int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv,
  94. bool control);
  95. int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up);
  96. int cnss_pci_prevent_l1(struct device *dev);
  97. void cnss_pci_allow_l1(struct device *dev);
  98. int cnss_pci_get_msi_assignment(struct cnss_pci_data *pci_priv);
  99. int cnss_pci_get_one_msi_assignment(struct cnss_pci_data *pci_priv);
  100. bool cnss_pci_fallback_one_msi(struct cnss_pci_data *pci_priv,
  101. int *num_vectors);
  102. bool cnss_pci_is_one_msi(struct cnss_pci_data *pci_priv);
  103. int cnss_pci_get_one_msi_mhi_irq_array_size(struct cnss_pci_data *pci_priv);
  104. bool cnss_pci_is_force_one_msi(struct cnss_pci_data *pci_priv);
  105. int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv);
  106. void cnss_pci_update_drv_supported(struct cnss_pci_data *pci_priv);
  107. int cnss_pci_dsp_link_control(struct cnss_pci_data *pci_priv,
  108. bool link_enable);
  109. /**
  110. * _cnss_pci_get_reg_dump() - Dump PCIe RC registers for debug
  111. * @pci_priv: driver PCI bus context pointer
  112. * @buf: destination buffer pointer
  113. * @len: length of the buffer
  114. *
  115. * This function shall call corresponding PCIe root complex driver API
  116. * to dump PCIe RC registers for debug purpose.
  117. *
  118. * Return: 0 for success, negative value for error
  119. */
  120. int _cnss_pci_get_reg_dump(struct cnss_pci_data *pci_priv,
  121. u8 *buf, u32 len);
  122. int cnss_pci_set_dsp_link_status(struct cnss_pci_data *pci_priv,
  123. bool link_enable);
  124. int cnss_pci_get_dsp_link_status(struct cnss_pci_data *pci_priv);
  125. int cnss_pci_dsp_link_enable(struct cnss_pci_data *pci_priv);
  126. #else
  127. int _cnss_pci_enumerate(struct cnss_plat_data *plat_priv, u32 rc_num)
  128. {
  129. return -EOPNOTSUPP;
  130. }
  131. int cnss_pci_assert_perst(struct cnss_pci_data *pci_priv)
  132. {
  133. return -EOPNOTSUPP;
  134. }
  135. int cnss_pci_disable_pc(struct cnss_pci_data *pci_priv, bool vote)
  136. {
  137. return 0;
  138. }
  139. int cnss_pci_set_link_bandwidth(struct cnss_pci_data *pci_priv,
  140. u16 link_speed, u16 link_width)
  141. {
  142. return 0;
  143. }
  144. int cnss_pci_set_max_link_speed(struct cnss_pci_data *pci_priv,
  145. u32 rc_num, u16 link_speed)
  146. {
  147. return 0;
  148. }
  149. int cnss_reg_pci_event(struct cnss_pci_data *pci_priv)
  150. {
  151. return 0;
  152. }
  153. void cnss_dereg_pci_event(struct cnss_pci_data *pci_priv) {}
  154. int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv, bool control)
  155. {
  156. return 0;
  157. }
  158. int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up)
  159. {
  160. return 0;
  161. }
  162. int cnss_pci_prevent_l1(struct device *dev)
  163. {
  164. return 0;
  165. }
  166. EXPORT_SYMBOL(cnss_pci_prevent_l1);
  167. void cnss_pci_allow_l1(struct device *dev)
  168. {
  169. }
  170. EXPORT_SYMBOL(cnss_pci_allow_l1);
  171. int cnss_pci_get_msi_assignment(struct cnss_pci_data *pci_priv)
  172. {
  173. return 0;
  174. }
  175. int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv)
  176. {
  177. return 0;
  178. }
  179. int _cnss_pci_get_reg_dump(struct cnss_pci_data *pci_priv,
  180. u8 *buf, u32 len)
  181. {
  182. return 0;
  183. }
  184. void cnss_pci_update_drv_supported(struct cnss_pci_data *pci_priv)
  185. {
  186. pci_priv->drv_supported = false;
  187. }
  188. int cnss_pci_dsp_link_control(struct cnss_pci_data *pci_priv,
  189. bool link_enable)
  190. {
  191. return -EOPNOTSUPP;
  192. }
  193. int cnss_pci_set_dsp_link_status(struct cnss_pci_data *pci_priv,
  194. bool link_enable)
  195. {
  196. return -EOPNOTSUPP;
  197. }
  198. int cnss_pci_get_dsp_link_status(struct cnss_pci_data *pci_priv)
  199. {
  200. return -EOPNOTSUPP;
  201. }
  202. int cnss_pci_dsp_link_enable(struct cnss_pci_data *pci_priv)
  203. {
  204. return -EOPNOTSUPP;
  205. }
  206. #endif /* CONFIG_PCI_MSM */
  207. static inline bool cnss_pci_get_drv_supported(struct cnss_pci_data *pci_priv)
  208. {
  209. return pci_priv->drv_supported;
  210. }
  211. #if IS_ENABLED(CONFIG_ARCH_QCOM)
  212. int cnss_pci_of_reserved_mem_device_init(struct cnss_pci_data *pci_priv);
  213. int cnss_pci_wake_gpio_init(struct cnss_pci_data *pci_priv);
  214. void cnss_pci_wake_gpio_deinit(struct cnss_pci_data *pci_priv);
  215. #endif /* CONFIG_ARCH_QCOM */
  216. #endif /* _CNSS_PCI_PLATFORM_H*/