hal_api.h 76 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_API_H_
  19. #define _HAL_API_H_
  20. #include "qdf_types.h"
  21. #include "qdf_util.h"
  22. #include "qdf_atomic.h"
  23. #include "hal_internal.h"
  24. #include "hif.h"
  25. #include "hif_io32.h"
  26. #include "qdf_platform.h"
  27. /* Ring index for WBM2SW2 release ring */
  28. #define HAL_IPA_TX_COMP_RING_IDX 2
  29. /* calculate the register address offset from bar0 of shadow register x */
  30. #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490)
  31. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x000008FC
  32. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  33. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  34. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  35. #elif defined(QCA_WIFI_QCA6290) || defined(QCA_WIFI_QCN9000)
  36. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x00003024
  37. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  38. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  39. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  40. #elif defined(QCA_WIFI_QCA6750)
  41. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x00000504
  42. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  43. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  44. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  45. #else
  46. #define SHADOW_REGISTER(x) 0
  47. #endif /* QCA_WIFI_QCA6390 || QCA_WIFI_QCA6490 || QCA_WIFI_QCA6750 */
  48. #define MAX_UNWINDOWED_ADDRESS 0x80000
  49. #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \
  50. defined(QCA_WIFI_QCN9000) || defined(QCA_WIFI_QCA6750)
  51. #define WINDOW_ENABLE_BIT 0x40000000
  52. #else
  53. #define WINDOW_ENABLE_BIT 0x80000000
  54. #endif
  55. #define WINDOW_REG_ADDRESS 0x310C
  56. #define WINDOW_SHIFT 19
  57. #define WINDOW_VALUE_MASK 0x3F
  58. #define WINDOW_START MAX_UNWINDOWED_ADDRESS
  59. #define WINDOW_RANGE_MASK 0x7FFFF
  60. /*
  61. * BAR + 4K is always accessible, any access outside this
  62. * space requires force wake procedure.
  63. * OFFSET = 4K - 32 bytes = 0xFE0
  64. */
  65. #define MAPPED_REF_OFF 0xFE0
  66. #ifdef ENABLE_VERBOSE_DEBUG
  67. static inline void
  68. hal_set_verbose_debug(bool flag)
  69. {
  70. is_hal_verbose_debug_enabled = flag;
  71. }
  72. #endif
  73. #ifdef ENABLE_HAL_SOC_STATS
  74. #define HAL_STATS_INC(_handle, _field, _delta) \
  75. { \
  76. if (likely(_handle)) \
  77. _handle->stats._field += _delta; \
  78. }
  79. #else
  80. #define HAL_STATS_INC(_handle, _field, _delta)
  81. #endif
  82. #ifdef ENABLE_HAL_REG_WR_HISTORY
  83. #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \
  84. hal_reg_wr_fail_history_add(hal_soc, offset, wr_val, rd_val)
  85. void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc,
  86. uint32_t offset,
  87. uint32_t wr_val,
  88. uint32_t rd_val);
  89. static inline int hal_history_get_next_index(qdf_atomic_t *table_index,
  90. int array_size)
  91. {
  92. int record_index = qdf_atomic_inc_return(table_index);
  93. return record_index & (array_size - 1);
  94. }
  95. #else
  96. #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \
  97. hal_err("write failed at reg offset 0x%x, write 0x%x read 0x%x\n", \
  98. offset, \
  99. wr_val, \
  100. rd_val)
  101. #endif
  102. /**
  103. * hal_reg_write_result_check() - check register writing result
  104. * @hal_soc: HAL soc handle
  105. * @offset: register offset to read
  106. * @exp_val: the expected value of register
  107. * @ret_confirm: result confirm flag
  108. *
  109. * Return: none
  110. */
  111. static inline void hal_reg_write_result_check(struct hal_soc *hal_soc,
  112. uint32_t offset,
  113. uint32_t exp_val)
  114. {
  115. uint32_t value;
  116. value = qdf_ioread32(hal_soc->dev_base_addr + offset);
  117. if (exp_val != value) {
  118. HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, exp_val, value);
  119. HAL_STATS_INC(hal_soc, reg_write_fail, 1);
  120. }
  121. }
  122. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490)
  123. static inline void hal_lock_reg_access(struct hal_soc *soc,
  124. unsigned long *flags)
  125. {
  126. qdf_spin_lock_irqsave(&soc->register_access_lock);
  127. }
  128. static inline void hal_unlock_reg_access(struct hal_soc *soc,
  129. unsigned long *flags)
  130. {
  131. qdf_spin_unlock_irqrestore(&soc->register_access_lock);
  132. }
  133. #else
  134. static inline void hal_lock_reg_access(struct hal_soc *soc,
  135. unsigned long *flags)
  136. {
  137. pld_lock_reg_window(soc->qdf_dev->dev, flags);
  138. }
  139. static inline void hal_unlock_reg_access(struct hal_soc *soc,
  140. unsigned long *flags)
  141. {
  142. pld_unlock_reg_window(soc->qdf_dev->dev, flags);
  143. }
  144. #endif
  145. #ifdef PCIE_REG_WINDOW_LOCAL_NO_CACHE
  146. /**
  147. * hal_select_window_confirm() - write remap window register and
  148. check writing result
  149. *
  150. */
  151. static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
  152. uint32_t offset)
  153. {
  154. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  155. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  156. WINDOW_ENABLE_BIT | window);
  157. hal_soc->register_window = window;
  158. hal_reg_write_result_check(hal_soc, WINDOW_REG_ADDRESS,
  159. WINDOW_ENABLE_BIT | window);
  160. }
  161. #else
  162. static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
  163. uint32_t offset)
  164. {
  165. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  166. if (window != hal_soc->register_window) {
  167. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  168. WINDOW_ENABLE_BIT | window);
  169. hal_soc->register_window = window;
  170. hal_reg_write_result_check(
  171. hal_soc,
  172. WINDOW_REG_ADDRESS,
  173. WINDOW_ENABLE_BIT | window);
  174. }
  175. }
  176. #endif
  177. static inline qdf_iomem_t hal_get_window_address(struct hal_soc *hal_soc,
  178. qdf_iomem_t addr)
  179. {
  180. return hal_soc->ops->hal_get_window_address(hal_soc, addr);
  181. }
  182. static inline void hal_tx_init_cmd_credit_ring(hal_soc_handle_t hal_soc_hdl,
  183. hal_ring_handle_t hal_ring_hdl)
  184. {
  185. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  186. return hal_soc->ops->hal_tx_init_cmd_credit_ring(hal_soc_hdl,
  187. hal_ring_hdl);
  188. }
  189. /**
  190. * hal_write32_mb() - Access registers to update configuration
  191. * @hal_soc: hal soc handle
  192. * @offset: offset address from the BAR
  193. * @value: value to write
  194. *
  195. * Return: None
  196. *
  197. * Description: Register address space is split below:
  198. * SHADOW REGION UNWINDOWED REGION WINDOWED REGION
  199. * |--------------------|-------------------|------------------|
  200. * BAR NO FORCE WAKE BAR+4K FORCE WAKE BAR+512K FORCE WAKE
  201. *
  202. * 1. Any access to the shadow region, doesn't need force wake
  203. * and windowing logic to access.
  204. * 2. Any access beyond BAR + 4K:
  205. * If init_phase enabled, no force wake is needed and access
  206. * should be based on windowed or unwindowed access.
  207. * If init_phase disabled, force wake is needed and access
  208. * should be based on windowed or unwindowed access.
  209. *
  210. * note1: WINDOW_RANGE_MASK = (1 << WINDOW_SHIFT) -1
  211. * note2: 1 << WINDOW_SHIFT = MAX_UNWINDOWED_ADDRESS
  212. * note3: WINDOW_VALUE_MASK = big enough that trying to write past
  213. * that window would be a bug
  214. */
  215. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
  216. !defined(QCA_WIFI_QCA6750)
  217. static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
  218. uint32_t value)
  219. {
  220. unsigned long flags;
  221. qdf_iomem_t new_addr;
  222. if (!hal_soc->use_register_windowing ||
  223. offset < MAX_UNWINDOWED_ADDRESS) {
  224. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  225. } else if (hal_soc->static_window_map) {
  226. new_addr = hal_get_window_address(hal_soc,
  227. hal_soc->dev_base_addr + offset);
  228. qdf_iowrite32(new_addr, value);
  229. } else {
  230. hal_lock_reg_access(hal_soc, &flags);
  231. hal_select_window_confirm(hal_soc, offset);
  232. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  233. (offset & WINDOW_RANGE_MASK), value);
  234. hal_unlock_reg_access(hal_soc, &flags);
  235. }
  236. }
  237. #define hal_write32_mb_confirm(_hal_soc, _offset, _value) \
  238. hal_write32_mb(_hal_soc, _offset, _value)
  239. #define hal_write32_mb_cmem(_hal_soc, _offset, _value)
  240. #else
  241. static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
  242. uint32_t value)
  243. {
  244. int ret;
  245. unsigned long flags;
  246. qdf_iomem_t new_addr;
  247. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  248. hal_soc->hif_handle))) {
  249. hal_err_rl("target access is not allowed");
  250. return;
  251. }
  252. /* Region < BAR + 4K can be directly accessed */
  253. if (offset < MAPPED_REF_OFF) {
  254. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  255. return;
  256. }
  257. /* Region greater than BAR + 4K */
  258. if (!hal_soc->init_phase) {
  259. ret = hif_force_wake_request(hal_soc->hif_handle);
  260. if (ret) {
  261. hal_err_rl("Wake up request failed");
  262. qdf_check_state_before_panic();
  263. return;
  264. }
  265. }
  266. if (!hal_soc->use_register_windowing ||
  267. offset < MAX_UNWINDOWED_ADDRESS) {
  268. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  269. } else if (hal_soc->static_window_map) {
  270. new_addr = hal_get_window_address(
  271. hal_soc,
  272. hal_soc->dev_base_addr + offset);
  273. qdf_iowrite32(new_addr, value);
  274. } else {
  275. hal_lock_reg_access(hal_soc, &flags);
  276. hal_select_window_confirm(hal_soc, offset);
  277. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  278. (offset & WINDOW_RANGE_MASK), value);
  279. hal_unlock_reg_access(hal_soc, &flags);
  280. }
  281. if (!hal_soc->init_phase) {
  282. ret = hif_force_wake_release(hal_soc->hif_handle);
  283. if (ret) {
  284. hal_err("Wake up release failed");
  285. qdf_check_state_before_panic();
  286. return;
  287. }
  288. }
  289. }
  290. /**
  291. * hal_write32_mb_confirm() - write register and check wirting result
  292. *
  293. */
  294. static inline void hal_write32_mb_confirm(struct hal_soc *hal_soc,
  295. uint32_t offset,
  296. uint32_t value)
  297. {
  298. int ret;
  299. unsigned long flags;
  300. qdf_iomem_t new_addr;
  301. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  302. hal_soc->hif_handle))) {
  303. hal_err_rl("target access is not allowed");
  304. return;
  305. }
  306. /* Region < BAR + 4K can be directly accessed */
  307. if (offset < MAPPED_REF_OFF) {
  308. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  309. return;
  310. }
  311. /* Region greater than BAR + 4K */
  312. if (!hal_soc->init_phase) {
  313. ret = hif_force_wake_request(hal_soc->hif_handle);
  314. if (ret) {
  315. hal_err("Wake up request failed");
  316. qdf_check_state_before_panic();
  317. return;
  318. }
  319. }
  320. if (!hal_soc->use_register_windowing ||
  321. offset < MAX_UNWINDOWED_ADDRESS) {
  322. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  323. hal_reg_write_result_check(hal_soc, offset,
  324. value);
  325. } else if (hal_soc->static_window_map) {
  326. new_addr = hal_get_window_address(
  327. hal_soc,
  328. hal_soc->dev_base_addr + offset);
  329. qdf_iowrite32(new_addr, value);
  330. hal_reg_write_result_check(hal_soc,
  331. new_addr - hal_soc->dev_base_addr,
  332. value);
  333. } else {
  334. hal_lock_reg_access(hal_soc, &flags);
  335. hal_select_window_confirm(hal_soc, offset);
  336. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  337. (offset & WINDOW_RANGE_MASK), value);
  338. hal_reg_write_result_check(
  339. hal_soc,
  340. WINDOW_START + (offset & WINDOW_RANGE_MASK),
  341. value);
  342. hal_unlock_reg_access(hal_soc, &flags);
  343. }
  344. if (!hal_soc->init_phase) {
  345. ret = hif_force_wake_release(hal_soc->hif_handle);
  346. if (ret) {
  347. hal_err("Wake up release failed");
  348. qdf_check_state_before_panic();
  349. return;
  350. }
  351. }
  352. }
  353. static inline void hal_write32_mb_cmem(struct hal_soc *hal_soc, uint32_t offset,
  354. uint32_t value)
  355. {
  356. unsigned long flags;
  357. qdf_iomem_t new_addr;
  358. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  359. hal_soc->hif_handle))) {
  360. hal_err_rl("%s: target access is not allowed", __func__);
  361. return;
  362. }
  363. if (!hal_soc->use_register_windowing ||
  364. offset < MAX_UNWINDOWED_ADDRESS) {
  365. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  366. } else if (hal_soc->static_window_map) {
  367. new_addr = hal_get_window_address(
  368. hal_soc,
  369. hal_soc->dev_base_addr + offset);
  370. qdf_iowrite32(new_addr, value);
  371. } else {
  372. hal_lock_reg_access(hal_soc, &flags);
  373. hal_select_window_confirm(hal_soc, offset);
  374. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  375. (offset & WINDOW_RANGE_MASK), value);
  376. hal_unlock_reg_access(hal_soc, &flags);
  377. }
  378. }
  379. #endif
  380. /**
  381. * hal_write_address_32_mb - write a value to a register
  382. *
  383. */
  384. static inline
  385. void hal_write_address_32_mb(struct hal_soc *hal_soc,
  386. qdf_iomem_t addr, uint32_t value, bool wr_confirm)
  387. {
  388. uint32_t offset;
  389. if (!hal_soc->use_register_windowing)
  390. return qdf_iowrite32(addr, value);
  391. offset = addr - hal_soc->dev_base_addr;
  392. if (qdf_unlikely(wr_confirm))
  393. hal_write32_mb_confirm(hal_soc, offset, value);
  394. else
  395. hal_write32_mb(hal_soc, offset, value);
  396. }
  397. #ifdef DP_HAL_MULTIWINDOW_DIRECT_ACCESS
  398. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  399. struct hal_srng *srng,
  400. void __iomem *addr,
  401. uint32_t value)
  402. {
  403. qdf_iowrite32(addr, value);
  404. }
  405. #elif defined(FEATURE_HAL_DELAYED_REG_WRITE)
  406. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  407. struct hal_srng *srng,
  408. void __iomem *addr,
  409. uint32_t value)
  410. {
  411. hal_delayed_reg_write(hal_soc, srng, addr, value);
  412. }
  413. #else
  414. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  415. struct hal_srng *srng,
  416. void __iomem *addr,
  417. uint32_t value)
  418. {
  419. hal_write_address_32_mb(hal_soc, addr, value, false);
  420. }
  421. #endif
  422. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
  423. !defined(QCA_WIFI_QCA6750)
  424. /**
  425. * hal_read32_mb() - Access registers to read configuration
  426. * @hal_soc: hal soc handle
  427. * @offset: offset address from the BAR
  428. * @value: value to write
  429. *
  430. * Description: Register address space is split below:
  431. * SHADOW REGION UNWINDOWED REGION WINDOWED REGION
  432. * |--------------------|-------------------|------------------|
  433. * BAR NO FORCE WAKE BAR+4K FORCE WAKE BAR+512K FORCE WAKE
  434. *
  435. * 1. Any access to the shadow region, doesn't need force wake
  436. * and windowing logic to access.
  437. * 2. Any access beyond BAR + 4K:
  438. * If init_phase enabled, no force wake is needed and access
  439. * should be based on windowed or unwindowed access.
  440. * If init_phase disabled, force wake is needed and access
  441. * should be based on windowed or unwindowed access.
  442. *
  443. * Return: < 0 for failure/>= 0 for success
  444. */
  445. static inline uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
  446. {
  447. uint32_t ret;
  448. unsigned long flags;
  449. qdf_iomem_t new_addr;
  450. if (!hal_soc->use_register_windowing ||
  451. offset < MAX_UNWINDOWED_ADDRESS) {
  452. return qdf_ioread32(hal_soc->dev_base_addr + offset);
  453. } else if (hal_soc->static_window_map) {
  454. new_addr = hal_get_window_address(hal_soc, hal_soc->dev_base_addr + offset);
  455. return qdf_ioread32(new_addr);
  456. }
  457. hal_lock_reg_access(hal_soc, &flags);
  458. hal_select_window_confirm(hal_soc, offset);
  459. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  460. (offset & WINDOW_RANGE_MASK));
  461. hal_unlock_reg_access(hal_soc, &flags);
  462. return ret;
  463. }
  464. #define hal_read32_mb_cmem(_hal_soc, _offset)
  465. #else
  466. static
  467. uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
  468. {
  469. uint32_t ret;
  470. unsigned long flags;
  471. qdf_iomem_t new_addr;
  472. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  473. hal_soc->hif_handle))) {
  474. hal_err_rl("target access is not allowed");
  475. return 0;
  476. }
  477. /* Region < BAR + 4K can be directly accessed */
  478. if (offset < MAPPED_REF_OFF)
  479. return qdf_ioread32(hal_soc->dev_base_addr + offset);
  480. if ((!hal_soc->init_phase) &&
  481. hif_force_wake_request(hal_soc->hif_handle)) {
  482. hal_err("Wake up request failed");
  483. qdf_check_state_before_panic();
  484. return 0;
  485. }
  486. if (!hal_soc->use_register_windowing ||
  487. offset < MAX_UNWINDOWED_ADDRESS) {
  488. ret = qdf_ioread32(hal_soc->dev_base_addr + offset);
  489. } else if (hal_soc->static_window_map) {
  490. new_addr = hal_get_window_address(
  491. hal_soc,
  492. hal_soc->dev_base_addr + offset);
  493. ret = qdf_ioread32(new_addr);
  494. } else {
  495. hal_lock_reg_access(hal_soc, &flags);
  496. hal_select_window_confirm(hal_soc, offset);
  497. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  498. (offset & WINDOW_RANGE_MASK));
  499. hal_unlock_reg_access(hal_soc, &flags);
  500. }
  501. if ((!hal_soc->init_phase) &&
  502. hif_force_wake_release(hal_soc->hif_handle)) {
  503. hal_err("Wake up release failed");
  504. qdf_check_state_before_panic();
  505. return 0;
  506. }
  507. return ret;
  508. }
  509. static inline
  510. uint32_t hal_read32_mb_cmem(struct hal_soc *hal_soc, uint32_t offset)
  511. {
  512. uint32_t ret;
  513. unsigned long flags;
  514. qdf_iomem_t new_addr;
  515. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  516. hal_soc->hif_handle))) {
  517. hal_err_rl("%s: target access is not allowed", __func__);
  518. return 0;
  519. }
  520. if (!hal_soc->use_register_windowing ||
  521. offset < MAX_UNWINDOWED_ADDRESS) {
  522. ret = qdf_ioread32(hal_soc->dev_base_addr + offset);
  523. } else if (hal_soc->static_window_map) {
  524. new_addr = hal_get_window_address(
  525. hal_soc,
  526. hal_soc->dev_base_addr + offset);
  527. ret = qdf_ioread32(new_addr);
  528. } else {
  529. hal_lock_reg_access(hal_soc, &flags);
  530. hal_select_window_confirm(hal_soc, offset);
  531. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  532. (offset & WINDOW_RANGE_MASK));
  533. hal_unlock_reg_access(hal_soc, &flags);
  534. }
  535. return ret;
  536. }
  537. #endif
  538. /* Max times allowed for register writing retry */
  539. #define HAL_REG_WRITE_RETRY_MAX 5
  540. /* Delay milliseconds for each time retry */
  541. #define HAL_REG_WRITE_RETRY_DELAY 1
  542. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  543. /* To check shadow config index range between 0..31 */
  544. #define HAL_SHADOW_REG_INDEX_LOW 32
  545. /* To check shadow config index range between 32..39 */
  546. #define HAL_SHADOW_REG_INDEX_HIGH 40
  547. /* Dirty bit reg offsets corresponding to shadow config index */
  548. #define HAL_SHADOW_REG_DIRTY_BIT_DATA_LOW_OFFSET 0x30C8
  549. #define HAL_SHADOW_REG_DIRTY_BIT_DATA_HIGH_OFFSET 0x30C4
  550. /* PCIE_PCIE_TOP base addr offset */
  551. #define HAL_PCIE_PCIE_TOP_WRAPPER 0x01E00000
  552. /* Max retry attempts to read the dirty bit reg */
  553. #ifdef HAL_CONFIG_SLUB_DEBUG_ON
  554. #define HAL_SHADOW_DIRTY_BIT_POLL_MAX 10000
  555. #else
  556. #define HAL_SHADOW_DIRTY_BIT_POLL_MAX 2000
  557. #endif
  558. /* Delay in usecs for polling dirty bit reg */
  559. #define HAL_SHADOW_DIRTY_BIT_POLL_DELAY 5
  560. /**
  561. * hal_poll_dirty_bit_reg() - Poll dirty register bit to confirm
  562. * write was successful
  563. * @hal_soc: hal soc handle
  564. * @shadow_config_index: index of shadow reg used to confirm
  565. * write
  566. *
  567. * Return: QDF_STATUS_SUCCESS on success
  568. */
  569. static inline QDF_STATUS hal_poll_dirty_bit_reg(struct hal_soc *hal,
  570. int shadow_config_index)
  571. {
  572. uint32_t read_value = 0;
  573. int retry_cnt = 0;
  574. uint32_t reg_offset = 0;
  575. if (shadow_config_index > 0 &&
  576. shadow_config_index < HAL_SHADOW_REG_INDEX_LOW) {
  577. reg_offset =
  578. HAL_SHADOW_REG_DIRTY_BIT_DATA_LOW_OFFSET;
  579. } else if (shadow_config_index >= HAL_SHADOW_REG_INDEX_LOW &&
  580. shadow_config_index < HAL_SHADOW_REG_INDEX_HIGH) {
  581. reg_offset =
  582. HAL_SHADOW_REG_DIRTY_BIT_DATA_HIGH_OFFSET;
  583. } else {
  584. hal_err("Invalid shadow_config_index = %d",
  585. shadow_config_index);
  586. return QDF_STATUS_E_INVAL;
  587. }
  588. while (retry_cnt < HAL_SHADOW_DIRTY_BIT_POLL_MAX) {
  589. read_value = hal_read32_mb(
  590. hal, HAL_PCIE_PCIE_TOP_WRAPPER + reg_offset);
  591. /* Check if dirty bit corresponding to shadow_index is set */
  592. if (read_value & BIT(shadow_config_index)) {
  593. /* Dirty reg bit not reset */
  594. qdf_udelay(HAL_SHADOW_DIRTY_BIT_POLL_DELAY);
  595. retry_cnt++;
  596. } else {
  597. hal_debug("Shadow write: offset 0x%x read val 0x%x",
  598. reg_offset, read_value);
  599. return QDF_STATUS_SUCCESS;
  600. }
  601. }
  602. return QDF_STATUS_E_TIMEOUT;
  603. }
  604. /**
  605. * hal_write32_mb_shadow_confirm() - write to shadow reg and
  606. * poll dirty register bit to confirm write
  607. * @hal_soc: hal soc handle
  608. * @reg_offset: target reg offset address from BAR
  609. * @value: value to write
  610. *
  611. * Return: QDF_STATUS_SUCCESS on success
  612. */
  613. static inline QDF_STATUS hal_write32_mb_shadow_confirm(
  614. struct hal_soc *hal,
  615. uint32_t reg_offset,
  616. uint32_t value)
  617. {
  618. int i;
  619. QDF_STATUS ret;
  620. uint32_t shadow_reg_offset;
  621. int shadow_config_index;
  622. bool is_reg_offset_present = false;
  623. for (i = 0; i < MAX_GENERIC_SHADOW_REG; i++) {
  624. /* Found the shadow config for the reg_offset */
  625. struct shadow_reg_config *hal_shadow_reg_list =
  626. &hal->list_shadow_reg_config[i];
  627. if (hal_shadow_reg_list->target_register ==
  628. reg_offset) {
  629. shadow_config_index =
  630. hal_shadow_reg_list->shadow_config_index;
  631. shadow_reg_offset =
  632. SHADOW_REGISTER(shadow_config_index);
  633. hal_write32_mb_confirm(
  634. hal, shadow_reg_offset, value);
  635. is_reg_offset_present = true;
  636. break;
  637. }
  638. ret = QDF_STATUS_E_FAILURE;
  639. }
  640. if (is_reg_offset_present) {
  641. ret = hal_poll_dirty_bit_reg(hal, shadow_config_index);
  642. hal_info("Shadow write:reg 0x%x val 0x%x ret %d",
  643. reg_offset, value, ret);
  644. if (QDF_IS_STATUS_ERROR(ret)) {
  645. HAL_STATS_INC(hal, shadow_reg_write_fail, 1);
  646. return ret;
  647. }
  648. HAL_STATS_INC(hal, shadow_reg_write_succ, 1);
  649. }
  650. return ret;
  651. }
  652. /**
  653. * hal_write32_mb_confirm_retry() - write register with confirming and
  654. do retry/recovery if writing failed
  655. * @hal_soc: hal soc handle
  656. * @offset: offset address from the BAR
  657. * @value: value to write
  658. * @recovery: is recovery needed or not.
  659. *
  660. * Write the register value with confirming and read it back, if
  661. * read back value is not as expected, do retry for writing, if
  662. * retry hit max times allowed but still fail, check if recovery
  663. * needed.
  664. *
  665. * Return: None
  666. */
  667. static inline void hal_write32_mb_confirm_retry(struct hal_soc *hal_soc,
  668. uint32_t offset,
  669. uint32_t value,
  670. bool recovery)
  671. {
  672. QDF_STATUS ret;
  673. ret = hal_write32_mb_shadow_confirm(hal_soc, offset, value);
  674. if (QDF_IS_STATUS_ERROR(ret) && recovery)
  675. qdf_trigger_self_recovery(NULL, QDF_HAL_REG_WRITE_FAILURE);
  676. }
  677. #else /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  678. static inline void hal_write32_mb_confirm_retry(struct hal_soc *hal_soc,
  679. uint32_t offset,
  680. uint32_t value,
  681. bool recovery)
  682. {
  683. uint8_t retry_cnt = 0;
  684. uint32_t read_value;
  685. while (retry_cnt <= HAL_REG_WRITE_RETRY_MAX) {
  686. hal_write32_mb_confirm(hal_soc, offset, value);
  687. read_value = hal_read32_mb(hal_soc, offset);
  688. if (qdf_likely(read_value == value))
  689. break;
  690. /* write failed, do retry */
  691. hal_warn("Retry reg offset 0x%x, value 0x%x, read value 0x%x",
  692. offset, value, read_value);
  693. qdf_mdelay(HAL_REG_WRITE_RETRY_DELAY);
  694. retry_cnt++;
  695. }
  696. if (retry_cnt > HAL_REG_WRITE_RETRY_MAX && recovery)
  697. qdf_trigger_self_recovery(NULL, QDF_HAL_REG_WRITE_FAILURE);
  698. }
  699. #endif /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  700. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  701. /**
  702. * hal_dump_reg_write_srng_stats() - dump SRNG reg write stats
  703. * @hal_soc: HAL soc handle
  704. *
  705. * Return: none
  706. */
  707. void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl);
  708. /**
  709. * hal_dump_reg_write_stats() - dump reg write stats
  710. * @hal_soc: HAL soc handle
  711. *
  712. * Return: none
  713. */
  714. void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl);
  715. /**
  716. * hal_get_reg_write_pending_work() - get the number of entries
  717. * pending in the workqueue to be processed.
  718. * @hal_soc: HAL soc handle
  719. *
  720. * Returns: the number of entries pending to be processed
  721. */
  722. int hal_get_reg_write_pending_work(void *hal_soc);
  723. #else
  724. static inline void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
  725. {
  726. }
  727. static inline void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
  728. {
  729. }
  730. static inline int hal_get_reg_write_pending_work(void *hal_soc)
  731. {
  732. return 0;
  733. }
  734. #endif
  735. /**
  736. * hal_read_address_32_mb() - Read 32-bit value from the register
  737. * @soc: soc handle
  738. * @addr: register address to read
  739. *
  740. * Return: 32-bit value
  741. */
  742. static inline
  743. uint32_t hal_read_address_32_mb(struct hal_soc *soc,
  744. qdf_iomem_t addr)
  745. {
  746. uint32_t offset;
  747. uint32_t ret;
  748. if (!soc->use_register_windowing)
  749. return qdf_ioread32(addr);
  750. offset = addr - soc->dev_base_addr;
  751. ret = hal_read32_mb(soc, offset);
  752. return ret;
  753. }
  754. /**
  755. * hal_attach - Initialize HAL layer
  756. * @hif_handle: Opaque HIF handle
  757. * @qdf_dev: QDF device
  758. *
  759. * Return: Opaque HAL SOC handle
  760. * NULL on failure (if given ring is not available)
  761. *
  762. * This function should be called as part of HIF initialization (for accessing
  763. * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle()
  764. */
  765. void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev);
  766. /**
  767. * hal_detach - Detach HAL layer
  768. * @hal_soc: HAL SOC handle
  769. *
  770. * This function should be called as part of HIF detach
  771. *
  772. */
  773. extern void hal_detach(void *hal_soc);
  774. /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */
  775. enum hal_ring_type {
  776. REO_DST = 0,
  777. REO_EXCEPTION = 1,
  778. REO_REINJECT = 2,
  779. REO_CMD = 3,
  780. REO_STATUS = 4,
  781. TCL_DATA = 5,
  782. TCL_CMD_CREDIT = 6,
  783. TCL_STATUS = 7,
  784. CE_SRC = 8,
  785. CE_DST = 9,
  786. CE_DST_STATUS = 10,
  787. WBM_IDLE_LINK = 11,
  788. SW2WBM_RELEASE = 12,
  789. WBM2SW_RELEASE = 13,
  790. RXDMA_BUF = 14,
  791. RXDMA_DST = 15,
  792. RXDMA_MONITOR_BUF = 16,
  793. RXDMA_MONITOR_STATUS = 17,
  794. RXDMA_MONITOR_DST = 18,
  795. RXDMA_MONITOR_DESC = 19,
  796. DIR_BUF_RX_DMA_SRC = 20,
  797. #ifdef WLAN_FEATURE_CIF_CFR
  798. WIFI_POS_SRC,
  799. #endif
  800. MAX_RING_TYPES
  801. };
  802. #define HAL_SRNG_LMAC_RING 0x80000000
  803. /* SRNG flags passed in hal_srng_params.flags */
  804. #define HAL_SRNG_MSI_SWAP 0x00000008
  805. #define HAL_SRNG_RING_PTR_SWAP 0x00000010
  806. #define HAL_SRNG_DATA_TLV_SWAP 0x00000020
  807. #define HAL_SRNG_LOW_THRES_INTR_ENABLE 0x00010000
  808. #define HAL_SRNG_MSI_INTR 0x00020000
  809. #define HAL_SRNG_CACHED_DESC 0x00040000
  810. #ifdef QCA_WIFI_QCA6490
  811. #define HAL_SRNG_PREFETCH_TIMER 1
  812. #else
  813. #define HAL_SRNG_PREFETCH_TIMER 0
  814. #endif
  815. #define PN_SIZE_24 0
  816. #define PN_SIZE_48 1
  817. #define PN_SIZE_128 2
  818. #ifdef FORCE_WAKE
  819. /**
  820. * hal_set_init_phase() - Indicate initialization of
  821. * datapath rings
  822. * @soc: hal_soc handle
  823. * @init_phase: flag to indicate datapath rings
  824. * initialization status
  825. *
  826. * Return: None
  827. */
  828. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase);
  829. #else
  830. static inline
  831. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase)
  832. {
  833. }
  834. #endif /* FORCE_WAKE */
  835. /**
  836. * hal_srng_get_entrysize - Returns size of ring entry in bytes. Should be
  837. * used by callers for calculating the size of memory to be allocated before
  838. * calling hal_srng_setup to setup the ring
  839. *
  840. * @hal_soc: Opaque HAL SOC handle
  841. * @ring_type: one of the types from hal_ring_type
  842. *
  843. */
  844. extern uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type);
  845. /**
  846. * hal_srng_max_entries - Returns maximum possible number of ring entries
  847. * @hal_soc: Opaque HAL SOC handle
  848. * @ring_type: one of the types from hal_ring_type
  849. *
  850. * Return: Maximum number of entries for the given ring_type
  851. */
  852. uint32_t hal_srng_max_entries(void *hal_soc, int ring_type);
  853. void hal_set_low_threshold(hal_ring_handle_t hal_ring_hdl,
  854. uint32_t low_threshold);
  855. /**
  856. * hal_srng_dump - Dump ring status
  857. * @srng: hal srng pointer
  858. */
  859. void hal_srng_dump(struct hal_srng *srng);
  860. /**
  861. * hal_srng_get_dir - Returns the direction of the ring
  862. * @hal_soc: Opaque HAL SOC handle
  863. * @ring_type: one of the types from hal_ring_type
  864. *
  865. * Return: Ring direction
  866. */
  867. enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type);
  868. /* HAL memory information */
  869. struct hal_mem_info {
  870. /* dev base virutal addr */
  871. void *dev_base_addr;
  872. /* dev base physical addr */
  873. void *dev_base_paddr;
  874. /* dev base ce virutal addr - applicable only for qca5018 */
  875. /* In qca5018 CE register are outside wcss block */
  876. /* using a separate address space to access CE registers */
  877. void *dev_base_addr_ce;
  878. /* dev base ce physical addr */
  879. void *dev_base_paddr_ce;
  880. /* Remote virtual pointer memory for HW/FW updates */
  881. void *shadow_rdptr_mem_vaddr;
  882. /* Remote physical pointer memory for HW/FW updates */
  883. void *shadow_rdptr_mem_paddr;
  884. /* Shared memory for ring pointer updates from host to FW */
  885. void *shadow_wrptr_mem_vaddr;
  886. /* Shared physical memory for ring pointer updates from host to FW */
  887. void *shadow_wrptr_mem_paddr;
  888. };
  889. /* SRNG parameters to be passed to hal_srng_setup */
  890. struct hal_srng_params {
  891. /* Physical base address of the ring */
  892. qdf_dma_addr_t ring_base_paddr;
  893. /* Virtual base address of the ring */
  894. void *ring_base_vaddr;
  895. /* Number of entries in ring */
  896. uint32_t num_entries;
  897. /* max transfer length */
  898. uint16_t max_buffer_length;
  899. /* MSI Address */
  900. qdf_dma_addr_t msi_addr;
  901. /* MSI data */
  902. uint32_t msi_data;
  903. /* Interrupt timer threshold – in micro seconds */
  904. uint32_t intr_timer_thres_us;
  905. /* Interrupt batch counter threshold – in number of ring entries */
  906. uint32_t intr_batch_cntr_thres_entries;
  907. /* Low threshold – in number of ring entries
  908. * (valid for src rings only)
  909. */
  910. uint32_t low_threshold;
  911. /* Misc flags */
  912. uint32_t flags;
  913. /* Unique ring id */
  914. uint8_t ring_id;
  915. /* Source or Destination ring */
  916. enum hal_srng_dir ring_dir;
  917. /* Size of ring entry */
  918. uint32_t entry_size;
  919. /* hw register base address */
  920. void *hwreg_base[MAX_SRNG_REG_GROUPS];
  921. /* prefetch timer config - in micro seconds */
  922. uint32_t prefetch_timer;
  923. };
  924. /* hal_construct_srng_shadow_regs() - initialize the shadow
  925. * registers for srngs
  926. * @hal_soc: hal handle
  927. *
  928. * Return: QDF_STATUS_OK on success
  929. */
  930. QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc);
  931. /* hal_set_one_shadow_config() - add a config for the specified ring
  932. * @hal_soc: hal handle
  933. * @ring_type: ring type
  934. * @ring_num: ring num
  935. *
  936. * The ring type and ring num uniquely specify the ring. After this call,
  937. * the hp/tp will be added as the next entry int the shadow register
  938. * configuration table. The hal code will use the shadow register address
  939. * in place of the hp/tp address.
  940. *
  941. * This function is exposed, so that the CE module can skip configuring shadow
  942. * registers for unused ring and rings assigned to the firmware.
  943. *
  944. * Return: QDF_STATUS_OK on success
  945. */
  946. QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type,
  947. int ring_num);
  948. /**
  949. * hal_get_shadow_config() - retrieve the config table
  950. * @hal_soc: hal handle
  951. * @shadow_config: will point to the table after
  952. * @num_shadow_registers_configured: will contain the number of valid entries
  953. */
  954. extern void hal_get_shadow_config(void *hal_soc,
  955. struct pld_shadow_reg_v2_cfg **shadow_config,
  956. int *num_shadow_registers_configured);
  957. /**
  958. * hal_srng_setup - Initialize HW SRNG ring.
  959. *
  960. * @hal_soc: Opaque HAL SOC handle
  961. * @ring_type: one of the types from hal_ring_type
  962. * @ring_num: Ring number if there are multiple rings of
  963. * same type (staring from 0)
  964. * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
  965. * @ring_params: SRNG ring params in hal_srng_params structure.
  966. * Callers are expected to allocate contiguous ring memory of size
  967. * 'num_entries * entry_size' bytes and pass the physical and virtual base
  968. * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in hal_srng_params
  969. * structure. Ring base address should be 8 byte aligned and size of each ring
  970. * entry should be queried using the API hal_srng_get_entrysize
  971. *
  972. * Return: Opaque pointer to ring on success
  973. * NULL on failure (if given ring is not available)
  974. */
  975. extern void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
  976. int mac_id, struct hal_srng_params *ring_params);
  977. /* Remapping ids of REO rings */
  978. #define REO_REMAP_TCL 0
  979. #define REO_REMAP_SW1 1
  980. #define REO_REMAP_SW2 2
  981. #define REO_REMAP_SW3 3
  982. #define REO_REMAP_SW4 4
  983. #define REO_REMAP_RELEASE 5
  984. #define REO_REMAP_FW 6
  985. #define REO_REMAP_UNUSED 7
  986. /*
  987. * Macro to access HWIO_REO_R0_ERROR_DESTINATION_RING_CTRL_IX_0
  988. * to map destination to rings
  989. */
  990. #define HAL_REO_ERR_REMAP_IX0(_VALUE, _OFFSET) \
  991. ((_VALUE) << \
  992. (HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_ ## \
  993. DESTINATION_RING_ ## _OFFSET ## _SHFT))
  994. /*
  995. * Macro to access HWIO_REO_R0_ERROR_DESTINATION_RING_CTRL_IX_1
  996. * to map destination to rings
  997. */
  998. #define HAL_REO_ERR_REMAP_IX1(_VALUE, _OFFSET) \
  999. ((_VALUE) << \
  1000. (HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_ ## \
  1001. DESTINATION_RING_ ## _OFFSET ## _SHFT))
  1002. /*
  1003. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0
  1004. * to map destination to rings
  1005. */
  1006. #define HAL_REO_REMAP_IX0(_VALUE, _OFFSET) \
  1007. ((_VALUE) << \
  1008. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_ ## \
  1009. _OFFSET ## _SHFT))
  1010. /*
  1011. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1
  1012. * to map destination to rings
  1013. */
  1014. #define HAL_REO_REMAP_IX2(_VALUE, _OFFSET) \
  1015. ((_VALUE) << \
  1016. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_ ## \
  1017. _OFFSET ## _SHFT))
  1018. /*
  1019. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3
  1020. * to map destination to rings
  1021. */
  1022. #define HAL_REO_REMAP_IX3(_VALUE, _OFFSET) \
  1023. ((_VALUE) << \
  1024. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_ ## \
  1025. _OFFSET ## _SHFT))
  1026. /**
  1027. * hal_reo_read_write_ctrl_ix - Read or write REO_DESTINATION_RING_CTRL_IX
  1028. * @hal_soc_hdl: HAL SOC handle
  1029. * @read: boolean value to indicate if read or write
  1030. * @ix0: pointer to store IX0 reg value
  1031. * @ix1: pointer to store IX1 reg value
  1032. * @ix2: pointer to store IX2 reg value
  1033. * @ix3: pointer to store IX3 reg value
  1034. */
  1035. void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read,
  1036. uint32_t *ix0, uint32_t *ix1,
  1037. uint32_t *ix2, uint32_t *ix3);
  1038. /**
  1039. * hal_srng_set_hp_paddr() - Set physical address to dest SRNG head pointer
  1040. * @sring: sring pointer
  1041. * @paddr: physical address
  1042. */
  1043. extern void hal_srng_dst_set_hp_paddr(struct hal_srng *sring, uint64_t paddr);
  1044. /**
  1045. * hal_srng_dst_init_hp() - Initilaize head pointer with cached head pointer
  1046. * @hal_soc: hal_soc handle
  1047. * @srng: sring pointer
  1048. * @vaddr: virtual address
  1049. */
  1050. void hal_srng_dst_init_hp(struct hal_soc_handle *hal_soc,
  1051. struct hal_srng *srng,
  1052. uint32_t *vaddr);
  1053. /**
  1054. * hal_srng_cleanup - Deinitialize HW SRNG ring.
  1055. * @hal_soc: Opaque HAL SOC handle
  1056. * @hal_srng: Opaque HAL SRNG pointer
  1057. */
  1058. void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl);
  1059. static inline bool hal_srng_initialized(hal_ring_handle_t hal_ring_hdl)
  1060. {
  1061. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1062. return !!srng->initialized;
  1063. }
  1064. /**
  1065. * hal_srng_dst_peek - Check if there are any entries in the ring (peek)
  1066. * @hal_soc: Opaque HAL SOC handle
  1067. * @hal_ring_hdl: Destination ring pointer
  1068. *
  1069. * Caller takes responsibility for any locking needs.
  1070. *
  1071. * Return: Opaque pointer for next ring entry; NULL on failire
  1072. */
  1073. static inline
  1074. void *hal_srng_dst_peek(hal_soc_handle_t hal_soc_hdl,
  1075. hal_ring_handle_t hal_ring_hdl)
  1076. {
  1077. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1078. if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp)
  1079. return (void *)(&srng->ring_base_vaddr[srng->u.dst_ring.tp]);
  1080. return NULL;
  1081. }
  1082. /**
  1083. * hal_mem_dma_cache_sync - Cache sync the specified virtual address Range
  1084. * @hal_soc: HAL soc handle
  1085. * @desc: desc start address
  1086. * @entry_size: size of memory to sync
  1087. *
  1088. * Return: void
  1089. */
  1090. #if defined(__LINUX_MIPS32_ARCH__) || defined(__LINUX_MIPS64_ARCH__)
  1091. static inline void hal_mem_dma_cache_sync(struct hal_soc *soc, uint32_t *desc,
  1092. uint32_t entry_size)
  1093. {
  1094. qdf_nbuf_dma_inv_range((void *)desc, (void *)(desc + entry_size));
  1095. }
  1096. #else
  1097. static inline void hal_mem_dma_cache_sync(struct hal_soc *soc, uint32_t *desc,
  1098. uint32_t entry_size)
  1099. {
  1100. qdf_mem_dma_cache_sync(soc->qdf_dev, qdf_mem_virt_to_phys(desc),
  1101. QDF_DMA_FROM_DEVICE,
  1102. (entry_size * sizeof(uint32_t)));
  1103. }
  1104. #endif
  1105. /**
  1106. * hal_srng_access_start_unlocked - Start ring access (unlocked). Should use
  1107. * hal_srng_access_start if locked access is required
  1108. *
  1109. * @hal_soc: Opaque HAL SOC handle
  1110. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1111. *
  1112. * This API doesn't implement any byte-order conversion on reading hp/tp.
  1113. * So, Use API only for those srngs for which the target writes hp/tp values to
  1114. * the DDR in the Host order.
  1115. *
  1116. * Return: 0 on success; error on failire
  1117. */
  1118. static inline int
  1119. hal_srng_access_start_unlocked(hal_soc_handle_t hal_soc_hdl,
  1120. hal_ring_handle_t hal_ring_hdl)
  1121. {
  1122. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1123. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  1124. uint32_t *desc;
  1125. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1126. srng->u.src_ring.cached_tp =
  1127. *(volatile uint32_t *)(srng->u.src_ring.tp_addr);
  1128. else {
  1129. srng->u.dst_ring.cached_hp =
  1130. *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1131. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  1132. desc = hal_srng_dst_peek(hal_soc_hdl, hal_ring_hdl);
  1133. if (qdf_likely(desc)) {
  1134. hal_mem_dma_cache_sync(soc, desc,
  1135. srng->entry_size);
  1136. qdf_prefetch(desc);
  1137. }
  1138. }
  1139. }
  1140. return 0;
  1141. }
  1142. /**
  1143. * hal_le_srng_access_start_unlocked_in_cpu_order - Start ring access
  1144. * (unlocked) with endianness correction.
  1145. * @hal_soc: Opaque HAL SOC handle
  1146. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1147. *
  1148. * This API provides same functionally as hal_srng_access_start_unlocked()
  1149. * except that it converts the little-endian formatted hp/tp values to
  1150. * Host order on reading them. So, this API should only be used for those srngs
  1151. * for which the target always writes hp/tp values in little-endian order
  1152. * regardless of Host order.
  1153. *
  1154. * Also, this API doesn't take the lock. For locked access, use
  1155. * hal_srng_access_start/hal_le_srng_access_start_in_cpu_order.
  1156. *
  1157. * Return: 0 on success; error on failire
  1158. */
  1159. static inline int
  1160. hal_le_srng_access_start_unlocked_in_cpu_order(
  1161. hal_soc_handle_t hal_soc_hdl,
  1162. hal_ring_handle_t hal_ring_hdl)
  1163. {
  1164. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1165. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  1166. uint32_t *desc;
  1167. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1168. srng->u.src_ring.cached_tp =
  1169. qdf_le32_to_cpu(*(volatile uint32_t *)
  1170. (srng->u.src_ring.tp_addr));
  1171. else {
  1172. srng->u.dst_ring.cached_hp =
  1173. qdf_le32_to_cpu(*(volatile uint32_t *)
  1174. (srng->u.dst_ring.hp_addr));
  1175. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  1176. desc = hal_srng_dst_peek(hal_soc_hdl, hal_ring_hdl);
  1177. if (qdf_likely(desc)) {
  1178. hal_mem_dma_cache_sync(soc, desc,
  1179. srng->entry_size);
  1180. qdf_prefetch(desc);
  1181. }
  1182. }
  1183. }
  1184. return 0;
  1185. }
  1186. /**
  1187. * hal_srng_try_access_start - Try to start (locked) ring access
  1188. *
  1189. * @hal_soc: Opaque HAL SOC handle
  1190. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1191. *
  1192. * Return: 0 on success; error on failure
  1193. */
  1194. static inline int hal_srng_try_access_start(hal_soc_handle_t hal_soc_hdl,
  1195. hal_ring_handle_t hal_ring_hdl)
  1196. {
  1197. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1198. if (qdf_unlikely(!hal_ring_hdl)) {
  1199. qdf_print("Error: Invalid hal_ring\n");
  1200. return -EINVAL;
  1201. }
  1202. if (!SRNG_TRY_LOCK(&(srng->lock)))
  1203. return -EINVAL;
  1204. return hal_srng_access_start_unlocked(hal_soc_hdl, hal_ring_hdl);
  1205. }
  1206. /**
  1207. * hal_srng_access_start - Start (locked) ring access
  1208. *
  1209. * @hal_soc: Opaque HAL SOC handle
  1210. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1211. *
  1212. * This API doesn't implement any byte-order conversion on reading hp/tp.
  1213. * So, Use API only for those srngs for which the target writes hp/tp values to
  1214. * the DDR in the Host order.
  1215. *
  1216. * Return: 0 on success; error on failire
  1217. */
  1218. static inline int hal_srng_access_start(hal_soc_handle_t hal_soc_hdl,
  1219. hal_ring_handle_t hal_ring_hdl)
  1220. {
  1221. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1222. if (qdf_unlikely(!hal_ring_hdl)) {
  1223. qdf_print("Error: Invalid hal_ring\n");
  1224. return -EINVAL;
  1225. }
  1226. SRNG_LOCK(&(srng->lock));
  1227. return hal_srng_access_start_unlocked(hal_soc_hdl, hal_ring_hdl);
  1228. }
  1229. /**
  1230. * hal_le_srng_access_start_in_cpu_order - Start (locked) ring access with
  1231. * endianness correction
  1232. * @hal_soc: Opaque HAL SOC handle
  1233. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1234. *
  1235. * This API provides same functionally as hal_srng_access_start()
  1236. * except that it converts the little-endian formatted hp/tp values to
  1237. * Host order on reading them. So, this API should only be used for those srngs
  1238. * for which the target always writes hp/tp values in little-endian order
  1239. * regardless of Host order.
  1240. *
  1241. * Return: 0 on success; error on failire
  1242. */
  1243. static inline int
  1244. hal_le_srng_access_start_in_cpu_order(
  1245. hal_soc_handle_t hal_soc_hdl,
  1246. hal_ring_handle_t hal_ring_hdl)
  1247. {
  1248. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1249. if (qdf_unlikely(!hal_ring_hdl)) {
  1250. qdf_print("Error: Invalid hal_ring\n");
  1251. return -EINVAL;
  1252. }
  1253. SRNG_LOCK(&(srng->lock));
  1254. return hal_le_srng_access_start_unlocked_in_cpu_order(
  1255. hal_soc_hdl, hal_ring_hdl);
  1256. }
  1257. /**
  1258. * hal_srng_dst_get_next - Get next entry from a destination ring
  1259. * @hal_soc: Opaque HAL SOC handle
  1260. * @hal_ring_hdl: Destination ring pointer
  1261. *
  1262. * Return: Opaque pointer for next ring entry; NULL on failure
  1263. */
  1264. static inline
  1265. void *hal_srng_dst_get_next(void *hal_soc,
  1266. hal_ring_handle_t hal_ring_hdl)
  1267. {
  1268. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1269. uint32_t *desc;
  1270. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  1271. return NULL;
  1272. desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1273. /* TODO: Using % is expensive, but we have to do this since
  1274. * size of some SRNG rings is not power of 2 (due to descriptor
  1275. * sizes). Need to create separate API for rings used
  1276. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1277. * SW2RXDMA and CE rings)
  1278. */
  1279. srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size);
  1280. if (srng->u.dst_ring.tp == srng->ring_size)
  1281. srng->u.dst_ring.tp = 0;
  1282. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  1283. struct hal_soc *soc = (struct hal_soc *)hal_soc;
  1284. uint32_t *desc_next;
  1285. uint32_t tp;
  1286. tp = srng->u.dst_ring.tp;
  1287. desc_next = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1288. hal_mem_dma_cache_sync(soc, desc_next, srng->entry_size);
  1289. qdf_prefetch(desc_next);
  1290. }
  1291. return (void *)desc;
  1292. }
  1293. /**
  1294. * hal_srng_dst_get_next_cached - Get cached next entry
  1295. * @hal_soc: Opaque HAL SOC handle
  1296. * @hal_ring_hdl: Destination ring pointer
  1297. *
  1298. * Get next entry from a destination ring and move cached tail pointer
  1299. *
  1300. * Return: Opaque pointer for next ring entry; NULL on failure
  1301. */
  1302. static inline
  1303. void *hal_srng_dst_get_next_cached(void *hal_soc,
  1304. hal_ring_handle_t hal_ring_hdl)
  1305. {
  1306. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1307. uint32_t *desc;
  1308. uint32_t *desc_next;
  1309. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  1310. return NULL;
  1311. desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1312. /* TODO: Using % is expensive, but we have to do this since
  1313. * size of some SRNG rings is not power of 2 (due to descriptor
  1314. * sizes). Need to create separate API for rings used
  1315. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1316. * SW2RXDMA and CE rings)
  1317. */
  1318. srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size);
  1319. if (srng->u.dst_ring.tp == srng->ring_size)
  1320. srng->u.dst_ring.tp = 0;
  1321. desc_next = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1322. qdf_prefetch(desc_next);
  1323. return (void *)desc;
  1324. }
  1325. /**
  1326. * hal_srng_dst_get_next_hp - Get next entry from a destination ring and move
  1327. * cached head pointer
  1328. *
  1329. * @hal_soc: Opaque HAL SOC handle
  1330. * @hal_ring_hdl: Destination ring pointer
  1331. *
  1332. * Return: Opaque pointer for next ring entry; NULL on failire
  1333. */
  1334. static inline void *
  1335. hal_srng_dst_get_next_hp(hal_soc_handle_t hal_soc_hdl,
  1336. hal_ring_handle_t hal_ring_hdl)
  1337. {
  1338. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1339. uint32_t *desc;
  1340. /* TODO: Using % is expensive, but we have to do this since
  1341. * size of some SRNG rings is not power of 2 (due to descriptor
  1342. * sizes). Need to create separate API for rings used
  1343. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1344. * SW2RXDMA and CE rings)
  1345. */
  1346. uint32_t next_hp = (srng->u.dst_ring.cached_hp + srng->entry_size) %
  1347. srng->ring_size;
  1348. if (next_hp != srng->u.dst_ring.tp) {
  1349. desc = &(srng->ring_base_vaddr[srng->u.dst_ring.cached_hp]);
  1350. srng->u.dst_ring.cached_hp = next_hp;
  1351. return (void *)desc;
  1352. }
  1353. return NULL;
  1354. }
  1355. /**
  1356. * hal_srng_dst_peek_sync - Check if there are any entries in the ring (peek)
  1357. * @hal_soc: Opaque HAL SOC handle
  1358. * @hal_ring_hdl: Destination ring pointer
  1359. *
  1360. * Sync cached head pointer with HW.
  1361. * Caller takes responsibility for any locking needs.
  1362. *
  1363. * Return: Opaque pointer for next ring entry; NULL on failire
  1364. */
  1365. static inline
  1366. void *hal_srng_dst_peek_sync(hal_soc_handle_t hal_soc_hdl,
  1367. hal_ring_handle_t hal_ring_hdl)
  1368. {
  1369. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1370. srng->u.dst_ring.cached_hp =
  1371. *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1372. if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp)
  1373. return (void *)(&(srng->ring_base_vaddr[srng->u.dst_ring.tp]));
  1374. return NULL;
  1375. }
  1376. /**
  1377. * hal_srng_dst_peek_sync_locked - Peek for any entries in the ring
  1378. * @hal_soc: Opaque HAL SOC handle
  1379. * @hal_ring_hdl: Destination ring pointer
  1380. *
  1381. * Sync cached head pointer with HW.
  1382. * This function takes up SRNG_LOCK. Should not be called with SRNG lock held.
  1383. *
  1384. * Return: Opaque pointer for next ring entry; NULL on failire
  1385. */
  1386. static inline
  1387. void *hal_srng_dst_peek_sync_locked(hal_soc_handle_t hal_soc_hdl,
  1388. hal_ring_handle_t hal_ring_hdl)
  1389. {
  1390. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1391. void *ring_desc_ptr = NULL;
  1392. if (qdf_unlikely(!hal_ring_hdl)) {
  1393. qdf_print("Error: Invalid hal_ring\n");
  1394. return NULL;
  1395. }
  1396. SRNG_LOCK(&srng->lock);
  1397. ring_desc_ptr = hal_srng_dst_peek_sync(hal_soc_hdl, hal_ring_hdl);
  1398. SRNG_UNLOCK(&srng->lock);
  1399. return ring_desc_ptr;
  1400. }
  1401. /**
  1402. * hal_srng_dst_num_valid - Returns number of valid entries (to be processed
  1403. * by SW) in destination ring
  1404. *
  1405. * @hal_soc: Opaque HAL SOC handle
  1406. * @hal_ring_hdl: Destination ring pointer
  1407. * @sync_hw_ptr: Sync cached head pointer with HW
  1408. *
  1409. */
  1410. static inline
  1411. uint32_t hal_srng_dst_num_valid(void *hal_soc,
  1412. hal_ring_handle_t hal_ring_hdl,
  1413. int sync_hw_ptr)
  1414. {
  1415. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1416. uint32_t hp;
  1417. uint32_t tp = srng->u.dst_ring.tp;
  1418. if (sync_hw_ptr) {
  1419. hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1420. srng->u.dst_ring.cached_hp = hp;
  1421. } else {
  1422. hp = srng->u.dst_ring.cached_hp;
  1423. }
  1424. if (hp >= tp)
  1425. return (hp - tp) / srng->entry_size;
  1426. return (srng->ring_size - tp + hp) / srng->entry_size;
  1427. }
  1428. /**
  1429. * hal_srng_dst_inv_cached_descs - API to invalidate descriptors in batch mode
  1430. * @hal_soc: Opaque HAL SOC handle
  1431. * @hal_ring_hdl: Destination ring pointer
  1432. * @entry_count: Number of descriptors to be invalidated
  1433. *
  1434. * Invalidates a set of cached descriptors starting from tail to
  1435. * provided count worth
  1436. *
  1437. * Return - None
  1438. */
  1439. static inline void hal_srng_dst_inv_cached_descs(void *hal_soc,
  1440. hal_ring_handle_t hal_ring_hdl,
  1441. uint32_t entry_count)
  1442. {
  1443. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1444. uint32_t hp = srng->u.dst_ring.cached_hp;
  1445. uint32_t tp = srng->u.dst_ring.tp;
  1446. uint32_t sync_p = 0;
  1447. /*
  1448. * If SRNG does not have cached descriptors this
  1449. * API call should be a no op
  1450. */
  1451. if (!(srng->flags & HAL_SRNG_CACHED_DESC))
  1452. return;
  1453. if (qdf_unlikely(entry_count == 0))
  1454. return;
  1455. sync_p = (entry_count - 1) * srng->entry_size;
  1456. if (hp > tp) {
  1457. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[tp],
  1458. &srng->ring_base_vaddr[tp + sync_p]
  1459. + (srng->entry_size * sizeof(uint32_t)));
  1460. } else {
  1461. /*
  1462. * We have wrapped around
  1463. */
  1464. uint32_t wrap_cnt = ((srng->ring_size - tp) / srng->entry_size);
  1465. if (entry_count <= wrap_cnt) {
  1466. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[tp],
  1467. &srng->ring_base_vaddr[tp + sync_p] +
  1468. (srng->entry_size * sizeof(uint32_t)));
  1469. return;
  1470. }
  1471. entry_count -= wrap_cnt;
  1472. sync_p = (entry_count - 1) * srng->entry_size;
  1473. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[tp],
  1474. &srng->ring_base_vaddr[srng->ring_size - srng->entry_size] +
  1475. (srng->entry_size * sizeof(uint32_t)));
  1476. qdf_nbuf_dma_inv_range(&srng->ring_base_vaddr[0],
  1477. &srng->ring_base_vaddr[sync_p]
  1478. + (srng->entry_size * sizeof(uint32_t)));
  1479. }
  1480. }
  1481. /**
  1482. * hal_srng_dst_num_valid_locked - Returns num valid entries to be processed
  1483. *
  1484. * @hal_soc: Opaque HAL SOC handle
  1485. * @hal_ring_hdl: Destination ring pointer
  1486. * @sync_hw_ptr: Sync cached head pointer with HW
  1487. *
  1488. * Returns number of valid entries to be processed by the host driver. The
  1489. * function takes up SRNG lock.
  1490. *
  1491. * Return: Number of valid destination entries
  1492. */
  1493. static inline uint32_t
  1494. hal_srng_dst_num_valid_locked(hal_soc_handle_t hal_soc,
  1495. hal_ring_handle_t hal_ring_hdl,
  1496. int sync_hw_ptr)
  1497. {
  1498. uint32_t num_valid;
  1499. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1500. SRNG_LOCK(&srng->lock);
  1501. num_valid = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, sync_hw_ptr);
  1502. SRNG_UNLOCK(&srng->lock);
  1503. return num_valid;
  1504. }
  1505. /**
  1506. * hal_srng_sync_cachedhp - sync cachehp pointer from hw hp
  1507. *
  1508. * @hal_soc: Opaque HAL SOC handle
  1509. * @hal_ring_hdl: Destination ring pointer
  1510. *
  1511. */
  1512. static inline
  1513. void hal_srng_sync_cachedhp(void *hal_soc,
  1514. hal_ring_handle_t hal_ring_hdl)
  1515. {
  1516. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1517. uint32_t hp;
  1518. hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1519. srng->u.dst_ring.cached_hp = hp;
  1520. }
  1521. /**
  1522. * hal_srng_src_reap_next - Reap next entry from a source ring and move reap
  1523. * pointer. This can be used to release any buffers associated with completed
  1524. * ring entries. Note that this should not be used for posting new descriptor
  1525. * entries. Posting of new entries should be done only using
  1526. * hal_srng_src_get_next_reaped when this function is used for reaping.
  1527. *
  1528. * @hal_soc: Opaque HAL SOC handle
  1529. * @hal_ring_hdl: Source ring pointer
  1530. *
  1531. * Return: Opaque pointer for next ring entry; NULL on failire
  1532. */
  1533. static inline void *
  1534. hal_srng_src_reap_next(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1535. {
  1536. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1537. uint32_t *desc;
  1538. /* TODO: Using % is expensive, but we have to do this since
  1539. * size of some SRNG rings is not power of 2 (due to descriptor
  1540. * sizes). Need to create separate API for rings used
  1541. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1542. * SW2RXDMA and CE rings)
  1543. */
  1544. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1545. srng->ring_size;
  1546. if (next_reap_hp != srng->u.src_ring.cached_tp) {
  1547. desc = &(srng->ring_base_vaddr[next_reap_hp]);
  1548. srng->u.src_ring.reap_hp = next_reap_hp;
  1549. return (void *)desc;
  1550. }
  1551. return NULL;
  1552. }
  1553. /**
  1554. * hal_srng_src_get_next_reaped - Get next entry from a source ring that is
  1555. * already reaped using hal_srng_src_reap_next, for posting new entries to
  1556. * the ring
  1557. *
  1558. * @hal_soc: Opaque HAL SOC handle
  1559. * @hal_ring_hdl: Source ring pointer
  1560. *
  1561. * Return: Opaque pointer for next (reaped) source ring entry; NULL on failire
  1562. */
  1563. static inline void *
  1564. hal_srng_src_get_next_reaped(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1565. {
  1566. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1567. uint32_t *desc;
  1568. if (srng->u.src_ring.hp != srng->u.src_ring.reap_hp) {
  1569. desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]);
  1570. srng->u.src_ring.hp = (srng->u.src_ring.hp + srng->entry_size) %
  1571. srng->ring_size;
  1572. return (void *)desc;
  1573. }
  1574. return NULL;
  1575. }
  1576. /**
  1577. * hal_srng_src_pending_reap_next - Reap next entry from a source ring and
  1578. * move reap pointer. This API is used in detach path to release any buffers
  1579. * associated with ring entries which are pending reap.
  1580. *
  1581. * @hal_soc: Opaque HAL SOC handle
  1582. * @hal_ring_hdl: Source ring pointer
  1583. *
  1584. * Return: Opaque pointer for next ring entry; NULL on failire
  1585. */
  1586. static inline void *
  1587. hal_srng_src_pending_reap_next(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1588. {
  1589. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1590. uint32_t *desc;
  1591. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1592. srng->ring_size;
  1593. if (next_reap_hp != srng->u.src_ring.hp) {
  1594. desc = &(srng->ring_base_vaddr[next_reap_hp]);
  1595. srng->u.src_ring.reap_hp = next_reap_hp;
  1596. return (void *)desc;
  1597. }
  1598. return NULL;
  1599. }
  1600. /**
  1601. * hal_srng_src_done_val -
  1602. *
  1603. * @hal_soc: Opaque HAL SOC handle
  1604. * @hal_ring_hdl: Source ring pointer
  1605. *
  1606. * Return: Opaque pointer for next ring entry; NULL on failire
  1607. */
  1608. static inline uint32_t
  1609. hal_srng_src_done_val(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1610. {
  1611. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1612. /* TODO: Using % is expensive, but we have to do this since
  1613. * size of some SRNG rings is not power of 2 (due to descriptor
  1614. * sizes). Need to create separate API for rings used
  1615. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1616. * SW2RXDMA and CE rings)
  1617. */
  1618. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1619. srng->ring_size;
  1620. if (next_reap_hp == srng->u.src_ring.cached_tp)
  1621. return 0;
  1622. if (srng->u.src_ring.cached_tp > next_reap_hp)
  1623. return (srng->u.src_ring.cached_tp - next_reap_hp) /
  1624. srng->entry_size;
  1625. else
  1626. return ((srng->ring_size - next_reap_hp) +
  1627. srng->u.src_ring.cached_tp) / srng->entry_size;
  1628. }
  1629. /**
  1630. * hal_get_entrysize_from_srng() - Retrieve ring entry size
  1631. * @hal_ring_hdl: Source ring pointer
  1632. *
  1633. * Return: uint8_t
  1634. */
  1635. static inline
  1636. uint8_t hal_get_entrysize_from_srng(hal_ring_handle_t hal_ring_hdl)
  1637. {
  1638. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1639. return srng->entry_size;
  1640. }
  1641. /**
  1642. * hal_get_sw_hptp - Get SW head and tail pointer location for any ring
  1643. * @hal_soc: Opaque HAL SOC handle
  1644. * @hal_ring_hdl: Source ring pointer
  1645. * @tailp: Tail Pointer
  1646. * @headp: Head Pointer
  1647. *
  1648. * Return: Update tail pointer and head pointer in arguments.
  1649. */
  1650. static inline
  1651. void hal_get_sw_hptp(void *hal_soc, hal_ring_handle_t hal_ring_hdl,
  1652. uint32_t *tailp, uint32_t *headp)
  1653. {
  1654. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1655. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1656. *headp = srng->u.src_ring.hp;
  1657. *tailp = *srng->u.src_ring.tp_addr;
  1658. } else {
  1659. *tailp = srng->u.dst_ring.tp;
  1660. *headp = *srng->u.dst_ring.hp_addr;
  1661. }
  1662. }
  1663. /**
  1664. * hal_srng_src_get_next - Get next entry from a source ring and move cached tail pointer
  1665. *
  1666. * @hal_soc: Opaque HAL SOC handle
  1667. * @hal_ring_hdl: Source ring pointer
  1668. *
  1669. * Return: Opaque pointer for next ring entry; NULL on failire
  1670. */
  1671. static inline
  1672. void *hal_srng_src_get_next(void *hal_soc,
  1673. hal_ring_handle_t hal_ring_hdl)
  1674. {
  1675. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1676. uint32_t *desc;
  1677. /* TODO: Using % is expensive, but we have to do this since
  1678. * size of some SRNG rings is not power of 2 (due to descriptor
  1679. * sizes). Need to create separate API for rings used
  1680. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1681. * SW2RXDMA and CE rings)
  1682. */
  1683. uint32_t next_hp = (srng->u.src_ring.hp + srng->entry_size) %
  1684. srng->ring_size;
  1685. if (next_hp != srng->u.src_ring.cached_tp) {
  1686. desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]);
  1687. srng->u.src_ring.hp = next_hp;
  1688. /* TODO: Since reap function is not used by all rings, we can
  1689. * remove the following update of reap_hp in this function
  1690. * if we can ensure that only hal_srng_src_get_next_reaped
  1691. * is used for the rings requiring reap functionality
  1692. */
  1693. srng->u.src_ring.reap_hp = next_hp;
  1694. return (void *)desc;
  1695. }
  1696. return NULL;
  1697. }
  1698. /**
  1699. * hal_srng_src_peek_n_get_next - Get next entry from a ring without
  1700. * moving head pointer.
  1701. * hal_srng_src_get_next should be called subsequently to move the head pointer
  1702. *
  1703. * @hal_soc: Opaque HAL SOC handle
  1704. * @hal_ring_hdl: Source ring pointer
  1705. *
  1706. * Return: Opaque pointer for next ring entry; NULL on failire
  1707. */
  1708. static inline
  1709. void *hal_srng_src_peek_n_get_next(hal_soc_handle_t hal_soc_hdl,
  1710. hal_ring_handle_t hal_ring_hdl)
  1711. {
  1712. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1713. uint32_t *desc;
  1714. /* TODO: Using % is expensive, but we have to do this since
  1715. * size of some SRNG rings is not power of 2 (due to descriptor
  1716. * sizes). Need to create separate API for rings used
  1717. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1718. * SW2RXDMA and CE rings)
  1719. */
  1720. if (((srng->u.src_ring.hp + srng->entry_size) %
  1721. srng->ring_size) != srng->u.src_ring.cached_tp) {
  1722. desc = &(srng->ring_base_vaddr[(srng->u.src_ring.hp +
  1723. srng->entry_size) %
  1724. srng->ring_size]);
  1725. return (void *)desc;
  1726. }
  1727. return NULL;
  1728. }
  1729. /**
  1730. * hal_srng_src_peek_n_get_next_next - Get next to next, i.e HP + 2 entry
  1731. * from a ring without moving head pointer.
  1732. *
  1733. * @hal_soc: Opaque HAL SOC handle
  1734. * @hal_ring_hdl: Source ring pointer
  1735. *
  1736. * Return: Opaque pointer for next to next ring entry; NULL on failire
  1737. */
  1738. static inline
  1739. void *hal_srng_src_peek_n_get_next_next(hal_soc_handle_t hal_soc_hdl,
  1740. hal_ring_handle_t hal_ring_hdl)
  1741. {
  1742. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1743. uint32_t *desc;
  1744. /* TODO: Using % is expensive, but we have to do this since
  1745. * size of some SRNG rings is not power of 2 (due to descriptor
  1746. * sizes). Need to create separate API for rings used
  1747. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1748. * SW2RXDMA and CE rings)
  1749. */
  1750. if ((((srng->u.src_ring.hp + (srng->entry_size)) %
  1751. srng->ring_size) != srng->u.src_ring.cached_tp) &&
  1752. (((srng->u.src_ring.hp + (srng->entry_size * 2)) %
  1753. srng->ring_size) != srng->u.src_ring.cached_tp)) {
  1754. desc = &(srng->ring_base_vaddr[(srng->u.src_ring.hp +
  1755. (srng->entry_size * 2)) %
  1756. srng->ring_size]);
  1757. return (void *)desc;
  1758. }
  1759. return NULL;
  1760. }
  1761. /**
  1762. * hal_srng_src_get_cur_hp_n_move_next () - API returns current hp
  1763. * and move hp to next in src ring
  1764. *
  1765. * Usage: This API should only be used at init time replenish.
  1766. *
  1767. * @hal_soc_hdl: HAL soc handle
  1768. * @hal_ring_hdl: Source ring pointer
  1769. *
  1770. */
  1771. static inline void *
  1772. hal_srng_src_get_cur_hp_n_move_next(hal_soc_handle_t hal_soc_hdl,
  1773. hal_ring_handle_t hal_ring_hdl)
  1774. {
  1775. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1776. uint32_t *cur_desc = NULL;
  1777. uint32_t next_hp;
  1778. cur_desc = &srng->ring_base_vaddr[(srng->u.src_ring.hp)];
  1779. next_hp = (srng->u.src_ring.hp + srng->entry_size) %
  1780. srng->ring_size;
  1781. if (next_hp != srng->u.src_ring.cached_tp)
  1782. srng->u.src_ring.hp = next_hp;
  1783. return (void *)cur_desc;
  1784. }
  1785. /**
  1786. * hal_srng_src_num_avail - Returns number of available entries in src ring
  1787. *
  1788. * @hal_soc: Opaque HAL SOC handle
  1789. * @hal_ring_hdl: Source ring pointer
  1790. * @sync_hw_ptr: Sync cached tail pointer with HW
  1791. *
  1792. */
  1793. static inline uint32_t
  1794. hal_srng_src_num_avail(void *hal_soc,
  1795. hal_ring_handle_t hal_ring_hdl, int sync_hw_ptr)
  1796. {
  1797. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1798. uint32_t tp;
  1799. uint32_t hp = srng->u.src_ring.hp;
  1800. if (sync_hw_ptr) {
  1801. tp = *(srng->u.src_ring.tp_addr);
  1802. srng->u.src_ring.cached_tp = tp;
  1803. } else {
  1804. tp = srng->u.src_ring.cached_tp;
  1805. }
  1806. if (tp > hp)
  1807. return ((tp - hp) / srng->entry_size) - 1;
  1808. else
  1809. return ((srng->ring_size - hp + tp) / srng->entry_size) - 1;
  1810. }
  1811. /**
  1812. * hal_srng_access_end_unlocked - End ring access (unlocked) - update cached
  1813. * ring head/tail pointers to HW.
  1814. *
  1815. * @hal_soc: Opaque HAL SOC handle
  1816. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1817. *
  1818. * The target expects cached head/tail pointer to be updated to the
  1819. * shared location in the little-endian order, This API ensures that.
  1820. * This API should be used only if hal_srng_access_start_unlocked was used to
  1821. * start ring access
  1822. *
  1823. * Return: None
  1824. */
  1825. static inline void
  1826. hal_srng_access_end_unlocked(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1827. {
  1828. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1829. /* TODO: See if we need a write memory barrier here */
  1830. if (srng->flags & HAL_SRNG_LMAC_RING) {
  1831. /* For LMAC rings, ring pointer updates are done through FW and
  1832. * hence written to a shared memory location that is read by FW
  1833. */
  1834. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1835. *srng->u.src_ring.hp_addr =
  1836. qdf_cpu_to_le32(srng->u.src_ring.hp);
  1837. } else {
  1838. *srng->u.dst_ring.tp_addr =
  1839. qdf_cpu_to_le32(srng->u.dst_ring.tp);
  1840. }
  1841. } else {
  1842. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1843. hal_srng_write_address_32_mb(hal_soc,
  1844. srng,
  1845. srng->u.src_ring.hp_addr,
  1846. srng->u.src_ring.hp);
  1847. else
  1848. hal_srng_write_address_32_mb(hal_soc,
  1849. srng,
  1850. srng->u.dst_ring.tp_addr,
  1851. srng->u.dst_ring.tp);
  1852. }
  1853. }
  1854. /* hal_srng_access_end_unlocked already handles endianness conversion,
  1855. * use the same.
  1856. */
  1857. #define hal_le_srng_access_end_unlocked_in_cpu_order \
  1858. hal_srng_access_end_unlocked
  1859. /**
  1860. * hal_srng_access_end - Unlock ring access and update cached ring head/tail
  1861. * pointers to HW
  1862. *
  1863. * @hal_soc: Opaque HAL SOC handle
  1864. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1865. *
  1866. * The target expects cached head/tail pointer to be updated to the
  1867. * shared location in the little-endian order, This API ensures that.
  1868. * This API should be used only if hal_srng_access_start was used to
  1869. * start ring access
  1870. *
  1871. * Return: 0 on success; error on failire
  1872. */
  1873. static inline void
  1874. hal_srng_access_end(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1875. {
  1876. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1877. if (qdf_unlikely(!hal_ring_hdl)) {
  1878. qdf_print("Error: Invalid hal_ring\n");
  1879. return;
  1880. }
  1881. hal_srng_access_end_unlocked(hal_soc, hal_ring_hdl);
  1882. SRNG_UNLOCK(&(srng->lock));
  1883. }
  1884. /* hal_srng_access_end already handles endianness conversion, so use the same */
  1885. #define hal_le_srng_access_end_in_cpu_order \
  1886. hal_srng_access_end
  1887. /**
  1888. * hal_srng_access_end_reap - Unlock ring access
  1889. * This should be used only if hal_srng_access_start to start ring access
  1890. * and should be used only while reaping SRC ring completions
  1891. *
  1892. * @hal_soc: Opaque HAL SOC handle
  1893. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1894. *
  1895. * Return: 0 on success; error on failire
  1896. */
  1897. static inline void
  1898. hal_srng_access_end_reap(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1899. {
  1900. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1901. SRNG_UNLOCK(&(srng->lock));
  1902. }
  1903. /* TODO: Check if the following definitions is available in HW headers */
  1904. #define WBM_IDLE_SCATTER_BUF_SIZE 32704
  1905. #define NUM_MPDUS_PER_LINK_DESC 6
  1906. #define NUM_MSDUS_PER_LINK_DESC 7
  1907. #define REO_QUEUE_DESC_ALIGN 128
  1908. #define LINK_DESC_ALIGN 128
  1909. #define ADDRESS_MATCH_TAG_VAL 0x5
  1910. /* Number of mpdu link pointers is 9 in case of TX_MPDU_QUEUE_HEAD and 14 in
  1911. * of TX_MPDU_QUEUE_EXT. We are defining a common average count here
  1912. */
  1913. #define NUM_MPDU_LINKS_PER_QUEUE_DESC 12
  1914. /* TODO: Check with HW team on the scatter buffer size supported. As per WBM
  1915. * MLD, scatter_buffer_size in IDLE_LIST_CONTROL register is 9 bits and size
  1916. * should be specified in 16 word units. But the number of bits defined for
  1917. * this field in HW header files is 5.
  1918. */
  1919. #define WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE 8
  1920. /**
  1921. * hal_idle_list_scatter_buf_size - Get the size of each scatter buffer
  1922. * in an idle list
  1923. *
  1924. * @hal_soc: Opaque HAL SOC handle
  1925. *
  1926. */
  1927. static inline
  1928. uint32_t hal_idle_list_scatter_buf_size(hal_soc_handle_t hal_soc_hdl)
  1929. {
  1930. return WBM_IDLE_SCATTER_BUF_SIZE;
  1931. }
  1932. /**
  1933. * hal_get_link_desc_size - Get the size of each link descriptor
  1934. *
  1935. * @hal_soc: Opaque HAL SOC handle
  1936. *
  1937. */
  1938. static inline uint32_t hal_get_link_desc_size(hal_soc_handle_t hal_soc_hdl)
  1939. {
  1940. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1941. if (!hal_soc || !hal_soc->ops) {
  1942. qdf_print("Error: Invalid ops\n");
  1943. QDF_BUG(0);
  1944. return -EINVAL;
  1945. }
  1946. if (!hal_soc->ops->hal_get_link_desc_size) {
  1947. qdf_print("Error: Invalid function pointer\n");
  1948. QDF_BUG(0);
  1949. return -EINVAL;
  1950. }
  1951. return hal_soc->ops->hal_get_link_desc_size();
  1952. }
  1953. /**
  1954. * hal_get_link_desc_align - Get the required start address alignment for
  1955. * link descriptors
  1956. *
  1957. * @hal_soc: Opaque HAL SOC handle
  1958. *
  1959. */
  1960. static inline
  1961. uint32_t hal_get_link_desc_align(hal_soc_handle_t hal_soc_hdl)
  1962. {
  1963. return LINK_DESC_ALIGN;
  1964. }
  1965. /**
  1966. * hal_num_mpdus_per_link_desc - Get number of mpdus each link desc can hold
  1967. *
  1968. * @hal_soc: Opaque HAL SOC handle
  1969. *
  1970. */
  1971. static inline
  1972. uint32_t hal_num_mpdus_per_link_desc(hal_soc_handle_t hal_soc_hdl)
  1973. {
  1974. return NUM_MPDUS_PER_LINK_DESC;
  1975. }
  1976. /**
  1977. * hal_num_msdus_per_link_desc - Get number of msdus each link desc can hold
  1978. *
  1979. * @hal_soc: Opaque HAL SOC handle
  1980. *
  1981. */
  1982. static inline
  1983. uint32_t hal_num_msdus_per_link_desc(hal_soc_handle_t hal_soc_hdl)
  1984. {
  1985. return NUM_MSDUS_PER_LINK_DESC;
  1986. }
  1987. /**
  1988. * hal_num_mpdu_links_per_queue_desc - Get number of mpdu links each queue
  1989. * descriptor can hold
  1990. *
  1991. * @hal_soc: Opaque HAL SOC handle
  1992. *
  1993. */
  1994. static inline
  1995. uint32_t hal_num_mpdu_links_per_queue_desc(hal_soc_handle_t hal_soc_hdl)
  1996. {
  1997. return NUM_MPDU_LINKS_PER_QUEUE_DESC;
  1998. }
  1999. /**
  2000. * hal_idle_list_scatter_buf_num_entries - Get the number of link desc entries
  2001. * that the given buffer size
  2002. *
  2003. * @hal_soc: Opaque HAL SOC handle
  2004. * @scatter_buf_size: Size of scatter buffer
  2005. *
  2006. */
  2007. static inline
  2008. uint32_t hal_idle_scatter_buf_num_entries(hal_soc_handle_t hal_soc_hdl,
  2009. uint32_t scatter_buf_size)
  2010. {
  2011. return (scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) /
  2012. hal_srng_get_entrysize(hal_soc_hdl, WBM_IDLE_LINK);
  2013. }
  2014. /**
  2015. * hal_idle_list_num_scatter_bufs - Get the number of sctater buffer
  2016. * each given buffer size
  2017. *
  2018. * @hal_soc: Opaque HAL SOC handle
  2019. * @total_mem: size of memory to be scattered
  2020. * @scatter_buf_size: Size of scatter buffer
  2021. *
  2022. */
  2023. static inline
  2024. uint32_t hal_idle_list_num_scatter_bufs(hal_soc_handle_t hal_soc_hdl,
  2025. uint32_t total_mem,
  2026. uint32_t scatter_buf_size)
  2027. {
  2028. uint8_t rem = (total_mem % (scatter_buf_size -
  2029. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) ? 1 : 0;
  2030. uint32_t num_scatter_bufs = (total_mem / (scatter_buf_size -
  2031. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) + rem;
  2032. return num_scatter_bufs;
  2033. }
  2034. enum hal_pn_type {
  2035. HAL_PN_NONE,
  2036. HAL_PN_WPA,
  2037. HAL_PN_WAPI_EVEN,
  2038. HAL_PN_WAPI_UNEVEN,
  2039. };
  2040. #define HAL_RX_MAX_BA_WINDOW 256
  2041. /**
  2042. * hal_get_reo_qdesc_align - Get start address alignment for reo
  2043. * queue descriptors
  2044. *
  2045. * @hal_soc: Opaque HAL SOC handle
  2046. *
  2047. */
  2048. static inline
  2049. uint32_t hal_get_reo_qdesc_align(hal_soc_handle_t hal_soc_hdl)
  2050. {
  2051. return REO_QUEUE_DESC_ALIGN;
  2052. }
  2053. /**
  2054. * hal_reo_qdesc_setup - Setup HW REO queue descriptor
  2055. *
  2056. * @hal_soc: Opaque HAL SOC handle
  2057. * @ba_window_size: BlockAck window size
  2058. * @start_seq: Starting sequence number
  2059. * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
  2060. * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
  2061. * @pn_type: PN type (one of the types defined in 'enum hal_pn_type')
  2062. *
  2063. */
  2064. void hal_reo_qdesc_setup(hal_soc_handle_t hal_soc_hdl,
  2065. int tid, uint32_t ba_window_size,
  2066. uint32_t start_seq, void *hw_qdesc_vaddr,
  2067. qdf_dma_addr_t hw_qdesc_paddr,
  2068. int pn_type);
  2069. /**
  2070. * hal_srng_get_hp_addr - Get head pointer physical address
  2071. *
  2072. * @hal_soc: Opaque HAL SOC handle
  2073. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2074. *
  2075. */
  2076. static inline qdf_dma_addr_t
  2077. hal_srng_get_hp_addr(void *hal_soc,
  2078. hal_ring_handle_t hal_ring_hdl)
  2079. {
  2080. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2081. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  2082. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  2083. return hal->shadow_wrptr_mem_paddr +
  2084. ((unsigned long)(srng->u.src_ring.hp_addr) -
  2085. (unsigned long)(hal->shadow_wrptr_mem_vaddr));
  2086. } else {
  2087. return hal->shadow_rdptr_mem_paddr +
  2088. ((unsigned long)(srng->u.dst_ring.hp_addr) -
  2089. (unsigned long)(hal->shadow_rdptr_mem_vaddr));
  2090. }
  2091. }
  2092. /**
  2093. * hal_srng_get_tp_addr - Get tail pointer physical address
  2094. *
  2095. * @hal_soc: Opaque HAL SOC handle
  2096. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2097. *
  2098. */
  2099. static inline qdf_dma_addr_t
  2100. hal_srng_get_tp_addr(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  2101. {
  2102. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2103. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  2104. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  2105. return hal->shadow_rdptr_mem_paddr +
  2106. ((unsigned long)(srng->u.src_ring.tp_addr) -
  2107. (unsigned long)(hal->shadow_rdptr_mem_vaddr));
  2108. } else {
  2109. return hal->shadow_wrptr_mem_paddr +
  2110. ((unsigned long)(srng->u.dst_ring.tp_addr) -
  2111. (unsigned long)(hal->shadow_wrptr_mem_vaddr));
  2112. }
  2113. }
  2114. /**
  2115. * hal_srng_get_num_entries - Get total entries in the HAL Srng
  2116. *
  2117. * @hal_soc: Opaque HAL SOC handle
  2118. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2119. *
  2120. * Return: total number of entries in hal ring
  2121. */
  2122. static inline
  2123. uint32_t hal_srng_get_num_entries(hal_soc_handle_t hal_soc_hdl,
  2124. hal_ring_handle_t hal_ring_hdl)
  2125. {
  2126. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2127. return srng->num_entries;
  2128. }
  2129. /**
  2130. * hal_get_srng_params - Retrieve SRNG parameters for a given ring from HAL
  2131. *
  2132. * @hal_soc: Opaque HAL SOC handle
  2133. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2134. * @ring_params: SRNG parameters will be returned through this structure
  2135. */
  2136. void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl,
  2137. hal_ring_handle_t hal_ring_hdl,
  2138. struct hal_srng_params *ring_params);
  2139. /**
  2140. * hal_mem_info - Retrieve hal memory base address
  2141. *
  2142. * @hal_soc: Opaque HAL SOC handle
  2143. * @mem: pointer to structure to be updated with hal mem info
  2144. */
  2145. void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem);
  2146. /**
  2147. * hal_get_target_type - Return target type
  2148. *
  2149. * @hal_soc: Opaque HAL SOC handle
  2150. */
  2151. uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl);
  2152. /**
  2153. * hal_get_ba_aging_timeout - Retrieve BA aging timeout
  2154. *
  2155. * @hal_soc: Opaque HAL SOC handle
  2156. * @ac: Access category
  2157. * @value: timeout duration in millisec
  2158. */
  2159. void hal_get_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
  2160. uint32_t *value);
  2161. /**
  2162. * hal_set_aging_timeout - Set BA aging timeout
  2163. *
  2164. * @hal_soc: Opaque HAL SOC handle
  2165. * @ac: Access category in millisec
  2166. * @value: timeout duration value
  2167. */
  2168. void hal_set_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
  2169. uint32_t value);
  2170. /**
  2171. * hal_srng_dst_hw_init - Private function to initialize SRNG
  2172. * destination ring HW
  2173. * @hal_soc: HAL SOC handle
  2174. * @srng: SRNG ring pointer
  2175. */
  2176. static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
  2177. struct hal_srng *srng)
  2178. {
  2179. hal->ops->hal_srng_dst_hw_init(hal, srng);
  2180. }
  2181. /**
  2182. * hal_srng_src_hw_init - Private function to initialize SRNG
  2183. * source ring HW
  2184. * @hal_soc: HAL SOC handle
  2185. * @srng: SRNG ring pointer
  2186. */
  2187. static inline void hal_srng_src_hw_init(struct hal_soc *hal,
  2188. struct hal_srng *srng)
  2189. {
  2190. hal->ops->hal_srng_src_hw_init(hal, srng);
  2191. }
  2192. /**
  2193. * hal_get_hw_hptp() - Get HW head and tail pointer value for any ring
  2194. * @hal_soc: Opaque HAL SOC handle
  2195. * @hal_ring_hdl: Source ring pointer
  2196. * @headp: Head Pointer
  2197. * @tailp: Tail Pointer
  2198. * @ring_type: Ring
  2199. *
  2200. * Return: Update tail pointer and head pointer in arguments.
  2201. */
  2202. static inline
  2203. void hal_get_hw_hptp(hal_soc_handle_t hal_soc_hdl,
  2204. hal_ring_handle_t hal_ring_hdl,
  2205. uint32_t *headp, uint32_t *tailp,
  2206. uint8_t ring_type)
  2207. {
  2208. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2209. hal_soc->ops->hal_get_hw_hptp(hal_soc, hal_ring_hdl,
  2210. headp, tailp, ring_type);
  2211. }
  2212. /**
  2213. * hal_reo_setup - Initialize HW REO block
  2214. *
  2215. * @hal_soc: Opaque HAL SOC handle
  2216. * @reo_params: parameters needed by HAL for REO config
  2217. */
  2218. static inline void hal_reo_setup(hal_soc_handle_t hal_soc_hdl,
  2219. void *reoparams)
  2220. {
  2221. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2222. hal_soc->ops->hal_reo_setup(hal_soc, reoparams);
  2223. }
  2224. static inline
  2225. void hal_compute_reo_remap_ix2_ix3(hal_soc_handle_t hal_soc_hdl,
  2226. uint32_t *ring, uint32_t num_rings,
  2227. uint32_t *remap1, uint32_t *remap2)
  2228. {
  2229. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2230. return hal_soc->ops->hal_compute_reo_remap_ix2_ix3(ring,
  2231. num_rings, remap1, remap2);
  2232. }
  2233. /**
  2234. * hal_setup_link_idle_list - Setup scattered idle list using the
  2235. * buffer list provided
  2236. *
  2237. * @hal_soc: Opaque HAL SOC handle
  2238. * @scatter_bufs_base_paddr: Array of physical base addresses
  2239. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  2240. * @num_scatter_bufs: Number of scatter buffers in the above lists
  2241. * @scatter_buf_size: Size of each scatter buffer
  2242. * @last_buf_end_offset: Offset to the last entry
  2243. * @num_entries: Total entries of all scatter bufs
  2244. *
  2245. */
  2246. static inline
  2247. void hal_setup_link_idle_list(hal_soc_handle_t hal_soc_hdl,
  2248. qdf_dma_addr_t scatter_bufs_base_paddr[],
  2249. void *scatter_bufs_base_vaddr[],
  2250. uint32_t num_scatter_bufs,
  2251. uint32_t scatter_buf_size,
  2252. uint32_t last_buf_end_offset,
  2253. uint32_t num_entries)
  2254. {
  2255. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2256. hal_soc->ops->hal_setup_link_idle_list(hal_soc, scatter_bufs_base_paddr,
  2257. scatter_bufs_base_vaddr, num_scatter_bufs,
  2258. scatter_buf_size, last_buf_end_offset,
  2259. num_entries);
  2260. }
  2261. /**
  2262. * hal_srng_dump_ring_desc() - Dump ring descriptor info
  2263. *
  2264. * @hal_soc: Opaque HAL SOC handle
  2265. * @hal_ring_hdl: Source ring pointer
  2266. * @ring_desc: Opaque ring descriptor handle
  2267. */
  2268. static inline void hal_srng_dump_ring_desc(hal_soc_handle_t hal_soc_hdl,
  2269. hal_ring_handle_t hal_ring_hdl,
  2270. hal_ring_desc_t ring_desc)
  2271. {
  2272. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2273. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2274. ring_desc, (srng->entry_size << 2));
  2275. }
  2276. /**
  2277. * hal_srng_dump_ring() - Dump last 128 descs of the ring
  2278. *
  2279. * @hal_soc: Opaque HAL SOC handle
  2280. * @hal_ring_hdl: Source ring pointer
  2281. */
  2282. static inline void hal_srng_dump_ring(hal_soc_handle_t hal_soc_hdl,
  2283. hal_ring_handle_t hal_ring_hdl)
  2284. {
  2285. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2286. uint32_t *desc;
  2287. uint32_t tp, i;
  2288. tp = srng->u.dst_ring.tp;
  2289. for (i = 0; i < 128; i++) {
  2290. if (!tp)
  2291. tp = srng->ring_size;
  2292. desc = &srng->ring_base_vaddr[tp - srng->entry_size];
  2293. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP,
  2294. QDF_TRACE_LEVEL_DEBUG,
  2295. desc, (srng->entry_size << 2));
  2296. tp -= srng->entry_size;
  2297. }
  2298. }
  2299. /*
  2300. * hal_rxdma_desc_to_hal_ring_desc - API to convert rxdma ring desc
  2301. * to opaque dp_ring desc type
  2302. * @ring_desc - rxdma ring desc
  2303. *
  2304. * Return: hal_rxdma_desc_t type
  2305. */
  2306. static inline
  2307. hal_ring_desc_t hal_rxdma_desc_to_hal_ring_desc(hal_rxdma_desc_t ring_desc)
  2308. {
  2309. return (hal_ring_desc_t)ring_desc;
  2310. }
  2311. /**
  2312. * hal_srng_set_event() - Set hal_srng event
  2313. * @hal_ring_hdl: Source ring pointer
  2314. * @event: SRNG ring event
  2315. *
  2316. * Return: None
  2317. */
  2318. static inline void hal_srng_set_event(hal_ring_handle_t hal_ring_hdl, int event)
  2319. {
  2320. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2321. qdf_atomic_set_bit(event, &srng->srng_event);
  2322. }
  2323. /**
  2324. * hal_srng_clear_event() - Clear hal_srng event
  2325. * @hal_ring_hdl: Source ring pointer
  2326. * @event: SRNG ring event
  2327. *
  2328. * Return: None
  2329. */
  2330. static inline
  2331. void hal_srng_clear_event(hal_ring_handle_t hal_ring_hdl, int event)
  2332. {
  2333. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2334. qdf_atomic_clear_bit(event, &srng->srng_event);
  2335. }
  2336. /**
  2337. * hal_srng_get_clear_event() - Clear srng event and return old value
  2338. * @hal_ring_hdl: Source ring pointer
  2339. * @event: SRNG ring event
  2340. *
  2341. * Return: Return old event value
  2342. */
  2343. static inline
  2344. int hal_srng_get_clear_event(hal_ring_handle_t hal_ring_hdl, int event)
  2345. {
  2346. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2347. return qdf_atomic_test_and_clear_bit(event, &srng->srng_event);
  2348. }
  2349. /**
  2350. * hal_srng_set_flush_last_ts() - Record last flush time stamp
  2351. * @hal_ring_hdl: Source ring pointer
  2352. *
  2353. * Return: None
  2354. */
  2355. static inline void hal_srng_set_flush_last_ts(hal_ring_handle_t hal_ring_hdl)
  2356. {
  2357. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2358. srng->last_flush_ts = qdf_get_log_timestamp();
  2359. }
  2360. /**
  2361. * hal_srng_inc_flush_cnt() - Increment flush counter
  2362. * @hal_ring_hdl: Source ring pointer
  2363. *
  2364. * Return: None
  2365. */
  2366. static inline void hal_srng_inc_flush_cnt(hal_ring_handle_t hal_ring_hdl)
  2367. {
  2368. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2369. srng->flush_count++;
  2370. }
  2371. /**
  2372. * hal_rx_sw_mon_desc_info_get () - Get SW monitor desc info
  2373. *
  2374. * @hal: Core HAL soc handle
  2375. * @ring_desc: Mon dest ring descriptor
  2376. * @desc_info: Desc info to be populated
  2377. *
  2378. * Return void
  2379. */
  2380. static inline void
  2381. hal_rx_sw_mon_desc_info_get(struct hal_soc *hal,
  2382. hal_ring_desc_t ring_desc,
  2383. hal_rx_mon_desc_info_t desc_info)
  2384. {
  2385. return hal->ops->hal_rx_sw_mon_desc_info_get(ring_desc, desc_info);
  2386. }
  2387. /**
  2388. * hal_reo_set_err_dst_remap() - Set REO error destination ring remap
  2389. * register value.
  2390. *
  2391. * @hal_soc_hdl: Opaque HAL soc handle
  2392. *
  2393. * Return: None
  2394. */
  2395. static inline void hal_reo_set_err_dst_remap(hal_soc_handle_t hal_soc_hdl)
  2396. {
  2397. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2398. if (hal_soc->ops->hal_reo_set_err_dst_remap)
  2399. hal_soc->ops->hal_reo_set_err_dst_remap(hal_soc);
  2400. }
  2401. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  2402. /**
  2403. * hal_set_one_target_reg_config() - Populate the target reg
  2404. * offset in hal_soc for one non srng related register at the
  2405. * given list index
  2406. * @hal_soc: hal handle
  2407. * @target_reg_offset: target register offset
  2408. * @list_index: index in hal list for shadow regs
  2409. *
  2410. * Return: none
  2411. */
  2412. void hal_set_one_target_reg_config(struct hal_soc *hal,
  2413. uint32_t target_reg_offset,
  2414. int list_index);
  2415. /**
  2416. * hal_set_shadow_regs() - Populate register offset for
  2417. * registers that need to be populated in list_shadow_reg_config
  2418. * in order to be sent to FW. These reg offsets will be mapped
  2419. * to shadow registers.
  2420. * @hal_soc: hal handle
  2421. *
  2422. * Return: QDF_STATUS_OK on success
  2423. */
  2424. QDF_STATUS hal_set_shadow_regs(void *hal_soc);
  2425. /**
  2426. * hal_construct_shadow_regs() - initialize the shadow registers
  2427. * for non-srng related register configs
  2428. * @hal_soc: hal handle
  2429. *
  2430. * Return: QDF_STATUS_OK on success
  2431. */
  2432. QDF_STATUS hal_construct_shadow_regs(void *hal_soc);
  2433. #else /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  2434. static inline void hal_set_one_target_reg_config(
  2435. struct hal_soc *hal,
  2436. uint32_t target_reg_offset,
  2437. int list_index)
  2438. {
  2439. }
  2440. static inline QDF_STATUS hal_set_shadow_regs(void *hal_soc)
  2441. {
  2442. return QDF_STATUS_SUCCESS;
  2443. }
  2444. static inline QDF_STATUS hal_construct_shadow_regs(void *hal_soc)
  2445. {
  2446. return QDF_STATUS_SUCCESS;
  2447. }
  2448. #endif /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  2449. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  2450. /**
  2451. * hal_flush_reg_write_work() - flush all writes from register write queue
  2452. * @arg: hal_soc pointer
  2453. *
  2454. * Return: None
  2455. */
  2456. void hal_flush_reg_write_work(hal_soc_handle_t hal_handle);
  2457. #else
  2458. static inline void hal_flush_reg_write_work(hal_soc_handle_t hal_handle) { }
  2459. #endif
  2460. #endif /* _HAL_APIH_ */