wcd938x.c 118 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VARIANT_ENTRY_SIZE 32
  27. #define WCD938X_VERSION_1_0 1
  28. #define WCD938X_VERSION_ENTRY_SIZE 32
  29. #define EAR_RX_PATH_AUX 1
  30. #define ADC_MODE_VAL_HIFI 0x01
  31. #define ADC_MODE_VAL_LO_HIF 0x02
  32. #define ADC_MODE_VAL_NORMAL 0x03
  33. #define ADC_MODE_VAL_LP 0x05
  34. #define ADC_MODE_VAL_ULP1 0x09
  35. #define ADC_MODE_VAL_ULP2 0x0B
  36. #define NUM_ATTEMPTS 5
  37. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  38. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  39. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  40. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  41. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  42. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  43. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  44. SNDRV_PCM_RATE_384000)
  45. /* Fractional Rates */
  46. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  47. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  48. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  49. SNDRV_PCM_FMTBIT_S24_LE |\
  50. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  51. enum {
  52. CODEC_TX = 0,
  53. CODEC_RX,
  54. };
  55. enum {
  56. WCD_ADC1 = 0,
  57. WCD_ADC2,
  58. WCD_ADC3,
  59. WCD_ADC4,
  60. ALLOW_BUCK_DISABLE,
  61. HPH_COMP_DELAY,
  62. HPH_PA_DELAY,
  63. AMIC2_BCS_ENABLE,
  64. };
  65. enum {
  66. ADC_MODE_INVALID = 0,
  67. ADC_MODE_HIFI,
  68. ADC_MODE_LO_HIF,
  69. ADC_MODE_NORMAL,
  70. ADC_MODE_LP,
  71. ADC_MODE_ULP1,
  72. ADC_MODE_ULP2,
  73. };
  74. static u8 tx_mode_bit[] = {
  75. [ADC_MODE_INVALID] = 0x00,
  76. [ADC_MODE_HIFI] = 0x01,
  77. [ADC_MODE_LO_HIF] = 0x02,
  78. [ADC_MODE_NORMAL] = 0x04,
  79. [ADC_MODE_LP] = 0x08,
  80. [ADC_MODE_ULP1] = 0x10,
  81. [ADC_MODE_ULP2] = 0x20,
  82. };
  83. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  84. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  85. static int wcd938x_handle_post_irq(void *data);
  86. static int wcd938x_reset(struct device *dev);
  87. static int wcd938x_reset_low(struct device *dev);
  88. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  89. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  90. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  91. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  92. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  93. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  94. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  95. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  96. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  97. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  109. };
  110. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  111. .name = "wcd938x",
  112. .irqs = wcd938x_irqs,
  113. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  114. .num_regs = 3,
  115. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  116. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  117. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  118. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  119. .use_ack = 1,
  120. .runtime_pm = false,
  121. .handle_post_irq = wcd938x_handle_post_irq,
  122. .irq_drv_data = NULL,
  123. };
  124. static int wcd938x_handle_post_irq(void *data)
  125. {
  126. struct wcd938x_priv *wcd938x = data;
  127. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  128. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  129. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  130. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  131. wcd938x->tx_swr_dev->slave_irq_pending =
  132. ((sts1 || sts2 || sts3) ? true : false);
  133. return IRQ_HANDLED;
  134. }
  135. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  136. {
  137. int ret = 0;
  138. int bank = 0;
  139. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  140. if (ret)
  141. return -EINVAL;
  142. return ((bank & 0x40) ? 1: 0);
  143. }
  144. static int wcd938x_get_clk_rate(int mode)
  145. {
  146. int rate;
  147. switch (mode) {
  148. case ADC_MODE_ULP2:
  149. rate = SWR_CLK_RATE_0P6MHZ;
  150. break;
  151. case ADC_MODE_ULP1:
  152. rate = SWR_CLK_RATE_1P2MHZ;
  153. break;
  154. case ADC_MODE_LP:
  155. rate = SWR_CLK_RATE_4P8MHZ;
  156. break;
  157. case ADC_MODE_NORMAL:
  158. case ADC_MODE_LO_HIF:
  159. case ADC_MODE_HIFI:
  160. case ADC_MODE_INVALID:
  161. default:
  162. rate = SWR_CLK_RATE_9P6MHZ;
  163. break;
  164. }
  165. return rate;
  166. }
  167. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  168. int rate, int bank)
  169. {
  170. u8 mask = (bank ? 0xF0 : 0x0F);
  171. u8 val = 0;
  172. switch (rate) {
  173. case SWR_CLK_RATE_0P6MHZ:
  174. val = (bank ? 0x60 : 0x06);
  175. break;
  176. case SWR_CLK_RATE_1P2MHZ:
  177. val = (bank ? 0x50 : 0x05);
  178. break;
  179. case SWR_CLK_RATE_2P4MHZ:
  180. val = (bank ? 0x30 : 0x03);
  181. break;
  182. case SWR_CLK_RATE_4P8MHZ:
  183. val = (bank ? 0x10 : 0x01);
  184. break;
  185. case SWR_CLK_RATE_9P6MHZ:
  186. default:
  187. val = 0x00;
  188. break;
  189. }
  190. snd_soc_component_update_bits(component,
  191. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  192. mask, val);
  193. return 0;
  194. }
  195. static int wcd938x_init_reg(struct snd_soc_component *component)
  196. {
  197. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  198. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  199. /* 1 msec delay as per HW requirement */
  200. usleep_range(1000, 1010);
  201. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  202. /* 1 msec delay as per HW requirement */
  203. usleep_range(1000, 1010);
  204. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  205. 0x10, 0x00);
  206. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  207. 0xF0, 0x80);
  208. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  209. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  210. /* 10 msec delay as per HW requirement */
  211. usleep_range(10000, 10010);
  212. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  213. snd_soc_component_update_bits(component,
  214. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  215. 0xF0, 0x00);
  216. snd_soc_component_update_bits(component,
  217. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  218. 0x1F, 0x15);
  219. snd_soc_component_update_bits(component,
  220. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  221. 0x1F, 0x15);
  222. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  223. 0xC0, 0x80);
  224. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  225. 0x02, 0x02);
  226. snd_soc_component_update_bits(component,
  227. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  228. 0xFF, 0x14);
  229. snd_soc_component_update_bits(component,
  230. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  231. 0x1F, 0x08);
  232. snd_soc_component_update_bits(component,
  233. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  234. snd_soc_component_update_bits(component,
  235. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  236. snd_soc_component_update_bits(component,
  237. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  238. snd_soc_component_update_bits(component,
  239. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  240. snd_soc_component_update_bits(component,
  241. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  242. snd_soc_component_update_bits(component,
  243. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  244. snd_soc_component_update_bits(component,
  245. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  246. snd_soc_component_update_bits(component,
  247. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  248. snd_soc_component_update_bits(component,
  249. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  250. snd_soc_component_update_bits(component,
  251. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  252. return 0;
  253. }
  254. static int wcd938x_set_port_params(struct snd_soc_component *component,
  255. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  256. u8 *ch_mask, u32 *ch_rate,
  257. u8 *port_type, u8 path)
  258. {
  259. int i, j;
  260. u8 num_ports = 0;
  261. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  262. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  263. switch (path) {
  264. case CODEC_RX:
  265. map = &wcd938x->rx_port_mapping;
  266. num_ports = wcd938x->num_rx_ports;
  267. break;
  268. case CODEC_TX:
  269. map = &wcd938x->tx_port_mapping;
  270. num_ports = wcd938x->num_tx_ports;
  271. break;
  272. default:
  273. dev_err(component->dev, "%s Invalid path selected %u\n",
  274. __func__, path);
  275. return -EINVAL;
  276. }
  277. for (i = 0; i <= num_ports; i++) {
  278. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  279. if ((*map)[i][j].slave_port_type == slv_prt_type)
  280. goto found;
  281. }
  282. }
  283. found:
  284. if (i > num_ports || j == MAX_CH_PER_PORT) {
  285. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  286. __func__, slv_prt_type);
  287. return -EINVAL;
  288. }
  289. *port_id = i;
  290. *num_ch = (*map)[i][j].num_ch;
  291. *ch_mask = (*map)[i][j].ch_mask;
  292. *ch_rate = (*map)[i][j].ch_rate;
  293. *port_type = (*map)[i][j].master_port_type;
  294. return 0;
  295. }
  296. static int wcd938x_parse_port_mapping(struct device *dev,
  297. char *prop, u8 path)
  298. {
  299. u32 *dt_array, map_size, map_length;
  300. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  301. u32 slave_port_type, master_port_type;
  302. u32 i, ch_iter = 0;
  303. int ret = 0;
  304. u8 *num_ports = NULL;
  305. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  306. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  307. switch (path) {
  308. case CODEC_RX:
  309. map = &wcd938x->rx_port_mapping;
  310. num_ports = &wcd938x->num_rx_ports;
  311. break;
  312. case CODEC_TX:
  313. map = &wcd938x->tx_port_mapping;
  314. num_ports = &wcd938x->num_tx_ports;
  315. break;
  316. default:
  317. dev_err(dev, "%s Invalid path selected %u\n",
  318. __func__, path);
  319. return -EINVAL;
  320. }
  321. if (!of_find_property(dev->of_node, prop,
  322. &map_size)) {
  323. dev_err(dev, "missing port mapping prop %s\n", prop);
  324. ret = -EINVAL;
  325. goto err_port_map;
  326. }
  327. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  328. dt_array = kzalloc(map_size, GFP_KERNEL);
  329. if (!dt_array) {
  330. ret = -ENOMEM;
  331. goto err_alloc;
  332. }
  333. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  334. NUM_SWRS_DT_PARAMS * map_length);
  335. if (ret) {
  336. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  337. __func__, prop);
  338. goto err_pdata_fail;
  339. }
  340. for (i = 0; i < map_length; i++) {
  341. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  342. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  343. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  344. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  345. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  346. if (port_num != old_port_num)
  347. ch_iter = 0;
  348. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  349. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  350. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  351. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  352. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  353. old_port_num = port_num;
  354. }
  355. *num_ports = port_num;
  356. kfree(dt_array);
  357. return 0;
  358. err_pdata_fail:
  359. kfree(dt_array);
  360. err_alloc:
  361. err_port_map:
  362. return ret;
  363. }
  364. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  365. u8 slv_port_type, int clk_rate,
  366. u8 enable)
  367. {
  368. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  369. u8 port_id, num_ch, ch_mask;
  370. u8 ch_type = 0;
  371. u32 ch_rate;
  372. int slave_ch_idx;
  373. u8 num_port = 1;
  374. int ret = 0;
  375. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  376. &num_ch, &ch_mask, &ch_rate,
  377. &ch_type, CODEC_TX);
  378. if (ret)
  379. return ret;
  380. if (clk_rate)
  381. ch_rate = clk_rate;
  382. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  383. if (slave_ch_idx != -EINVAL)
  384. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  385. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  386. __func__, slave_ch_idx, ch_type);
  387. if (enable)
  388. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  389. num_port, &ch_mask, &ch_rate,
  390. &num_ch, &ch_type);
  391. else
  392. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  393. num_port, &ch_mask, &ch_type);
  394. return ret;
  395. }
  396. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  397. u8 slv_port_type, u8 enable)
  398. {
  399. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  400. u8 port_id, num_ch, ch_mask, port_type;
  401. u32 ch_rate;
  402. u8 num_port = 1;
  403. int ret = 0;
  404. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  405. &num_ch, &ch_mask, &ch_rate,
  406. &port_type, CODEC_RX);
  407. if (ret)
  408. return ret;
  409. if (enable)
  410. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  411. num_port, &ch_mask, &ch_rate,
  412. &num_ch, &port_type);
  413. else
  414. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  415. num_port, &ch_mask, &port_type);
  416. return ret;
  417. }
  418. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  419. {
  420. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  421. if (wcd938x->rx_clk_cnt == 0) {
  422. snd_soc_component_update_bits(component,
  423. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  424. snd_soc_component_update_bits(component,
  425. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  426. snd_soc_component_update_bits(component,
  427. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  428. snd_soc_component_update_bits(component,
  429. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  430. snd_soc_component_update_bits(component,
  431. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  432. snd_soc_component_update_bits(component,
  433. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  434. snd_soc_component_update_bits(component,
  435. WCD938X_AUX_AUXPA, 0x10, 0x10);
  436. }
  437. wcd938x->rx_clk_cnt++;
  438. return 0;
  439. }
  440. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  441. {
  442. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  443. wcd938x->rx_clk_cnt--;
  444. if (wcd938x->rx_clk_cnt == 0) {
  445. snd_soc_component_update_bits(component,
  446. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  447. snd_soc_component_update_bits(component,
  448. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  449. snd_soc_component_update_bits(component,
  450. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  451. snd_soc_component_update_bits(component,
  452. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  453. snd_soc_component_update_bits(component,
  454. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  455. }
  456. return 0;
  457. }
  458. /*
  459. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  460. * @component: handle to snd_soc_component *
  461. *
  462. * return wcd938x_mbhc handle or error code in case of failure
  463. */
  464. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  465. {
  466. struct wcd938x_priv *wcd938x;
  467. if (!component) {
  468. pr_err("%s: Invalid params, NULL component\n", __func__);
  469. return NULL;
  470. }
  471. wcd938x = snd_soc_component_get_drvdata(component);
  472. if (!wcd938x) {
  473. pr_err("%s: wcd938x is NULL\n", __func__);
  474. return NULL;
  475. }
  476. return wcd938x->mbhc;
  477. }
  478. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  479. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  480. struct snd_kcontrol *kcontrol,
  481. int event)
  482. {
  483. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  484. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  485. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  486. w->name, event);
  487. switch (event) {
  488. case SND_SOC_DAPM_PRE_PMU:
  489. wcd938x_rx_clk_enable(component);
  490. snd_soc_component_update_bits(component,
  491. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  492. snd_soc_component_update_bits(component,
  493. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  494. snd_soc_component_update_bits(component,
  495. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  496. break;
  497. case SND_SOC_DAPM_POST_PMU:
  498. snd_soc_component_update_bits(component,
  499. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  500. if (wcd938x->comp1_enable) {
  501. snd_soc_component_update_bits(component,
  502. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  503. /* 5msec compander delay as per HW requirement */
  504. if (!wcd938x->comp2_enable ||
  505. (snd_soc_component_read32(component,
  506. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  507. usleep_range(5000, 5010);
  508. snd_soc_component_update_bits(component,
  509. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  510. } else {
  511. snd_soc_component_update_bits(component,
  512. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  513. 0x02, 0x00);
  514. snd_soc_component_update_bits(component,
  515. WCD938X_HPH_L_EN, 0x20, 0x20);
  516. }
  517. break;
  518. case SND_SOC_DAPM_POST_PMD:
  519. snd_soc_component_update_bits(component,
  520. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  521. 0x0F, 0x01);
  522. break;
  523. }
  524. return 0;
  525. }
  526. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  527. struct snd_kcontrol *kcontrol,
  528. int event)
  529. {
  530. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  531. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  532. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  533. w->name, event);
  534. switch (event) {
  535. case SND_SOC_DAPM_PRE_PMU:
  536. wcd938x_rx_clk_enable(component);
  537. snd_soc_component_update_bits(component,
  538. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  539. snd_soc_component_update_bits(component,
  540. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  541. snd_soc_component_update_bits(component,
  542. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  543. break;
  544. case SND_SOC_DAPM_POST_PMU:
  545. snd_soc_component_update_bits(component,
  546. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  547. if (wcd938x->comp2_enable) {
  548. snd_soc_component_update_bits(component,
  549. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  550. /* 5msec compander delay as per HW requirement */
  551. if (!wcd938x->comp1_enable ||
  552. (snd_soc_component_read32(component,
  553. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  554. usleep_range(5000, 5010);
  555. snd_soc_component_update_bits(component,
  556. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  557. } else {
  558. snd_soc_component_update_bits(component,
  559. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  560. 0x01, 0x00);
  561. snd_soc_component_update_bits(component,
  562. WCD938X_HPH_R_EN, 0x20, 0x20);
  563. }
  564. break;
  565. case SND_SOC_DAPM_POST_PMD:
  566. snd_soc_component_update_bits(component,
  567. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  568. 0x0F, 0x01);
  569. break;
  570. }
  571. return 0;
  572. }
  573. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  574. struct snd_kcontrol *kcontrol,
  575. int event)
  576. {
  577. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  578. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  579. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  580. w->name, event);
  581. switch (event) {
  582. case SND_SOC_DAPM_PRE_PMU:
  583. wcd938x_rx_clk_enable(component);
  584. wcd938x->ear_rx_path =
  585. snd_soc_component_read32(
  586. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  587. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  588. snd_soc_component_update_bits(component,
  589. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  590. snd_soc_component_update_bits(component,
  591. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  592. snd_soc_component_update_bits(component,
  593. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  594. snd_soc_component_update_bits(component,
  595. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  596. } else {
  597. snd_soc_component_update_bits(component,
  598. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  599. snd_soc_component_update_bits(component,
  600. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  601. snd_soc_component_update_bits(component,
  602. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  603. }
  604. /* 5 msec delay as per HW requirement */
  605. usleep_range(5000, 5010);
  606. if (wcd938x->flyback_cur_det_disable == 0)
  607. snd_soc_component_update_bits(component,
  608. WCD938X_FLYBACK_EN,
  609. 0x04, 0x00);
  610. wcd938x->flyback_cur_det_disable++;
  611. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  612. WCD_CLSH_EVENT_PRE_DAC,
  613. WCD_CLSH_STATE_EAR,
  614. wcd938x->hph_mode);
  615. break;
  616. case SND_SOC_DAPM_POST_PMD:
  617. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  618. snd_soc_component_update_bits(component,
  619. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  620. }
  621. snd_soc_component_update_bits(component,
  622. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  623. snd_soc_component_update_bits(component,
  624. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  625. break;
  626. };
  627. return 0;
  628. }
  629. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  630. struct snd_kcontrol *kcontrol,
  631. int event)
  632. {
  633. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  634. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  635. int ret = 0;
  636. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  637. w->name, event);
  638. switch (event) {
  639. case SND_SOC_DAPM_PRE_PMU:
  640. wcd938x_rx_clk_enable(component);
  641. snd_soc_component_update_bits(component,
  642. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  643. snd_soc_component_update_bits(component,
  644. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  645. snd_soc_component_update_bits(component,
  646. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  647. if (wcd938x->flyback_cur_det_disable == 0)
  648. snd_soc_component_update_bits(component,
  649. WCD938X_FLYBACK_EN,
  650. 0x04, 0x00);
  651. wcd938x->flyback_cur_det_disable++;
  652. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  653. WCD_CLSH_EVENT_PRE_DAC,
  654. WCD_CLSH_STATE_AUX,
  655. wcd938x->hph_mode);
  656. break;
  657. case SND_SOC_DAPM_POST_PMD:
  658. snd_soc_component_update_bits(component,
  659. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  660. break;
  661. };
  662. return ret;
  663. }
  664. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  665. struct snd_kcontrol *kcontrol,
  666. int event)
  667. {
  668. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  669. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  670. int ret = 0;
  671. int hph_mode = wcd938x->hph_mode;
  672. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  673. w->name, event);
  674. switch (event) {
  675. case SND_SOC_DAPM_PRE_PMU:
  676. if (wcd938x->ldoh)
  677. snd_soc_component_update_bits(component,
  678. WCD938X_LDOH_MODE,
  679. 0x80, 0x80);
  680. if (wcd938x->update_wcd_event)
  681. wcd938x->update_wcd_event(wcd938x->handle,
  682. WCD_BOLERO_EVT_RX_MUTE,
  683. (WCD_RX2 << 0x10 | 0x1));
  684. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  685. wcd938x->rx_swr_dev->dev_num,
  686. true);
  687. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  688. WCD_CLSH_EVENT_PRE_DAC,
  689. WCD_CLSH_STATE_HPHR,
  690. hph_mode);
  691. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  692. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  693. hph_mode == CLS_H_ULP) {
  694. snd_soc_component_update_bits(component,
  695. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  696. }
  697. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  698. 0x10, 0x10);
  699. wcd_clsh_set_hph_mode(component, hph_mode);
  700. /* 100 usec delay as per HW requirement */
  701. usleep_range(100, 110);
  702. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  703. snd_soc_component_update_bits(component,
  704. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  705. break;
  706. case SND_SOC_DAPM_POST_PMU:
  707. /*
  708. * 7ms sleep is required if compander is enabled as per
  709. * HW requirement. If compander is disabled, then
  710. * 20ms delay is required.
  711. */
  712. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  713. if (!wcd938x->comp2_enable)
  714. usleep_range(20000, 20100);
  715. else
  716. usleep_range(7000, 7100);
  717. if (hph_mode == CLS_H_LP ||
  718. hph_mode == CLS_H_LOHIFI ||
  719. hph_mode == CLS_H_ULP)
  720. snd_soc_component_update_bits(component,
  721. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  722. 0x00);
  723. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  724. }
  725. snd_soc_component_update_bits(component,
  726. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  727. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  728. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  729. snd_soc_component_update_bits(component,
  730. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  731. if (wcd938x->update_wcd_event)
  732. wcd938x->update_wcd_event(wcd938x->handle,
  733. WCD_BOLERO_EVT_RX_MUTE,
  734. (WCD_RX2 << 0x10));
  735. wcd_enable_irq(&wcd938x->irq_info,
  736. WCD938X_IRQ_HPHR_PDM_WD_INT);
  737. break;
  738. case SND_SOC_DAPM_PRE_PMD:
  739. if (wcd938x->update_wcd_event)
  740. wcd938x->update_wcd_event(wcd938x->handle,
  741. WCD_BOLERO_EVT_RX_MUTE,
  742. (WCD_RX2 << 0x10 | 0x1));
  743. wcd_disable_irq(&wcd938x->irq_info,
  744. WCD938X_IRQ_HPHR_PDM_WD_INT);
  745. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  746. wcd938x->update_wcd_event(wcd938x->handle,
  747. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  748. (WCD_RX2 << 0x10));
  749. /*
  750. * 7ms sleep is required if compander is enabled as per
  751. * HW requirement. If compander is disabled, then
  752. * 20ms delay is required.
  753. */
  754. if (!wcd938x->comp2_enable)
  755. usleep_range(20000, 20100);
  756. else
  757. usleep_range(7000, 7100);
  758. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  759. 0x40, 0x00);
  760. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  761. WCD_EVENT_PRE_HPHR_PA_OFF,
  762. &wcd938x->mbhc->wcd_mbhc);
  763. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  764. break;
  765. case SND_SOC_DAPM_POST_PMD:
  766. /*
  767. * 7ms sleep is required if compander is enabled as per
  768. * HW requirement. If compander is disabled, then
  769. * 20ms delay is required.
  770. */
  771. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  772. if (!wcd938x->comp2_enable)
  773. usleep_range(20000, 20100);
  774. else
  775. usleep_range(7000, 7100);
  776. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  777. }
  778. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  779. WCD_EVENT_POST_HPHR_PA_OFF,
  780. &wcd938x->mbhc->wcd_mbhc);
  781. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  782. 0x10, 0x00);
  783. snd_soc_component_update_bits(component,
  784. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  785. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  786. WCD_CLSH_EVENT_POST_PA,
  787. WCD_CLSH_STATE_HPHR,
  788. hph_mode);
  789. if (wcd938x->ldoh)
  790. snd_soc_component_update_bits(component,
  791. WCD938X_LDOH_MODE,
  792. 0x80, 0x00);
  793. break;
  794. };
  795. return ret;
  796. }
  797. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  798. struct snd_kcontrol *kcontrol,
  799. int event)
  800. {
  801. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  802. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  803. int ret = 0;
  804. int hph_mode = wcd938x->hph_mode;
  805. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  806. w->name, event);
  807. switch (event) {
  808. case SND_SOC_DAPM_PRE_PMU:
  809. if (wcd938x->ldoh)
  810. snd_soc_component_update_bits(component,
  811. WCD938X_LDOH_MODE,
  812. 0x80, 0x80);
  813. if (wcd938x->update_wcd_event)
  814. wcd938x->update_wcd_event(wcd938x->handle,
  815. WCD_BOLERO_EVT_RX_MUTE,
  816. (WCD_RX1 << 0x10 | 0x01));
  817. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  818. wcd938x->rx_swr_dev->dev_num,
  819. true);
  820. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  821. WCD_CLSH_EVENT_PRE_DAC,
  822. WCD_CLSH_STATE_HPHL,
  823. hph_mode);
  824. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  825. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  826. hph_mode == CLS_H_ULP) {
  827. snd_soc_component_update_bits(component,
  828. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  829. }
  830. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  831. 0x20, 0x20);
  832. wcd_clsh_set_hph_mode(component, hph_mode);
  833. /* 100 usec delay as per HW requirement */
  834. usleep_range(100, 110);
  835. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  836. snd_soc_component_update_bits(component,
  837. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  838. break;
  839. case SND_SOC_DAPM_POST_PMU:
  840. /*
  841. * 7ms sleep is required if compander is enabled as per
  842. * HW requirement. If compander is disabled, then
  843. * 20ms delay is required.
  844. */
  845. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  846. if (!wcd938x->comp1_enable)
  847. usleep_range(20000, 20100);
  848. else
  849. usleep_range(7000, 7100);
  850. if (hph_mode == CLS_H_LP ||
  851. hph_mode == CLS_H_LOHIFI ||
  852. hph_mode == CLS_H_ULP)
  853. snd_soc_component_update_bits(component,
  854. WCD938X_HPH_REFBUFF_LP_CTL,
  855. 0x01, 0x00);
  856. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  857. }
  858. snd_soc_component_update_bits(component,
  859. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  860. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  861. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  862. snd_soc_component_update_bits(component,
  863. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  864. if (wcd938x->update_wcd_event)
  865. wcd938x->update_wcd_event(wcd938x->handle,
  866. WCD_BOLERO_EVT_RX_MUTE,
  867. (WCD_RX1 << 0x10));
  868. wcd_enable_irq(&wcd938x->irq_info,
  869. WCD938X_IRQ_HPHL_PDM_WD_INT);
  870. break;
  871. case SND_SOC_DAPM_PRE_PMD:
  872. if (wcd938x->update_wcd_event)
  873. wcd938x->update_wcd_event(wcd938x->handle,
  874. WCD_BOLERO_EVT_RX_MUTE,
  875. (WCD_RX1 << 0x10 | 0x1));
  876. wcd_disable_irq(&wcd938x->irq_info,
  877. WCD938X_IRQ_HPHL_PDM_WD_INT);
  878. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  879. wcd938x->update_wcd_event(wcd938x->handle,
  880. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  881. (WCD_RX1 << 0x10));
  882. /*
  883. * 7ms sleep is required if compander is enabled as per
  884. * HW requirement. If compander is disabled, then
  885. * 20ms delay is required.
  886. */
  887. if (!wcd938x->comp1_enable)
  888. usleep_range(20000, 20100);
  889. else
  890. usleep_range(7000, 7100);
  891. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  892. 0x80, 0x00);
  893. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  894. WCD_EVENT_PRE_HPHL_PA_OFF,
  895. &wcd938x->mbhc->wcd_mbhc);
  896. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  897. break;
  898. case SND_SOC_DAPM_POST_PMD:
  899. /*
  900. * 7ms sleep is required if compander is enabled as per
  901. * HW requirement. If compander is disabled, then
  902. * 20ms delay is required.
  903. */
  904. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  905. if (!wcd938x->comp1_enable)
  906. usleep_range(21000, 21100);
  907. else
  908. usleep_range(7000, 7100);
  909. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  910. }
  911. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  912. WCD_EVENT_POST_HPHL_PA_OFF,
  913. &wcd938x->mbhc->wcd_mbhc);
  914. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  915. 0x20, 0x00);
  916. snd_soc_component_update_bits(component,
  917. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  918. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  919. WCD_CLSH_EVENT_POST_PA,
  920. WCD_CLSH_STATE_HPHL,
  921. hph_mode);
  922. if (wcd938x->ldoh)
  923. snd_soc_component_update_bits(component,
  924. WCD938X_LDOH_MODE,
  925. 0x80, 0x00);
  926. break;
  927. };
  928. return ret;
  929. }
  930. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  931. struct snd_kcontrol *kcontrol,
  932. int event)
  933. {
  934. struct snd_soc_component *component =
  935. snd_soc_dapm_to_component(w->dapm);
  936. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  937. int hph_mode = wcd938x->hph_mode;
  938. int ret = 0;
  939. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  940. w->name, event);
  941. switch (event) {
  942. case SND_SOC_DAPM_PRE_PMU:
  943. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  944. wcd938x->rx_swr_dev->dev_num,
  945. true);
  946. snd_soc_component_update_bits(component,
  947. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  948. break;
  949. case SND_SOC_DAPM_POST_PMU:
  950. /* 1 msec delay as per HW requirement */
  951. usleep_range(1000, 1010);
  952. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  953. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  954. snd_soc_component_update_bits(component,
  955. WCD938X_ANA_RX_SUPPLIES,
  956. 0x02, 0x02);
  957. if (wcd938x->update_wcd_event)
  958. wcd938x->update_wcd_event(wcd938x->handle,
  959. WCD_BOLERO_EVT_RX_MUTE,
  960. (WCD_RX3 << 0x10));
  961. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  962. break;
  963. case SND_SOC_DAPM_PRE_PMD:
  964. wcd_disable_irq(&wcd938x->irq_info,
  965. WCD938X_IRQ_AUX_PDM_WD_INT);
  966. if (wcd938x->update_wcd_event)
  967. wcd938x->update_wcd_event(wcd938x->handle,
  968. WCD_BOLERO_EVT_RX_MUTE,
  969. (WCD_RX3 << 0x10 | 0x1));
  970. break;
  971. case SND_SOC_DAPM_POST_PMD:
  972. /* 1 msec delay as per HW requirement */
  973. usleep_range(1000, 1010);
  974. snd_soc_component_update_bits(component,
  975. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  976. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  977. WCD_CLSH_EVENT_POST_PA,
  978. WCD_CLSH_STATE_AUX,
  979. hph_mode);
  980. wcd938x->flyback_cur_det_disable--;
  981. if (wcd938x->flyback_cur_det_disable == 0)
  982. snd_soc_component_update_bits(component,
  983. WCD938X_FLYBACK_EN,
  984. 0x04, 0x04);
  985. break;
  986. };
  987. return ret;
  988. }
  989. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  990. struct snd_kcontrol *kcontrol,
  991. int event)
  992. {
  993. struct snd_soc_component *component =
  994. snd_soc_dapm_to_component(w->dapm);
  995. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  996. int hph_mode = wcd938x->hph_mode;
  997. int ret = 0;
  998. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  999. w->name, event);
  1000. switch (event) {
  1001. case SND_SOC_DAPM_PRE_PMU:
  1002. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1003. wcd938x->rx_swr_dev->dev_num,
  1004. true);
  1005. /*
  1006. * Enable watchdog interrupt for HPHL or AUX
  1007. * depending on mux value
  1008. */
  1009. wcd938x->ear_rx_path =
  1010. snd_soc_component_read32(
  1011. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1012. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1013. snd_soc_component_update_bits(component,
  1014. WCD938X_DIGITAL_PDM_WD_CTL2,
  1015. 0x05, 0x05);
  1016. else
  1017. snd_soc_component_update_bits(component,
  1018. WCD938X_DIGITAL_PDM_WD_CTL0,
  1019. 0x17, 0x13);
  1020. if (!wcd938x->comp1_enable)
  1021. snd_soc_component_update_bits(component,
  1022. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1023. break;
  1024. case SND_SOC_DAPM_POST_PMU:
  1025. /* 6 msec delay as per HW requirement */
  1026. usleep_range(6000, 6010);
  1027. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1028. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1029. snd_soc_component_update_bits(component,
  1030. WCD938X_ANA_RX_SUPPLIES,
  1031. 0x02, 0x02);
  1032. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1033. if (wcd938x->update_wcd_event)
  1034. wcd938x->update_wcd_event(wcd938x->handle,
  1035. WCD_BOLERO_EVT_RX_MUTE,
  1036. (WCD_RX3 << 0x10));
  1037. wcd_enable_irq(&wcd938x->irq_info,
  1038. WCD938X_IRQ_AUX_PDM_WD_INT);
  1039. } else {
  1040. if (wcd938x->update_wcd_event)
  1041. wcd938x->update_wcd_event(wcd938x->handle,
  1042. WCD_BOLERO_EVT_RX_MUTE,
  1043. (WCD_RX1 << 0x10));
  1044. wcd_enable_irq(&wcd938x->irq_info,
  1045. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1046. }
  1047. break;
  1048. case SND_SOC_DAPM_PRE_PMD:
  1049. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1050. wcd_disable_irq(&wcd938x->irq_info,
  1051. WCD938X_IRQ_AUX_PDM_WD_INT);
  1052. if (wcd938x->update_wcd_event)
  1053. wcd938x->update_wcd_event(wcd938x->handle,
  1054. WCD_BOLERO_EVT_RX_MUTE,
  1055. (WCD_RX3 << 0x10 | 0x1));
  1056. } else {
  1057. wcd_disable_irq(&wcd938x->irq_info,
  1058. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1059. if (wcd938x->update_wcd_event)
  1060. wcd938x->update_wcd_event(wcd938x->handle,
  1061. WCD_BOLERO_EVT_RX_MUTE,
  1062. (WCD_RX1 << 0x10 | 0x1));
  1063. }
  1064. break;
  1065. case SND_SOC_DAPM_POST_PMD:
  1066. if (!wcd938x->comp1_enable)
  1067. snd_soc_component_update_bits(component,
  1068. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1069. /* 7 msec delay as per HW requirement */
  1070. usleep_range(7000, 7010);
  1071. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1072. snd_soc_component_update_bits(component,
  1073. WCD938X_DIGITAL_PDM_WD_CTL2,
  1074. 0x05, 0x00);
  1075. else
  1076. snd_soc_component_update_bits(component,
  1077. WCD938X_DIGITAL_PDM_WD_CTL0,
  1078. 0x17, 0x00);
  1079. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1080. WCD_CLSH_EVENT_POST_PA,
  1081. WCD_CLSH_STATE_EAR,
  1082. hph_mode);
  1083. wcd938x->flyback_cur_det_disable--;
  1084. if (wcd938x->flyback_cur_det_disable == 0)
  1085. snd_soc_component_update_bits(component,
  1086. WCD938X_FLYBACK_EN,
  1087. 0x04, 0x04);
  1088. break;
  1089. };
  1090. return ret;
  1091. }
  1092. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1093. struct snd_kcontrol *kcontrol,
  1094. int event)
  1095. {
  1096. struct snd_soc_component *component =
  1097. snd_soc_dapm_to_component(w->dapm);
  1098. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1099. int mode = wcd938x->hph_mode;
  1100. int ret = 0;
  1101. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1102. w->name, event);
  1103. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1104. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1105. wcd938x_rx_connect_port(component, CLSH,
  1106. SND_SOC_DAPM_EVENT_ON(event));
  1107. }
  1108. if (SND_SOC_DAPM_EVENT_OFF(event))
  1109. ret = swr_slvdev_datapath_control(
  1110. wcd938x->rx_swr_dev,
  1111. wcd938x->rx_swr_dev->dev_num,
  1112. false);
  1113. return ret;
  1114. }
  1115. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1116. struct snd_kcontrol *kcontrol,
  1117. int event)
  1118. {
  1119. struct snd_soc_component *component =
  1120. snd_soc_dapm_to_component(w->dapm);
  1121. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1122. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1123. w->name, event);
  1124. switch (event) {
  1125. case SND_SOC_DAPM_PRE_PMU:
  1126. wcd938x_rx_connect_port(component, HPH_L, true);
  1127. if (wcd938x->comp1_enable)
  1128. wcd938x_rx_connect_port(component, COMP_L, true);
  1129. break;
  1130. case SND_SOC_DAPM_POST_PMD:
  1131. wcd938x_rx_connect_port(component, HPH_L, false);
  1132. if (wcd938x->comp1_enable)
  1133. wcd938x_rx_connect_port(component, COMP_L, false);
  1134. wcd938x_rx_clk_disable(component);
  1135. snd_soc_component_update_bits(component,
  1136. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1137. 0x01, 0x00);
  1138. break;
  1139. };
  1140. return 0;
  1141. }
  1142. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1143. struct snd_kcontrol *kcontrol, int event)
  1144. {
  1145. struct snd_soc_component *component =
  1146. snd_soc_dapm_to_component(w->dapm);
  1147. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1148. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1149. w->name, event);
  1150. switch (event) {
  1151. case SND_SOC_DAPM_PRE_PMU:
  1152. wcd938x_rx_connect_port(component, HPH_R, true);
  1153. if (wcd938x->comp2_enable)
  1154. wcd938x_rx_connect_port(component, COMP_R, true);
  1155. break;
  1156. case SND_SOC_DAPM_POST_PMD:
  1157. wcd938x_rx_connect_port(component, HPH_R, false);
  1158. if (wcd938x->comp2_enable)
  1159. wcd938x_rx_connect_port(component, COMP_R, false);
  1160. wcd938x_rx_clk_disable(component);
  1161. snd_soc_component_update_bits(component,
  1162. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1163. 0x02, 0x00);
  1164. break;
  1165. };
  1166. return 0;
  1167. }
  1168. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1169. struct snd_kcontrol *kcontrol,
  1170. int event)
  1171. {
  1172. struct snd_soc_component *component =
  1173. snd_soc_dapm_to_component(w->dapm);
  1174. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1175. w->name, event);
  1176. switch (event) {
  1177. case SND_SOC_DAPM_PRE_PMU:
  1178. wcd938x_rx_connect_port(component, LO, true);
  1179. break;
  1180. case SND_SOC_DAPM_POST_PMD:
  1181. wcd938x_rx_connect_port(component, LO, false);
  1182. /* 6 msec delay as per HW requirement */
  1183. usleep_range(6000, 6010);
  1184. wcd938x_rx_clk_disable(component);
  1185. snd_soc_component_update_bits(component,
  1186. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1187. break;
  1188. }
  1189. return 0;
  1190. }
  1191. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1192. struct snd_kcontrol *kcontrol,
  1193. int event)
  1194. {
  1195. struct snd_soc_component *component =
  1196. snd_soc_dapm_to_component(w->dapm);
  1197. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1198. u16 dmic_clk_reg, dmic_clk_en_reg;
  1199. s32 *dmic_clk_cnt;
  1200. u8 dmic_ctl_shift = 0;
  1201. u8 dmic_clk_shift = 0;
  1202. u8 dmic_clk_mask = 0;
  1203. u16 dmic2_left_en = 0;
  1204. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1205. w->name, event);
  1206. switch (w->shift) {
  1207. case 0:
  1208. case 1:
  1209. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1210. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1211. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1212. dmic_clk_mask = 0x0F;
  1213. dmic_clk_shift = 0x00;
  1214. dmic_ctl_shift = 0x00;
  1215. break;
  1216. case 2:
  1217. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1218. case 3:
  1219. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1220. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1221. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1222. dmic_clk_mask = 0xF0;
  1223. dmic_clk_shift = 0x04;
  1224. dmic_ctl_shift = 0x01;
  1225. break;
  1226. case 4:
  1227. case 5:
  1228. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1229. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1230. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1231. dmic_clk_mask = 0x0F;
  1232. dmic_clk_shift = 0x00;
  1233. dmic_ctl_shift = 0x02;
  1234. break;
  1235. case 6:
  1236. case 7:
  1237. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1238. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1239. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1240. dmic_clk_mask = 0xF0;
  1241. dmic_clk_shift = 0x04;
  1242. dmic_ctl_shift = 0x03;
  1243. break;
  1244. default:
  1245. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1246. __func__);
  1247. return -EINVAL;
  1248. };
  1249. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1250. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1251. switch (event) {
  1252. case SND_SOC_DAPM_PRE_PMU:
  1253. snd_soc_component_update_bits(component,
  1254. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1255. (0x01 << dmic_ctl_shift), 0x00);
  1256. /* 250us sleep as per HW requirement */
  1257. usleep_range(250, 260);
  1258. if (dmic2_left_en)
  1259. snd_soc_component_update_bits(component,
  1260. dmic2_left_en, 0x80, 0x80);
  1261. /* Setting DMIC clock rate to 2.4MHz */
  1262. snd_soc_component_update_bits(component,
  1263. dmic_clk_reg, dmic_clk_mask,
  1264. (0x03 << dmic_clk_shift));
  1265. snd_soc_component_update_bits(component,
  1266. dmic_clk_en_reg, 0x08, 0x08);
  1267. /* enable clock scaling */
  1268. snd_soc_component_update_bits(component,
  1269. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1270. wcd938x_tx_connect_port(component, DMIC0 + (w->shift),
  1271. SWR_CLK_RATE_2P4MHZ, true);
  1272. break;
  1273. case SND_SOC_DAPM_POST_PMD:
  1274. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1275. false);
  1276. snd_soc_component_update_bits(component,
  1277. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1278. (0x01 << dmic_ctl_shift),
  1279. (0x01 << dmic_ctl_shift));
  1280. if (dmic2_left_en)
  1281. snd_soc_component_update_bits(component,
  1282. dmic2_left_en, 0x80, 0x00);
  1283. snd_soc_component_update_bits(component,
  1284. dmic_clk_en_reg, 0x08, 0x00);
  1285. break;
  1286. };
  1287. return 0;
  1288. }
  1289. /*
  1290. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1291. * @micb_mv: micbias in mv
  1292. *
  1293. * return register value converted
  1294. */
  1295. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1296. {
  1297. /* min micbias voltage is 1V and maximum is 2.85V */
  1298. if (micb_mv < 1000 || micb_mv > 2850) {
  1299. pr_err("%s: unsupported micbias voltage\n", __func__);
  1300. return -EINVAL;
  1301. }
  1302. return (micb_mv - 1000) / 50;
  1303. }
  1304. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1305. /*
  1306. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1307. * @component: handle to snd_soc_component *
  1308. * @req_volt: micbias voltage to be set
  1309. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1310. *
  1311. * return 0 if adjustment is success or error code in case of failure
  1312. */
  1313. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1314. int req_volt, int micb_num)
  1315. {
  1316. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1317. int cur_vout_ctl, req_vout_ctl;
  1318. int micb_reg, micb_val, micb_en;
  1319. int ret = 0;
  1320. switch (micb_num) {
  1321. case MIC_BIAS_1:
  1322. micb_reg = WCD938X_ANA_MICB1;
  1323. break;
  1324. case MIC_BIAS_2:
  1325. micb_reg = WCD938X_ANA_MICB2;
  1326. break;
  1327. case MIC_BIAS_3:
  1328. micb_reg = WCD938X_ANA_MICB3;
  1329. break;
  1330. case MIC_BIAS_4:
  1331. micb_reg = WCD938X_ANA_MICB4;
  1332. break;
  1333. default:
  1334. return -EINVAL;
  1335. }
  1336. mutex_lock(&wcd938x->micb_lock);
  1337. /*
  1338. * If requested micbias voltage is same as current micbias
  1339. * voltage, then just return. Otherwise, adjust voltage as
  1340. * per requested value. If micbias is already enabled, then
  1341. * to avoid slow micbias ramp-up or down enable pull-up
  1342. * momentarily, change the micbias value and then re-enable
  1343. * micbias.
  1344. */
  1345. micb_val = snd_soc_component_read32(component, micb_reg);
  1346. micb_en = (micb_val & 0xC0) >> 6;
  1347. cur_vout_ctl = micb_val & 0x3F;
  1348. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1349. if (req_vout_ctl < 0) {
  1350. ret = -EINVAL;
  1351. goto exit;
  1352. }
  1353. if (cur_vout_ctl == req_vout_ctl) {
  1354. ret = 0;
  1355. goto exit;
  1356. }
  1357. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1358. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1359. req_volt, micb_en);
  1360. if (micb_en == 0x1)
  1361. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1362. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1363. if (micb_en == 0x1) {
  1364. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1365. /*
  1366. * Add 2ms delay as per HW requirement after enabling
  1367. * micbias
  1368. */
  1369. usleep_range(2000, 2100);
  1370. }
  1371. exit:
  1372. mutex_unlock(&wcd938x->micb_lock);
  1373. return ret;
  1374. }
  1375. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1376. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1377. struct snd_kcontrol *kcontrol,
  1378. int event)
  1379. {
  1380. struct snd_soc_component *component =
  1381. snd_soc_dapm_to_component(w->dapm);
  1382. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1383. int ret = 0;
  1384. int bank = 0;
  1385. u8 mode = 0;
  1386. int i = 0;
  1387. int rate = 0;
  1388. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1389. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1390. switch (event) {
  1391. case SND_SOC_DAPM_PRE_PMU:
  1392. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1393. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1394. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1395. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1396. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1397. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1398. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1399. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1400. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1401. if (mode != 0) {
  1402. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1403. if (mode & (1 << i)) {
  1404. i++;
  1405. break;
  1406. }
  1407. }
  1408. }
  1409. rate = wcd938x_get_clk_rate(i);
  1410. wcd938x_set_swr_clk_rate(component, rate, bank);
  1411. }
  1412. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1413. wcd938x->tx_swr_dev->dev_num,
  1414. true);
  1415. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1416. /* Copy clk settings to active bank */
  1417. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1418. }
  1419. break;
  1420. case SND_SOC_DAPM_POST_PMD:
  1421. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1422. rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
  1423. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1424. }
  1425. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1426. wcd938x->tx_swr_dev->dev_num,
  1427. false);
  1428. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1429. wcd938x_set_swr_clk_rate(component, rate, bank);
  1430. break;
  1431. };
  1432. return ret;
  1433. }
  1434. static int wcd938x_get_adc_mode(int val)
  1435. {
  1436. int ret = 0;
  1437. switch (val) {
  1438. case ADC_MODE_INVALID:
  1439. ret = ADC_MODE_VAL_NORMAL;
  1440. break;
  1441. case ADC_MODE_HIFI:
  1442. ret = ADC_MODE_VAL_HIFI;
  1443. break;
  1444. case ADC_MODE_LO_HIF:
  1445. ret = ADC_MODE_VAL_LO_HIF;
  1446. break;
  1447. case ADC_MODE_NORMAL:
  1448. ret = ADC_MODE_VAL_NORMAL;
  1449. break;
  1450. case ADC_MODE_LP:
  1451. ret = ADC_MODE_VAL_LP;
  1452. break;
  1453. case ADC_MODE_ULP1:
  1454. ret = ADC_MODE_VAL_ULP1;
  1455. break;
  1456. case ADC_MODE_ULP2:
  1457. ret = ADC_MODE_VAL_ULP2;
  1458. break;
  1459. default:
  1460. ret = -EINVAL;
  1461. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1462. break;
  1463. }
  1464. return ret;
  1465. }
  1466. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1467. struct snd_kcontrol *kcontrol,
  1468. int event){
  1469. struct snd_soc_component *component =
  1470. snd_soc_dapm_to_component(w->dapm);
  1471. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1472. int clk_rate = 0;
  1473. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1474. w->name, event);
  1475. switch (event) {
  1476. case SND_SOC_DAPM_PRE_PMU:
  1477. snd_soc_component_update_bits(component,
  1478. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1479. snd_soc_component_update_bits(component,
  1480. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1481. set_bit(w->shift, &wcd938x->status_mask);
  1482. clk_rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift]);
  1483. /* Enable BCS for Headset mic */
  1484. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1485. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1486. if (!wcd938x->bcs_dis)
  1487. wcd938x_tx_connect_port(component, MBHC,
  1488. SWR_CLK_RATE_4P8MHZ, true);
  1489. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1490. }
  1491. wcd938x_tx_connect_port(component, ADC1 + (w->shift), clk_rate,
  1492. true);
  1493. break;
  1494. case SND_SOC_DAPM_POST_PMD:
  1495. wcd938x_tx_connect_port(component, ADC1 + (w->shift), 0, false);
  1496. if (w->shift == 1 &&
  1497. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1498. if (!wcd938x->bcs_dis)
  1499. wcd938x_tx_connect_port(component, MBHC, 0,
  1500. false);
  1501. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1502. }
  1503. snd_soc_component_update_bits(component,
  1504. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1505. clear_bit(w->shift, &wcd938x->status_mask);
  1506. break;
  1507. };
  1508. return 0;
  1509. }
  1510. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1511. bool bcs_disable)
  1512. {
  1513. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1514. if (wcd938x->update_wcd_event) {
  1515. if (bcs_disable)
  1516. wcd938x->update_wcd_event(wcd938x->handle,
  1517. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1518. else
  1519. wcd938x->update_wcd_event(wcd938x->handle,
  1520. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1521. }
  1522. }
  1523. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1524. int channel, int mode)
  1525. {
  1526. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1527. int ret = 0;
  1528. switch (channel) {
  1529. case 0:
  1530. reg = WCD938X_ANA_TX_CH2;
  1531. mask = 0x40;
  1532. break;
  1533. case 1:
  1534. reg = WCD938X_ANA_TX_CH2;
  1535. mask = 0x20;
  1536. break;
  1537. case 2:
  1538. reg = WCD938X_ANA_TX_CH4;
  1539. mask = 0x40;
  1540. break;
  1541. case 3:
  1542. reg = WCD938X_ANA_TX_CH4;
  1543. mask = 0x20;
  1544. break;
  1545. default:
  1546. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1547. ret = -EINVAL;
  1548. break;
  1549. }
  1550. if (!mode)
  1551. val = 0x00;
  1552. else
  1553. val = mask;
  1554. if (!ret)
  1555. snd_soc_component_update_bits(component, reg, mask, val);
  1556. return ret;
  1557. }
  1558. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1559. struct snd_kcontrol *kcontrol, int event)
  1560. {
  1561. struct snd_soc_component *component =
  1562. snd_soc_dapm_to_component(w->dapm);
  1563. int mode;
  1564. int ret = 0;
  1565. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1566. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1567. w->name, event);
  1568. switch (event) {
  1569. case SND_SOC_DAPM_PRE_PMU:
  1570. snd_soc_component_update_bits(component,
  1571. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1572. snd_soc_component_update_bits(component,
  1573. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1574. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1575. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1576. if (mode < 0) {
  1577. dev_info(component->dev,
  1578. "%s: invalid mode, setting to normal mode\n",
  1579. __func__);
  1580. mode = ADC_MODE_VAL_NORMAL;
  1581. }
  1582. switch (w->shift) {
  1583. case 0:
  1584. snd_soc_component_update_bits(component,
  1585. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1586. mode);
  1587. snd_soc_component_update_bits(component,
  1588. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1589. break;
  1590. case 1:
  1591. snd_soc_component_update_bits(component,
  1592. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1593. mode << 4);
  1594. snd_soc_component_update_bits(component,
  1595. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1596. break;
  1597. case 2:
  1598. snd_soc_component_update_bits(component,
  1599. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1600. mode);
  1601. snd_soc_component_update_bits(component,
  1602. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1603. break;
  1604. case 3:
  1605. snd_soc_component_update_bits(component,
  1606. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1607. mode << 4);
  1608. snd_soc_component_update_bits(component,
  1609. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1610. break;
  1611. default:
  1612. break;
  1613. }
  1614. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1615. break;
  1616. case SND_SOC_DAPM_POST_PMD:
  1617. switch (w->shift) {
  1618. case 0:
  1619. snd_soc_component_update_bits(component,
  1620. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1621. 0x00);
  1622. snd_soc_component_update_bits(component,
  1623. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1624. break;
  1625. case 1:
  1626. snd_soc_component_update_bits(component,
  1627. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1628. 0x00);
  1629. snd_soc_component_update_bits(component,
  1630. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1631. break;
  1632. case 2:
  1633. snd_soc_component_update_bits(component,
  1634. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1635. 0x00);
  1636. snd_soc_component_update_bits(component,
  1637. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1638. break;
  1639. case 3:
  1640. snd_soc_component_update_bits(component,
  1641. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1642. 0x00);
  1643. snd_soc_component_update_bits(component,
  1644. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1645. break;
  1646. default:
  1647. break;
  1648. }
  1649. snd_soc_component_update_bits(component,
  1650. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1651. break;
  1652. };
  1653. return ret;
  1654. }
  1655. int wcd938x_micbias_control(struct snd_soc_component *component,
  1656. int micb_num, int req, bool is_dapm)
  1657. {
  1658. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1659. int micb_index = micb_num - 1;
  1660. u16 micb_reg;
  1661. int pre_off_event = 0, post_off_event = 0;
  1662. int post_on_event = 0, post_dapm_off = 0;
  1663. int post_dapm_on = 0;
  1664. int ret = 0;
  1665. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1666. dev_err(component->dev,
  1667. "%s: Invalid micbias index, micb_ind:%d\n",
  1668. __func__, micb_index);
  1669. return -EINVAL;
  1670. }
  1671. if (NULL == wcd938x) {
  1672. dev_err(component->dev,
  1673. "%s: wcd938x private data is NULL\n", __func__);
  1674. return -EINVAL;
  1675. }
  1676. switch (micb_num) {
  1677. case MIC_BIAS_1:
  1678. micb_reg = WCD938X_ANA_MICB1;
  1679. break;
  1680. case MIC_BIAS_2:
  1681. micb_reg = WCD938X_ANA_MICB2;
  1682. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1683. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1684. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1685. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1686. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1687. break;
  1688. case MIC_BIAS_3:
  1689. micb_reg = WCD938X_ANA_MICB3;
  1690. break;
  1691. case MIC_BIAS_4:
  1692. micb_reg = WCD938X_ANA_MICB4;
  1693. break;
  1694. default:
  1695. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1696. __func__, micb_num);
  1697. return -EINVAL;
  1698. };
  1699. mutex_lock(&wcd938x->micb_lock);
  1700. switch (req) {
  1701. case MICB_PULLUP_ENABLE:
  1702. if (!wcd938x->dev_up) {
  1703. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1704. __func__, req);
  1705. ret = -ENODEV;
  1706. goto done;
  1707. }
  1708. wcd938x->pullup_ref[micb_index]++;
  1709. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1710. (wcd938x->micb_ref[micb_index] == 0))
  1711. snd_soc_component_update_bits(component, micb_reg,
  1712. 0xC0, 0x80);
  1713. break;
  1714. case MICB_PULLUP_DISABLE:
  1715. if (wcd938x->pullup_ref[micb_index] > 0)
  1716. wcd938x->pullup_ref[micb_index]--;
  1717. if (!wcd938x->dev_up) {
  1718. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1719. __func__, req);
  1720. ret = -ENODEV;
  1721. goto done;
  1722. }
  1723. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1724. (wcd938x->micb_ref[micb_index] == 0))
  1725. snd_soc_component_update_bits(component, micb_reg,
  1726. 0xC0, 0x00);
  1727. break;
  1728. case MICB_ENABLE:
  1729. if (!wcd938x->dev_up) {
  1730. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1731. __func__, req);
  1732. ret = -ENODEV;
  1733. goto done;
  1734. }
  1735. wcd938x->micb_ref[micb_index]++;
  1736. if (wcd938x->micb_ref[micb_index] == 1) {
  1737. snd_soc_component_update_bits(component,
  1738. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1739. snd_soc_component_update_bits(component,
  1740. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1741. snd_soc_component_update_bits(component,
  1742. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1743. snd_soc_component_update_bits(component,
  1744. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1745. snd_soc_component_update_bits(component,
  1746. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1747. snd_soc_component_update_bits(component,
  1748. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1749. snd_soc_component_update_bits(component,
  1750. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1751. snd_soc_component_update_bits(component,
  1752. micb_reg, 0xC0, 0x40);
  1753. if (post_on_event)
  1754. blocking_notifier_call_chain(
  1755. &wcd938x->mbhc->notifier,
  1756. post_on_event,
  1757. &wcd938x->mbhc->wcd_mbhc);
  1758. }
  1759. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1760. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1761. post_dapm_on,
  1762. &wcd938x->mbhc->wcd_mbhc);
  1763. break;
  1764. case MICB_DISABLE:
  1765. if (wcd938x->micb_ref[micb_index] > 0)
  1766. wcd938x->micb_ref[micb_index]--;
  1767. if (!wcd938x->dev_up) {
  1768. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1769. __func__, req);
  1770. ret = -ENODEV;
  1771. goto done;
  1772. }
  1773. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1774. (wcd938x->pullup_ref[micb_index] > 0))
  1775. snd_soc_component_update_bits(component, micb_reg,
  1776. 0xC0, 0x80);
  1777. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1778. (wcd938x->pullup_ref[micb_index] == 0)) {
  1779. if (pre_off_event && wcd938x->mbhc)
  1780. blocking_notifier_call_chain(
  1781. &wcd938x->mbhc->notifier,
  1782. pre_off_event,
  1783. &wcd938x->mbhc->wcd_mbhc);
  1784. snd_soc_component_update_bits(component, micb_reg,
  1785. 0xC0, 0x00);
  1786. if (post_off_event && wcd938x->mbhc)
  1787. blocking_notifier_call_chain(
  1788. &wcd938x->mbhc->notifier,
  1789. post_off_event,
  1790. &wcd938x->mbhc->wcd_mbhc);
  1791. }
  1792. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1793. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1794. post_dapm_off,
  1795. &wcd938x->mbhc->wcd_mbhc);
  1796. break;
  1797. };
  1798. dev_dbg(component->dev,
  1799. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1800. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1801. wcd938x->pullup_ref[micb_index]);
  1802. done:
  1803. mutex_unlock(&wcd938x->micb_lock);
  1804. return ret;
  1805. }
  1806. EXPORT_SYMBOL(wcd938x_micbias_control);
  1807. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1808. {
  1809. int ret = 0;
  1810. uint8_t devnum = 0;
  1811. int num_retry = NUM_ATTEMPTS;
  1812. do {
  1813. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1814. if (ret) {
  1815. dev_err(&swr_dev->dev,
  1816. "%s get devnum %d for dev addr %lx failed\n",
  1817. __func__, devnum, swr_dev->addr);
  1818. /* retry after 1ms */
  1819. usleep_range(1000, 1010);
  1820. }
  1821. } while (ret && --num_retry);
  1822. swr_dev->dev_num = devnum;
  1823. return 0;
  1824. }
  1825. static int wcd938x_event_notify(struct notifier_block *block,
  1826. unsigned long val,
  1827. void *data)
  1828. {
  1829. u16 event = (val & 0xffff);
  1830. int ret = 0;
  1831. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1832. struct snd_soc_component *component = wcd938x->component;
  1833. struct wcd_mbhc *mbhc;
  1834. switch (event) {
  1835. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1836. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1837. snd_soc_component_update_bits(component,
  1838. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1839. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1840. }
  1841. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1842. snd_soc_component_update_bits(component,
  1843. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1844. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1845. }
  1846. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1847. snd_soc_component_update_bits(component,
  1848. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1849. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1850. }
  1851. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1852. snd_soc_component_update_bits(component,
  1853. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1854. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1855. }
  1856. break;
  1857. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1858. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1859. 0xC0, 0x00);
  1860. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1861. 0x80, 0x00);
  1862. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1863. 0x80, 0x00);
  1864. break;
  1865. case BOLERO_WCD_EVT_SSR_DOWN:
  1866. wcd938x->dev_up = false;
  1867. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1868. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1869. wcd938x_reset_low(wcd938x->dev);
  1870. break;
  1871. case BOLERO_WCD_EVT_SSR_UP:
  1872. wcd938x_reset(wcd938x->dev);
  1873. /* allow reset to take effect */
  1874. usleep_range(10000, 10010);
  1875. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1876. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1877. wcd938x_init_reg(component);
  1878. regcache_mark_dirty(wcd938x->regmap);
  1879. regcache_sync(wcd938x->regmap);
  1880. /* Initialize MBHC module */
  1881. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1882. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1883. if (ret) {
  1884. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1885. __func__);
  1886. } else {
  1887. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1888. }
  1889. wcd938x->dev_up = true;
  1890. break;
  1891. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1892. snd_soc_component_update_bits(component,
  1893. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1894. ((val >> 0x10) << 0x01));
  1895. break;
  1896. default:
  1897. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1898. break;
  1899. }
  1900. return 0;
  1901. }
  1902. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1903. int event)
  1904. {
  1905. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1906. int micb_num;
  1907. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1908. __func__, w->name, event);
  1909. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1910. micb_num = MIC_BIAS_1;
  1911. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1912. micb_num = MIC_BIAS_2;
  1913. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1914. micb_num = MIC_BIAS_3;
  1915. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1916. micb_num = MIC_BIAS_4;
  1917. else
  1918. return -EINVAL;
  1919. switch (event) {
  1920. case SND_SOC_DAPM_PRE_PMU:
  1921. wcd938x_micbias_control(component, micb_num,
  1922. MICB_ENABLE, true);
  1923. break;
  1924. case SND_SOC_DAPM_POST_PMU:
  1925. /* 1 msec delay as per HW requirement */
  1926. usleep_range(1000, 1100);
  1927. break;
  1928. case SND_SOC_DAPM_POST_PMD:
  1929. wcd938x_micbias_control(component, micb_num,
  1930. MICB_DISABLE, true);
  1931. break;
  1932. };
  1933. return 0;
  1934. }
  1935. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1936. struct snd_kcontrol *kcontrol,
  1937. int event)
  1938. {
  1939. return __wcd938x_codec_enable_micbias(w, event);
  1940. }
  1941. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1942. int event)
  1943. {
  1944. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1945. int micb_num;
  1946. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1947. __func__, w->name, event);
  1948. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1949. micb_num = MIC_BIAS_1;
  1950. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1951. micb_num = MIC_BIAS_2;
  1952. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1953. micb_num = MIC_BIAS_3;
  1954. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1955. micb_num = MIC_BIAS_4;
  1956. else
  1957. return -EINVAL;
  1958. switch (event) {
  1959. case SND_SOC_DAPM_PRE_PMU:
  1960. wcd938x_micbias_control(component, micb_num,
  1961. MICB_PULLUP_ENABLE, true);
  1962. break;
  1963. case SND_SOC_DAPM_POST_PMU:
  1964. /* 1 msec delay as per HW requirement */
  1965. usleep_range(1000, 1100);
  1966. break;
  1967. case SND_SOC_DAPM_POST_PMD:
  1968. wcd938x_micbias_control(component, micb_num,
  1969. MICB_PULLUP_DISABLE, true);
  1970. break;
  1971. };
  1972. return 0;
  1973. }
  1974. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1975. struct snd_kcontrol *kcontrol,
  1976. int event)
  1977. {
  1978. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1979. }
  1980. static int wcd938x_wakeup(void *handle, bool enable)
  1981. {
  1982. struct wcd938x_priv *priv;
  1983. int ret = 0;
  1984. if (!handle) {
  1985. pr_err("%s: NULL handle\n", __func__);
  1986. return -EINVAL;
  1987. }
  1988. priv = (struct wcd938x_priv *)handle;
  1989. if (!priv->tx_swr_dev) {
  1990. pr_err("%s: tx swr dev is NULL\n", __func__);
  1991. return -EINVAL;
  1992. }
  1993. mutex_lock(&priv->wakeup_lock);
  1994. if (enable)
  1995. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  1996. else
  1997. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  1998. mutex_unlock(&priv->wakeup_lock);
  1999. return ret;
  2000. }
  2001. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2002. struct snd_kcontrol *kcontrol,
  2003. int event)
  2004. {
  2005. int ret = 0;
  2006. struct snd_soc_component *component =
  2007. snd_soc_dapm_to_component(w->dapm);
  2008. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2009. switch (event) {
  2010. case SND_SOC_DAPM_PRE_PMU:
  2011. wcd938x_wakeup(wcd938x, true);
  2012. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2013. wcd938x_wakeup(wcd938x, false);
  2014. break;
  2015. case SND_SOC_DAPM_POST_PMD:
  2016. wcd938x_wakeup(wcd938x, true);
  2017. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2018. wcd938x_wakeup(wcd938x, false);
  2019. break;
  2020. }
  2021. return ret;
  2022. }
  2023. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2024. int micb_num, int req)
  2025. {
  2026. int micb_index = micb_num - 1;
  2027. u16 micb_reg;
  2028. if (NULL == wcd938x) {
  2029. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2030. return -EINVAL;
  2031. }
  2032. switch (micb_num) {
  2033. case MIC_BIAS_1:
  2034. micb_reg = WCD938X_ANA_MICB1;
  2035. break;
  2036. case MIC_BIAS_2:
  2037. micb_reg = WCD938X_ANA_MICB2;
  2038. break;
  2039. case MIC_BIAS_3:
  2040. micb_reg = WCD938X_ANA_MICB3;
  2041. break;
  2042. case MIC_BIAS_4:
  2043. micb_reg = WCD938X_ANA_MICB4;
  2044. break;
  2045. default:
  2046. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2047. return -EINVAL;
  2048. };
  2049. mutex_lock(&wcd938x->micb_lock);
  2050. switch (req) {
  2051. case MICB_ENABLE:
  2052. wcd938x->micb_ref[micb_index]++;
  2053. if (wcd938x->micb_ref[micb_index] == 1) {
  2054. regmap_update_bits(wcd938x->regmap,
  2055. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2056. regmap_update_bits(wcd938x->regmap,
  2057. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2058. regmap_update_bits(wcd938x->regmap,
  2059. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2060. regmap_update_bits(wcd938x->regmap,
  2061. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2062. regmap_update_bits(wcd938x->regmap,
  2063. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2064. regmap_update_bits(wcd938x->regmap,
  2065. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2066. regmap_update_bits(wcd938x->regmap,
  2067. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2068. regmap_update_bits(wcd938x->regmap,
  2069. micb_reg, 0xC0, 0x40);
  2070. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2071. }
  2072. break;
  2073. case MICB_PULLUP_ENABLE:
  2074. wcd938x->pullup_ref[micb_index]++;
  2075. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2076. (wcd938x->micb_ref[micb_index] == 0))
  2077. regmap_update_bits(wcd938x->regmap, micb_reg,
  2078. 0xC0, 0x80);
  2079. break;
  2080. case MICB_PULLUP_DISABLE:
  2081. if (wcd938x->pullup_ref[micb_index] > 0)
  2082. wcd938x->pullup_ref[micb_index]--;
  2083. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2084. (wcd938x->micb_ref[micb_index] == 0))
  2085. regmap_update_bits(wcd938x->regmap, micb_reg,
  2086. 0xC0, 0x00);
  2087. break;
  2088. case MICB_DISABLE:
  2089. if (wcd938x->micb_ref[micb_index] > 0)
  2090. wcd938x->micb_ref[micb_index]--;
  2091. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2092. (wcd938x->pullup_ref[micb_index] > 0))
  2093. regmap_update_bits(wcd938x->regmap, micb_reg,
  2094. 0xC0, 0x80);
  2095. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2096. (wcd938x->pullup_ref[micb_index] == 0))
  2097. regmap_update_bits(wcd938x->regmap, micb_reg,
  2098. 0xC0, 0x00);
  2099. break;
  2100. };
  2101. mutex_unlock(&wcd938x->micb_lock);
  2102. return 0;
  2103. }
  2104. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2105. int event, int micb_num)
  2106. {
  2107. struct wcd938x_priv *wcd938x_priv = NULL;
  2108. if(NULL == component) {
  2109. pr_err("%s: wcd938x component is NULL\n", __func__);
  2110. return -EINVAL;
  2111. }
  2112. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2113. pr_err("%s: invalid event: %d\n", __func__, event);
  2114. return -EINVAL;
  2115. }
  2116. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2117. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2118. return -EINVAL;
  2119. }
  2120. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2121. switch (event) {
  2122. case SND_SOC_DAPM_PRE_PMU:
  2123. wcd938x_wakeup(wcd938x_priv, true);
  2124. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2125. wcd938x_wakeup(wcd938x_priv, false);
  2126. break;
  2127. case SND_SOC_DAPM_POST_PMD:
  2128. wcd938x_wakeup(wcd938x_priv, true);
  2129. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2130. wcd938x_wakeup(wcd938x_priv, false);
  2131. break;
  2132. }
  2133. return 0;
  2134. }
  2135. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2136. static inline int wcd938x_tx_path_get(const char *wname,
  2137. unsigned int *path_num)
  2138. {
  2139. int ret = 0;
  2140. char *widget_name = NULL;
  2141. char *w_name = NULL;
  2142. char *path_num_char = NULL;
  2143. char *path_name = NULL;
  2144. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2145. if (!widget_name)
  2146. return -EINVAL;
  2147. w_name = widget_name;
  2148. path_name = strsep(&widget_name, " ");
  2149. if (!path_name) {
  2150. pr_err("%s: Invalid widget name = %s\n",
  2151. __func__, widget_name);
  2152. ret = -EINVAL;
  2153. goto err;
  2154. }
  2155. path_num_char = strpbrk(path_name, "0123");
  2156. if (!path_num_char) {
  2157. pr_err("%s: tx path index not found\n",
  2158. __func__);
  2159. ret = -EINVAL;
  2160. goto err;
  2161. }
  2162. ret = kstrtouint(path_num_char, 10, path_num);
  2163. if (ret < 0)
  2164. pr_err("%s: Invalid tx path = %s\n",
  2165. __func__, w_name);
  2166. err:
  2167. kfree(w_name);
  2168. return ret;
  2169. }
  2170. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2171. struct snd_ctl_elem_value *ucontrol)
  2172. {
  2173. struct snd_soc_component *component =
  2174. snd_soc_kcontrol_component(kcontrol);
  2175. struct wcd938x_priv *wcd938x = NULL;
  2176. int ret = 0;
  2177. unsigned int path = 0;
  2178. if (!component)
  2179. return -EINVAL;
  2180. wcd938x = snd_soc_component_get_drvdata(component);
  2181. if (!wcd938x)
  2182. return -EINVAL;
  2183. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2184. if (ret < 0)
  2185. return ret;
  2186. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2187. return 0;
  2188. }
  2189. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2190. struct snd_ctl_elem_value *ucontrol)
  2191. {
  2192. struct snd_soc_component *component =
  2193. snd_soc_kcontrol_component(kcontrol);
  2194. struct wcd938x_priv *wcd938x = NULL;
  2195. u32 mode_val;
  2196. unsigned int path = 0;
  2197. int ret = 0;
  2198. if (!component)
  2199. return -EINVAL;
  2200. wcd938x = snd_soc_component_get_drvdata(component);
  2201. if (!wcd938x)
  2202. return -EINVAL;
  2203. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2204. if (ret)
  2205. return ret;
  2206. mode_val = ucontrol->value.enumerated.item[0];
  2207. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2208. wcd938x->tx_mode[path] = mode_val;
  2209. return 0;
  2210. }
  2211. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2212. struct snd_ctl_elem_value *ucontrol)
  2213. {
  2214. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2215. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2216. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2217. return 0;
  2218. }
  2219. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2220. struct snd_ctl_elem_value *ucontrol)
  2221. {
  2222. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2223. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2224. u32 mode_val;
  2225. mode_val = ucontrol->value.enumerated.item[0];
  2226. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2227. if (wcd938x->variant == WCD9380) {
  2228. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2229. dev_info(component->dev,
  2230. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2231. __func__);
  2232. mode_val = CLS_H_ULP;
  2233. }
  2234. }
  2235. if (mode_val == CLS_H_NORMAL) {
  2236. dev_info(component->dev,
  2237. "%s:Invalid HPH Mode, default to class_AB\n",
  2238. __func__);
  2239. mode_val = CLS_H_ULP;
  2240. }
  2241. wcd938x->hph_mode = mode_val;
  2242. return 0;
  2243. }
  2244. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2245. struct snd_ctl_elem_value *ucontrol)
  2246. {
  2247. u8 ear_pa_gain = 0;
  2248. struct snd_soc_component *component =
  2249. snd_soc_kcontrol_component(kcontrol);
  2250. ear_pa_gain = snd_soc_component_read32(component,
  2251. WCD938X_ANA_EAR_COMPANDER_CTL);
  2252. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2253. ucontrol->value.integer.value[0] = ear_pa_gain;
  2254. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2255. ear_pa_gain);
  2256. return 0;
  2257. }
  2258. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2259. struct snd_ctl_elem_value *ucontrol)
  2260. {
  2261. u8 ear_pa_gain = 0;
  2262. struct snd_soc_component *component =
  2263. snd_soc_kcontrol_component(kcontrol);
  2264. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2265. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2266. __func__, ucontrol->value.integer.value[0]);
  2267. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2268. if (!wcd938x->comp1_enable) {
  2269. snd_soc_component_update_bits(component,
  2270. WCD938X_ANA_EAR_COMPANDER_CTL,
  2271. 0x7C, ear_pa_gain);
  2272. }
  2273. return 0;
  2274. }
  2275. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2276. struct snd_ctl_elem_value *ucontrol)
  2277. {
  2278. struct snd_soc_component *component =
  2279. snd_soc_kcontrol_component(kcontrol);
  2280. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2281. bool hphr;
  2282. struct soc_multi_mixer_control *mc;
  2283. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2284. hphr = mc->shift;
  2285. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2286. wcd938x->comp1_enable;
  2287. return 0;
  2288. }
  2289. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2290. struct snd_ctl_elem_value *ucontrol)
  2291. {
  2292. struct snd_soc_component *component =
  2293. snd_soc_kcontrol_component(kcontrol);
  2294. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2295. int value = ucontrol->value.integer.value[0];
  2296. bool hphr;
  2297. struct soc_multi_mixer_control *mc;
  2298. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2299. hphr = mc->shift;
  2300. if (hphr)
  2301. wcd938x->comp2_enable = value;
  2302. else
  2303. wcd938x->comp1_enable = value;
  2304. return 0;
  2305. }
  2306. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2307. struct snd_ctl_elem_value *ucontrol)
  2308. {
  2309. struct snd_soc_component *component =
  2310. snd_soc_kcontrol_component(kcontrol);
  2311. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2312. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2313. return 0;
  2314. }
  2315. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2316. struct snd_ctl_elem_value *ucontrol)
  2317. {
  2318. struct snd_soc_component *component =
  2319. snd_soc_kcontrol_component(kcontrol);
  2320. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2321. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2322. return 0;
  2323. }
  2324. const char * const tx_master_ch_text[] = {
  2325. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2326. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2327. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2328. "SWRM_PCM_IN",
  2329. };
  2330. const struct soc_enum tx_master_ch_enum =
  2331. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2332. tx_master_ch_text);
  2333. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2334. {
  2335. u8 ch_type = 0;
  2336. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2337. ch_type = ADC1;
  2338. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2339. ch_type = ADC2;
  2340. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2341. ch_type = ADC3;
  2342. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2343. ch_type = ADC4;
  2344. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2345. ch_type = DMIC0;
  2346. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2347. ch_type = DMIC1;
  2348. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2349. ch_type = MBHC;
  2350. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2351. ch_type = DMIC2;
  2352. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2353. ch_type = DMIC3;
  2354. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2355. ch_type = DMIC4;
  2356. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2357. ch_type = DMIC5;
  2358. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2359. ch_type = DMIC6;
  2360. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2361. ch_type = DMIC7;
  2362. else
  2363. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2364. if (ch_type)
  2365. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2366. else
  2367. *ch_idx = -EINVAL;
  2368. }
  2369. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2370. struct snd_ctl_elem_value *ucontrol)
  2371. {
  2372. struct snd_soc_component *component =
  2373. snd_soc_kcontrol_component(kcontrol);
  2374. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2375. int slave_ch_idx;
  2376. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2377. if (slave_ch_idx != -EINVAL)
  2378. ucontrol->value.integer.value[0] =
  2379. wcd938x_slave_get_master_ch_val(
  2380. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2381. return 0;
  2382. }
  2383. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2384. struct snd_ctl_elem_value *ucontrol)
  2385. {
  2386. struct snd_soc_component *component =
  2387. snd_soc_kcontrol_component(kcontrol);
  2388. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2389. int slave_ch_idx;
  2390. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2391. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2392. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2393. __func__, ucontrol->value.enumerated.item[0]);
  2394. if (slave_ch_idx != -EINVAL)
  2395. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2396. wcd938x_slave_get_master_ch(
  2397. ucontrol->value.enumerated.item[0]);
  2398. return 0;
  2399. }
  2400. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2401. struct snd_ctl_elem_value *ucontrol)
  2402. {
  2403. struct snd_soc_component *component =
  2404. snd_soc_kcontrol_component(kcontrol);
  2405. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2406. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2407. return 0;
  2408. }
  2409. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2410. struct snd_ctl_elem_value *ucontrol)
  2411. {
  2412. struct snd_soc_component *component =
  2413. snd_soc_kcontrol_component(kcontrol);
  2414. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2415. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2416. return 0;
  2417. }
  2418. static const char * const tx_mode_mux_text_wcd9380[] = {
  2419. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2420. };
  2421. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2422. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2423. tx_mode_mux_text_wcd9380);
  2424. static const char * const tx_mode_mux_text[] = {
  2425. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2426. "ADC_ULP1", "ADC_ULP2",
  2427. };
  2428. static const struct soc_enum tx_mode_mux_enum =
  2429. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2430. tx_mode_mux_text);
  2431. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2432. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2433. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2434. "CLS_AB_LOHIFI",
  2435. };
  2436. static const char * const wcd938x_ear_pa_gain_text[] = {
  2437. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2438. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2439. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2440. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2441. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2442. };
  2443. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2444. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2445. rx_hph_mode_mux_text_wcd9380);
  2446. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2447. wcd938x_ear_pa_gain_text);
  2448. static const char * const rx_hph_mode_mux_text[] = {
  2449. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2450. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2451. };
  2452. static const struct soc_enum rx_hph_mode_mux_enum =
  2453. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2454. rx_hph_mode_mux_text);
  2455. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2456. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2457. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2458. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2459. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2460. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2461. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2462. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2463. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2464. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2465. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2466. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2467. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2468. };
  2469. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2470. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2471. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2472. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2473. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2474. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2475. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2476. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2477. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2478. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2479. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2480. };
  2481. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2482. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2483. wcd938x_get_compander, wcd938x_set_compander),
  2484. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2485. wcd938x_get_compander, wcd938x_set_compander),
  2486. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2487. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2488. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2489. wcd938x_bcs_get, wcd938x_bcs_put),
  2490. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2491. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2492. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2493. analog_gain),
  2494. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2495. analog_gain),
  2496. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2497. analog_gain),
  2498. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2499. analog_gain),
  2500. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2501. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2502. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2503. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2504. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2505. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2506. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2507. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2508. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2509. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2510. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2511. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2512. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2513. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2514. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2515. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2516. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2517. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2518. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2519. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2520. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2521. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2522. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2523. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2524. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2525. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2526. };
  2527. static const struct snd_kcontrol_new adc1_switch[] = {
  2528. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2529. };
  2530. static const struct snd_kcontrol_new adc2_switch[] = {
  2531. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2532. };
  2533. static const struct snd_kcontrol_new adc3_switch[] = {
  2534. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2535. };
  2536. static const struct snd_kcontrol_new adc4_switch[] = {
  2537. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2538. };
  2539. static const struct snd_kcontrol_new dmic1_switch[] = {
  2540. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2541. };
  2542. static const struct snd_kcontrol_new dmic2_switch[] = {
  2543. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2544. };
  2545. static const struct snd_kcontrol_new dmic3_switch[] = {
  2546. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2547. };
  2548. static const struct snd_kcontrol_new dmic4_switch[] = {
  2549. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2550. };
  2551. static const struct snd_kcontrol_new dmic5_switch[] = {
  2552. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2553. };
  2554. static const struct snd_kcontrol_new dmic6_switch[] = {
  2555. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2556. };
  2557. static const struct snd_kcontrol_new dmic7_switch[] = {
  2558. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2559. };
  2560. static const struct snd_kcontrol_new dmic8_switch[] = {
  2561. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2562. };
  2563. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2564. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2565. };
  2566. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2567. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2568. };
  2569. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2570. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2571. };
  2572. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2573. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2574. };
  2575. static const char * const adc2_mux_text[] = {
  2576. "INP2", "INP3"
  2577. };
  2578. static const struct soc_enum adc2_enum =
  2579. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2580. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2581. static const struct snd_kcontrol_new tx_adc2_mux =
  2582. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2583. static const char * const adc3_mux_text[] = {
  2584. "INP4", "INP6"
  2585. };
  2586. static const struct soc_enum adc3_enum =
  2587. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2588. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2589. static const struct snd_kcontrol_new tx_adc3_mux =
  2590. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2591. static const char * const adc4_mux_text[] = {
  2592. "INP5", "INP7"
  2593. };
  2594. static const struct soc_enum adc4_enum =
  2595. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2596. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2597. static const struct snd_kcontrol_new tx_adc4_mux =
  2598. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2599. static const char * const rdac3_mux_text[] = {
  2600. "RX1", "RX3"
  2601. };
  2602. static const char * const hdr12_mux_text[] = {
  2603. "NO_HDR12", "HDR12"
  2604. };
  2605. static const struct soc_enum hdr12_enum =
  2606. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2607. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2608. static const struct snd_kcontrol_new tx_hdr12_mux =
  2609. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2610. static const char * const hdr34_mux_text[] = {
  2611. "NO_HDR34", "HDR34"
  2612. };
  2613. static const struct soc_enum hdr34_enum =
  2614. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2615. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2616. static const struct snd_kcontrol_new tx_hdr34_mux =
  2617. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2618. static const struct soc_enum rdac3_enum =
  2619. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2620. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2621. static const struct snd_kcontrol_new rx_rdac3_mux =
  2622. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2623. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2624. /*input widgets*/
  2625. SND_SOC_DAPM_INPUT("AMIC1"),
  2626. SND_SOC_DAPM_INPUT("AMIC2"),
  2627. SND_SOC_DAPM_INPUT("AMIC3"),
  2628. SND_SOC_DAPM_INPUT("AMIC4"),
  2629. SND_SOC_DAPM_INPUT("AMIC5"),
  2630. SND_SOC_DAPM_INPUT("AMIC6"),
  2631. SND_SOC_DAPM_INPUT("AMIC7"),
  2632. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2633. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2634. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2635. /*tx widgets*/
  2636. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2637. wcd938x_codec_enable_adc,
  2638. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2639. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2640. wcd938x_codec_enable_adc,
  2641. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2642. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2643. wcd938x_codec_enable_adc,
  2644. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2645. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2646. wcd938x_codec_enable_adc,
  2647. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2648. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2649. wcd938x_codec_enable_dmic,
  2650. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2651. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2652. wcd938x_codec_enable_dmic,
  2653. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2654. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2655. wcd938x_codec_enable_dmic,
  2656. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2657. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2658. wcd938x_codec_enable_dmic,
  2659. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2660. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2661. wcd938x_codec_enable_dmic,
  2662. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2663. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2664. wcd938x_codec_enable_dmic,
  2665. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2666. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2667. wcd938x_codec_enable_dmic,
  2668. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2669. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2670. wcd938x_codec_enable_dmic,
  2671. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2672. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2673. NULL, 0, wcd938x_enable_req,
  2674. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2675. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2676. NULL, 0, wcd938x_enable_req,
  2677. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2678. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2679. NULL, 0, wcd938x_enable_req,
  2680. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2681. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2682. NULL, 0, wcd938x_enable_req,
  2683. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2684. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2685. &tx_adc2_mux),
  2686. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2687. &tx_adc3_mux),
  2688. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2689. &tx_adc4_mux),
  2690. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2691. &tx_hdr12_mux),
  2692. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2693. &tx_hdr34_mux),
  2694. /*tx mixers*/
  2695. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2696. adc1_switch, ARRAY_SIZE(adc1_switch),
  2697. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2698. SND_SOC_DAPM_POST_PMD),
  2699. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2700. adc2_switch, ARRAY_SIZE(adc2_switch),
  2701. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2702. SND_SOC_DAPM_POST_PMD),
  2703. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2704. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2705. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2706. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2707. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2708. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2709. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2710. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2711. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2712. SND_SOC_DAPM_POST_PMD),
  2713. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2714. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2715. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2716. SND_SOC_DAPM_POST_PMD),
  2717. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2718. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2719. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2720. SND_SOC_DAPM_POST_PMD),
  2721. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2722. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2723. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2724. SND_SOC_DAPM_POST_PMD),
  2725. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2726. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2727. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2728. SND_SOC_DAPM_POST_PMD),
  2729. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2730. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2731. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2732. SND_SOC_DAPM_POST_PMD),
  2733. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2734. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2735. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2736. SND_SOC_DAPM_POST_PMD),
  2737. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2738. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2739. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2740. SND_SOC_DAPM_POST_PMD),
  2741. /* micbias widgets*/
  2742. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2743. wcd938x_codec_enable_micbias,
  2744. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2745. SND_SOC_DAPM_POST_PMD),
  2746. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2747. wcd938x_codec_enable_micbias,
  2748. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2749. SND_SOC_DAPM_POST_PMD),
  2750. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2751. wcd938x_codec_enable_micbias,
  2752. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2753. SND_SOC_DAPM_POST_PMD),
  2754. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2755. wcd938x_codec_enable_micbias,
  2756. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2757. SND_SOC_DAPM_POST_PMD),
  2758. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2759. wcd938x_codec_force_enable_micbias,
  2760. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2761. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2762. wcd938x_codec_force_enable_micbias,
  2763. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2764. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2765. wcd938x_codec_force_enable_micbias,
  2766. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2767. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2768. wcd938x_codec_force_enable_micbias,
  2769. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2770. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2771. wcd938x_enable_clsh,
  2772. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2773. /*rx widgets*/
  2774. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2775. wcd938x_codec_enable_ear_pa,
  2776. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2777. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2778. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2779. wcd938x_codec_enable_aux_pa,
  2780. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2781. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2782. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2783. wcd938x_codec_enable_hphl_pa,
  2784. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2785. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2786. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2787. wcd938x_codec_enable_hphr_pa,
  2788. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2789. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2790. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2791. wcd938x_codec_hphl_dac_event,
  2792. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2793. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2794. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2795. wcd938x_codec_hphr_dac_event,
  2796. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2797. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2798. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2799. wcd938x_codec_ear_dac_event,
  2800. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2801. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2802. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2803. wcd938x_codec_aux_dac_event,
  2804. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2805. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2806. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2807. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2808. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2809. SND_SOC_DAPM_POST_PMD),
  2810. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2811. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2812. SND_SOC_DAPM_POST_PMD),
  2813. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2814. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2815. SND_SOC_DAPM_POST_PMD),
  2816. /* rx mixer widgets*/
  2817. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2818. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2819. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2820. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2821. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2822. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2823. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2824. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2825. /*output widgets tx*/
  2826. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2827. /*output widgets rx*/
  2828. SND_SOC_DAPM_OUTPUT("EAR"),
  2829. SND_SOC_DAPM_OUTPUT("AUX"),
  2830. SND_SOC_DAPM_OUTPUT("HPHL"),
  2831. SND_SOC_DAPM_OUTPUT("HPHR"),
  2832. /* micbias pull up widgets*/
  2833. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2834. wcd938x_codec_enable_micbias_pullup,
  2835. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2836. SND_SOC_DAPM_POST_PMD),
  2837. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2838. wcd938x_codec_enable_micbias_pullup,
  2839. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2840. SND_SOC_DAPM_POST_PMD),
  2841. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2842. wcd938x_codec_enable_micbias_pullup,
  2843. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2844. SND_SOC_DAPM_POST_PMD),
  2845. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2846. wcd938x_codec_enable_micbias_pullup,
  2847. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2848. SND_SOC_DAPM_POST_PMD),
  2849. };
  2850. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2851. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2852. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2853. {"ADC1 REQ", NULL, "ADC1"},
  2854. {"ADC1", NULL, "AMIC1"},
  2855. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2856. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2857. {"ADC2 REQ", NULL, "ADC2"},
  2858. {"ADC2", NULL, "HDR12 MUX"},
  2859. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2860. {"HDR12 MUX", "HDR12", "AMIC1"},
  2861. {"ADC2 MUX", "INP3", "AMIC3"},
  2862. {"ADC2 MUX", "INP2", "AMIC2"},
  2863. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2864. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2865. {"ADC3 REQ", NULL, "ADC3"},
  2866. {"ADC3", NULL, "HDR34 MUX"},
  2867. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2868. {"HDR34 MUX", "HDR34", "AMIC5"},
  2869. {"ADC3 MUX", "INP4", "AMIC4"},
  2870. {"ADC3 MUX", "INP6", "AMIC6"},
  2871. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  2872. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2873. {"ADC4 REQ", NULL, "ADC4"},
  2874. {"ADC4", NULL, "ADC4 MUX"},
  2875. {"ADC4 MUX", "INP5", "AMIC5"},
  2876. {"ADC4 MUX", "INP7", "AMIC7"},
  2877. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2878. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2879. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2880. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2881. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2882. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2883. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2884. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2885. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2886. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2887. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2888. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2889. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  2890. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2891. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  2892. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2893. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2894. {"RX1", NULL, "IN1_HPHL"},
  2895. {"RDAC1", NULL, "RX1"},
  2896. {"HPHL_RDAC", "Switch", "RDAC1"},
  2897. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2898. {"HPHL", NULL, "HPHL PGA"},
  2899. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2900. {"RX2", NULL, "IN2_HPHR"},
  2901. {"RDAC2", NULL, "RX2"},
  2902. {"HPHR_RDAC", "Switch", "RDAC2"},
  2903. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2904. {"HPHR", NULL, "HPHR PGA"},
  2905. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2906. {"RX3", NULL, "IN3_AUX"},
  2907. {"RDAC4", NULL, "RX3"},
  2908. {"AUX_RDAC", "Switch", "RDAC4"},
  2909. {"AUX PGA", NULL, "AUX_RDAC"},
  2910. {"AUX", NULL, "AUX PGA"},
  2911. {"RDAC3_MUX", "RX3", "RX3"},
  2912. {"RDAC3_MUX", "RX1", "RX1"},
  2913. {"RDAC3", NULL, "RDAC3_MUX"},
  2914. {"EAR_RDAC", "Switch", "RDAC3"},
  2915. {"EAR PGA", NULL, "EAR_RDAC"},
  2916. {"EAR", NULL, "EAR PGA"},
  2917. };
  2918. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2919. void *file_private_data,
  2920. struct file *file,
  2921. char __user *buf, size_t count,
  2922. loff_t pos)
  2923. {
  2924. struct wcd938x_priv *priv;
  2925. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2926. int len = 0;
  2927. priv = (struct wcd938x_priv *) entry->private_data;
  2928. if (!priv) {
  2929. pr_err("%s: wcd938x priv is null\n", __func__);
  2930. return -EINVAL;
  2931. }
  2932. switch (priv->version) {
  2933. case WCD938X_VERSION_1_0:
  2934. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2935. break;
  2936. default:
  2937. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2938. }
  2939. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2940. }
  2941. static struct snd_info_entry_ops wcd938x_info_ops = {
  2942. .read = wcd938x_version_read,
  2943. };
  2944. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2945. void *file_private_data,
  2946. struct file *file,
  2947. char __user *buf, size_t count,
  2948. loff_t pos)
  2949. {
  2950. struct wcd938x_priv *priv;
  2951. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2952. int len = 0;
  2953. priv = (struct wcd938x_priv *) entry->private_data;
  2954. if (!priv) {
  2955. pr_err("%s: wcd938x priv is null\n", __func__);
  2956. return -EINVAL;
  2957. }
  2958. switch (priv->variant) {
  2959. case WCD9380:
  2960. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2961. break;
  2962. case WCD9385:
  2963. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2964. break;
  2965. default:
  2966. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2967. }
  2968. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2969. }
  2970. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2971. .read = wcd938x_variant_read,
  2972. };
  2973. /*
  2974. * wcd938x_get_codec_variant
  2975. * @component: component instance
  2976. *
  2977. * Return: codec variant or -EINVAL in error.
  2978. */
  2979. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  2980. {
  2981. struct wcd938x_priv *priv = NULL;
  2982. if (!component)
  2983. return -EINVAL;
  2984. priv = snd_soc_component_get_drvdata(component);
  2985. if (!priv) {
  2986. dev_err(component->dev,
  2987. "%s:wcd938x not probed\n", __func__);
  2988. return 0;
  2989. }
  2990. return priv->variant;
  2991. }
  2992. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  2993. /*
  2994. * wcd938x_info_create_codec_entry - creates wcd938x module
  2995. * @codec_root: The parent directory
  2996. * @component: component instance
  2997. *
  2998. * Creates wcd938x module, variant and version entry under the given
  2999. * parent directory.
  3000. *
  3001. * Return: 0 on success or negative error code on failure.
  3002. */
  3003. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3004. struct snd_soc_component *component)
  3005. {
  3006. struct snd_info_entry *version_entry;
  3007. struct snd_info_entry *variant_entry;
  3008. struct wcd938x_priv *priv;
  3009. struct snd_soc_card *card;
  3010. if (!codec_root || !component)
  3011. return -EINVAL;
  3012. priv = snd_soc_component_get_drvdata(component);
  3013. if (priv->entry) {
  3014. dev_dbg(priv->dev,
  3015. "%s:wcd938x module already created\n", __func__);
  3016. return 0;
  3017. }
  3018. card = component->card;
  3019. priv->entry = snd_info_create_module_entry(codec_root->module,
  3020. "wcd938x", codec_root);
  3021. if (!priv->entry) {
  3022. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3023. __func__);
  3024. return -ENOMEM;
  3025. }
  3026. priv->entry->mode = S_IFDIR | 0555;
  3027. if (snd_info_register(priv->entry) < 0) {
  3028. snd_info_free_entry(priv->entry);
  3029. return -ENOMEM;
  3030. }
  3031. version_entry = snd_info_create_card_entry(card->snd_card,
  3032. "version",
  3033. priv->entry);
  3034. if (!version_entry) {
  3035. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3036. __func__);
  3037. snd_info_free_entry(priv->entry);
  3038. return -ENOMEM;
  3039. }
  3040. version_entry->private_data = priv;
  3041. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3042. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3043. version_entry->c.ops = &wcd938x_info_ops;
  3044. if (snd_info_register(version_entry) < 0) {
  3045. snd_info_free_entry(version_entry);
  3046. snd_info_free_entry(priv->entry);
  3047. return -ENOMEM;
  3048. }
  3049. priv->version_entry = version_entry;
  3050. variant_entry = snd_info_create_card_entry(card->snd_card,
  3051. "variant",
  3052. priv->entry);
  3053. if (!variant_entry) {
  3054. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3055. __func__);
  3056. snd_info_free_entry(version_entry);
  3057. snd_info_free_entry(priv->entry);
  3058. return -ENOMEM;
  3059. }
  3060. variant_entry->private_data = priv;
  3061. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3062. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3063. variant_entry->c.ops = &wcd938x_variant_ops;
  3064. if (snd_info_register(variant_entry) < 0) {
  3065. snd_info_free_entry(variant_entry);
  3066. snd_info_free_entry(version_entry);
  3067. snd_info_free_entry(priv->entry);
  3068. return -ENOMEM;
  3069. }
  3070. priv->variant_entry = variant_entry;
  3071. return 0;
  3072. }
  3073. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3074. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3075. struct wcd938x_pdata *pdata)
  3076. {
  3077. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3078. int rc = 0;
  3079. if (!pdata) {
  3080. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3081. return -ENODEV;
  3082. }
  3083. /* set micbias voltage */
  3084. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3085. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3086. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3087. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3088. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3089. vout_ctl_4 < 0) {
  3090. rc = -EINVAL;
  3091. goto done;
  3092. }
  3093. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3094. vout_ctl_1);
  3095. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3096. vout_ctl_2);
  3097. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3098. vout_ctl_3);
  3099. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3100. vout_ctl_4);
  3101. done:
  3102. return rc;
  3103. }
  3104. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3105. {
  3106. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3107. struct snd_soc_dapm_context *dapm =
  3108. snd_soc_component_get_dapm(component);
  3109. int variant;
  3110. int ret = -EINVAL;
  3111. dev_info(component->dev, "%s()\n", __func__);
  3112. wcd938x = snd_soc_component_get_drvdata(component);
  3113. if (!wcd938x)
  3114. return -EINVAL;
  3115. wcd938x->component = component;
  3116. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3117. variant = (snd_soc_component_read32(component,
  3118. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3119. wcd938x->variant = variant;
  3120. wcd938x->fw_data = devm_kzalloc(component->dev,
  3121. sizeof(*(wcd938x->fw_data)),
  3122. GFP_KERNEL);
  3123. if (!wcd938x->fw_data) {
  3124. dev_err(component->dev, "Failed to allocate fw_data\n");
  3125. ret = -ENOMEM;
  3126. goto err;
  3127. }
  3128. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3129. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3130. WCD9XXX_CODEC_HWDEP_NODE, component);
  3131. if (ret < 0) {
  3132. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3133. goto err_hwdep;
  3134. }
  3135. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3136. if (ret) {
  3137. pr_err("%s: mbhc initialization failed\n", __func__);
  3138. goto err_hwdep;
  3139. }
  3140. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3141. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3142. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3143. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3144. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3145. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3146. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3147. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3148. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3149. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3150. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3151. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3152. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3153. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3154. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3155. snd_soc_dapm_sync(dapm);
  3156. wcd_cls_h_init(&wcd938x->clsh_info);
  3157. wcd938x_init_reg(component);
  3158. if (wcd938x->variant == WCD9380) {
  3159. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3160. ARRAY_SIZE(wcd9380_snd_controls));
  3161. if (ret < 0) {
  3162. dev_err(component->dev,
  3163. "%s: Failed to add snd ctrls for variant: %d\n",
  3164. __func__, wcd938x->variant);
  3165. goto err_hwdep;
  3166. }
  3167. }
  3168. if (wcd938x->variant == WCD9385) {
  3169. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3170. ARRAY_SIZE(wcd9385_snd_controls));
  3171. if (ret < 0) {
  3172. dev_err(component->dev,
  3173. "%s: Failed to add snd ctrls for variant: %d\n",
  3174. __func__, wcd938x->variant);
  3175. goto err_hwdep;
  3176. }
  3177. }
  3178. wcd938x->version = WCD938X_VERSION_1_0;
  3179. /* Register event notifier */
  3180. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3181. if (wcd938x->register_notifier) {
  3182. ret = wcd938x->register_notifier(wcd938x->handle,
  3183. &wcd938x->nblock,
  3184. true);
  3185. if (ret) {
  3186. dev_err(component->dev,
  3187. "%s: Failed to register notifier %d\n",
  3188. __func__, ret);
  3189. return ret;
  3190. }
  3191. }
  3192. wcd938x->dev_up = true;
  3193. return ret;
  3194. err_hwdep:
  3195. wcd938x->fw_data = NULL;
  3196. err:
  3197. return ret;
  3198. }
  3199. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3200. {
  3201. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3202. if (!wcd938x) {
  3203. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3204. __func__);
  3205. return;
  3206. }
  3207. if (wcd938x->register_notifier)
  3208. wcd938x->register_notifier(wcd938x->handle,
  3209. &wcd938x->nblock,
  3210. false);
  3211. }
  3212. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3213. .name = WCD938X_DRV_NAME,
  3214. .probe = wcd938x_soc_codec_probe,
  3215. .remove = wcd938x_soc_codec_remove,
  3216. .controls = wcd938x_snd_controls,
  3217. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3218. .dapm_widgets = wcd938x_dapm_widgets,
  3219. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3220. .dapm_routes = wcd938x_audio_map,
  3221. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3222. };
  3223. static int wcd938x_reset(struct device *dev)
  3224. {
  3225. struct wcd938x_priv *wcd938x = NULL;
  3226. int rc = 0;
  3227. int value = 0;
  3228. if (!dev)
  3229. return -ENODEV;
  3230. wcd938x = dev_get_drvdata(dev);
  3231. if (!wcd938x)
  3232. return -EINVAL;
  3233. if (!wcd938x->rst_np) {
  3234. dev_err(dev, "%s: reset gpio device node not specified\n",
  3235. __func__);
  3236. return -EINVAL;
  3237. }
  3238. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3239. if (value > 0)
  3240. return 0;
  3241. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3242. if (rc) {
  3243. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3244. __func__);
  3245. return rc;
  3246. }
  3247. /* 20us sleep required after pulling the reset gpio to LOW */
  3248. usleep_range(20, 30);
  3249. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3250. if (rc) {
  3251. dev_err(dev, "%s: wcd active state request fail!\n",
  3252. __func__);
  3253. return rc;
  3254. }
  3255. /* 20us sleep required after pulling the reset gpio to HIGH */
  3256. usleep_range(20, 30);
  3257. return rc;
  3258. }
  3259. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3260. u32 *val)
  3261. {
  3262. int rc = 0;
  3263. rc = of_property_read_u32(dev->of_node, name, val);
  3264. if (rc)
  3265. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3266. __func__, name, dev->of_node->full_name);
  3267. return rc;
  3268. }
  3269. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3270. struct wcd938x_micbias_setting *mb)
  3271. {
  3272. u32 prop_val = 0;
  3273. int rc = 0;
  3274. /* MB1 */
  3275. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3276. NULL)) {
  3277. rc = wcd938x_read_of_property_u32(dev,
  3278. "qcom,cdc-micbias1-mv",
  3279. &prop_val);
  3280. if (!rc)
  3281. mb->micb1_mv = prop_val;
  3282. } else {
  3283. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3284. __func__);
  3285. }
  3286. /* MB2 */
  3287. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3288. NULL)) {
  3289. rc = wcd938x_read_of_property_u32(dev,
  3290. "qcom,cdc-micbias2-mv",
  3291. &prop_val);
  3292. if (!rc)
  3293. mb->micb2_mv = prop_val;
  3294. } else {
  3295. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3296. __func__);
  3297. }
  3298. /* MB3 */
  3299. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3300. NULL)) {
  3301. rc = wcd938x_read_of_property_u32(dev,
  3302. "qcom,cdc-micbias3-mv",
  3303. &prop_val);
  3304. if (!rc)
  3305. mb->micb3_mv = prop_val;
  3306. } else {
  3307. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3308. __func__);
  3309. }
  3310. /* MB4 */
  3311. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3312. NULL)) {
  3313. rc = wcd938x_read_of_property_u32(dev,
  3314. "qcom,cdc-micbias4-mv",
  3315. &prop_val);
  3316. if (!rc)
  3317. mb->micb4_mv = prop_val;
  3318. } else {
  3319. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3320. __func__);
  3321. }
  3322. }
  3323. static int wcd938x_reset_low(struct device *dev)
  3324. {
  3325. struct wcd938x_priv *wcd938x = NULL;
  3326. int rc = 0;
  3327. if (!dev)
  3328. return -ENODEV;
  3329. wcd938x = dev_get_drvdata(dev);
  3330. if (!wcd938x)
  3331. return -EINVAL;
  3332. if (!wcd938x->rst_np) {
  3333. dev_err(dev, "%s: reset gpio device node not specified\n",
  3334. __func__);
  3335. return -EINVAL;
  3336. }
  3337. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3338. if (rc) {
  3339. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3340. __func__);
  3341. return rc;
  3342. }
  3343. /* 20us sleep required after pulling the reset gpio to LOW */
  3344. usleep_range(20, 30);
  3345. return rc;
  3346. }
  3347. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3348. {
  3349. struct wcd938x_pdata *pdata = NULL;
  3350. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3351. GFP_KERNEL);
  3352. if (!pdata)
  3353. return NULL;
  3354. pdata->rst_np = of_parse_phandle(dev->of_node,
  3355. "qcom,wcd-rst-gpio-node", 0);
  3356. if (!pdata->rst_np) {
  3357. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3358. __func__, "qcom,wcd-rst-gpio-node",
  3359. dev->of_node->full_name);
  3360. return NULL;
  3361. }
  3362. /* Parse power supplies */
  3363. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3364. &pdata->num_supplies);
  3365. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3366. dev_err(dev, "%s: no power supplies defined for codec\n",
  3367. __func__);
  3368. return NULL;
  3369. }
  3370. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3371. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3372. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3373. return pdata;
  3374. }
  3375. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3376. {
  3377. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3378. __func__, irq);
  3379. return IRQ_HANDLED;
  3380. }
  3381. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3382. {
  3383. .name = "wcd938x_cdc",
  3384. .playback = {
  3385. .stream_name = "WCD938X_AIF Playback",
  3386. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3387. .formats = WCD938X_FORMATS,
  3388. .rate_max = 192000,
  3389. .rate_min = 8000,
  3390. .channels_min = 1,
  3391. .channels_max = 4,
  3392. },
  3393. .capture = {
  3394. .stream_name = "WCD938X_AIF Capture",
  3395. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3396. .formats = WCD938X_FORMATS,
  3397. .rate_max = 192000,
  3398. .rate_min = 8000,
  3399. .channels_min = 1,
  3400. .channels_max = 4,
  3401. },
  3402. },
  3403. };
  3404. static int wcd938x_bind(struct device *dev)
  3405. {
  3406. int ret = 0, i = 0;
  3407. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3408. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3409. /*
  3410. * Add 5msec delay to provide sufficient time for
  3411. * soundwire auto enumeration of slave devices as
  3412. * as per HW requirement.
  3413. */
  3414. usleep_range(5000, 5010);
  3415. ret = component_bind_all(dev, wcd938x);
  3416. if (ret) {
  3417. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3418. __func__, ret);
  3419. return ret;
  3420. }
  3421. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3422. if (!wcd938x->rx_swr_dev) {
  3423. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3424. __func__);
  3425. ret = -ENODEV;
  3426. goto err;
  3427. }
  3428. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3429. if (!wcd938x->tx_swr_dev) {
  3430. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3431. __func__);
  3432. ret = -ENODEV;
  3433. goto err;
  3434. }
  3435. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3436. &wcd938x_regmap_config);
  3437. if (!wcd938x->regmap) {
  3438. dev_err(dev, "%s: Regmap init failed\n",
  3439. __func__);
  3440. goto err;
  3441. }
  3442. /* Set all interupts as edge triggered */
  3443. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3444. regmap_write(wcd938x->regmap,
  3445. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3446. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3447. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3448. wcd938x->irq_info.codec_name = "WCD938X";
  3449. wcd938x->irq_info.regmap = wcd938x->regmap;
  3450. wcd938x->irq_info.dev = dev;
  3451. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3452. if (ret) {
  3453. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3454. __func__, ret);
  3455. goto err;
  3456. }
  3457. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3458. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3459. if (ret < 0) {
  3460. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3461. goto err_irq;
  3462. }
  3463. /* Request for watchdog interrupt */
  3464. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3465. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3466. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3467. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3468. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3469. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3470. /* Disable watchdog interrupt for HPH and AUX */
  3471. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3472. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3473. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3474. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3475. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3476. if (ret) {
  3477. dev_err(dev, "%s: Codec registration failed\n",
  3478. __func__);
  3479. goto err_irq;
  3480. }
  3481. return ret;
  3482. err_irq:
  3483. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3484. err:
  3485. component_unbind_all(dev, wcd938x);
  3486. return ret;
  3487. }
  3488. static void wcd938x_unbind(struct device *dev)
  3489. {
  3490. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3491. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3492. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3493. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3494. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3495. snd_soc_unregister_component(dev);
  3496. component_unbind_all(dev, wcd938x);
  3497. }
  3498. static const struct of_device_id wcd938x_dt_match[] = {
  3499. { .compatible = "qcom,wcd938x-codec" },
  3500. {}
  3501. };
  3502. static const struct component_master_ops wcd938x_comp_ops = {
  3503. .bind = wcd938x_bind,
  3504. .unbind = wcd938x_unbind,
  3505. };
  3506. static int wcd938x_compare_of(struct device *dev, void *data)
  3507. {
  3508. return dev->of_node == data;
  3509. }
  3510. static void wcd938x_release_of(struct device *dev, void *data)
  3511. {
  3512. of_node_put(data);
  3513. }
  3514. static int wcd938x_add_slave_components(struct device *dev,
  3515. struct component_match **matchptr)
  3516. {
  3517. struct device_node *np, *rx_node, *tx_node;
  3518. np = dev->of_node;
  3519. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3520. if (!rx_node) {
  3521. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3522. return -ENODEV;
  3523. }
  3524. of_node_get(rx_node);
  3525. component_match_add_release(dev, matchptr,
  3526. wcd938x_release_of,
  3527. wcd938x_compare_of,
  3528. rx_node);
  3529. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3530. if (!tx_node) {
  3531. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3532. return -ENODEV;
  3533. }
  3534. of_node_get(tx_node);
  3535. component_match_add_release(dev, matchptr,
  3536. wcd938x_release_of,
  3537. wcd938x_compare_of,
  3538. tx_node);
  3539. return 0;
  3540. }
  3541. static int wcd938x_probe(struct platform_device *pdev)
  3542. {
  3543. struct component_match *match = NULL;
  3544. struct wcd938x_priv *wcd938x = NULL;
  3545. struct wcd938x_pdata *pdata = NULL;
  3546. struct wcd_ctrl_platform_data *plat_data = NULL;
  3547. struct device *dev = &pdev->dev;
  3548. int ret;
  3549. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3550. GFP_KERNEL);
  3551. if (!wcd938x)
  3552. return -ENOMEM;
  3553. dev_set_drvdata(dev, wcd938x);
  3554. wcd938x->dev = dev;
  3555. pdata = wcd938x_populate_dt_data(dev);
  3556. if (!pdata) {
  3557. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3558. return -EINVAL;
  3559. }
  3560. dev->platform_data = pdata;
  3561. wcd938x->rst_np = pdata->rst_np;
  3562. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3563. pdata->regulator, pdata->num_supplies);
  3564. if (!wcd938x->supplies) {
  3565. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3566. __func__);
  3567. return ret;
  3568. }
  3569. plat_data = dev_get_platdata(dev->parent);
  3570. if (!plat_data) {
  3571. dev_err(dev, "%s: platform data from parent is NULL\n",
  3572. __func__);
  3573. return -EINVAL;
  3574. }
  3575. wcd938x->handle = (void *)plat_data->handle;
  3576. if (!wcd938x->handle) {
  3577. dev_err(dev, "%s: handle is NULL\n", __func__);
  3578. return -EINVAL;
  3579. }
  3580. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3581. if (!wcd938x->update_wcd_event) {
  3582. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3583. __func__);
  3584. return -EINVAL;
  3585. }
  3586. wcd938x->register_notifier = plat_data->register_notifier;
  3587. if (!wcd938x->register_notifier) {
  3588. dev_err(dev, "%s: register_notifier api is null!\n",
  3589. __func__);
  3590. return -EINVAL;
  3591. }
  3592. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3593. pdata->regulator,
  3594. pdata->num_supplies);
  3595. if (ret) {
  3596. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3597. __func__);
  3598. return ret;
  3599. }
  3600. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3601. CODEC_RX);
  3602. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3603. CODEC_TX);
  3604. if (ret) {
  3605. dev_err(dev, "Failed to read port mapping\n");
  3606. goto err;
  3607. }
  3608. mutex_init(&wcd938x->wakeup_lock);
  3609. mutex_init(&wcd938x->micb_lock);
  3610. ret = wcd938x_add_slave_components(dev, &match);
  3611. if (ret)
  3612. goto err_lock_init;
  3613. wcd938x_reset(dev);
  3614. wcd938x->wakeup = wcd938x_wakeup;
  3615. return component_master_add_with_match(dev,
  3616. &wcd938x_comp_ops, match);
  3617. err_lock_init:
  3618. mutex_destroy(&wcd938x->micb_lock);
  3619. mutex_destroy(&wcd938x->wakeup_lock);
  3620. err:
  3621. return ret;
  3622. }
  3623. static int wcd938x_remove(struct platform_device *pdev)
  3624. {
  3625. struct wcd938x_priv *wcd938x = NULL;
  3626. wcd938x = platform_get_drvdata(pdev);
  3627. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3628. mutex_destroy(&wcd938x->micb_lock);
  3629. mutex_destroy(&wcd938x->wakeup_lock);
  3630. dev_set_drvdata(&pdev->dev, NULL);
  3631. return 0;
  3632. }
  3633. #ifdef CONFIG_PM_SLEEP
  3634. static int wcd938x_suspend(struct device *dev)
  3635. {
  3636. return 0;
  3637. }
  3638. static int wcd938x_resume(struct device *dev)
  3639. {
  3640. return 0;
  3641. }
  3642. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3643. SET_SYSTEM_SLEEP_PM_OPS(
  3644. wcd938x_suspend,
  3645. wcd938x_resume
  3646. )
  3647. };
  3648. #endif
  3649. static struct platform_driver wcd938x_codec_driver = {
  3650. .probe = wcd938x_probe,
  3651. .remove = wcd938x_remove,
  3652. .driver = {
  3653. .name = "wcd938x_codec",
  3654. .owner = THIS_MODULE,
  3655. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3656. #ifdef CONFIG_PM_SLEEP
  3657. .pm = &wcd938x_dev_pm_ops,
  3658. #endif
  3659. .suppress_bind_attrs = true,
  3660. },
  3661. };
  3662. module_platform_driver(wcd938x_codec_driver);
  3663. MODULE_DESCRIPTION("WCD938X Codec driver");
  3664. MODULE_LICENSE("GPL v2");