dp_tx.c 99 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #define DP_TX_QUEUE_MASK 0x3
  33. /* TODO Add support in TSO */
  34. #define DP_DESC_NUM_FRAG(x) 0
  35. /* disable TQM_BYPASS */
  36. #define TQM_BYPASS_WAR 0
  37. /* invalid peer id for reinject*/
  38. #define DP_INVALID_PEER 0XFFFE
  39. /*mapping between hal encrypt type and cdp_sec_type*/
  40. #define MAX_CDP_SEC_TYPE 12
  41. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  42. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  43. HAL_TX_ENCRYPT_TYPE_WEP_128,
  44. HAL_TX_ENCRYPT_TYPE_WEP_104,
  45. HAL_TX_ENCRYPT_TYPE_WEP_40,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  47. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  48. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  49. HAL_TX_ENCRYPT_TYPE_WAPI,
  50. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  52. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  53. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  54. /**
  55. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  56. * @vdev: DP Virtual device handle
  57. * @nbuf: Buffer pointer
  58. * @queue: queue ids container for nbuf
  59. *
  60. * TX packet queue has 2 instances, software descriptors id and dma ring id
  61. * Based on tx feature and hardware configuration queue id combination could be
  62. * different.
  63. * For example -
  64. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  65. * With no XPS,lock based resource protection, Descriptor pool ids are different
  66. * for each vdev, dma ring id will be same as single pdev id
  67. *
  68. * Return: None
  69. */
  70. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  71. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  72. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  73. {
  74. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  75. queue->desc_pool_id = queue_offset;
  76. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  77. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  78. "%s, pool_id:%d ring_id: %d",
  79. __func__, queue->desc_pool_id, queue->ring_id);
  80. return;
  81. }
  82. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #endif
  95. #if defined(FEATURE_TSO)
  96. /**
  97. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  98. *
  99. * @soc - core txrx main context
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  106. if (qdf_unlikely(!tx_desc->tso_desc)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO num desc is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. bool is_last_seg;
  118. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  119. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  120. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1)
  121. is_last_seg = false;
  122. else
  123. is_last_seg = true;
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_nbuf_unmap_tso_segment(soc->osdev,
  126. tx_desc->tso_desc, is_last_seg);
  127. }
  128. }
  129. /**
  130. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  131. * back to the freelist
  132. *
  133. * @soc - soc device handle
  134. * @tx_desc - Tx software descriptor
  135. */
  136. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  137. struct dp_tx_desc_s *tx_desc)
  138. {
  139. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  140. if (qdf_unlikely(!tx_desc->tso_desc)) {
  141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  142. "%s %d TSO desc is NULL!",
  143. __func__, __LINE__);
  144. qdf_assert(0);
  145. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  147. "%s %d TSO num desc is NULL!",
  148. __func__, __LINE__);
  149. qdf_assert(0);
  150. } else {
  151. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  152. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  153. /* Add the tso num segment into the free list */
  154. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  155. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  156. tx_desc->tso_num_desc);
  157. tx_desc->tso_num_desc = NULL;
  158. }
  159. /* Add the tso segment into the free list*/
  160. dp_tx_tso_desc_free(soc,
  161. tx_desc->pool_id, tx_desc->tso_desc);
  162. tx_desc->tso_desc = NULL;
  163. }
  164. }
  165. #else
  166. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  167. struct dp_tx_desc_s *tx_desc)
  168. {
  169. }
  170. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  171. struct dp_tx_desc_s *tx_desc)
  172. {
  173. }
  174. #endif
  175. /**
  176. * dp_tx_desc_release() - Release Tx Descriptor
  177. * @tx_desc : Tx Descriptor
  178. * @desc_pool_id: Descriptor Pool ID
  179. *
  180. * Deallocate all resources attached to Tx descriptor and free the Tx
  181. * descriptor.
  182. *
  183. * Return:
  184. */
  185. static void
  186. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  187. {
  188. struct dp_pdev *pdev = tx_desc->pdev;
  189. struct dp_soc *soc;
  190. uint8_t comp_status = 0;
  191. qdf_assert(pdev);
  192. soc = pdev->soc;
  193. if (tx_desc->frm_type == dp_tx_frm_tso)
  194. dp_tx_tso_desc_release(soc, tx_desc);
  195. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  196. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  197. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  198. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  199. qdf_atomic_dec(&pdev->num_tx_outstanding);
  200. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  201. qdf_atomic_dec(&pdev->num_tx_exception);
  202. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  203. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  204. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  205. else
  206. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  207. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  208. "Tx Completion Release desc %d status %d outstanding %d",
  209. tx_desc->id, comp_status,
  210. qdf_atomic_read(&pdev->num_tx_outstanding));
  211. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  212. return;
  213. }
  214. /**
  215. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  216. * @vdev: DP vdev Handle
  217. * @nbuf: skb
  218. *
  219. * Prepares and fills HTT metadata in the frame pre-header for special frames
  220. * that should be transmitted using varying transmit parameters.
  221. * There are 2 VDEV modes that currently needs this special metadata -
  222. * 1) Mesh Mode
  223. * 2) DSRC Mode
  224. *
  225. * Return: HTT metadata size
  226. *
  227. */
  228. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  229. uint32_t *meta_data)
  230. {
  231. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  232. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  233. uint8_t htt_desc_size;
  234. /* Size rounded of multiple of 8 bytes */
  235. uint8_t htt_desc_size_aligned;
  236. uint8_t *hdr = NULL;
  237. /*
  238. * Metadata - HTT MSDU Extension header
  239. */
  240. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  241. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  242. if (vdev->mesh_vdev) {
  243. /* Fill and add HTT metaheader */
  244. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  245. if (hdr == NULL) {
  246. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  247. "Error in filling HTT metadata");
  248. return 0;
  249. }
  250. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  251. } else if (vdev->opmode == wlan_op_mode_ocb) {
  252. /* Todo - Add support for DSRC */
  253. }
  254. return htt_desc_size_aligned;
  255. }
  256. /**
  257. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  258. * @tso_seg: TSO segment to process
  259. * @ext_desc: Pointer to MSDU extension descriptor
  260. *
  261. * Return: void
  262. */
  263. #if defined(FEATURE_TSO)
  264. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  265. void *ext_desc)
  266. {
  267. uint8_t num_frag;
  268. uint32_t tso_flags;
  269. /*
  270. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  271. * tcp_flag_mask
  272. *
  273. * Checksum enable flags are set in TCL descriptor and not in Extension
  274. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  275. */
  276. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  277. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  278. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  279. tso_seg->tso_flags.ip_len);
  280. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  281. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  282. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  283. uint32_t lo = 0;
  284. uint32_t hi = 0;
  285. qdf_dmaaddr_to_32s(
  286. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  287. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  288. tso_seg->tso_frags[num_frag].length);
  289. }
  290. return;
  291. }
  292. #else
  293. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  294. void *ext_desc)
  295. {
  296. return;
  297. }
  298. #endif
  299. #if defined(FEATURE_TSO)
  300. /**
  301. * dp_tx_free_tso_seg() - Loop through the tso segments
  302. * allocated and free them
  303. *
  304. * @soc: soc handle
  305. * @free_seg: list of tso segments
  306. * @msdu_info: msdu descriptor
  307. *
  308. * Return - void
  309. */
  310. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  311. struct qdf_tso_seg_elem_t *free_seg,
  312. struct dp_tx_msdu_info_s *msdu_info)
  313. {
  314. struct qdf_tso_seg_elem_t *next_seg;
  315. while (free_seg) {
  316. next_seg = free_seg->next;
  317. dp_tx_tso_desc_free(soc,
  318. msdu_info->tx_queue.desc_pool_id,
  319. free_seg);
  320. free_seg = next_seg;
  321. }
  322. }
  323. /**
  324. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  325. * allocated and free them
  326. *
  327. * @soc: soc handle
  328. * @free_seg: list of tso segments
  329. * @msdu_info: msdu descriptor
  330. * Return - void
  331. */
  332. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  333. struct qdf_tso_num_seg_elem_t *free_seg,
  334. struct dp_tx_msdu_info_s *msdu_info)
  335. {
  336. struct qdf_tso_num_seg_elem_t *next_seg;
  337. while (free_seg) {
  338. next_seg = free_seg->next;
  339. dp_tso_num_seg_free(soc,
  340. msdu_info->tx_queue.desc_pool_id,
  341. free_seg);
  342. free_seg = next_seg;
  343. }
  344. }
  345. /**
  346. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  347. * @vdev: virtual device handle
  348. * @msdu: network buffer
  349. * @msdu_info: meta data associated with the msdu
  350. *
  351. * Return: QDF_STATUS_SUCCESS success
  352. */
  353. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  354. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  355. {
  356. struct qdf_tso_seg_elem_t *tso_seg;
  357. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  358. struct dp_soc *soc = vdev->pdev->soc;
  359. struct qdf_tso_info_t *tso_info;
  360. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  361. tso_info = &msdu_info->u.tso_info;
  362. tso_info->curr_seg = NULL;
  363. tso_info->tso_seg_list = NULL;
  364. tso_info->num_segs = num_seg;
  365. msdu_info->frm_type = dp_tx_frm_tso;
  366. tso_info->tso_num_seg_list = NULL;
  367. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  368. while (num_seg) {
  369. tso_seg = dp_tx_tso_desc_alloc(
  370. soc, msdu_info->tx_queue.desc_pool_id);
  371. if (tso_seg) {
  372. tso_seg->next = tso_info->tso_seg_list;
  373. tso_info->tso_seg_list = tso_seg;
  374. num_seg--;
  375. } else {
  376. struct qdf_tso_seg_elem_t *free_seg =
  377. tso_info->tso_seg_list;
  378. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  379. return QDF_STATUS_E_NOMEM;
  380. }
  381. }
  382. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  383. tso_num_seg = dp_tso_num_seg_alloc(soc,
  384. msdu_info->tx_queue.desc_pool_id);
  385. if (tso_num_seg) {
  386. tso_num_seg->next = tso_info->tso_num_seg_list;
  387. tso_info->tso_num_seg_list = tso_num_seg;
  388. } else {
  389. /* Bug: free tso_num_seg and tso_seg */
  390. /* Free the already allocated num of segments */
  391. struct qdf_tso_seg_elem_t *free_seg =
  392. tso_info->tso_seg_list;
  393. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  394. __func__);
  395. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  396. return QDF_STATUS_E_NOMEM;
  397. }
  398. msdu_info->num_seg =
  399. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  400. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  401. msdu_info->num_seg);
  402. if (!(msdu_info->num_seg)) {
  403. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  404. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  405. msdu_info);
  406. return QDF_STATUS_E_INVAL;
  407. }
  408. tso_info->curr_seg = tso_info->tso_seg_list;
  409. return QDF_STATUS_SUCCESS;
  410. }
  411. #else
  412. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  413. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  414. {
  415. return QDF_STATUS_E_NOMEM;
  416. }
  417. #endif
  418. /**
  419. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  420. * @vdev: DP Vdev handle
  421. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  422. * @desc_pool_id: Descriptor Pool ID
  423. *
  424. * Return:
  425. */
  426. static
  427. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  428. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  429. {
  430. uint8_t i;
  431. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  432. struct dp_tx_seg_info_s *seg_info;
  433. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  434. struct dp_soc *soc = vdev->pdev->soc;
  435. /* Allocate an extension descriptor */
  436. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  437. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  438. if (!msdu_ext_desc) {
  439. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  440. return NULL;
  441. }
  442. if (msdu_info->exception_fw &&
  443. qdf_unlikely(vdev->mesh_vdev)) {
  444. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  445. &msdu_info->meta_data[0],
  446. sizeof(struct htt_tx_msdu_desc_ext2_t));
  447. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  448. }
  449. switch (msdu_info->frm_type) {
  450. case dp_tx_frm_sg:
  451. case dp_tx_frm_me:
  452. case dp_tx_frm_raw:
  453. seg_info = msdu_info->u.sg_info.curr_seg;
  454. /* Update the buffer pointers in MSDU Extension Descriptor */
  455. for (i = 0; i < seg_info->frag_cnt; i++) {
  456. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  457. seg_info->frags[i].paddr_lo,
  458. seg_info->frags[i].paddr_hi,
  459. seg_info->frags[i].len);
  460. }
  461. break;
  462. case dp_tx_frm_tso:
  463. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  464. &cached_ext_desc[0]);
  465. break;
  466. default:
  467. break;
  468. }
  469. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  470. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  471. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  472. msdu_ext_desc->vaddr);
  473. return msdu_ext_desc;
  474. }
  475. /**
  476. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  477. *
  478. * @skb: skb to be traced
  479. * @msdu_id: msdu_id of the packet
  480. * @vdev_id: vdev_id of the packet
  481. *
  482. * Return: None
  483. */
  484. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  485. uint8_t vdev_id)
  486. {
  487. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  488. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  489. DPTRACE(qdf_dp_trace_ptr(skb,
  490. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  491. QDF_TRACE_DEFAULT_PDEV_ID,
  492. qdf_nbuf_data_addr(skb),
  493. sizeof(qdf_nbuf_data(skb)),
  494. msdu_id, vdev_id));
  495. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  496. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  497. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  498. msdu_id, QDF_TX));
  499. }
  500. /**
  501. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  502. * @vdev: DP vdev handle
  503. * @nbuf: skb
  504. * @desc_pool_id: Descriptor pool ID
  505. * @meta_data: Metadata to the fw
  506. * @tx_exc_metadata: Handle that holds exception path metadata
  507. * Allocate and prepare Tx descriptor with msdu information.
  508. *
  509. * Return: Pointer to Tx Descriptor on success,
  510. * NULL on failure
  511. */
  512. static
  513. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  514. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  515. struct dp_tx_msdu_info_s *msdu_info,
  516. struct cdp_tx_exception_metadata *tx_exc_metadata)
  517. {
  518. uint8_t align_pad;
  519. uint8_t is_exception = 0;
  520. uint8_t htt_hdr_size;
  521. struct ether_header *eh;
  522. struct dp_tx_desc_s *tx_desc;
  523. struct dp_pdev *pdev = vdev->pdev;
  524. struct dp_soc *soc = pdev->soc;
  525. /* Allocate software Tx descriptor */
  526. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  527. if (qdf_unlikely(!tx_desc)) {
  528. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  529. return NULL;
  530. }
  531. /* Flow control/Congestion Control counters */
  532. qdf_atomic_inc(&pdev->num_tx_outstanding);
  533. /* Initialize the SW tx descriptor */
  534. tx_desc->nbuf = nbuf;
  535. tx_desc->frm_type = dp_tx_frm_std;
  536. tx_desc->tx_encap_type = (tx_exc_metadata ?
  537. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  538. tx_desc->vdev = vdev;
  539. tx_desc->pdev = pdev;
  540. tx_desc->msdu_ext_desc = NULL;
  541. tx_desc->pkt_offset = 0;
  542. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  543. /* Reset the control block */
  544. qdf_nbuf_reset_ctxt(nbuf);
  545. /*
  546. * For special modes (vdev_type == ocb or mesh), data frames should be
  547. * transmitted using varying transmit parameters (tx spec) which include
  548. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  549. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  550. * These frames are sent as exception packets to firmware.
  551. *
  552. * HW requirement is that metadata should always point to a
  553. * 8-byte aligned address. So we add alignment pad to start of buffer.
  554. * HTT Metadata should be ensured to be multiple of 8-bytes,
  555. * to get 8-byte aligned start address along with align_pad added
  556. *
  557. * |-----------------------------|
  558. * | |
  559. * |-----------------------------| <-----Buffer Pointer Address given
  560. * | | ^ in HW descriptor (aligned)
  561. * | HTT Metadata | |
  562. * | | |
  563. * | | | Packet Offset given in descriptor
  564. * | | |
  565. * |-----------------------------| |
  566. * | Alignment Pad | v
  567. * |-----------------------------| <----- Actual buffer start address
  568. * | SKB Data | (Unaligned)
  569. * | |
  570. * | |
  571. * | |
  572. * | |
  573. * | |
  574. * |-----------------------------|
  575. */
  576. if (qdf_unlikely((msdu_info->exception_fw)) ||
  577. (vdev->opmode == wlan_op_mode_ocb)) {
  578. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  579. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  581. "qdf_nbuf_push_head failed");
  582. goto failure;
  583. }
  584. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  585. msdu_info->meta_data);
  586. if (htt_hdr_size == 0)
  587. goto failure;
  588. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  589. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  590. is_exception = 1;
  591. }
  592. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  593. qdf_nbuf_map(soc->osdev, nbuf,
  594. QDF_DMA_TO_DEVICE))) {
  595. /* Handle failure */
  596. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  597. "qdf_nbuf_map failed");
  598. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  599. goto failure;
  600. }
  601. if (qdf_unlikely(vdev->nawds_enabled)) {
  602. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  603. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  604. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  605. is_exception = 1;
  606. }
  607. }
  608. #if !TQM_BYPASS_WAR
  609. if (is_exception || tx_exc_metadata)
  610. #endif
  611. {
  612. /* Temporary WAR due to TQM VP issues */
  613. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  614. qdf_atomic_inc(&pdev->num_tx_exception);
  615. }
  616. return tx_desc;
  617. failure:
  618. dp_tx_desc_release(tx_desc, desc_pool_id);
  619. return NULL;
  620. }
  621. /**
  622. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  623. * @vdev: DP vdev handle
  624. * @nbuf: skb
  625. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  626. * @desc_pool_id : Descriptor Pool ID
  627. *
  628. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  629. * information. For frames wth fragments, allocate and prepare
  630. * an MSDU extension descriptor
  631. *
  632. * Return: Pointer to Tx Descriptor on success,
  633. * NULL on failure
  634. */
  635. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  636. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  637. uint8_t desc_pool_id)
  638. {
  639. struct dp_tx_desc_s *tx_desc;
  640. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  641. struct dp_pdev *pdev = vdev->pdev;
  642. struct dp_soc *soc = pdev->soc;
  643. /* Allocate software Tx descriptor */
  644. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  645. if (!tx_desc) {
  646. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  647. return NULL;
  648. }
  649. /* Flow control/Congestion Control counters */
  650. qdf_atomic_inc(&pdev->num_tx_outstanding);
  651. /* Initialize the SW tx descriptor */
  652. tx_desc->nbuf = nbuf;
  653. tx_desc->frm_type = msdu_info->frm_type;
  654. tx_desc->tx_encap_type = vdev->tx_encap_type;
  655. tx_desc->vdev = vdev;
  656. tx_desc->pdev = pdev;
  657. tx_desc->pkt_offset = 0;
  658. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  659. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  660. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  661. /* Reset the control block */
  662. qdf_nbuf_reset_ctxt(nbuf);
  663. /* Handle scattered frames - TSO/SG/ME */
  664. /* Allocate and prepare an extension descriptor for scattered frames */
  665. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  666. if (!msdu_ext_desc) {
  667. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  668. "%s Tx Extension Descriptor Alloc Fail",
  669. __func__);
  670. goto failure;
  671. }
  672. #if TQM_BYPASS_WAR
  673. /* Temporary WAR due to TQM VP issues */
  674. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  675. qdf_atomic_inc(&pdev->num_tx_exception);
  676. #endif
  677. if (qdf_unlikely(msdu_info->exception_fw))
  678. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  679. tx_desc->msdu_ext_desc = msdu_ext_desc;
  680. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  681. return tx_desc;
  682. failure:
  683. dp_tx_desc_release(tx_desc, desc_pool_id);
  684. return NULL;
  685. }
  686. /**
  687. * dp_tx_prepare_raw() - Prepare RAW packet TX
  688. * @vdev: DP vdev handle
  689. * @nbuf: buffer pointer
  690. * @seg_info: Pointer to Segment info Descriptor to be prepared
  691. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  692. * descriptor
  693. *
  694. * Return:
  695. */
  696. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  697. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  698. {
  699. qdf_nbuf_t curr_nbuf = NULL;
  700. uint16_t total_len = 0;
  701. qdf_dma_addr_t paddr;
  702. int32_t i;
  703. int32_t mapped_buf_num = 0;
  704. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  705. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  706. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  707. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  708. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  709. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  710. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  711. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  712. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  713. QDF_DMA_TO_DEVICE)) {
  714. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  715. "%s dma map error ", __func__);
  716. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  717. mapped_buf_num = i;
  718. goto error;
  719. }
  720. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  721. seg_info->frags[i].paddr_lo = paddr;
  722. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  723. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  724. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  725. total_len += qdf_nbuf_len(curr_nbuf);
  726. }
  727. seg_info->frag_cnt = i;
  728. seg_info->total_len = total_len;
  729. seg_info->next = NULL;
  730. sg_info->curr_seg = seg_info;
  731. msdu_info->frm_type = dp_tx_frm_raw;
  732. msdu_info->num_seg = 1;
  733. return nbuf;
  734. error:
  735. i = 0;
  736. while (nbuf) {
  737. curr_nbuf = nbuf;
  738. if (i < mapped_buf_num) {
  739. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  740. i++;
  741. }
  742. nbuf = qdf_nbuf_next(nbuf);
  743. qdf_nbuf_free(curr_nbuf);
  744. }
  745. return NULL;
  746. }
  747. /**
  748. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  749. * @soc: DP Soc Handle
  750. * @vdev: DP vdev handle
  751. * @tx_desc: Tx Descriptor Handle
  752. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  753. * @fw_metadata: Metadata to send to Target Firmware along with frame
  754. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  755. * @tx_exc_metadata: Handle that holds exception path meta data
  756. *
  757. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  758. * from software Tx descriptor
  759. *
  760. * Return:
  761. */
  762. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  763. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  764. uint16_t fw_metadata, uint8_t ring_id,
  765. struct cdp_tx_exception_metadata
  766. *tx_exc_metadata)
  767. {
  768. uint8_t type;
  769. uint16_t length;
  770. void *hal_tx_desc, *hal_tx_desc_cached;
  771. qdf_dma_addr_t dma_addr;
  772. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  773. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  774. tx_exc_metadata->sec_type : vdev->sec_type);
  775. /* Return Buffer Manager ID */
  776. uint8_t bm_id = ring_id;
  777. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  778. hal_tx_desc_cached = (void *) cached_desc;
  779. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  780. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  781. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  782. type = HAL_TX_BUF_TYPE_EXT_DESC;
  783. dma_addr = tx_desc->msdu_ext_desc->paddr;
  784. } else {
  785. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  786. type = HAL_TX_BUF_TYPE_BUFFER;
  787. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  788. }
  789. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  790. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  791. dma_addr , bm_id, tx_desc->id, type);
  792. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  793. return QDF_STATUS_E_RESOURCES;
  794. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  795. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  796. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  797. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  798. HAL_TX_DESC_DEFAULT_LMAC_ID);
  799. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  800. vdev->dscp_tid_map_id);
  801. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  802. sec_type_map[sec_type]);
  803. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  804. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  805. __func__, length, type, (uint64_t)dma_addr,
  806. tx_desc->pkt_offset, tx_desc->id);
  807. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  808. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  809. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  810. vdev->hal_desc_addr_search_flags);
  811. /* verify checksum offload configuration*/
  812. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  813. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  814. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  815. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  816. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  817. }
  818. if (tid != HTT_TX_EXT_TID_INVALID)
  819. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  820. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  821. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  822. /* Sync cached descriptor with HW */
  823. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  824. if (!hal_tx_desc) {
  825. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  826. "%s TCL ring full ring_id:%d", __func__, ring_id);
  827. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  828. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  829. return QDF_STATUS_E_RESOURCES;
  830. }
  831. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  832. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  833. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  834. /*
  835. * If one packet is enqueued in HW, PM usage count needs to be
  836. * incremented by one to prevent future runtime suspend. This
  837. * should be tied with the success of enqueuing. It will be
  838. * decremented after the packet has been sent.
  839. */
  840. hif_pm_runtime_get_noresume(soc->hif_handle);
  841. return QDF_STATUS_SUCCESS;
  842. }
  843. /**
  844. * dp_cce_classify() - Classify the frame based on CCE rules
  845. * @vdev: DP vdev handle
  846. * @nbuf: skb
  847. *
  848. * Classify frames based on CCE rules
  849. * Return: bool( true if classified,
  850. * else false)
  851. */
  852. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  853. {
  854. struct ether_header *eh = NULL;
  855. uint16_t ether_type;
  856. qdf_llc_t *llcHdr;
  857. qdf_nbuf_t nbuf_clone = NULL;
  858. qdf_dot3_qosframe_t *qos_wh = NULL;
  859. /* for mesh packets don't do any classification */
  860. if (qdf_unlikely(vdev->mesh_vdev))
  861. return false;
  862. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  863. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  864. ether_type = eh->ether_type;
  865. llcHdr = (qdf_llc_t *)(nbuf->data +
  866. sizeof(struct ether_header));
  867. } else {
  868. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  869. /* For encrypted packets don't do any classification */
  870. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  871. return false;
  872. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  873. if (qdf_unlikely(
  874. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  875. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  876. ether_type = *(uint16_t *)(nbuf->data
  877. + QDF_IEEE80211_4ADDR_HDR_LEN
  878. + sizeof(qdf_llc_t)
  879. - sizeof(ether_type));
  880. llcHdr = (qdf_llc_t *)(nbuf->data +
  881. QDF_IEEE80211_4ADDR_HDR_LEN);
  882. } else {
  883. ether_type = *(uint16_t *)(nbuf->data
  884. + QDF_IEEE80211_3ADDR_HDR_LEN
  885. + sizeof(qdf_llc_t)
  886. - sizeof(ether_type));
  887. llcHdr = (qdf_llc_t *)(nbuf->data +
  888. QDF_IEEE80211_3ADDR_HDR_LEN);
  889. }
  890. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  891. && (ether_type ==
  892. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  893. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  894. return true;
  895. }
  896. }
  897. return false;
  898. }
  899. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  900. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  901. sizeof(*llcHdr));
  902. nbuf_clone = qdf_nbuf_clone(nbuf);
  903. if (qdf_unlikely(nbuf_clone)) {
  904. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  905. if (ether_type == htons(ETHERTYPE_8021Q)) {
  906. qdf_nbuf_pull_head(nbuf_clone,
  907. sizeof(qdf_net_vlanhdr_t));
  908. }
  909. }
  910. } else {
  911. if (ether_type == htons(ETHERTYPE_8021Q)) {
  912. nbuf_clone = qdf_nbuf_clone(nbuf);
  913. if (qdf_unlikely(nbuf_clone)) {
  914. qdf_nbuf_pull_head(nbuf_clone,
  915. sizeof(qdf_net_vlanhdr_t));
  916. }
  917. }
  918. }
  919. if (qdf_unlikely(nbuf_clone))
  920. nbuf = nbuf_clone;
  921. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  922. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  923. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  924. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  925. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  926. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  927. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  928. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  929. if (qdf_unlikely(nbuf_clone != NULL))
  930. qdf_nbuf_free(nbuf_clone);
  931. return true;
  932. }
  933. if (qdf_unlikely(nbuf_clone != NULL))
  934. qdf_nbuf_free(nbuf_clone);
  935. return false;
  936. }
  937. /**
  938. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  939. * @vdev: DP vdev handle
  940. * @nbuf: skb
  941. *
  942. * Extract the DSCP or PCP information from frame and map into TID value.
  943. * Software based TID classification is required when more than 2 DSCP-TID
  944. * mapping tables are needed.
  945. * Hardware supports 2 DSCP-TID mapping tables
  946. *
  947. * Return: void
  948. */
  949. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  950. struct dp_tx_msdu_info_s *msdu_info)
  951. {
  952. uint8_t tos = 0, dscp_tid_override = 0;
  953. uint8_t *hdr_ptr, *L3datap;
  954. uint8_t is_mcast = 0;
  955. struct ether_header *eh = NULL;
  956. qdf_ethervlan_header_t *evh = NULL;
  957. uint16_t ether_type;
  958. qdf_llc_t *llcHdr;
  959. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  960. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  961. if (vdev->dscp_tid_map_id <= 1)
  962. return;
  963. /* for mesh packets don't do any classification */
  964. if (qdf_unlikely(vdev->mesh_vdev))
  965. return;
  966. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  967. eh = (struct ether_header *) nbuf->data;
  968. hdr_ptr = eh->ether_dhost;
  969. L3datap = hdr_ptr + sizeof(struct ether_header);
  970. } else {
  971. qdf_dot3_qosframe_t *qos_wh =
  972. (qdf_dot3_qosframe_t *) nbuf->data;
  973. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  974. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  975. return;
  976. }
  977. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  978. ether_type = eh->ether_type;
  979. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  980. /*
  981. * Check if packet is dot3 or eth2 type.
  982. */
  983. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  984. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  985. sizeof(*llcHdr));
  986. if (ether_type == htons(ETHERTYPE_8021Q)) {
  987. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  988. sizeof(*llcHdr);
  989. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  990. + sizeof(*llcHdr) +
  991. sizeof(qdf_net_vlanhdr_t));
  992. } else {
  993. L3datap = hdr_ptr + sizeof(struct ether_header) +
  994. sizeof(*llcHdr);
  995. }
  996. } else {
  997. if (ether_type == htons(ETHERTYPE_8021Q)) {
  998. evh = (qdf_ethervlan_header_t *) eh;
  999. ether_type = evh->ether_type;
  1000. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1001. }
  1002. }
  1003. /*
  1004. * Find priority from IP TOS DSCP field
  1005. */
  1006. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1007. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1008. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1009. /* Only for unicast frames */
  1010. if (!is_mcast) {
  1011. /* send it on VO queue */
  1012. msdu_info->tid = DP_VO_TID;
  1013. }
  1014. } else {
  1015. /*
  1016. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1017. * from TOS byte.
  1018. */
  1019. tos = ip->ip_tos;
  1020. dscp_tid_override = 1;
  1021. }
  1022. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1023. /* TODO
  1024. * use flowlabel
  1025. *igmpmld cases to be handled in phase 2
  1026. */
  1027. unsigned long ver_pri_flowlabel;
  1028. unsigned long pri;
  1029. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1030. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1031. DP_IPV6_PRIORITY_SHIFT;
  1032. tos = pri;
  1033. dscp_tid_override = 1;
  1034. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1035. msdu_info->tid = DP_VO_TID;
  1036. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1037. /* Only for unicast frames */
  1038. if (!is_mcast) {
  1039. /* send ucast arp on VO queue */
  1040. msdu_info->tid = DP_VO_TID;
  1041. }
  1042. }
  1043. /*
  1044. * Assign all MCAST packets to BE
  1045. */
  1046. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1047. if (is_mcast) {
  1048. tos = 0;
  1049. dscp_tid_override = 1;
  1050. }
  1051. }
  1052. if (dscp_tid_override == 1) {
  1053. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1054. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1055. }
  1056. return;
  1057. }
  1058. #ifdef CONVERGED_TDLS_ENABLE
  1059. /**
  1060. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1061. * @tx_desc: TX descriptor
  1062. *
  1063. * Return: None
  1064. */
  1065. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1066. {
  1067. if (tx_desc->vdev) {
  1068. if (tx_desc->vdev->is_tdls_frame)
  1069. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1070. tx_desc->vdev->is_tdls_frame = false;
  1071. }
  1072. }
  1073. /**
  1074. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1075. * @tx_desc: TX descriptor
  1076. * @vdev: datapath vdev handle
  1077. *
  1078. * Return: None
  1079. */
  1080. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1081. struct dp_vdev *vdev)
  1082. {
  1083. struct hal_tx_completion_status ts = {0};
  1084. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1085. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1086. if (vdev->tx_non_std_data_callback.func) {
  1087. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1088. vdev->tx_non_std_data_callback.func(
  1089. vdev->tx_non_std_data_callback.ctxt,
  1090. nbuf, ts.status);
  1091. return;
  1092. }
  1093. }
  1094. #endif
  1095. /**
  1096. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1097. * @vdev: DP vdev handle
  1098. * @nbuf: skb
  1099. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1100. * @meta_data: Metadata to the fw
  1101. * @tx_q: Tx queue to be used for this Tx frame
  1102. * @peer_id: peer_id of the peer in case of NAWDS frames
  1103. * @tx_exc_metadata: Handle that holds exception path metadata
  1104. *
  1105. * Return: NULL on success,
  1106. * nbuf when it fails to send
  1107. */
  1108. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1109. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1110. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1111. {
  1112. struct dp_pdev *pdev = vdev->pdev;
  1113. struct dp_soc *soc = pdev->soc;
  1114. struct dp_tx_desc_s *tx_desc;
  1115. QDF_STATUS status;
  1116. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1117. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1118. uint16_t htt_tcl_metadata = 0;
  1119. uint8_t tid = msdu_info->tid;
  1120. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1121. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1122. msdu_info, tx_exc_metadata);
  1123. if (!tx_desc) {
  1124. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1125. "%s Tx_desc prepare Fail vdev %pK queue %d",
  1126. __func__, vdev, tx_q->desc_pool_id);
  1127. return nbuf;
  1128. }
  1129. if (qdf_unlikely(soc->cce_disable)) {
  1130. if (dp_cce_classify(vdev, nbuf) == true) {
  1131. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1132. tid = DP_VO_TID;
  1133. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1134. }
  1135. }
  1136. dp_tx_update_tdls_flags(tx_desc);
  1137. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1138. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1139. "%s %d : HAL RING Access Failed -- %pK",
  1140. __func__, __LINE__, hal_srng);
  1141. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1142. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1143. goto fail_return;
  1144. }
  1145. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1146. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1147. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1148. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1149. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1150. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1151. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1152. peer_id);
  1153. } else
  1154. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1155. if (msdu_info->exception_fw) {
  1156. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1157. }
  1158. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1159. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1160. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1161. if (status != QDF_STATUS_SUCCESS) {
  1162. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1163. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1164. __func__, tx_desc, tx_q->ring_id);
  1165. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1166. goto fail_return;
  1167. }
  1168. nbuf = NULL;
  1169. fail_return:
  1170. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1171. hal_srng_access_end(soc->hal_soc, hal_srng);
  1172. hif_pm_runtime_put(soc->hif_handle);
  1173. } else {
  1174. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1175. }
  1176. return nbuf;
  1177. }
  1178. /**
  1179. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1180. * @vdev: DP vdev handle
  1181. * @nbuf: skb
  1182. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1183. *
  1184. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1185. *
  1186. * Return: NULL on success,
  1187. * nbuf when it fails to send
  1188. */
  1189. #if QDF_LOCK_STATS
  1190. static noinline
  1191. #else
  1192. static
  1193. #endif
  1194. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1195. struct dp_tx_msdu_info_s *msdu_info)
  1196. {
  1197. uint8_t i;
  1198. struct dp_pdev *pdev = vdev->pdev;
  1199. struct dp_soc *soc = pdev->soc;
  1200. struct dp_tx_desc_s *tx_desc;
  1201. bool is_cce_classified = false;
  1202. QDF_STATUS status;
  1203. uint16_t htt_tcl_metadata = 0;
  1204. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1205. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1206. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1207. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1208. "%s %d : HAL RING Access Failed -- %pK",
  1209. __func__, __LINE__, hal_srng);
  1210. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1211. return nbuf;
  1212. }
  1213. if (qdf_unlikely(soc->cce_disable)) {
  1214. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1215. if (is_cce_classified) {
  1216. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1217. msdu_info->tid = DP_VO_TID;
  1218. }
  1219. }
  1220. if (msdu_info->frm_type == dp_tx_frm_me)
  1221. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1222. i = 0;
  1223. /* Print statement to track i and num_seg */
  1224. /*
  1225. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1226. * descriptors using information in msdu_info
  1227. */
  1228. while (i < msdu_info->num_seg) {
  1229. /*
  1230. * Setup Tx descriptor for an MSDU, and MSDU extension
  1231. * descriptor
  1232. */
  1233. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1234. tx_q->desc_pool_id);
  1235. if (!tx_desc) {
  1236. if (msdu_info->frm_type == dp_tx_frm_me) {
  1237. dp_tx_me_free_buf(pdev,
  1238. (void *)(msdu_info->u.sg_info
  1239. .curr_seg->frags[0].vaddr));
  1240. }
  1241. goto done;
  1242. }
  1243. if (msdu_info->frm_type == dp_tx_frm_me) {
  1244. tx_desc->me_buffer =
  1245. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1246. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1247. }
  1248. if (is_cce_classified)
  1249. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1250. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1251. if (msdu_info->exception_fw) {
  1252. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1253. }
  1254. /*
  1255. * Enqueue the Tx MSDU descriptor to HW for transmit
  1256. */
  1257. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1258. htt_tcl_metadata, tx_q->ring_id, NULL);
  1259. if (status != QDF_STATUS_SUCCESS) {
  1260. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1261. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1262. __func__, tx_desc, tx_q->ring_id);
  1263. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1264. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1265. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1266. goto done;
  1267. }
  1268. /*
  1269. * TODO
  1270. * if tso_info structure can be modified to have curr_seg
  1271. * as first element, following 2 blocks of code (for TSO and SG)
  1272. * can be combined into 1
  1273. */
  1274. /*
  1275. * For frames with multiple segments (TSO, ME), jump to next
  1276. * segment.
  1277. */
  1278. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1279. if (msdu_info->u.tso_info.curr_seg->next) {
  1280. msdu_info->u.tso_info.curr_seg =
  1281. msdu_info->u.tso_info.curr_seg->next;
  1282. /*
  1283. * If this is a jumbo nbuf, then increment the number of
  1284. * nbuf users for each additional segment of the msdu.
  1285. * This will ensure that the skb is freed only after
  1286. * receiving tx completion for all segments of an nbuf
  1287. */
  1288. qdf_nbuf_inc_users(nbuf);
  1289. /* Check with MCL if this is needed */
  1290. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1291. }
  1292. }
  1293. /*
  1294. * For Multicast-Unicast converted packets,
  1295. * each converted frame (for a client) is represented as
  1296. * 1 segment
  1297. */
  1298. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1299. (msdu_info->frm_type == dp_tx_frm_me)) {
  1300. if (msdu_info->u.sg_info.curr_seg->next) {
  1301. msdu_info->u.sg_info.curr_seg =
  1302. msdu_info->u.sg_info.curr_seg->next;
  1303. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1304. }
  1305. }
  1306. i++;
  1307. }
  1308. nbuf = NULL;
  1309. done:
  1310. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1311. hal_srng_access_end(soc->hal_soc, hal_srng);
  1312. hif_pm_runtime_put(soc->hif_handle);
  1313. } else {
  1314. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1315. }
  1316. return nbuf;
  1317. }
  1318. /**
  1319. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1320. * for SG frames
  1321. * @vdev: DP vdev handle
  1322. * @nbuf: skb
  1323. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1324. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1325. *
  1326. * Return: NULL on success,
  1327. * nbuf when it fails to send
  1328. */
  1329. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1330. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1331. {
  1332. uint32_t cur_frag, nr_frags;
  1333. qdf_dma_addr_t paddr;
  1334. struct dp_tx_sg_info_s *sg_info;
  1335. sg_info = &msdu_info->u.sg_info;
  1336. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1337. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1338. QDF_DMA_TO_DEVICE)) {
  1339. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1340. "dma map error");
  1341. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1342. qdf_nbuf_free(nbuf);
  1343. return NULL;
  1344. }
  1345. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1346. seg_info->frags[0].paddr_lo = paddr;
  1347. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1348. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1349. seg_info->frags[0].vaddr = (void *) nbuf;
  1350. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1351. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1352. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1353. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1354. "frag dma map error");
  1355. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1356. qdf_nbuf_free(nbuf);
  1357. return NULL;
  1358. }
  1359. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1360. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1361. seg_info->frags[cur_frag + 1].paddr_hi =
  1362. ((uint64_t) paddr) >> 32;
  1363. seg_info->frags[cur_frag + 1].len =
  1364. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1365. }
  1366. seg_info->frag_cnt = (cur_frag + 1);
  1367. seg_info->total_len = qdf_nbuf_len(nbuf);
  1368. seg_info->next = NULL;
  1369. sg_info->curr_seg = seg_info;
  1370. msdu_info->frm_type = dp_tx_frm_sg;
  1371. msdu_info->num_seg = 1;
  1372. return nbuf;
  1373. }
  1374. #ifdef MESH_MODE_SUPPORT
  1375. /**
  1376. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1377. and prepare msdu_info for mesh frames.
  1378. * @vdev: DP vdev handle
  1379. * @nbuf: skb
  1380. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1381. *
  1382. * Return: NULL on failure,
  1383. * nbuf when extracted successfully
  1384. */
  1385. static
  1386. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1387. struct dp_tx_msdu_info_s *msdu_info)
  1388. {
  1389. struct meta_hdr_s *mhdr;
  1390. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1391. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1392. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1393. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1394. msdu_info->exception_fw = 0;
  1395. goto remove_meta_hdr;
  1396. }
  1397. msdu_info->exception_fw = 1;
  1398. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1399. meta_data->host_tx_desc_pool = 1;
  1400. meta_data->update_peer_cache = 1;
  1401. meta_data->learning_frame = 1;
  1402. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1403. meta_data->power = mhdr->power;
  1404. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1405. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1406. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1407. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1408. meta_data->dyn_bw = 1;
  1409. meta_data->valid_pwr = 1;
  1410. meta_data->valid_mcs_mask = 1;
  1411. meta_data->valid_nss_mask = 1;
  1412. meta_data->valid_preamble_type = 1;
  1413. meta_data->valid_retries = 1;
  1414. meta_data->valid_bw_info = 1;
  1415. }
  1416. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1417. meta_data->encrypt_type = 0;
  1418. meta_data->valid_encrypt_type = 1;
  1419. meta_data->learning_frame = 0;
  1420. }
  1421. meta_data->valid_key_flags = 1;
  1422. meta_data->key_flags = (mhdr->keyix & 0x3);
  1423. remove_meta_hdr:
  1424. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1425. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1426. "qdf_nbuf_pull_head failed");
  1427. qdf_nbuf_free(nbuf);
  1428. return NULL;
  1429. }
  1430. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1431. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1432. else
  1433. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1434. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1435. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1436. " tid %d to_fw %d",
  1437. __func__, msdu_info->meta_data[0],
  1438. msdu_info->meta_data[1],
  1439. msdu_info->meta_data[2],
  1440. msdu_info->meta_data[3],
  1441. msdu_info->meta_data[4],
  1442. msdu_info->meta_data[5],
  1443. msdu_info->tid, msdu_info->exception_fw);
  1444. return nbuf;
  1445. }
  1446. #else
  1447. static
  1448. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1449. struct dp_tx_msdu_info_s *msdu_info)
  1450. {
  1451. return nbuf;
  1452. }
  1453. #endif
  1454. #ifdef DP_FEATURE_NAWDS_TX
  1455. /**
  1456. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1457. * @vdev: dp_vdev handle
  1458. * @nbuf: skb
  1459. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1460. * @tx_q: Tx queue to be used for this Tx frame
  1461. * @meta_data: Meta date for mesh
  1462. * @peer_id: peer_id of the peer in case of NAWDS frames
  1463. *
  1464. * return: NULL on success nbuf on failure
  1465. */
  1466. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1467. struct dp_tx_msdu_info_s *msdu_info)
  1468. {
  1469. struct dp_peer *peer = NULL;
  1470. struct dp_soc *soc = vdev->pdev->soc;
  1471. struct dp_ast_entry *ast_entry = NULL;
  1472. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1473. uint16_t peer_id = HTT_INVALID_PEER;
  1474. struct dp_peer *sa_peer = NULL;
  1475. qdf_nbuf_t nbuf_copy;
  1476. qdf_spin_lock_bh(&(soc->ast_lock));
  1477. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1478. if (ast_entry)
  1479. sa_peer = ast_entry->peer;
  1480. qdf_spin_unlock_bh(&(soc->ast_lock));
  1481. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1482. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1483. (peer->nawds_enabled)) {
  1484. if (sa_peer == peer) {
  1485. QDF_TRACE(QDF_MODULE_ID_DP,
  1486. QDF_TRACE_LEVEL_DEBUG,
  1487. " %s: broadcast multicast packet",
  1488. __func__);
  1489. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1490. continue;
  1491. }
  1492. nbuf_copy = qdf_nbuf_copy(nbuf);
  1493. if (!nbuf_copy) {
  1494. QDF_TRACE(QDF_MODULE_ID_DP,
  1495. QDF_TRACE_LEVEL_ERROR,
  1496. "nbuf copy failed");
  1497. }
  1498. peer_id = peer->peer_ids[0];
  1499. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1500. msdu_info, peer_id, NULL);
  1501. if (nbuf_copy != NULL) {
  1502. qdf_nbuf_free(nbuf_copy);
  1503. continue;
  1504. }
  1505. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1506. 1, qdf_nbuf_len(nbuf));
  1507. }
  1508. }
  1509. if (peer_id == HTT_INVALID_PEER)
  1510. return nbuf;
  1511. return NULL;
  1512. }
  1513. #endif
  1514. /**
  1515. * dp_check_exc_metadata() - Checks if parameters are valid
  1516. * @tx_exc - holds all exception path parameters
  1517. *
  1518. * Returns true when all the parameters are valid else false
  1519. *
  1520. */
  1521. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1522. {
  1523. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1524. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1525. tx_exc->sec_type > cdp_num_sec_types) {
  1526. return false;
  1527. }
  1528. return true;
  1529. }
  1530. /**
  1531. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1532. * @vap_dev: DP vdev handle
  1533. * @nbuf: skb
  1534. * @tx_exc_metadata: Handle that holds exception path meta data
  1535. *
  1536. * Entry point for Core Tx layer (DP_TX) invoked from
  1537. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1538. *
  1539. * Return: NULL on success,
  1540. * nbuf when it fails to send
  1541. */
  1542. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1543. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1544. {
  1545. struct ether_header *eh = NULL;
  1546. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1547. struct dp_tx_msdu_info_s msdu_info;
  1548. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1549. msdu_info.tid = tx_exc_metadata->tid;
  1550. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1551. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1552. "%s , skb %pM",
  1553. __func__, nbuf->data);
  1554. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1555. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1556. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1557. "Invalid parameters in exception path");
  1558. goto fail;
  1559. }
  1560. /* Basic sanity checks for unsupported packets */
  1561. /* MESH mode */
  1562. if (qdf_unlikely(vdev->mesh_vdev)) {
  1563. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1564. "Mesh mode is not supported in exception path");
  1565. goto fail;
  1566. }
  1567. /* TSO or SG */
  1568. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1569. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1570. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1571. "TSO and SG are not supported in exception path");
  1572. goto fail;
  1573. }
  1574. /* RAW */
  1575. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1576. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1577. "Raw frame is not supported in exception path");
  1578. goto fail;
  1579. }
  1580. /* Mcast enhancement*/
  1581. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1582. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1583. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1584. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1585. }
  1586. }
  1587. /*
  1588. * Get HW Queue to use for this frame.
  1589. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1590. * dedicated for data and 1 for command.
  1591. * "queue_id" maps to one hardware ring.
  1592. * With each ring, we also associate a unique Tx descriptor pool
  1593. * to minimize lock contention for these resources.
  1594. */
  1595. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1596. /* Single linear frame */
  1597. /*
  1598. * If nbuf is a simple linear frame, use send_single function to
  1599. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1600. * SRNG. There is no need to setup a MSDU extension descriptor.
  1601. */
  1602. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1603. tx_exc_metadata->peer_id, tx_exc_metadata);
  1604. return nbuf;
  1605. fail:
  1606. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1607. "pkt send failed");
  1608. return nbuf;
  1609. }
  1610. /**
  1611. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1612. * @vap_dev: DP vdev handle
  1613. * @nbuf: skb
  1614. *
  1615. * Entry point for Core Tx layer (DP_TX) invoked from
  1616. * hard_start_xmit in OSIF/HDD
  1617. *
  1618. * Return: NULL on success,
  1619. * nbuf when it fails to send
  1620. */
  1621. #ifdef MESH_MODE_SUPPORT
  1622. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1623. {
  1624. struct meta_hdr_s *mhdr;
  1625. qdf_nbuf_t nbuf_mesh = NULL;
  1626. qdf_nbuf_t nbuf_clone = NULL;
  1627. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1628. uint8_t no_enc_frame = 0;
  1629. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1630. if (nbuf_mesh == NULL) {
  1631. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1632. "qdf_nbuf_unshare failed");
  1633. return nbuf;
  1634. }
  1635. nbuf = nbuf_mesh;
  1636. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1637. if ((vdev->sec_type != cdp_sec_type_none) &&
  1638. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1639. no_enc_frame = 1;
  1640. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1641. !no_enc_frame) {
  1642. nbuf_clone = qdf_nbuf_clone(nbuf);
  1643. if (nbuf_clone == NULL) {
  1644. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1645. "qdf_nbuf_clone failed");
  1646. return nbuf;
  1647. }
  1648. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1649. }
  1650. if (nbuf_clone) {
  1651. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1652. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1653. } else {
  1654. qdf_nbuf_free(nbuf_clone);
  1655. }
  1656. }
  1657. if (no_enc_frame)
  1658. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1659. else
  1660. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1661. nbuf = dp_tx_send(vap_dev, nbuf);
  1662. if ((nbuf == NULL) && no_enc_frame) {
  1663. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1664. }
  1665. return nbuf;
  1666. }
  1667. #else
  1668. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1669. {
  1670. return dp_tx_send(vap_dev, nbuf);
  1671. }
  1672. #endif
  1673. /**
  1674. * dp_tx_send() - Transmit a frame on a given VAP
  1675. * @vap_dev: DP vdev handle
  1676. * @nbuf: skb
  1677. *
  1678. * Entry point for Core Tx layer (DP_TX) invoked from
  1679. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1680. * cases
  1681. *
  1682. * Return: NULL on success,
  1683. * nbuf when it fails to send
  1684. */
  1685. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1686. {
  1687. struct ether_header *eh = NULL;
  1688. struct dp_tx_msdu_info_s msdu_info;
  1689. struct dp_tx_seg_info_s seg_info;
  1690. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1691. uint16_t peer_id = HTT_INVALID_PEER;
  1692. qdf_nbuf_t nbuf_mesh = NULL;
  1693. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1694. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1695. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1696. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1697. "%s , skb %pM",
  1698. __func__, nbuf->data);
  1699. /*
  1700. * Set Default Host TID value to invalid TID
  1701. * (TID override disabled)
  1702. */
  1703. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1704. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1705. if (qdf_unlikely(vdev->mesh_vdev)) {
  1706. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1707. &msdu_info);
  1708. if (nbuf_mesh == NULL) {
  1709. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1710. "Extracting mesh metadata failed");
  1711. return nbuf;
  1712. }
  1713. nbuf = nbuf_mesh;
  1714. }
  1715. /*
  1716. * Get HW Queue to use for this frame.
  1717. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1718. * dedicated for data and 1 for command.
  1719. * "queue_id" maps to one hardware ring.
  1720. * With each ring, we also associate a unique Tx descriptor pool
  1721. * to minimize lock contention for these resources.
  1722. */
  1723. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1724. /*
  1725. * TCL H/W supports 2 DSCP-TID mapping tables.
  1726. * Table 1 - Default DSCP-TID mapping table
  1727. * Table 2 - 1 DSCP-TID override table
  1728. *
  1729. * If we need a different DSCP-TID mapping for this vap,
  1730. * call tid_classify to extract DSCP/ToS from frame and
  1731. * map to a TID and store in msdu_info. This is later used
  1732. * to fill in TCL Input descriptor (per-packet TID override).
  1733. */
  1734. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1735. /*
  1736. * Classify the frame and call corresponding
  1737. * "prepare" function which extracts the segment (TSO)
  1738. * and fragmentation information (for TSO , SG, ME, or Raw)
  1739. * into MSDU_INFO structure which is later used to fill
  1740. * SW and HW descriptors.
  1741. */
  1742. if (qdf_nbuf_is_tso(nbuf)) {
  1743. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1744. "%s TSO frame %pK", __func__, vdev);
  1745. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1746. qdf_nbuf_len(nbuf));
  1747. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1748. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1749. qdf_nbuf_len(nbuf));
  1750. return nbuf;
  1751. }
  1752. goto send_multiple;
  1753. }
  1754. /* SG */
  1755. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1756. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1757. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1758. "%s non-TSO SG frame %pK", __func__, vdev);
  1759. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1760. qdf_nbuf_len(nbuf));
  1761. goto send_multiple;
  1762. }
  1763. #ifdef ATH_SUPPORT_IQUE
  1764. /* Mcast to Ucast Conversion*/
  1765. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1766. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1767. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1768. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1769. "%s Mcast frm for ME %pK", __func__, vdev);
  1770. DP_STATS_INC_PKT(vdev,
  1771. tx_i.mcast_en.mcast_pkt, 1,
  1772. qdf_nbuf_len(nbuf));
  1773. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1774. QDF_STATUS_SUCCESS) {
  1775. return NULL;
  1776. }
  1777. }
  1778. }
  1779. #endif
  1780. /* RAW */
  1781. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1782. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1783. if (nbuf == NULL)
  1784. return NULL;
  1785. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1786. "%s Raw frame %pK", __func__, vdev);
  1787. goto send_multiple;
  1788. }
  1789. /* Single linear frame */
  1790. /*
  1791. * If nbuf is a simple linear frame, use send_single function to
  1792. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1793. * SRNG. There is no need to setup a MSDU extension descriptor.
  1794. */
  1795. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1796. return nbuf;
  1797. send_multiple:
  1798. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1799. return nbuf;
  1800. }
  1801. /**
  1802. * dp_tx_reinject_handler() - Tx Reinject Handler
  1803. * @tx_desc: software descriptor head pointer
  1804. * @status : Tx completion status from HTT descriptor
  1805. *
  1806. * This function reinjects frames back to Target.
  1807. * Todo - Host queue needs to be added
  1808. *
  1809. * Return: none
  1810. */
  1811. static
  1812. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1813. {
  1814. struct dp_vdev *vdev;
  1815. struct dp_peer *peer = NULL;
  1816. uint32_t peer_id = HTT_INVALID_PEER;
  1817. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1818. qdf_nbuf_t nbuf_copy = NULL;
  1819. struct dp_tx_msdu_info_s msdu_info;
  1820. struct dp_peer *sa_peer = NULL;
  1821. struct dp_ast_entry *ast_entry = NULL;
  1822. struct dp_soc *soc = NULL;
  1823. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1824. #ifdef WDS_VENDOR_EXTENSION
  1825. int is_mcast = 0, is_ucast = 0;
  1826. int num_peers_3addr = 0;
  1827. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1828. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1829. #endif
  1830. vdev = tx_desc->vdev;
  1831. soc = vdev->pdev->soc;
  1832. qdf_assert(vdev);
  1833. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1834. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1835. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1836. "%s Tx reinject path", __func__);
  1837. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1838. qdf_nbuf_len(tx_desc->nbuf));
  1839. qdf_spin_lock_bh(&(soc->ast_lock));
  1840. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1841. if (ast_entry)
  1842. sa_peer = ast_entry->peer;
  1843. qdf_spin_unlock_bh(&(soc->ast_lock));
  1844. #ifdef WDS_VENDOR_EXTENSION
  1845. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1846. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1847. } else {
  1848. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1849. }
  1850. is_ucast = !is_mcast;
  1851. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1852. if (peer->bss_peer)
  1853. continue;
  1854. /* Detect wds peers that use 3-addr framing for mcast.
  1855. * if there are any, the bss_peer is used to send the
  1856. * the mcast frame using 3-addr format. all wds enabled
  1857. * peers that use 4-addr framing for mcast frames will
  1858. * be duplicated and sent as 4-addr frames below.
  1859. */
  1860. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1861. num_peers_3addr = 1;
  1862. break;
  1863. }
  1864. }
  1865. #endif
  1866. if (qdf_unlikely(vdev->mesh_vdev)) {
  1867. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1868. } else {
  1869. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1870. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1871. #ifdef WDS_VENDOR_EXTENSION
  1872. /*
  1873. * . if 3-addr STA, then send on BSS Peer
  1874. * . if Peer WDS enabled and accept 4-addr mcast,
  1875. * send mcast on that peer only
  1876. * . if Peer WDS enabled and accept 4-addr ucast,
  1877. * send ucast on that peer only
  1878. */
  1879. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1880. (peer->wds_enabled &&
  1881. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1882. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1883. #else
  1884. ((peer->bss_peer &&
  1885. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1886. peer->nawds_enabled)) {
  1887. #endif
  1888. peer_id = DP_INVALID_PEER;
  1889. if (peer->nawds_enabled) {
  1890. peer_id = peer->peer_ids[0];
  1891. if (sa_peer == peer) {
  1892. QDF_TRACE(
  1893. QDF_MODULE_ID_DP,
  1894. QDF_TRACE_LEVEL_DEBUG,
  1895. " %s: multicast packet",
  1896. __func__);
  1897. DP_STATS_INC(peer,
  1898. tx.nawds_mcast_drop, 1);
  1899. continue;
  1900. }
  1901. }
  1902. nbuf_copy = qdf_nbuf_copy(nbuf);
  1903. if (!nbuf_copy) {
  1904. QDF_TRACE(QDF_MODULE_ID_DP,
  1905. QDF_TRACE_LEVEL_DEBUG,
  1906. FL("nbuf copy failed"));
  1907. break;
  1908. }
  1909. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1910. nbuf_copy,
  1911. &msdu_info,
  1912. peer_id,
  1913. NULL);
  1914. if (nbuf_copy) {
  1915. QDF_TRACE(QDF_MODULE_ID_DP,
  1916. QDF_TRACE_LEVEL_DEBUG,
  1917. FL("pkt send failed"));
  1918. qdf_nbuf_free(nbuf_copy);
  1919. } else {
  1920. if (peer_id != DP_INVALID_PEER)
  1921. DP_STATS_INC_PKT(peer,
  1922. tx.nawds_mcast,
  1923. 1, qdf_nbuf_len(nbuf));
  1924. }
  1925. }
  1926. }
  1927. }
  1928. if (vdev->nawds_enabled) {
  1929. peer_id = DP_INVALID_PEER;
  1930. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1931. 1, qdf_nbuf_len(nbuf));
  1932. nbuf = dp_tx_send_msdu_single(vdev,
  1933. nbuf,
  1934. &msdu_info,
  1935. peer_id, NULL);
  1936. if (nbuf) {
  1937. QDF_TRACE(QDF_MODULE_ID_DP,
  1938. QDF_TRACE_LEVEL_DEBUG,
  1939. FL("pkt send failed"));
  1940. qdf_nbuf_free(nbuf);
  1941. }
  1942. } else
  1943. qdf_nbuf_free(nbuf);
  1944. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1945. }
  1946. /**
  1947. * dp_tx_inspect_handler() - Tx Inspect Handler
  1948. * @tx_desc: software descriptor head pointer
  1949. * @status : Tx completion status from HTT descriptor
  1950. *
  1951. * Handles Tx frames sent back to Host for inspection
  1952. * (ProxyARP)
  1953. *
  1954. * Return: none
  1955. */
  1956. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1957. {
  1958. struct dp_soc *soc;
  1959. struct dp_pdev *pdev = tx_desc->pdev;
  1960. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1961. "%s Tx inspect path",
  1962. __func__);
  1963. qdf_assert(pdev);
  1964. soc = pdev->soc;
  1965. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1966. qdf_nbuf_len(tx_desc->nbuf));
  1967. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1968. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1969. }
  1970. #ifdef FEATURE_PERPKT_INFO
  1971. /**
  1972. * dp_get_completion_indication_for_stack() - send completion to stack
  1973. * @soc : dp_soc handle
  1974. * @pdev: dp_pdev handle
  1975. * @peer_id: peer_id of the peer for which completion came
  1976. * @ppdu_id: ppdu_id
  1977. * @first_msdu: first msdu
  1978. * @last_msdu: last msdu
  1979. * @netbuf: Buffer pointer for free
  1980. *
  1981. * This function is used for indication whether buffer needs to be
  1982. * send to stack for free or not
  1983. */
  1984. QDF_STATUS
  1985. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1986. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1987. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1988. {
  1989. struct tx_capture_hdr *ppdu_hdr;
  1990. struct dp_peer *peer = NULL;
  1991. struct ether_header *eh;
  1992. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1993. return QDF_STATUS_E_NOSUPPORT;
  1994. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1995. dp_peer_find_by_id(soc, peer_id);
  1996. if (!peer) {
  1997. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1998. FL("Peer Invalid"));
  1999. return QDF_STATUS_E_INVAL;
  2000. }
  2001. if (pdev->mcopy_mode) {
  2002. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2003. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2004. return QDF_STATUS_E_INVAL;
  2005. }
  2006. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2007. pdev->m_copy_id.tx_peer_id = peer_id;
  2008. }
  2009. eh = (struct ether_header *)qdf_nbuf_data(netbuf);
  2010. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2011. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2012. FL("No headroom"));
  2013. return QDF_STATUS_E_NOMEM;
  2014. }
  2015. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2016. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2017. IEEE80211_ADDR_LEN);
  2018. if (peer->bss_peer) {
  2019. qdf_mem_copy(ppdu_hdr->ra, eh->ether_dhost, IEEE80211_ADDR_LEN);
  2020. } else {
  2021. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2022. IEEE80211_ADDR_LEN);
  2023. }
  2024. ppdu_hdr->ppdu_id = ppdu_id;
  2025. ppdu_hdr->peer_id = peer_id;
  2026. ppdu_hdr->first_msdu = first_msdu;
  2027. ppdu_hdr->last_msdu = last_msdu;
  2028. return QDF_STATUS_SUCCESS;
  2029. }
  2030. /**
  2031. * dp_send_completion_to_stack() - send completion to stack
  2032. * @soc : dp_soc handle
  2033. * @pdev: dp_pdev handle
  2034. * @peer_id: peer_id of the peer for which completion came
  2035. * @ppdu_id: ppdu_id
  2036. * @netbuf: Buffer pointer for free
  2037. *
  2038. * This function is used to send completion to stack
  2039. * to free buffer
  2040. */
  2041. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2042. uint16_t peer_id, uint32_t ppdu_id,
  2043. qdf_nbuf_t netbuf)
  2044. {
  2045. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2046. netbuf, peer_id,
  2047. WDI_NO_VAL, pdev->pdev_id);
  2048. }
  2049. #else
  2050. static QDF_STATUS
  2051. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2052. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  2053. uint8_t last_msdu, qdf_nbuf_t netbuf)
  2054. {
  2055. return QDF_STATUS_E_NOSUPPORT;
  2056. }
  2057. static void
  2058. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2059. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2060. {
  2061. }
  2062. #endif
  2063. /**
  2064. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2065. * @soc: Soc handle
  2066. * @desc: software Tx descriptor to be processed
  2067. *
  2068. * Return: none
  2069. */
  2070. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2071. struct dp_tx_desc_s *desc)
  2072. {
  2073. struct dp_vdev *vdev = desc->vdev;
  2074. qdf_nbuf_t nbuf = desc->nbuf;
  2075. /* If it is TDLS mgmt, don't unmap or free the frame */
  2076. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2077. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2078. /* 0 : MSDU buffer, 1 : MLE */
  2079. if (desc->msdu_ext_desc) {
  2080. /* TSO free */
  2081. if (hal_tx_ext_desc_get_tso_enable(
  2082. desc->msdu_ext_desc->vaddr)) {
  2083. /* unmap eash TSO seg before free the nbuf */
  2084. dp_tx_tso_unmap_segment(soc, desc);
  2085. qdf_nbuf_free(nbuf);
  2086. return;
  2087. }
  2088. }
  2089. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2090. if (qdf_likely(!vdev->mesh_vdev))
  2091. qdf_nbuf_free(nbuf);
  2092. else {
  2093. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2094. qdf_nbuf_free(nbuf);
  2095. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2096. } else
  2097. vdev->osif_tx_free_ext((nbuf));
  2098. }
  2099. }
  2100. /**
  2101. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2102. * @vdev: pointer to dp dev handler
  2103. * @status : Tx completion status from HTT descriptor
  2104. *
  2105. * Handles MEC notify event sent from fw to Host
  2106. *
  2107. * Return: none
  2108. */
  2109. #ifdef FEATURE_WDS
  2110. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2111. {
  2112. struct dp_soc *soc;
  2113. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2114. struct dp_peer *peer;
  2115. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2116. if (!vdev->wds_enabled)
  2117. return;
  2118. /* MEC required only in STA mode */
  2119. if (vdev->opmode != wlan_op_mode_sta)
  2120. return;
  2121. soc = vdev->pdev->soc;
  2122. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2123. peer = TAILQ_FIRST(&vdev->peer_list);
  2124. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2125. if (!peer) {
  2126. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2127. FL("peer is NULL"));
  2128. return;
  2129. }
  2130. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2131. "%s Tx MEC Handler",
  2132. __func__);
  2133. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2134. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2135. status[(DP_MAC_ADDR_LEN - 2) + i];
  2136. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2137. dp_peer_add_ast(soc,
  2138. peer,
  2139. mac_addr,
  2140. CDP_TXRX_AST_TYPE_MEC,
  2141. flags);
  2142. }
  2143. #endif
  2144. /**
  2145. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2146. * @tx_desc: software descriptor head pointer
  2147. * @status : Tx completion status from HTT descriptor
  2148. *
  2149. * This function will process HTT Tx indication messages from Target
  2150. *
  2151. * Return: none
  2152. */
  2153. static
  2154. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2155. {
  2156. uint8_t tx_status;
  2157. struct dp_pdev *pdev;
  2158. struct dp_vdev *vdev;
  2159. struct dp_soc *soc;
  2160. uint32_t *htt_status_word = (uint32_t *) status;
  2161. qdf_assert(tx_desc->pdev);
  2162. pdev = tx_desc->pdev;
  2163. vdev = tx_desc->vdev;
  2164. soc = pdev->soc;
  2165. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2166. switch (tx_status) {
  2167. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2168. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2169. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2170. {
  2171. dp_tx_comp_free_buf(soc, tx_desc);
  2172. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2173. break;
  2174. }
  2175. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2176. {
  2177. dp_tx_reinject_handler(tx_desc, status);
  2178. break;
  2179. }
  2180. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2181. {
  2182. dp_tx_inspect_handler(tx_desc, status);
  2183. break;
  2184. }
  2185. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2186. {
  2187. dp_tx_mec_handler(vdev, status);
  2188. break;
  2189. }
  2190. default:
  2191. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2192. "%s Invalid HTT tx_status %d",
  2193. __func__, tx_status);
  2194. break;
  2195. }
  2196. }
  2197. #ifdef MESH_MODE_SUPPORT
  2198. /**
  2199. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2200. * in mesh meta header
  2201. * @tx_desc: software descriptor head pointer
  2202. * @ts: pointer to tx completion stats
  2203. * Return: none
  2204. */
  2205. static
  2206. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2207. struct hal_tx_completion_status *ts)
  2208. {
  2209. struct meta_hdr_s *mhdr;
  2210. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2211. if (!tx_desc->msdu_ext_desc) {
  2212. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2213. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2214. "netbuf %pK offset %d",
  2215. netbuf, tx_desc->pkt_offset);
  2216. return;
  2217. }
  2218. }
  2219. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2220. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2221. "netbuf %pK offset %d", netbuf,
  2222. sizeof(struct meta_hdr_s));
  2223. return;
  2224. }
  2225. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2226. mhdr->rssi = ts->ack_frame_rssi;
  2227. mhdr->channel = tx_desc->pdev->operating_channel;
  2228. }
  2229. #else
  2230. static
  2231. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2232. struct hal_tx_completion_status *ts)
  2233. {
  2234. }
  2235. #endif
  2236. /**
  2237. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2238. * @peer: Handle to DP peer
  2239. * @ts: pointer to HAL Tx completion stats
  2240. * @length: MSDU length
  2241. *
  2242. * Return: None
  2243. */
  2244. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2245. struct hal_tx_completion_status *ts, uint32_t length)
  2246. {
  2247. struct dp_pdev *pdev = peer->vdev->pdev;
  2248. struct dp_soc *soc = pdev->soc;
  2249. uint8_t mcs, pkt_type;
  2250. mcs = ts->mcs;
  2251. pkt_type = ts->pkt_type;
  2252. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2253. return;
  2254. if (peer->bss_peer) {
  2255. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2256. } else {
  2257. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2258. }
  2259. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2260. DP_STATS_INCC_PKT(peer, tx.tx_success, 1, length,
  2261. (ts->status == HAL_TX_TQM_RR_FRAME_ACKED));
  2262. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2263. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2264. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2265. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2266. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2267. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2268. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2269. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2270. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2271. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2272. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2273. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2274. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2275. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2276. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2277. return;
  2278. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2279. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2280. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2281. if (!(soc->process_tx_status))
  2282. return;
  2283. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2284. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2285. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2286. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2287. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2288. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2289. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2290. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2291. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2292. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2293. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2294. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2295. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2296. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2297. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2298. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2299. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2300. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2301. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2302. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2303. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2304. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2305. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2306. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2307. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2308. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2309. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2310. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2311. soc->cdp_soc.ol_ops->update_dp_stats(pdev->ctrl_pdev,
  2312. &peer->stats, ts->peer_id,
  2313. UPDATE_PEER_STATS);
  2314. }
  2315. }
  2316. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2317. /**
  2318. * dp_tx_flow_pool_lock() - take flow pool lock
  2319. * @soc: core txrx main context
  2320. * @tx_desc: tx desc
  2321. *
  2322. * Return: None
  2323. */
  2324. static inline
  2325. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2326. struct dp_tx_desc_s *tx_desc)
  2327. {
  2328. struct dp_tx_desc_pool_s *pool;
  2329. uint8_t desc_pool_id;
  2330. desc_pool_id = tx_desc->pool_id;
  2331. pool = &soc->tx_desc[desc_pool_id];
  2332. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2333. }
  2334. /**
  2335. * dp_tx_flow_pool_unlock() - release flow pool lock
  2336. * @soc: core txrx main context
  2337. * @tx_desc: tx desc
  2338. *
  2339. * Return: None
  2340. */
  2341. static inline
  2342. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2343. struct dp_tx_desc_s *tx_desc)
  2344. {
  2345. struct dp_tx_desc_pool_s *pool;
  2346. uint8_t desc_pool_id;
  2347. desc_pool_id = tx_desc->pool_id;
  2348. pool = &soc->tx_desc[desc_pool_id];
  2349. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2350. }
  2351. #else
  2352. static inline
  2353. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2354. {
  2355. }
  2356. static inline
  2357. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2358. {
  2359. }
  2360. #endif
  2361. /**
  2362. * dp_tx_notify_completion() - Notify tx completion for this desc
  2363. * @soc: core txrx main context
  2364. * @tx_desc: tx desc
  2365. * @netbuf: buffer
  2366. *
  2367. * Return: none
  2368. */
  2369. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2370. struct dp_tx_desc_s *tx_desc,
  2371. qdf_nbuf_t netbuf)
  2372. {
  2373. void *osif_dev;
  2374. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2375. qdf_assert(tx_desc);
  2376. dp_tx_flow_pool_lock(soc, tx_desc);
  2377. if (!tx_desc->vdev ||
  2378. !tx_desc->vdev->osif_vdev) {
  2379. dp_tx_flow_pool_unlock(soc, tx_desc);
  2380. return;
  2381. }
  2382. osif_dev = tx_desc->vdev->osif_vdev;
  2383. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2384. dp_tx_flow_pool_unlock(soc, tx_desc);
  2385. if (tx_compl_cbk)
  2386. tx_compl_cbk(netbuf, osif_dev);
  2387. }
  2388. /**
  2389. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2390. * @tx_desc: software descriptor head pointer
  2391. * @length: packet length
  2392. *
  2393. * Return: none
  2394. */
  2395. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2396. uint32_t length)
  2397. {
  2398. struct hal_tx_completion_status ts;
  2399. struct dp_soc *soc = NULL;
  2400. struct dp_vdev *vdev = tx_desc->vdev;
  2401. struct dp_peer *peer = NULL;
  2402. struct ether_header *eh =
  2403. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2404. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2405. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2406. "-------------------- \n"
  2407. "Tx Completion Stats: \n"
  2408. "-------------------- \n"
  2409. "ack_frame_rssi = %d \n"
  2410. "first_msdu = %d \n"
  2411. "last_msdu = %d \n"
  2412. "msdu_part_of_amsdu = %d \n"
  2413. "rate_stats valid = %d \n"
  2414. "bw = %d \n"
  2415. "pkt_type = %d \n"
  2416. "stbc = %d \n"
  2417. "ldpc = %d \n"
  2418. "sgi = %d \n"
  2419. "mcs = %d \n"
  2420. "ofdma = %d \n"
  2421. "tones_in_ru = %d \n"
  2422. "tsf = %d \n"
  2423. "ppdu_id = %d \n"
  2424. "transmit_cnt = %d \n"
  2425. "tid = %d \n"
  2426. "peer_id = %d ",
  2427. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2428. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2429. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2430. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2431. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2432. ts.peer_id);
  2433. if (!vdev) {
  2434. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2435. "invalid vdev");
  2436. goto out;
  2437. }
  2438. soc = vdev->pdev->soc;
  2439. /* Update SoC level stats */
  2440. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2441. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2442. /* Update per-packet stats */
  2443. if (qdf_unlikely(vdev->mesh_vdev) &&
  2444. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2445. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2446. /* Update peer level stats */
  2447. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2448. if (!peer) {
  2449. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2450. "invalid peer");
  2451. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2452. goto out;
  2453. }
  2454. if (qdf_likely(peer->vdev->tx_encap_type ==
  2455. htt_cmn_pkt_type_ethernet)) {
  2456. if (peer->bss_peer && IEEE80211_IS_BROADCAST(eh->ether_dhost))
  2457. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2458. }
  2459. dp_tx_update_peer_stats(peer, &ts, length);
  2460. out:
  2461. return;
  2462. }
  2463. /**
  2464. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2465. * @soc: core txrx main context
  2466. * @comp_head: software descriptor head pointer
  2467. *
  2468. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2469. * and release the software descriptors after processing is complete
  2470. *
  2471. * Return: none
  2472. */
  2473. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2474. struct dp_tx_desc_s *comp_head)
  2475. {
  2476. struct dp_tx_desc_s *desc;
  2477. struct dp_tx_desc_s *next;
  2478. struct hal_tx_completion_status ts = {0};
  2479. uint32_t length;
  2480. struct dp_peer *peer;
  2481. DP_HIST_INIT();
  2482. desc = comp_head;
  2483. while (desc) {
  2484. hal_tx_comp_get_status(&desc->comp, &ts);
  2485. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2486. length = qdf_nbuf_len(desc->nbuf);
  2487. /* check tx completion notification */
  2488. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(desc->nbuf))
  2489. dp_tx_notify_completion(soc, desc, desc->nbuf);
  2490. dp_tx_comp_process_tx_status(desc, length);
  2491. DPTRACE(qdf_dp_trace_ptr
  2492. (desc->nbuf,
  2493. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2494. QDF_TRACE_DEFAULT_PDEV_ID,
  2495. qdf_nbuf_data_addr(desc->nbuf),
  2496. sizeof(qdf_nbuf_data(desc->nbuf)),
  2497. desc->id, ts.status)
  2498. );
  2499. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2500. if (!(desc->msdu_ext_desc) && (dp_get_completion_indication_for_stack(soc,
  2501. desc->pdev, ts.peer_id, ts.ppdu_id,
  2502. ts.first_msdu, ts.last_msdu,
  2503. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2504. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2505. QDF_DMA_TO_DEVICE);
  2506. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2507. ts.ppdu_id, desc->nbuf);
  2508. } else {
  2509. dp_tx_comp_free_buf(soc, desc);
  2510. }
  2511. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2512. next = desc->next;
  2513. dp_tx_desc_release(desc, desc->pool_id);
  2514. desc = next;
  2515. }
  2516. DP_TX_HIST_STATS_PER_PDEV();
  2517. }
  2518. /**
  2519. * dp_tx_comp_handler() - Tx completion handler
  2520. * @soc: core txrx main context
  2521. * @ring_id: completion ring id
  2522. * @quota: No. of packets/descriptors that can be serviced in one loop
  2523. *
  2524. * This function will collect hardware release ring element contents and
  2525. * handle descriptor contents. Based on contents, free packet or handle error
  2526. * conditions
  2527. *
  2528. * Return: none
  2529. */
  2530. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2531. {
  2532. void *tx_comp_hal_desc;
  2533. uint8_t buffer_src;
  2534. uint8_t pool_id;
  2535. uint32_t tx_desc_id;
  2536. struct dp_tx_desc_s *tx_desc = NULL;
  2537. struct dp_tx_desc_s *head_desc = NULL;
  2538. struct dp_tx_desc_s *tail_desc = NULL;
  2539. uint32_t num_processed;
  2540. uint32_t count;
  2541. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2542. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2543. "%s %d : HAL RING Access Failed -- %pK",
  2544. __func__, __LINE__, hal_srng);
  2545. return 0;
  2546. }
  2547. num_processed = 0;
  2548. count = 0;
  2549. /* Find head descriptor from completion ring */
  2550. while (qdf_likely(tx_comp_hal_desc =
  2551. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2552. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2553. /* If this buffer was not released by TQM or FW, then it is not
  2554. * Tx completion indication, assert */
  2555. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2556. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2557. QDF_TRACE(QDF_MODULE_ID_DP,
  2558. QDF_TRACE_LEVEL_FATAL,
  2559. "Tx comp release_src != TQM | FW");
  2560. qdf_assert_always(0);
  2561. }
  2562. /* Get descriptor id */
  2563. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2564. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2565. DP_TX_DESC_ID_POOL_OS;
  2566. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2567. continue;
  2568. /* Find Tx descriptor */
  2569. tx_desc = dp_tx_desc_find(soc, pool_id,
  2570. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2571. DP_TX_DESC_ID_PAGE_OS,
  2572. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2573. DP_TX_DESC_ID_OFFSET_OS);
  2574. /*
  2575. * If the release source is FW, process the HTT status
  2576. */
  2577. if (qdf_unlikely(buffer_src ==
  2578. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2579. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2580. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2581. htt_tx_status);
  2582. dp_tx_process_htt_completion(tx_desc,
  2583. htt_tx_status);
  2584. } else {
  2585. /* Pool id is not matching. Error */
  2586. if (tx_desc->pool_id != pool_id) {
  2587. QDF_TRACE(QDF_MODULE_ID_DP,
  2588. QDF_TRACE_LEVEL_FATAL,
  2589. "Tx Comp pool id %d not matched %d",
  2590. pool_id, tx_desc->pool_id);
  2591. qdf_assert_always(0);
  2592. }
  2593. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2594. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2595. QDF_TRACE(QDF_MODULE_ID_DP,
  2596. QDF_TRACE_LEVEL_FATAL,
  2597. "Txdesc invalid, flgs = %x,id = %d",
  2598. tx_desc->flags, tx_desc_id);
  2599. qdf_assert_always(0);
  2600. }
  2601. /* First ring descriptor on the cycle */
  2602. if (!head_desc) {
  2603. head_desc = tx_desc;
  2604. tail_desc = tx_desc;
  2605. }
  2606. tail_desc->next = tx_desc;
  2607. tx_desc->next = NULL;
  2608. tail_desc = tx_desc;
  2609. /* Collect hw completion contents */
  2610. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2611. &tx_desc->comp, 1);
  2612. }
  2613. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2614. /* Decrement PM usage count if the packet has been sent.*/
  2615. hif_pm_runtime_put(soc->hif_handle);
  2616. /*
  2617. * Processed packet count is more than given quota
  2618. * stop to processing
  2619. */
  2620. if ((num_processed >= quota))
  2621. break;
  2622. count++;
  2623. }
  2624. hal_srng_access_end(soc->hal_soc, hal_srng);
  2625. /* Process the reaped descriptors */
  2626. if (head_desc)
  2627. dp_tx_comp_process_desc(soc, head_desc);
  2628. return num_processed;
  2629. }
  2630. #ifdef CONVERGED_TDLS_ENABLE
  2631. /**
  2632. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2633. *
  2634. * @data_vdev - which vdev should transmit the tx data frames
  2635. * @tx_spec - what non-standard handling to apply to the tx data frames
  2636. * @msdu_list - NULL-terminated list of tx MSDUs
  2637. *
  2638. * Return: NULL on success,
  2639. * nbuf when it fails to send
  2640. */
  2641. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2642. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2643. {
  2644. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2645. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2646. vdev->is_tdls_frame = true;
  2647. return dp_tx_send(vdev_handle, msdu_list);
  2648. }
  2649. #endif
  2650. /**
  2651. * dp_tx_vdev_attach() - attach vdev to dp tx
  2652. * @vdev: virtual device instance
  2653. *
  2654. * Return: QDF_STATUS_SUCCESS: success
  2655. * QDF_STATUS_E_RESOURCES: Error return
  2656. */
  2657. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2658. {
  2659. /*
  2660. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2661. */
  2662. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2663. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2664. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2665. vdev->vdev_id);
  2666. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2667. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2668. /*
  2669. * Set HTT Extension Valid bit to 0 by default
  2670. */
  2671. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2672. dp_tx_vdev_update_search_flags(vdev);
  2673. return QDF_STATUS_SUCCESS;
  2674. }
  2675. /**
  2676. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2677. * @vdev: virtual device instance
  2678. *
  2679. * Return: void
  2680. *
  2681. */
  2682. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2683. {
  2684. /*
  2685. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2686. * for TDLS link
  2687. *
  2688. * Enable AddrY (SA based search) only for non-WDS STA and
  2689. * ProxySTA VAP modes.
  2690. *
  2691. * In all other VAP modes, only DA based search should be
  2692. * enabled
  2693. */
  2694. if (vdev->opmode == wlan_op_mode_sta &&
  2695. vdev->tdls_link_connected)
  2696. vdev->hal_desc_addr_search_flags =
  2697. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2698. else if ((vdev->opmode == wlan_op_mode_sta &&
  2699. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2700. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2701. else
  2702. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2703. }
  2704. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2705. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2706. {
  2707. }
  2708. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2709. /* dp_tx_desc_flush() - release resources associated
  2710. * to tx_desc
  2711. * @vdev: virtual device instance
  2712. *
  2713. * This function will free all outstanding Tx buffers,
  2714. * including ME buffer for which either free during
  2715. * completion didn't happened or completion is not
  2716. * received.
  2717. */
  2718. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2719. {
  2720. uint8_t i, num_pool;
  2721. uint32_t j;
  2722. uint32_t num_desc;
  2723. struct dp_soc *soc = vdev->pdev->soc;
  2724. struct dp_tx_desc_s *tx_desc = NULL;
  2725. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2726. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2727. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2728. for (i = 0; i < num_pool; i++) {
  2729. for (j = 0; j < num_desc; j++) {
  2730. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2731. if (tx_desc_pool &&
  2732. tx_desc_pool->desc_pages.cacheable_pages) {
  2733. tx_desc = dp_tx_desc_find(soc, i,
  2734. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2735. DP_TX_DESC_ID_PAGE_OS,
  2736. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2737. DP_TX_DESC_ID_OFFSET_OS);
  2738. if (tx_desc && (tx_desc->vdev == vdev) &&
  2739. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2740. dp_tx_comp_free_buf(soc, tx_desc);
  2741. dp_tx_desc_release(tx_desc, i);
  2742. }
  2743. }
  2744. }
  2745. }
  2746. }
  2747. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2748. /**
  2749. * dp_tx_vdev_detach() - detach vdev from dp tx
  2750. * @vdev: virtual device instance
  2751. *
  2752. * Return: QDF_STATUS_SUCCESS: success
  2753. * QDF_STATUS_E_RESOURCES: Error return
  2754. */
  2755. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2756. {
  2757. dp_tx_desc_flush(vdev);
  2758. return QDF_STATUS_SUCCESS;
  2759. }
  2760. /**
  2761. * dp_tx_pdev_attach() - attach pdev to dp tx
  2762. * @pdev: physical device instance
  2763. *
  2764. * Return: QDF_STATUS_SUCCESS: success
  2765. * QDF_STATUS_E_RESOURCES: Error return
  2766. */
  2767. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2768. {
  2769. struct dp_soc *soc = pdev->soc;
  2770. /* Initialize Flow control counters */
  2771. qdf_atomic_init(&pdev->num_tx_exception);
  2772. qdf_atomic_init(&pdev->num_tx_outstanding);
  2773. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2774. /* Initialize descriptors in TCL Ring */
  2775. hal_tx_init_data_ring(soc->hal_soc,
  2776. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2777. }
  2778. return QDF_STATUS_SUCCESS;
  2779. }
  2780. /**
  2781. * dp_tx_pdev_detach() - detach pdev from dp tx
  2782. * @pdev: physical device instance
  2783. *
  2784. * Return: QDF_STATUS_SUCCESS: success
  2785. * QDF_STATUS_E_RESOURCES: Error return
  2786. */
  2787. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2788. {
  2789. dp_tx_me_exit(pdev);
  2790. return QDF_STATUS_SUCCESS;
  2791. }
  2792. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2793. /* Pools will be allocated dynamically */
  2794. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2795. int num_desc)
  2796. {
  2797. uint8_t i;
  2798. for (i = 0; i < num_pool; i++) {
  2799. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2800. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2801. }
  2802. return 0;
  2803. }
  2804. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2805. {
  2806. uint8_t i;
  2807. for (i = 0; i < num_pool; i++)
  2808. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2809. }
  2810. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2811. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2812. int num_desc)
  2813. {
  2814. uint8_t i;
  2815. /* Allocate software Tx descriptor pools */
  2816. for (i = 0; i < num_pool; i++) {
  2817. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2818. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2819. "%s Tx Desc Pool alloc %d failed %pK",
  2820. __func__, i, soc);
  2821. return ENOMEM;
  2822. }
  2823. }
  2824. return 0;
  2825. }
  2826. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2827. {
  2828. uint8_t i;
  2829. for (i = 0; i < num_pool; i++) {
  2830. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2831. if (dp_tx_desc_pool_free(soc, i)) {
  2832. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2833. "%s Tx Desc Pool Free failed", __func__);
  2834. }
  2835. }
  2836. }
  2837. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2838. /**
  2839. * dp_tx_soc_detach() - detach soc from dp tx
  2840. * @soc: core txrx main context
  2841. *
  2842. * This function will detach dp tx into main device context
  2843. * will free dp tx resource and initialize resources
  2844. *
  2845. * Return: QDF_STATUS_SUCCESS: success
  2846. * QDF_STATUS_E_RESOURCES: Error return
  2847. */
  2848. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2849. {
  2850. uint8_t num_pool;
  2851. uint16_t num_desc;
  2852. uint16_t num_ext_desc;
  2853. uint8_t i;
  2854. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2855. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2856. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2857. dp_tx_flow_control_deinit(soc);
  2858. dp_tx_delete_static_pools(soc, num_pool);
  2859. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2860. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  2861. __func__, num_pool, num_desc);
  2862. for (i = 0; i < num_pool; i++) {
  2863. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2864. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2865. "%s Tx Ext Desc Pool Free failed",
  2866. __func__);
  2867. return QDF_STATUS_E_RESOURCES;
  2868. }
  2869. }
  2870. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2871. "%s MSDU Ext Desc Pool %d Free descs = %d",
  2872. __func__, num_pool, num_ext_desc);
  2873. for (i = 0; i < num_pool; i++) {
  2874. dp_tx_tso_desc_pool_free(soc, i);
  2875. }
  2876. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2877. "%s TSO Desc Pool %d Free descs = %d",
  2878. __func__, num_pool, num_desc);
  2879. for (i = 0; i < num_pool; i++)
  2880. dp_tx_tso_num_seg_pool_free(soc, i);
  2881. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2882. "%s TSO Num of seg Desc Pool %d Free descs = %d",
  2883. __func__, num_pool, num_desc);
  2884. return QDF_STATUS_SUCCESS;
  2885. }
  2886. /**
  2887. * dp_tx_soc_attach() - attach soc to dp tx
  2888. * @soc: core txrx main context
  2889. *
  2890. * This function will attach dp tx into main device context
  2891. * will allocate dp tx resource and initialize resources
  2892. *
  2893. * Return: QDF_STATUS_SUCCESS: success
  2894. * QDF_STATUS_E_RESOURCES: Error return
  2895. */
  2896. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2897. {
  2898. uint8_t i;
  2899. uint8_t num_pool;
  2900. uint32_t num_desc;
  2901. uint32_t num_ext_desc;
  2902. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2903. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2904. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2905. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2906. goto fail;
  2907. dp_tx_flow_control_init(soc);
  2908. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2909. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  2910. __func__, num_pool, num_desc);
  2911. /* Allocate extension tx descriptor pools */
  2912. for (i = 0; i < num_pool; i++) {
  2913. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2914. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2915. "MSDU Ext Desc Pool alloc %d failed %pK",
  2916. i, soc);
  2917. goto fail;
  2918. }
  2919. }
  2920. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2921. "%s MSDU Ext Desc Alloc %d, descs = %d",
  2922. __func__, num_pool, num_ext_desc);
  2923. for (i = 0; i < num_pool; i++) {
  2924. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2925. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2926. "TSO Desc Pool alloc %d failed %pK",
  2927. i, soc);
  2928. goto fail;
  2929. }
  2930. }
  2931. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2932. "%s TSO Desc Alloc %d, descs = %d",
  2933. __func__, num_pool, num_desc);
  2934. for (i = 0; i < num_pool; i++) {
  2935. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2936. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2937. "TSO Num of seg Pool alloc %d failed %pK",
  2938. i, soc);
  2939. goto fail;
  2940. }
  2941. }
  2942. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2943. "%s TSO Num of seg pool Alloc %d, descs = %d",
  2944. __func__, num_pool, num_desc);
  2945. /* Initialize descriptors in TCL Rings */
  2946. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2947. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2948. hal_tx_init_data_ring(soc->hal_soc,
  2949. soc->tcl_data_ring[i].hal_srng);
  2950. }
  2951. }
  2952. /*
  2953. * todo - Add a runtime config option to enable this.
  2954. */
  2955. /*
  2956. * Due to multiple issues on NPR EMU, enable it selectively
  2957. * only for NPR EMU, should be removed, once NPR platforms
  2958. * are stable.
  2959. */
  2960. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2961. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2962. "%s HAL Tx init Success", __func__);
  2963. return QDF_STATUS_SUCCESS;
  2964. fail:
  2965. /* Detach will take care of freeing only allocated resources */
  2966. dp_tx_soc_detach(soc);
  2967. return QDF_STATUS_E_RESOURCES;
  2968. }
  2969. /*
  2970. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2971. * pdev: pointer to DP PDEV structure
  2972. * seg_info_head: Pointer to the head of list
  2973. *
  2974. * return: void
  2975. */
  2976. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2977. struct dp_tx_seg_info_s *seg_info_head)
  2978. {
  2979. struct dp_tx_me_buf_t *mc_uc_buf;
  2980. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2981. qdf_nbuf_t nbuf = NULL;
  2982. uint64_t phy_addr;
  2983. while (seg_info_head) {
  2984. nbuf = seg_info_head->nbuf;
  2985. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2986. seg_info_head->frags[0].vaddr;
  2987. phy_addr = seg_info_head->frags[0].paddr_hi;
  2988. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2989. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2990. phy_addr,
  2991. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2992. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2993. qdf_nbuf_free(nbuf);
  2994. seg_info_new = seg_info_head;
  2995. seg_info_head = seg_info_head->next;
  2996. qdf_mem_free(seg_info_new);
  2997. }
  2998. }
  2999. /**
  3000. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3001. * @vdev: DP VDEV handle
  3002. * @nbuf: Multicast nbuf
  3003. * @newmac: Table of the clients to which packets have to be sent
  3004. * @new_mac_cnt: No of clients
  3005. *
  3006. * return: no of converted packets
  3007. */
  3008. uint16_t
  3009. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3010. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  3011. {
  3012. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3013. struct dp_pdev *pdev = vdev->pdev;
  3014. struct ether_header *eh;
  3015. uint8_t *data;
  3016. uint16_t len;
  3017. /* reference to frame dst addr */
  3018. uint8_t *dstmac;
  3019. /* copy of original frame src addr */
  3020. uint8_t srcmac[DP_MAC_ADDR_LEN];
  3021. /* local index into newmac */
  3022. uint8_t new_mac_idx = 0;
  3023. struct dp_tx_me_buf_t *mc_uc_buf;
  3024. qdf_nbuf_t nbuf_clone;
  3025. struct dp_tx_msdu_info_s msdu_info;
  3026. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3027. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3028. struct dp_tx_seg_info_s *seg_info_new;
  3029. struct dp_tx_frag_info_s data_frag;
  3030. qdf_dma_addr_t paddr_data;
  3031. qdf_dma_addr_t paddr_mcbuf = 0;
  3032. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  3033. QDF_STATUS status;
  3034. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  3035. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3036. eh = (struct ether_header *) nbuf;
  3037. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  3038. len = qdf_nbuf_len(nbuf);
  3039. data = qdf_nbuf_data(nbuf);
  3040. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3041. QDF_DMA_TO_DEVICE);
  3042. if (status) {
  3043. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3044. "Mapping failure Error:%d", status);
  3045. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3046. qdf_nbuf_free(nbuf);
  3047. return 1;
  3048. }
  3049. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3050. /*preparing data fragment*/
  3051. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3052. data_frag.paddr_lo = (uint32_t)paddr_data;
  3053. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3054. data_frag.len = len - DP_MAC_ADDR_LEN;
  3055. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3056. dstmac = newmac[new_mac_idx];
  3057. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3058. "added mac addr (%pM)", dstmac);
  3059. /* Check for NULL Mac Address */
  3060. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3061. continue;
  3062. /* frame to self mac. skip */
  3063. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3064. continue;
  3065. /*
  3066. * TODO: optimize to avoid malloc in per-packet path
  3067. * For eg. seg_pool can be made part of vdev structure
  3068. */
  3069. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3070. if (!seg_info_new) {
  3071. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3072. "alloc failed");
  3073. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3074. goto fail_seg_alloc;
  3075. }
  3076. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3077. if (mc_uc_buf == NULL)
  3078. goto fail_buf_alloc;
  3079. /*
  3080. * TODO: Check if we need to clone the nbuf
  3081. * Or can we just use the reference for all cases
  3082. */
  3083. if (new_mac_idx < (new_mac_cnt - 1)) {
  3084. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3085. if (nbuf_clone == NULL) {
  3086. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3087. goto fail_clone;
  3088. }
  3089. } else {
  3090. /*
  3091. * Update the ref
  3092. * to account for frame sent without cloning
  3093. */
  3094. qdf_nbuf_ref(nbuf);
  3095. nbuf_clone = nbuf;
  3096. }
  3097. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3098. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3099. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3100. &paddr_mcbuf);
  3101. if (status) {
  3102. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3103. "Mapping failure Error:%d", status);
  3104. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3105. goto fail_map;
  3106. }
  3107. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3108. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3109. seg_info_new->frags[0].paddr_hi =
  3110. ((uint64_t) paddr_mcbuf >> 32);
  3111. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3112. seg_info_new->frags[1] = data_frag;
  3113. seg_info_new->nbuf = nbuf_clone;
  3114. seg_info_new->frag_cnt = 2;
  3115. seg_info_new->total_len = len;
  3116. seg_info_new->next = NULL;
  3117. if (seg_info_head == NULL)
  3118. seg_info_head = seg_info_new;
  3119. else
  3120. seg_info_tail->next = seg_info_new;
  3121. seg_info_tail = seg_info_new;
  3122. }
  3123. if (!seg_info_head) {
  3124. goto free_return;
  3125. }
  3126. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3127. msdu_info.num_seg = new_mac_cnt;
  3128. msdu_info.frm_type = dp_tx_frm_me;
  3129. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3130. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3131. while (seg_info_head->next) {
  3132. seg_info_new = seg_info_head;
  3133. seg_info_head = seg_info_head->next;
  3134. qdf_mem_free(seg_info_new);
  3135. }
  3136. qdf_mem_free(seg_info_head);
  3137. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3138. qdf_nbuf_free(nbuf);
  3139. return new_mac_cnt;
  3140. fail_map:
  3141. qdf_nbuf_free(nbuf_clone);
  3142. fail_clone:
  3143. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3144. fail_buf_alloc:
  3145. qdf_mem_free(seg_info_new);
  3146. fail_seg_alloc:
  3147. dp_tx_me_mem_free(pdev, seg_info_head);
  3148. free_return:
  3149. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3150. qdf_nbuf_free(nbuf);
  3151. return 1;
  3152. }