qcs405.c 239 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/i2c.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/input.h>
  22. #include <linux/of_device.h>
  23. #include <linux/pm_qos.h>
  24. #include <linux/regulator/consumer.h>
  25. #include <sound/core.h>
  26. #include <sound/soc.h>
  27. #include <sound/soc-dapm.h>
  28. #include <sound/pcm.h>
  29. #include <sound/pcm_params.h>
  30. #include <sound/info.h>
  31. #include <dsp/audio_notifier.h>
  32. #include <dsp/q6afe-v2.h>
  33. #include <dsp/q6core.h>
  34. #include <dsp/msm_mdf.h>
  35. #include "device_event.h"
  36. #include "msm-pcm-routing-v2.h"
  37. #include "codecs/msm-cdc-pinctrl.h"
  38. #include "codecs/wcd9335.h"
  39. #include "codecs/wsa881x.h"
  40. #include "codecs/csra66x0/csra66x0.h"
  41. #include <dt-bindings/sound/audio-codec-port-types.h>
  42. #include "codecs/bolero/bolero-cdc.h"
  43. #include "codecs/bolero/wsa-macro.h"
  44. #define DRV_NAME "qcs405-asoc-snd"
  45. #define __CHIPSET__ "QCS405 "
  46. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  47. #define DEV_NAME_STR_LEN 32
  48. #define SAMPLING_RATE_8KHZ 8000
  49. #define SAMPLING_RATE_11P025KHZ 11025
  50. #define SAMPLING_RATE_16KHZ 16000
  51. #define SAMPLING_RATE_22P05KHZ 22050
  52. #define SAMPLING_RATE_32KHZ 32000
  53. #define SAMPLING_RATE_44P1KHZ 44100
  54. #define SAMPLING_RATE_48KHZ 48000
  55. #define SAMPLING_RATE_88P2KHZ 88200
  56. #define SAMPLING_RATE_96KHZ 96000
  57. #define SAMPLING_RATE_176P4KHZ 176400
  58. #define SAMPLING_RATE_192KHZ 192000
  59. #define SAMPLING_RATE_352P8KHZ 352800
  60. #define SAMPLING_RATE_384KHZ 384000
  61. #define SPDIF_TX_CORE_CLK_163_P84_MHZ 163840000
  62. #define TLMM_EAST_SPARE 0x07BA0000
  63. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  64. #define WSA8810_NAME_1 "wsa881x.20170211"
  65. #define WSA8810_NAME_2 "wsa881x.20170212"
  66. #define WCN_CDC_SLIM_RX_CH_MAX 2
  67. #define WCN_CDC_SLIM_TX_CH_MAX 4
  68. #define TDM_CHANNEL_MAX 8
  69. #define BT_SLIM_TX SLIM_TX_9
  70. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  71. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  72. enum {
  73. SLIM_RX_0 = 0,
  74. SLIM_RX_1,
  75. SLIM_RX_2,
  76. SLIM_RX_3,
  77. SLIM_RX_4,
  78. SLIM_RX_5,
  79. SLIM_RX_6,
  80. SLIM_RX_7,
  81. SLIM_RX_MAX,
  82. };
  83. enum {
  84. SLIM_TX_0 = 0,
  85. SLIM_TX_1,
  86. SLIM_TX_2,
  87. SLIM_TX_3,
  88. SLIM_TX_4,
  89. SLIM_TX_5,
  90. SLIM_TX_6,
  91. SLIM_TX_7,
  92. SLIM_TX_8,
  93. SLIM_TX_9,
  94. SLIM_TX_MAX,
  95. };
  96. enum {
  97. PRIM_MI2S = 0,
  98. SEC_MI2S,
  99. TERT_MI2S,
  100. QUAT_MI2S,
  101. QUIN_MI2S,
  102. SEN_MI2S,
  103. MI2S_MAX,
  104. };
  105. enum {
  106. PRIM_AUX_PCM = 0,
  107. SEC_AUX_PCM,
  108. TERT_AUX_PCM,
  109. QUAT_AUX_PCM,
  110. QUIN_AUX_PCM,
  111. SEN_AUX_PCM,
  112. AUX_PCM_MAX,
  113. };
  114. enum {
  115. WSA_CDC_DMA_RX_0 = 0,
  116. WSA_CDC_DMA_RX_1,
  117. CDC_DMA_RX_MAX,
  118. };
  119. enum {
  120. WSA_CDC_DMA_TX_0 = 0,
  121. WSA_CDC_DMA_TX_1,
  122. WSA_CDC_DMA_TX_2,
  123. VA_CDC_DMA_TX_0,
  124. VA_CDC_DMA_TX_1,
  125. CDC_DMA_TX_MAX,
  126. };
  127. enum {
  128. PRIM_SPDIF_RX = 0,
  129. SEC_SPDIF_RX,
  130. SPDIF_RX_MAX,
  131. };
  132. enum {
  133. PRIM_SPDIF_TX = 0,
  134. SEC_SPDIF_TX,
  135. SPDIF_TX_MAX,
  136. };
  137. struct mi2s_conf {
  138. struct mutex lock;
  139. u32 ref_cnt;
  140. u32 msm_is_mi2s_master;
  141. };
  142. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  143. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  144. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  145. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  146. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  147. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT,
  148. Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT
  149. };
  150. struct dev_config {
  151. u32 sample_rate;
  152. u32 bit_format;
  153. u32 channels;
  154. };
  155. struct msm_wsa881x_dev_info {
  156. struct device_node *of_node;
  157. u32 index;
  158. };
  159. struct msm_csra66x0_dev_info {
  160. struct device_node *of_node;
  161. u32 index;
  162. };
  163. struct msm_asoc_mach_data {
  164. struct snd_info_entry *codec_root;
  165. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  166. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  167. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  168. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  169. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  170. int dmic_01_gpio_cnt;
  171. int dmic_23_gpio_cnt;
  172. int dmic_45_gpio_cnt;
  173. int dmic_67_gpio_cnt;
  174. struct regulator *tdm_micb_supply;
  175. u32 tdm_micb_voltage;
  176. u32 tdm_micb_current;
  177. bool codec_is_csra;
  178. };
  179. struct msm_asoc_wcd93xx_codec {
  180. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  181. enum afe_config_type config_type);
  182. };
  183. static const char *const pin_states[] = {"sleep", "i2s-active",
  184. "tdm-active"};
  185. enum {
  186. TDM_0 = 0,
  187. TDM_1,
  188. TDM_2,
  189. TDM_3,
  190. TDM_4,
  191. TDM_5,
  192. TDM_6,
  193. TDM_7,
  194. TDM_PORT_MAX,
  195. };
  196. enum {
  197. TDM_PRI = 0,
  198. TDM_SEC,
  199. TDM_TERT,
  200. TDM_QUAT,
  201. TDM_QUIN,
  202. TDM_INTERFACE_MAX,
  203. };
  204. struct tdm_port {
  205. u32 mode;
  206. u32 channel;
  207. };
  208. /* TDM default config */
  209. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  210. { /* PRI TDM */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  219. },
  220. { /* SEC TDM */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  229. },
  230. { /* TERT TDM */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  239. },
  240. { /* QUAT TDM */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  249. },
  250. { /* QUIN TDM */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  259. }
  260. };
  261. /* TDM default config */
  262. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  263. { /* PRI TDM */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  272. },
  273. { /* SEC TDM */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  282. },
  283. { /* TERT TDM */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  292. },
  293. { /* QUAT TDM */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  302. },
  303. { /* QUIN TDM */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  312. }
  313. };
  314. /* Default configuration of slimbus channels */
  315. static struct dev_config slim_rx_cfg[] = {
  316. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  318. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  319. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. };
  325. static struct dev_config slim_tx_cfg[] = {
  326. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  327. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  328. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  329. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  330. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  331. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  332. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  333. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  334. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  335. [SLIM_TX_9] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  336. };
  337. /* Default configuration of Codec DMA Interface Tx */
  338. static struct dev_config cdc_dma_rx_cfg[] = {
  339. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  340. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  341. };
  342. /* Default configuration of Codec DMA Interface Rx */
  343. static struct dev_config cdc_dma_tx_cfg[] = {
  344. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  345. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  346. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  347. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  348. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  349. };
  350. static struct dev_config usb_rx_cfg = {
  351. .sample_rate = SAMPLING_RATE_48KHZ,
  352. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  353. .channels = 2,
  354. };
  355. static struct dev_config usb_tx_cfg = {
  356. .sample_rate = SAMPLING_RATE_48KHZ,
  357. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  358. .channels = 1,
  359. };
  360. static struct dev_config proxy_rx_cfg = {
  361. .sample_rate = SAMPLING_RATE_48KHZ,
  362. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  363. .channels = 2,
  364. };
  365. /* Default configuration of MI2S channels */
  366. static struct dev_config mi2s_rx_cfg[] = {
  367. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  368. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  369. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  371. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  372. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  373. };
  374. /* Default configuration of SPDIF channels */
  375. static struct dev_config spdif_rx_cfg[] = {
  376. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  377. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  378. };
  379. static struct dev_config spdif_tx_cfg[] = {
  380. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  381. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  382. };
  383. static struct dev_config mi2s_tx_cfg[] = {
  384. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  385. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  389. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  390. };
  391. static struct dev_config aux_pcm_rx_cfg[] = {
  392. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  393. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. };
  399. static struct dev_config aux_pcm_tx_cfg[] = {
  400. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  401. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  402. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  403. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  404. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  405. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  406. };
  407. static int msm_vi_feed_tx_ch = 2;
  408. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  409. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  410. "Five", "Six", "Seven",
  411. "Eight"};
  412. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  413. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  414. "S32_LE"};
  415. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  416. "KHZ_32", "KHZ_44P1", "KHZ_48",
  417. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  418. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  419. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  420. "KHZ_44P1", "KHZ_48",
  421. "KHZ_88P2", "KHZ_96"};
  422. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  423. "Five", "Six", "Seven",
  424. "Eight"};
  425. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  426. "Six", "Seven", "Eight"};
  427. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  428. "KHZ_16", "KHZ_22P05",
  429. "KHZ_32", "KHZ_44P1", "KHZ_48",
  430. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  431. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  432. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  433. "Five", "Six", "Seven", "Eight"};
  434. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  435. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  436. "KHZ_48", "KHZ_176P4",
  437. "KHZ_352P8"};
  438. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  439. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  440. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  441. "KHZ_48", "KHZ_96", "KHZ_192", "KHZ_384"};
  442. static const char *const mi2s_ch_text[] = {
  443. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  444. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  445. "Fourteen", "Fifteen", "Sixteen"
  446. };
  447. static const char *const qos_text[] = {"Disable", "Enable"};
  448. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  449. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  450. "Five", "Six", "Seven",
  451. "Eight"};
  452. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  453. "KHZ_16", "KHZ_22P05",
  454. "KHZ_32", "KHZ_44P1", "KHZ_48",
  455. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  456. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  457. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  458. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  459. "KHZ_192"};
  460. static const char *spdif_ch_text[] = {"One", "Two"};
  461. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  462. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_sink, bt_sample_rate_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  547. cdc_dma_sample_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  549. cdc_dma_sample_rate_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  551. cdc_dma_sample_rate_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  553. cdc_dma_sample_rate_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  555. cdc_dma_sample_rate_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  557. cdc_dma_sample_rate_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  559. cdc_dma_sample_rate_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  566. static struct platform_device *spdev;
  567. static bool is_initial_boot;
  568. static bool codec_reg_done;
  569. static struct snd_soc_aux_dev *msm_aux_dev;
  570. static struct snd_soc_codec_conf *msm_codec_conf;
  571. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  572. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  573. int enable, bool dapm);
  574. static int msm_wsa881x_init(struct snd_soc_component *component);
  575. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  576. struct snd_ctl_elem_value *ucontrol);
  577. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  578. {"MIC BIAS1", NULL, "MCLK TX"},
  579. {"MIC BIAS2", NULL, "MCLK TX"},
  580. {"MIC BIAS3", NULL, "MCLK TX"},
  581. {"MIC BIAS4", NULL, "MCLK TX"},
  582. };
  583. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  584. {
  585. AFE_API_VERSION_I2S_CONFIG,
  586. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  587. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  588. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  589. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  590. 0,
  591. },
  592. {
  593. AFE_API_VERSION_I2S_CONFIG,
  594. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  595. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  596. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  597. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  598. 0,
  599. },
  600. {
  601. AFE_API_VERSION_I2S_CONFIG,
  602. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  603. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  604. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  605. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  606. 0,
  607. },
  608. {
  609. AFE_API_VERSION_I2S_CONFIG,
  610. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  611. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  612. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  613. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  614. 0,
  615. },
  616. {
  617. AFE_API_VERSION_I2S_CONFIG,
  618. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  619. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  620. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  621. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  622. 0,
  623. },
  624. {
  625. AFE_API_VERSION_I2S_CONFIG,
  626. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  627. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  628. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  629. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  630. 0,
  631. }
  632. };
  633. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  634. static int slim_get_sample_rate_val(int sample_rate)
  635. {
  636. int sample_rate_val = 0;
  637. switch (sample_rate) {
  638. case SAMPLING_RATE_8KHZ:
  639. sample_rate_val = 0;
  640. break;
  641. case SAMPLING_RATE_16KHZ:
  642. sample_rate_val = 1;
  643. break;
  644. case SAMPLING_RATE_32KHZ:
  645. sample_rate_val = 2;
  646. break;
  647. case SAMPLING_RATE_44P1KHZ:
  648. sample_rate_val = 3;
  649. break;
  650. case SAMPLING_RATE_48KHZ:
  651. sample_rate_val = 4;
  652. break;
  653. case SAMPLING_RATE_88P2KHZ:
  654. sample_rate_val = 5;
  655. break;
  656. case SAMPLING_RATE_96KHZ:
  657. sample_rate_val = 6;
  658. break;
  659. case SAMPLING_RATE_176P4KHZ:
  660. sample_rate_val = 7;
  661. break;
  662. case SAMPLING_RATE_192KHZ:
  663. sample_rate_val = 8;
  664. break;
  665. case SAMPLING_RATE_352P8KHZ:
  666. sample_rate_val = 9;
  667. break;
  668. case SAMPLING_RATE_384KHZ:
  669. sample_rate_val = 10;
  670. break;
  671. default:
  672. sample_rate_val = 4;
  673. break;
  674. }
  675. return sample_rate_val;
  676. }
  677. static int slim_get_sample_rate(int value)
  678. {
  679. int sample_rate = 0;
  680. switch (value) {
  681. case 0:
  682. sample_rate = SAMPLING_RATE_8KHZ;
  683. break;
  684. case 1:
  685. sample_rate = SAMPLING_RATE_16KHZ;
  686. break;
  687. case 2:
  688. sample_rate = SAMPLING_RATE_32KHZ;
  689. break;
  690. case 3:
  691. sample_rate = SAMPLING_RATE_44P1KHZ;
  692. break;
  693. case 4:
  694. sample_rate = SAMPLING_RATE_48KHZ;
  695. break;
  696. case 5:
  697. sample_rate = SAMPLING_RATE_88P2KHZ;
  698. break;
  699. case 6:
  700. sample_rate = SAMPLING_RATE_96KHZ;
  701. break;
  702. case 7:
  703. sample_rate = SAMPLING_RATE_176P4KHZ;
  704. break;
  705. case 8:
  706. sample_rate = SAMPLING_RATE_192KHZ;
  707. break;
  708. case 9:
  709. sample_rate = SAMPLING_RATE_352P8KHZ;
  710. break;
  711. case 10:
  712. sample_rate = SAMPLING_RATE_384KHZ;
  713. break;
  714. default:
  715. sample_rate = SAMPLING_RATE_48KHZ;
  716. break;
  717. }
  718. return sample_rate;
  719. }
  720. static int slim_get_bit_format_val(int bit_format)
  721. {
  722. int val = 0;
  723. switch (bit_format) {
  724. case SNDRV_PCM_FORMAT_S32_LE:
  725. val = 3;
  726. break;
  727. case SNDRV_PCM_FORMAT_S24_3LE:
  728. val = 2;
  729. break;
  730. case SNDRV_PCM_FORMAT_S24_LE:
  731. val = 1;
  732. break;
  733. case SNDRV_PCM_FORMAT_S16_LE:
  734. default:
  735. val = 0;
  736. break;
  737. }
  738. return val;
  739. }
  740. static int slim_get_bit_format(int val)
  741. {
  742. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  743. switch (val) {
  744. case 0:
  745. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  746. break;
  747. case 1:
  748. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  749. break;
  750. case 2:
  751. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  752. break;
  753. case 3:
  754. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  755. break;
  756. default:
  757. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  758. break;
  759. }
  760. return bit_fmt;
  761. }
  762. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  763. {
  764. int port_id = 0;
  765. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  766. port_id = SLIM_RX_0;
  767. } else if (strnstr(kcontrol->id.name,
  768. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  769. port_id = SLIM_RX_2;
  770. } else if (strnstr(kcontrol->id.name,
  771. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  772. port_id = SLIM_RX_5;
  773. } else if (strnstr(kcontrol->id.name,
  774. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  775. port_id = SLIM_RX_6;
  776. } else if (strnstr(kcontrol->id.name,
  777. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  778. port_id = SLIM_TX_0;
  779. } else if (strnstr(kcontrol->id.name,
  780. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  781. port_id = SLIM_TX_1;
  782. } else {
  783. pr_err("%s: unsupported channel: %s",
  784. __func__, kcontrol->id.name);
  785. return -EINVAL;
  786. }
  787. return port_id;
  788. }
  789. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  790. struct snd_ctl_elem_value *ucontrol)
  791. {
  792. int ch_num = slim_get_port_idx(kcontrol);
  793. if (ch_num < 0)
  794. return ch_num;
  795. ucontrol->value.enumerated.item[0] =
  796. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  797. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  798. ch_num, slim_rx_cfg[ch_num].sample_rate,
  799. ucontrol->value.enumerated.item[0]);
  800. return 0;
  801. }
  802. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  803. struct snd_ctl_elem_value *ucontrol)
  804. {
  805. int ch_num = slim_get_port_idx(kcontrol);
  806. if (ch_num < 0)
  807. return ch_num;
  808. slim_rx_cfg[ch_num].sample_rate =
  809. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  810. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  811. ch_num, slim_rx_cfg[ch_num].sample_rate,
  812. ucontrol->value.enumerated.item[0]);
  813. return 0;
  814. }
  815. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  816. struct snd_ctl_elem_value *ucontrol)
  817. {
  818. int ch_num = slim_get_port_idx(kcontrol);
  819. if (ch_num < 0)
  820. return ch_num;
  821. ucontrol->value.enumerated.item[0] =
  822. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  823. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  824. ch_num, slim_tx_cfg[ch_num].sample_rate,
  825. ucontrol->value.enumerated.item[0]);
  826. return 0;
  827. }
  828. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  829. struct snd_ctl_elem_value *ucontrol)
  830. {
  831. int sample_rate = 0;
  832. int ch_num = slim_get_port_idx(kcontrol);
  833. if (ch_num < 0)
  834. return ch_num;
  835. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  836. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  837. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  838. __func__, sample_rate);
  839. return -EINVAL;
  840. }
  841. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  842. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  843. ch_num, slim_tx_cfg[ch_num].sample_rate,
  844. ucontrol->value.enumerated.item[0]);
  845. return 0;
  846. }
  847. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  848. struct snd_ctl_elem_value *ucontrol)
  849. {
  850. int ch_num = slim_get_port_idx(kcontrol);
  851. if (ch_num < 0)
  852. return ch_num;
  853. ucontrol->value.enumerated.item[0] =
  854. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  855. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  856. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  857. ucontrol->value.enumerated.item[0]);
  858. return 0;
  859. }
  860. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  861. struct snd_ctl_elem_value *ucontrol)
  862. {
  863. int ch_num = slim_get_port_idx(kcontrol);
  864. if (ch_num < 0)
  865. return ch_num;
  866. slim_rx_cfg[ch_num].bit_format =
  867. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  868. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  869. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  870. ucontrol->value.enumerated.item[0]);
  871. return 0;
  872. }
  873. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  874. struct snd_ctl_elem_value *ucontrol)
  875. {
  876. int ch_num = slim_get_port_idx(kcontrol);
  877. if (ch_num < 0)
  878. return ch_num;
  879. ucontrol->value.enumerated.item[0] =
  880. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  881. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  882. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  883. ucontrol->value.enumerated.item[0]);
  884. return 0;
  885. }
  886. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  887. struct snd_ctl_elem_value *ucontrol)
  888. {
  889. int ch_num = slim_get_port_idx(kcontrol);
  890. if (ch_num < 0)
  891. return ch_num;
  892. slim_tx_cfg[ch_num].bit_format =
  893. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  894. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  895. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  896. ucontrol->value.enumerated.item[0]);
  897. return 0;
  898. }
  899. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  900. struct snd_ctl_elem_value *ucontrol)
  901. {
  902. int ch_num = slim_get_port_idx(kcontrol);
  903. if (ch_num < 0)
  904. return ch_num;
  905. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  906. ch_num, slim_rx_cfg[ch_num].channels);
  907. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  908. return 0;
  909. }
  910. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  911. struct snd_ctl_elem_value *ucontrol)
  912. {
  913. int ch_num = slim_get_port_idx(kcontrol);
  914. if (ch_num < 0)
  915. return ch_num;
  916. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  917. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  918. ch_num, slim_rx_cfg[ch_num].channels);
  919. return 1;
  920. }
  921. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  922. struct snd_ctl_elem_value *ucontrol)
  923. {
  924. int ch_num = slim_get_port_idx(kcontrol);
  925. if (ch_num < 0)
  926. return ch_num;
  927. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  928. ch_num, slim_tx_cfg[ch_num].channels);
  929. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  930. return 0;
  931. }
  932. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  933. struct snd_ctl_elem_value *ucontrol)
  934. {
  935. int ch_num = slim_get_port_idx(kcontrol);
  936. if (ch_num < 0)
  937. return ch_num;
  938. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  939. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  940. ch_num, slim_tx_cfg[ch_num].channels);
  941. return 1;
  942. }
  943. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  944. struct snd_ctl_elem_value *ucontrol)
  945. {
  946. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  947. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  948. ucontrol->value.integer.value[0]);
  949. return 0;
  950. }
  951. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  952. struct snd_ctl_elem_value *ucontrol)
  953. {
  954. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  955. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  956. return 1;
  957. }
  958. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  959. struct snd_ctl_elem_value *ucontrol)
  960. {
  961. /*
  962. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  963. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  964. * value.
  965. */
  966. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  967. case SAMPLING_RATE_96KHZ:
  968. ucontrol->value.integer.value[0] = 5;
  969. break;
  970. case SAMPLING_RATE_88P2KHZ:
  971. ucontrol->value.integer.value[0] = 4;
  972. break;
  973. case SAMPLING_RATE_48KHZ:
  974. ucontrol->value.integer.value[0] = 3;
  975. break;
  976. case SAMPLING_RATE_44P1KHZ:
  977. ucontrol->value.integer.value[0] = 2;
  978. break;
  979. case SAMPLING_RATE_16KHZ:
  980. ucontrol->value.integer.value[0] = 1;
  981. break;
  982. case SAMPLING_RATE_8KHZ:
  983. default:
  984. ucontrol->value.integer.value[0] = 0;
  985. break;
  986. }
  987. pr_debug("%s: sample rate = %d", __func__,
  988. slim_rx_cfg[SLIM_RX_7].sample_rate);
  989. return 0;
  990. }
  991. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  992. struct snd_ctl_elem_value *ucontrol)
  993. {
  994. switch (ucontrol->value.integer.value[0]) {
  995. case 1:
  996. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  997. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  998. break;
  999. case 2:
  1000. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1001. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1002. break;
  1003. case 3:
  1004. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1005. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1006. break;
  1007. case 4:
  1008. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1009. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1010. break;
  1011. case 5:
  1012. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1013. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1014. break;
  1015. case 0:
  1016. default:
  1017. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1018. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1019. break;
  1020. }
  1021. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1022. __func__,
  1023. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1024. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1025. ucontrol->value.enumerated.item[0]);
  1026. return 0;
  1027. }
  1028. static int msm_bt_sample_rate_sink_get(struct snd_kcontrol *kcontrol,
  1029. struct snd_ctl_elem_value *ucontrol)
  1030. {
  1031. switch (slim_tx_cfg[BT_SLIM_TX].sample_rate) {
  1032. case SAMPLING_RATE_96KHZ:
  1033. ucontrol->value.integer.value[0] = 5;
  1034. break;
  1035. case SAMPLING_RATE_88P2KHZ:
  1036. ucontrol->value.integer.value[0] = 4;
  1037. break;
  1038. case SAMPLING_RATE_48KHZ:
  1039. ucontrol->value.integer.value[0] = 3;
  1040. break;
  1041. case SAMPLING_RATE_44P1KHZ:
  1042. ucontrol->value.integer.value[0] = 2;
  1043. break;
  1044. case SAMPLING_RATE_16KHZ:
  1045. ucontrol->value.integer.value[0] = 1;
  1046. break;
  1047. case SAMPLING_RATE_8KHZ:
  1048. default:
  1049. ucontrol->value.integer.value[0] = 0;
  1050. break;
  1051. }
  1052. pr_debug("%s: sample rate = %d", __func__,
  1053. slim_tx_cfg[BT_SLIM_TX].sample_rate);
  1054. return 0;
  1055. }
  1056. static int msm_bt_sample_rate_sink_put(struct snd_kcontrol *kcontrol,
  1057. struct snd_ctl_elem_value *ucontrol)
  1058. {
  1059. switch (ucontrol->value.integer.value[0]) {
  1060. case 1:
  1061. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_16KHZ;
  1062. break;
  1063. case 2:
  1064. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_44P1KHZ;
  1065. break;
  1066. case 3:
  1067. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_48KHZ;
  1068. break;
  1069. case 4:
  1070. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_88P2KHZ;
  1071. break;
  1072. case 5:
  1073. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_96KHZ;
  1074. break;
  1075. case 0:
  1076. default:
  1077. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_8KHZ;
  1078. break;
  1079. }
  1080. pr_debug("%s: sample rate = %d, value = %d\n",
  1081. __func__,
  1082. slim_tx_cfg[BT_SLIM_TX].sample_rate,
  1083. ucontrol->value.enumerated.item[0]);
  1084. return 0;
  1085. }
  1086. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1087. {
  1088. int idx = 0;
  1089. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1090. sizeof("WSA_CDC_DMA_RX_0")))
  1091. idx = WSA_CDC_DMA_RX_0;
  1092. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1093. sizeof("WSA_CDC_DMA_RX_0")))
  1094. idx = WSA_CDC_DMA_RX_1;
  1095. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1096. sizeof("WSA_CDC_DMA_TX_0")))
  1097. idx = WSA_CDC_DMA_TX_0;
  1098. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1099. sizeof("WSA_CDC_DMA_TX_1")))
  1100. idx = WSA_CDC_DMA_TX_1;
  1101. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1102. sizeof("WSA_CDC_DMA_TX_2")))
  1103. idx = WSA_CDC_DMA_TX_2;
  1104. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1105. sizeof("VA_CDC_DMA_TX_0")))
  1106. idx = VA_CDC_DMA_TX_0;
  1107. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1108. sizeof("VA_CDC_DMA_TX_1")))
  1109. idx = VA_CDC_DMA_TX_1;
  1110. else {
  1111. pr_err("%s: unsupported port: %s\n",
  1112. __func__, kcontrol->id.name);
  1113. return -EINVAL;
  1114. }
  1115. return idx;
  1116. }
  1117. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1118. struct snd_ctl_elem_value *ucontrol)
  1119. {
  1120. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1121. if (ch_num < 0)
  1122. return ch_num;
  1123. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1124. cdc_dma_rx_cfg[ch_num].channels - 1);
  1125. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1126. return 0;
  1127. }
  1128. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1129. struct snd_ctl_elem_value *ucontrol)
  1130. {
  1131. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1132. if (ch_num < 0)
  1133. return ch_num;
  1134. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1135. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1136. cdc_dma_rx_cfg[ch_num].channels);
  1137. return 1;
  1138. }
  1139. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1140. struct snd_ctl_elem_value *ucontrol)
  1141. {
  1142. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1143. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1144. case SNDRV_PCM_FORMAT_S32_LE:
  1145. ucontrol->value.integer.value[0] = 3;
  1146. break;
  1147. case SNDRV_PCM_FORMAT_S24_3LE:
  1148. ucontrol->value.integer.value[0] = 2;
  1149. break;
  1150. case SNDRV_PCM_FORMAT_S24_LE:
  1151. ucontrol->value.integer.value[0] = 1;
  1152. break;
  1153. case SNDRV_PCM_FORMAT_S16_LE:
  1154. default:
  1155. ucontrol->value.integer.value[0] = 0;
  1156. break;
  1157. }
  1158. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1159. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1160. ucontrol->value.integer.value[0]);
  1161. return 0;
  1162. }
  1163. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1164. struct snd_ctl_elem_value *ucontrol)
  1165. {
  1166. int rc = 0;
  1167. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1168. switch (ucontrol->value.integer.value[0]) {
  1169. case 3:
  1170. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1171. break;
  1172. case 2:
  1173. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1174. break;
  1175. case 1:
  1176. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1177. break;
  1178. case 0:
  1179. default:
  1180. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1181. break;
  1182. }
  1183. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1184. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1185. ucontrol->value.integer.value[0]);
  1186. return rc;
  1187. }
  1188. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1189. {
  1190. int sample_rate_val = 0;
  1191. switch (sample_rate) {
  1192. case SAMPLING_RATE_8KHZ:
  1193. sample_rate_val = 0;
  1194. break;
  1195. case SAMPLING_RATE_11P025KHZ:
  1196. sample_rate_val = 1;
  1197. break;
  1198. case SAMPLING_RATE_16KHZ:
  1199. sample_rate_val = 2;
  1200. break;
  1201. case SAMPLING_RATE_22P05KHZ:
  1202. sample_rate_val = 3;
  1203. break;
  1204. case SAMPLING_RATE_32KHZ:
  1205. sample_rate_val = 4;
  1206. break;
  1207. case SAMPLING_RATE_44P1KHZ:
  1208. sample_rate_val = 5;
  1209. break;
  1210. case SAMPLING_RATE_48KHZ:
  1211. sample_rate_val = 6;
  1212. break;
  1213. case SAMPLING_RATE_88P2KHZ:
  1214. sample_rate_val = 7;
  1215. break;
  1216. case SAMPLING_RATE_96KHZ:
  1217. sample_rate_val = 8;
  1218. break;
  1219. case SAMPLING_RATE_176P4KHZ:
  1220. sample_rate_val = 9;
  1221. break;
  1222. case SAMPLING_RATE_192KHZ:
  1223. sample_rate_val = 10;
  1224. break;
  1225. case SAMPLING_RATE_352P8KHZ:
  1226. sample_rate_val = 11;
  1227. break;
  1228. case SAMPLING_RATE_384KHZ:
  1229. sample_rate_val = 12;
  1230. break;
  1231. default:
  1232. sample_rate_val = 6;
  1233. break;
  1234. }
  1235. return sample_rate_val;
  1236. }
  1237. static int cdc_dma_get_sample_rate(int value)
  1238. {
  1239. int sample_rate = 0;
  1240. switch (value) {
  1241. case 0:
  1242. sample_rate = SAMPLING_RATE_8KHZ;
  1243. break;
  1244. case 1:
  1245. sample_rate = SAMPLING_RATE_11P025KHZ;
  1246. break;
  1247. case 2:
  1248. sample_rate = SAMPLING_RATE_16KHZ;
  1249. break;
  1250. case 3:
  1251. sample_rate = SAMPLING_RATE_22P05KHZ;
  1252. break;
  1253. case 4:
  1254. sample_rate = SAMPLING_RATE_32KHZ;
  1255. break;
  1256. case 5:
  1257. sample_rate = SAMPLING_RATE_44P1KHZ;
  1258. break;
  1259. case 6:
  1260. sample_rate = SAMPLING_RATE_48KHZ;
  1261. break;
  1262. case 7:
  1263. sample_rate = SAMPLING_RATE_88P2KHZ;
  1264. break;
  1265. case 8:
  1266. sample_rate = SAMPLING_RATE_96KHZ;
  1267. break;
  1268. case 9:
  1269. sample_rate = SAMPLING_RATE_176P4KHZ;
  1270. break;
  1271. case 10:
  1272. sample_rate = SAMPLING_RATE_192KHZ;
  1273. break;
  1274. case 11:
  1275. sample_rate = SAMPLING_RATE_352P8KHZ;
  1276. break;
  1277. case 12:
  1278. sample_rate = SAMPLING_RATE_384KHZ;
  1279. break;
  1280. default:
  1281. sample_rate = SAMPLING_RATE_48KHZ;
  1282. break;
  1283. }
  1284. return sample_rate;
  1285. }
  1286. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1287. struct snd_ctl_elem_value *ucontrol)
  1288. {
  1289. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1290. if (ch_num < 0)
  1291. return ch_num;
  1292. ucontrol->value.enumerated.item[0] =
  1293. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1294. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1295. cdc_dma_rx_cfg[ch_num].sample_rate);
  1296. return 0;
  1297. }
  1298. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1299. struct snd_ctl_elem_value *ucontrol)
  1300. {
  1301. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1302. if (ch_num < 0)
  1303. return ch_num;
  1304. cdc_dma_rx_cfg[ch_num].sample_rate =
  1305. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1306. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1307. __func__, ucontrol->value.enumerated.item[0],
  1308. cdc_dma_rx_cfg[ch_num].sample_rate);
  1309. return 0;
  1310. }
  1311. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1312. struct snd_ctl_elem_value *ucontrol)
  1313. {
  1314. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1315. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1316. cdc_dma_tx_cfg[ch_num].channels);
  1317. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1318. return 0;
  1319. }
  1320. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1321. struct snd_ctl_elem_value *ucontrol)
  1322. {
  1323. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1324. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1325. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1326. cdc_dma_tx_cfg[ch_num].channels);
  1327. return 1;
  1328. }
  1329. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1330. struct snd_ctl_elem_value *ucontrol)
  1331. {
  1332. int sample_rate_val;
  1333. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1334. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1335. case SAMPLING_RATE_384KHZ:
  1336. sample_rate_val = 12;
  1337. break;
  1338. case SAMPLING_RATE_352P8KHZ:
  1339. sample_rate_val = 11;
  1340. break;
  1341. case SAMPLING_RATE_192KHZ:
  1342. sample_rate_val = 10;
  1343. break;
  1344. case SAMPLING_RATE_176P4KHZ:
  1345. sample_rate_val = 9;
  1346. break;
  1347. case SAMPLING_RATE_96KHZ:
  1348. sample_rate_val = 8;
  1349. break;
  1350. case SAMPLING_RATE_88P2KHZ:
  1351. sample_rate_val = 7;
  1352. break;
  1353. case SAMPLING_RATE_48KHZ:
  1354. sample_rate_val = 6;
  1355. break;
  1356. case SAMPLING_RATE_44P1KHZ:
  1357. sample_rate_val = 5;
  1358. break;
  1359. case SAMPLING_RATE_32KHZ:
  1360. sample_rate_val = 4;
  1361. break;
  1362. case SAMPLING_RATE_22P05KHZ:
  1363. sample_rate_val = 3;
  1364. break;
  1365. case SAMPLING_RATE_16KHZ:
  1366. sample_rate_val = 2;
  1367. break;
  1368. case SAMPLING_RATE_11P025KHZ:
  1369. sample_rate_val = 1;
  1370. break;
  1371. case SAMPLING_RATE_8KHZ:
  1372. sample_rate_val = 0;
  1373. break;
  1374. default:
  1375. sample_rate_val = 6;
  1376. break;
  1377. }
  1378. ucontrol->value.integer.value[0] = sample_rate_val;
  1379. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1380. cdc_dma_tx_cfg[ch_num].sample_rate);
  1381. return 0;
  1382. }
  1383. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1384. struct snd_ctl_elem_value *ucontrol)
  1385. {
  1386. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1387. switch (ucontrol->value.integer.value[0]) {
  1388. case 12:
  1389. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1390. break;
  1391. case 11:
  1392. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1393. break;
  1394. case 10:
  1395. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1396. break;
  1397. case 9:
  1398. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1399. break;
  1400. case 8:
  1401. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1402. break;
  1403. case 7:
  1404. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1405. break;
  1406. case 6:
  1407. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1408. break;
  1409. case 5:
  1410. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1411. break;
  1412. case 4:
  1413. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1414. break;
  1415. case 3:
  1416. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1417. break;
  1418. case 2:
  1419. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1420. break;
  1421. case 1:
  1422. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1423. break;
  1424. case 0:
  1425. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1426. break;
  1427. default:
  1428. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1429. break;
  1430. }
  1431. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1432. __func__, ucontrol->value.integer.value[0],
  1433. cdc_dma_tx_cfg[ch_num].sample_rate);
  1434. return 0;
  1435. }
  1436. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1437. struct snd_ctl_elem_value *ucontrol)
  1438. {
  1439. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1440. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1441. case SNDRV_PCM_FORMAT_S32_LE:
  1442. ucontrol->value.integer.value[0] = 3;
  1443. break;
  1444. case SNDRV_PCM_FORMAT_S24_3LE:
  1445. ucontrol->value.integer.value[0] = 2;
  1446. break;
  1447. case SNDRV_PCM_FORMAT_S24_LE:
  1448. ucontrol->value.integer.value[0] = 1;
  1449. break;
  1450. case SNDRV_PCM_FORMAT_S16_LE:
  1451. default:
  1452. ucontrol->value.integer.value[0] = 0;
  1453. break;
  1454. }
  1455. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1456. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1457. ucontrol->value.integer.value[0]);
  1458. return 0;
  1459. }
  1460. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1461. struct snd_ctl_elem_value *ucontrol)
  1462. {
  1463. int rc = 0;
  1464. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1465. switch (ucontrol->value.integer.value[0]) {
  1466. case 3:
  1467. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1468. break;
  1469. case 2:
  1470. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1471. break;
  1472. case 1:
  1473. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1474. break;
  1475. case 0:
  1476. default:
  1477. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1478. break;
  1479. }
  1480. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1481. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1482. ucontrol->value.integer.value[0]);
  1483. return rc;
  1484. }
  1485. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1486. struct snd_ctl_elem_value *ucontrol)
  1487. {
  1488. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1489. usb_rx_cfg.channels);
  1490. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1491. return 0;
  1492. }
  1493. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1494. struct snd_ctl_elem_value *ucontrol)
  1495. {
  1496. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1497. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1498. return 1;
  1499. }
  1500. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1501. struct snd_ctl_elem_value *ucontrol)
  1502. {
  1503. int sample_rate_val;
  1504. switch (usb_rx_cfg.sample_rate) {
  1505. case SAMPLING_RATE_384KHZ:
  1506. sample_rate_val = 12;
  1507. break;
  1508. case SAMPLING_RATE_352P8KHZ:
  1509. sample_rate_val = 11;
  1510. break;
  1511. case SAMPLING_RATE_192KHZ:
  1512. sample_rate_val = 10;
  1513. break;
  1514. case SAMPLING_RATE_176P4KHZ:
  1515. sample_rate_val = 9;
  1516. break;
  1517. case SAMPLING_RATE_96KHZ:
  1518. sample_rate_val = 8;
  1519. break;
  1520. case SAMPLING_RATE_88P2KHZ:
  1521. sample_rate_val = 7;
  1522. break;
  1523. case SAMPLING_RATE_48KHZ:
  1524. sample_rate_val = 6;
  1525. break;
  1526. case SAMPLING_RATE_44P1KHZ:
  1527. sample_rate_val = 5;
  1528. break;
  1529. case SAMPLING_RATE_32KHZ:
  1530. sample_rate_val = 4;
  1531. break;
  1532. case SAMPLING_RATE_22P05KHZ:
  1533. sample_rate_val = 3;
  1534. break;
  1535. case SAMPLING_RATE_16KHZ:
  1536. sample_rate_val = 2;
  1537. break;
  1538. case SAMPLING_RATE_11P025KHZ:
  1539. sample_rate_val = 1;
  1540. break;
  1541. case SAMPLING_RATE_8KHZ:
  1542. default:
  1543. sample_rate_val = 0;
  1544. break;
  1545. }
  1546. ucontrol->value.integer.value[0] = sample_rate_val;
  1547. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1548. usb_rx_cfg.sample_rate);
  1549. return 0;
  1550. }
  1551. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1552. struct snd_ctl_elem_value *ucontrol)
  1553. {
  1554. switch (ucontrol->value.integer.value[0]) {
  1555. case 12:
  1556. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1557. break;
  1558. case 11:
  1559. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1560. break;
  1561. case 10:
  1562. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1563. break;
  1564. case 9:
  1565. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1566. break;
  1567. case 8:
  1568. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1569. break;
  1570. case 7:
  1571. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1572. break;
  1573. case 6:
  1574. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1575. break;
  1576. case 5:
  1577. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1578. break;
  1579. case 4:
  1580. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1581. break;
  1582. case 3:
  1583. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1584. break;
  1585. case 2:
  1586. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1587. break;
  1588. case 1:
  1589. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1590. break;
  1591. case 0:
  1592. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1593. break;
  1594. default:
  1595. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1596. break;
  1597. }
  1598. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1599. __func__, ucontrol->value.integer.value[0],
  1600. usb_rx_cfg.sample_rate);
  1601. return 0;
  1602. }
  1603. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1604. struct snd_ctl_elem_value *ucontrol)
  1605. {
  1606. switch (usb_rx_cfg.bit_format) {
  1607. case SNDRV_PCM_FORMAT_S32_LE:
  1608. ucontrol->value.integer.value[0] = 3;
  1609. break;
  1610. case SNDRV_PCM_FORMAT_S24_3LE:
  1611. ucontrol->value.integer.value[0] = 2;
  1612. break;
  1613. case SNDRV_PCM_FORMAT_S24_LE:
  1614. ucontrol->value.integer.value[0] = 1;
  1615. break;
  1616. case SNDRV_PCM_FORMAT_S16_LE:
  1617. default:
  1618. ucontrol->value.integer.value[0] = 0;
  1619. break;
  1620. }
  1621. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1622. __func__, usb_rx_cfg.bit_format,
  1623. ucontrol->value.integer.value[0]);
  1624. return 0;
  1625. }
  1626. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1627. struct snd_ctl_elem_value *ucontrol)
  1628. {
  1629. int rc = 0;
  1630. switch (ucontrol->value.integer.value[0]) {
  1631. case 3:
  1632. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1633. break;
  1634. case 2:
  1635. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1636. break;
  1637. case 1:
  1638. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1639. break;
  1640. case 0:
  1641. default:
  1642. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1643. break;
  1644. }
  1645. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1646. __func__, usb_rx_cfg.bit_format,
  1647. ucontrol->value.integer.value[0]);
  1648. return rc;
  1649. }
  1650. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1651. struct snd_ctl_elem_value *ucontrol)
  1652. {
  1653. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1654. usb_tx_cfg.channels);
  1655. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1656. return 0;
  1657. }
  1658. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1659. struct snd_ctl_elem_value *ucontrol)
  1660. {
  1661. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1662. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1663. return 1;
  1664. }
  1665. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1666. struct snd_ctl_elem_value *ucontrol)
  1667. {
  1668. int sample_rate_val;
  1669. switch (usb_tx_cfg.sample_rate) {
  1670. case SAMPLING_RATE_384KHZ:
  1671. sample_rate_val = 12;
  1672. break;
  1673. case SAMPLING_RATE_352P8KHZ:
  1674. sample_rate_val = 11;
  1675. break;
  1676. case SAMPLING_RATE_192KHZ:
  1677. sample_rate_val = 10;
  1678. break;
  1679. case SAMPLING_RATE_176P4KHZ:
  1680. sample_rate_val = 9;
  1681. break;
  1682. case SAMPLING_RATE_96KHZ:
  1683. sample_rate_val = 8;
  1684. break;
  1685. case SAMPLING_RATE_88P2KHZ:
  1686. sample_rate_val = 7;
  1687. break;
  1688. case SAMPLING_RATE_48KHZ:
  1689. sample_rate_val = 6;
  1690. break;
  1691. case SAMPLING_RATE_44P1KHZ:
  1692. sample_rate_val = 5;
  1693. break;
  1694. case SAMPLING_RATE_32KHZ:
  1695. sample_rate_val = 4;
  1696. break;
  1697. case SAMPLING_RATE_22P05KHZ:
  1698. sample_rate_val = 3;
  1699. break;
  1700. case SAMPLING_RATE_16KHZ:
  1701. sample_rate_val = 2;
  1702. break;
  1703. case SAMPLING_RATE_11P025KHZ:
  1704. sample_rate_val = 1;
  1705. break;
  1706. case SAMPLING_RATE_8KHZ:
  1707. sample_rate_val = 0;
  1708. break;
  1709. default:
  1710. sample_rate_val = 6;
  1711. break;
  1712. }
  1713. ucontrol->value.integer.value[0] = sample_rate_val;
  1714. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1715. usb_tx_cfg.sample_rate);
  1716. return 0;
  1717. }
  1718. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1719. struct snd_ctl_elem_value *ucontrol)
  1720. {
  1721. switch (ucontrol->value.integer.value[0]) {
  1722. case 12:
  1723. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1724. break;
  1725. case 11:
  1726. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1727. break;
  1728. case 10:
  1729. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1730. break;
  1731. case 9:
  1732. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1733. break;
  1734. case 8:
  1735. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1736. break;
  1737. case 7:
  1738. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1739. break;
  1740. case 6:
  1741. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1742. break;
  1743. case 5:
  1744. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1745. break;
  1746. case 4:
  1747. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1748. break;
  1749. case 3:
  1750. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1751. break;
  1752. case 2:
  1753. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1754. break;
  1755. case 1:
  1756. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1757. break;
  1758. case 0:
  1759. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1760. break;
  1761. default:
  1762. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1763. break;
  1764. }
  1765. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1766. __func__, ucontrol->value.integer.value[0],
  1767. usb_tx_cfg.sample_rate);
  1768. return 0;
  1769. }
  1770. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1771. struct snd_ctl_elem_value *ucontrol)
  1772. {
  1773. switch (usb_tx_cfg.bit_format) {
  1774. case SNDRV_PCM_FORMAT_S32_LE:
  1775. ucontrol->value.integer.value[0] = 3;
  1776. break;
  1777. case SNDRV_PCM_FORMAT_S24_3LE:
  1778. ucontrol->value.integer.value[0] = 2;
  1779. break;
  1780. case SNDRV_PCM_FORMAT_S24_LE:
  1781. ucontrol->value.integer.value[0] = 1;
  1782. break;
  1783. case SNDRV_PCM_FORMAT_S16_LE:
  1784. default:
  1785. ucontrol->value.integer.value[0] = 0;
  1786. break;
  1787. }
  1788. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1789. __func__, usb_tx_cfg.bit_format,
  1790. ucontrol->value.integer.value[0]);
  1791. return 0;
  1792. }
  1793. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1794. struct snd_ctl_elem_value *ucontrol)
  1795. {
  1796. int rc = 0;
  1797. switch (ucontrol->value.integer.value[0]) {
  1798. case 3:
  1799. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1800. break;
  1801. case 2:
  1802. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1803. break;
  1804. case 1:
  1805. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1806. break;
  1807. case 0:
  1808. default:
  1809. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1810. break;
  1811. }
  1812. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1813. __func__, usb_tx_cfg.bit_format,
  1814. ucontrol->value.integer.value[0]);
  1815. return rc;
  1816. }
  1817. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1818. struct snd_ctl_elem_value *ucontrol)
  1819. {
  1820. pr_debug("%s: proxy_rx channels = %d\n",
  1821. __func__, proxy_rx_cfg.channels);
  1822. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1823. return 0;
  1824. }
  1825. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1826. struct snd_ctl_elem_value *ucontrol)
  1827. {
  1828. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1829. pr_debug("%s: proxy_rx channels = %d\n",
  1830. __func__, proxy_rx_cfg.channels);
  1831. return 1;
  1832. }
  1833. static int tdm_get_sample_rate(int value)
  1834. {
  1835. int sample_rate = 0;
  1836. switch (value) {
  1837. case 0:
  1838. sample_rate = SAMPLING_RATE_8KHZ;
  1839. break;
  1840. case 1:
  1841. sample_rate = SAMPLING_RATE_16KHZ;
  1842. break;
  1843. case 2:
  1844. sample_rate = SAMPLING_RATE_32KHZ;
  1845. break;
  1846. case 3:
  1847. sample_rate = SAMPLING_RATE_48KHZ;
  1848. break;
  1849. case 4:
  1850. sample_rate = SAMPLING_RATE_176P4KHZ;
  1851. break;
  1852. case 5:
  1853. sample_rate = SAMPLING_RATE_352P8KHZ;
  1854. break;
  1855. default:
  1856. sample_rate = SAMPLING_RATE_48KHZ;
  1857. break;
  1858. }
  1859. return sample_rate;
  1860. }
  1861. static int aux_pcm_get_sample_rate(int value)
  1862. {
  1863. int sample_rate;
  1864. switch (value) {
  1865. case 1:
  1866. sample_rate = SAMPLING_RATE_16KHZ;
  1867. break;
  1868. case 0:
  1869. default:
  1870. sample_rate = SAMPLING_RATE_8KHZ;
  1871. break;
  1872. }
  1873. return sample_rate;
  1874. }
  1875. static int tdm_get_sample_rate_val(int sample_rate)
  1876. {
  1877. int sample_rate_val = 0;
  1878. switch (sample_rate) {
  1879. case SAMPLING_RATE_8KHZ:
  1880. sample_rate_val = 0;
  1881. break;
  1882. case SAMPLING_RATE_16KHZ:
  1883. sample_rate_val = 1;
  1884. break;
  1885. case SAMPLING_RATE_32KHZ:
  1886. sample_rate_val = 2;
  1887. break;
  1888. case SAMPLING_RATE_48KHZ:
  1889. sample_rate_val = 3;
  1890. break;
  1891. case SAMPLING_RATE_176P4KHZ:
  1892. sample_rate_val = 4;
  1893. break;
  1894. case SAMPLING_RATE_352P8KHZ:
  1895. sample_rate_val = 5;
  1896. break;
  1897. default:
  1898. sample_rate_val = 3;
  1899. break;
  1900. }
  1901. return sample_rate_val;
  1902. }
  1903. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1904. {
  1905. int sample_rate_val;
  1906. switch (sample_rate) {
  1907. case SAMPLING_RATE_16KHZ:
  1908. sample_rate_val = 1;
  1909. break;
  1910. case SAMPLING_RATE_8KHZ:
  1911. default:
  1912. sample_rate_val = 0;
  1913. break;
  1914. }
  1915. return sample_rate_val;
  1916. }
  1917. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1918. struct tdm_port *port)
  1919. {
  1920. if (port) {
  1921. if (strnstr(kcontrol->id.name, "PRI",
  1922. sizeof(kcontrol->id.name))) {
  1923. port->mode = TDM_PRI;
  1924. } else if (strnstr(kcontrol->id.name, "SEC",
  1925. sizeof(kcontrol->id.name))) {
  1926. port->mode = TDM_SEC;
  1927. } else if (strnstr(kcontrol->id.name, "TERT",
  1928. sizeof(kcontrol->id.name))) {
  1929. port->mode = TDM_TERT;
  1930. } else if (strnstr(kcontrol->id.name, "QUAT",
  1931. sizeof(kcontrol->id.name))) {
  1932. port->mode = TDM_QUAT;
  1933. } else if (strnstr(kcontrol->id.name, "QUIN",
  1934. sizeof(kcontrol->id.name))) {
  1935. port->mode = TDM_QUIN;
  1936. } else {
  1937. pr_err("%s: unsupported mode in: %s",
  1938. __func__, kcontrol->id.name);
  1939. return -EINVAL;
  1940. }
  1941. if (strnstr(kcontrol->id.name, "RX_0",
  1942. sizeof(kcontrol->id.name)) ||
  1943. strnstr(kcontrol->id.name, "TX_0",
  1944. sizeof(kcontrol->id.name))) {
  1945. port->channel = TDM_0;
  1946. } else if (strnstr(kcontrol->id.name, "RX_1",
  1947. sizeof(kcontrol->id.name)) ||
  1948. strnstr(kcontrol->id.name, "TX_1",
  1949. sizeof(kcontrol->id.name))) {
  1950. port->channel = TDM_1;
  1951. } else if (strnstr(kcontrol->id.name, "RX_2",
  1952. sizeof(kcontrol->id.name)) ||
  1953. strnstr(kcontrol->id.name, "TX_2",
  1954. sizeof(kcontrol->id.name))) {
  1955. port->channel = TDM_2;
  1956. } else if (strnstr(kcontrol->id.name, "RX_3",
  1957. sizeof(kcontrol->id.name)) ||
  1958. strnstr(kcontrol->id.name, "TX_3",
  1959. sizeof(kcontrol->id.name))) {
  1960. port->channel = TDM_3;
  1961. } else if (strnstr(kcontrol->id.name, "RX_4",
  1962. sizeof(kcontrol->id.name)) ||
  1963. strnstr(kcontrol->id.name, "TX_4",
  1964. sizeof(kcontrol->id.name))) {
  1965. port->channel = TDM_4;
  1966. } else if (strnstr(kcontrol->id.name, "RX_5",
  1967. sizeof(kcontrol->id.name)) ||
  1968. strnstr(kcontrol->id.name, "TX_5",
  1969. sizeof(kcontrol->id.name))) {
  1970. port->channel = TDM_5;
  1971. } else if (strnstr(kcontrol->id.name, "RX_6",
  1972. sizeof(kcontrol->id.name)) ||
  1973. strnstr(kcontrol->id.name, "TX_6",
  1974. sizeof(kcontrol->id.name))) {
  1975. port->channel = TDM_6;
  1976. } else if (strnstr(kcontrol->id.name, "RX_7",
  1977. sizeof(kcontrol->id.name)) ||
  1978. strnstr(kcontrol->id.name, "TX_7",
  1979. sizeof(kcontrol->id.name))) {
  1980. port->channel = TDM_7;
  1981. } else {
  1982. pr_err("%s: unsupported channel in: %s",
  1983. __func__, kcontrol->id.name);
  1984. return -EINVAL;
  1985. }
  1986. } else
  1987. return -EINVAL;
  1988. return 0;
  1989. }
  1990. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1991. struct snd_ctl_elem_value *ucontrol)
  1992. {
  1993. struct tdm_port port;
  1994. int ret = tdm_get_port_idx(kcontrol, &port);
  1995. if (ret) {
  1996. pr_err("%s: unsupported control: %s",
  1997. __func__, kcontrol->id.name);
  1998. } else {
  1999. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2000. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  2001. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2002. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2003. ucontrol->value.enumerated.item[0]);
  2004. }
  2005. return ret;
  2006. }
  2007. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2008. struct snd_ctl_elem_value *ucontrol)
  2009. {
  2010. struct tdm_port port;
  2011. int ret = tdm_get_port_idx(kcontrol, &port);
  2012. if (ret) {
  2013. pr_err("%s: unsupported control: %s",
  2014. __func__, kcontrol->id.name);
  2015. } else {
  2016. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  2017. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2018. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2019. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2020. ucontrol->value.enumerated.item[0]);
  2021. }
  2022. return ret;
  2023. }
  2024. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2025. struct snd_ctl_elem_value *ucontrol)
  2026. {
  2027. struct tdm_port port;
  2028. int ret = tdm_get_port_idx(kcontrol, &port);
  2029. if (ret) {
  2030. pr_err("%s: unsupported control: %s",
  2031. __func__, kcontrol->id.name);
  2032. } else {
  2033. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2034. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  2035. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2036. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2037. ucontrol->value.enumerated.item[0]);
  2038. }
  2039. return ret;
  2040. }
  2041. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2042. struct snd_ctl_elem_value *ucontrol)
  2043. {
  2044. struct tdm_port port;
  2045. int ret = tdm_get_port_idx(kcontrol, &port);
  2046. if (ret) {
  2047. pr_err("%s: unsupported control: %s",
  2048. __func__, kcontrol->id.name);
  2049. } else {
  2050. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  2051. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2052. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2053. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2054. ucontrol->value.enumerated.item[0]);
  2055. }
  2056. return ret;
  2057. }
  2058. static int tdm_get_format(int value)
  2059. {
  2060. int format = 0;
  2061. switch (value) {
  2062. case 0:
  2063. format = SNDRV_PCM_FORMAT_S16_LE;
  2064. break;
  2065. case 1:
  2066. format = SNDRV_PCM_FORMAT_S24_LE;
  2067. break;
  2068. case 2:
  2069. format = SNDRV_PCM_FORMAT_S32_LE;
  2070. break;
  2071. default:
  2072. format = SNDRV_PCM_FORMAT_S16_LE;
  2073. break;
  2074. }
  2075. return format;
  2076. }
  2077. static int tdm_get_format_val(int format)
  2078. {
  2079. int value = 0;
  2080. switch (format) {
  2081. case SNDRV_PCM_FORMAT_S16_LE:
  2082. value = 0;
  2083. break;
  2084. case SNDRV_PCM_FORMAT_S24_LE:
  2085. value = 1;
  2086. break;
  2087. case SNDRV_PCM_FORMAT_S32_LE:
  2088. value = 2;
  2089. break;
  2090. default:
  2091. value = 0;
  2092. break;
  2093. }
  2094. return value;
  2095. }
  2096. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2097. struct snd_ctl_elem_value *ucontrol)
  2098. {
  2099. struct tdm_port port;
  2100. int ret = tdm_get_port_idx(kcontrol, &port);
  2101. if (ret) {
  2102. pr_err("%s: unsupported control: %s",
  2103. __func__, kcontrol->id.name);
  2104. } else {
  2105. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2106. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2107. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2108. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2109. ucontrol->value.enumerated.item[0]);
  2110. }
  2111. return ret;
  2112. }
  2113. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2114. struct snd_ctl_elem_value *ucontrol)
  2115. {
  2116. struct tdm_port port;
  2117. int ret = tdm_get_port_idx(kcontrol, &port);
  2118. if (ret) {
  2119. pr_err("%s: unsupported control: %s",
  2120. __func__, kcontrol->id.name);
  2121. } else {
  2122. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2123. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2124. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2125. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2126. ucontrol->value.enumerated.item[0]);
  2127. }
  2128. return ret;
  2129. }
  2130. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2131. struct snd_ctl_elem_value *ucontrol)
  2132. {
  2133. struct tdm_port port;
  2134. int ret = tdm_get_port_idx(kcontrol, &port);
  2135. if (ret) {
  2136. pr_err("%s: unsupported control: %s",
  2137. __func__, kcontrol->id.name);
  2138. } else {
  2139. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2140. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2141. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2142. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2143. ucontrol->value.enumerated.item[0]);
  2144. }
  2145. return ret;
  2146. }
  2147. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2148. struct snd_ctl_elem_value *ucontrol)
  2149. {
  2150. struct tdm_port port;
  2151. int ret = tdm_get_port_idx(kcontrol, &port);
  2152. if (ret) {
  2153. pr_err("%s: unsupported control: %s",
  2154. __func__, kcontrol->id.name);
  2155. } else {
  2156. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2157. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2158. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2159. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2160. ucontrol->value.enumerated.item[0]);
  2161. }
  2162. return ret;
  2163. }
  2164. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2165. struct snd_ctl_elem_value *ucontrol)
  2166. {
  2167. struct tdm_port port;
  2168. int ret = tdm_get_port_idx(kcontrol, &port);
  2169. if (ret) {
  2170. pr_err("%s: unsupported control: %s",
  2171. __func__, kcontrol->id.name);
  2172. } else {
  2173. ucontrol->value.enumerated.item[0] =
  2174. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2175. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2176. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2177. ucontrol->value.enumerated.item[0]);
  2178. }
  2179. return ret;
  2180. }
  2181. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2182. struct snd_ctl_elem_value *ucontrol)
  2183. {
  2184. struct tdm_port port;
  2185. int ret = tdm_get_port_idx(kcontrol, &port);
  2186. if (ret) {
  2187. pr_err("%s: unsupported control: %s",
  2188. __func__, kcontrol->id.name);
  2189. } else {
  2190. tdm_rx_cfg[port.mode][port.channel].channels =
  2191. ucontrol->value.enumerated.item[0] + 1;
  2192. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2193. tdm_rx_cfg[port.mode][port.channel].channels,
  2194. ucontrol->value.enumerated.item[0] + 1);
  2195. }
  2196. return ret;
  2197. }
  2198. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2199. struct snd_ctl_elem_value *ucontrol)
  2200. {
  2201. struct tdm_port port;
  2202. int ret = tdm_get_port_idx(kcontrol, &port);
  2203. if (ret) {
  2204. pr_err("%s: unsupported control: %s",
  2205. __func__, kcontrol->id.name);
  2206. } else {
  2207. ucontrol->value.enumerated.item[0] =
  2208. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2209. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2210. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2211. ucontrol->value.enumerated.item[0]);
  2212. }
  2213. return ret;
  2214. }
  2215. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2216. struct snd_ctl_elem_value *ucontrol)
  2217. {
  2218. struct tdm_port port;
  2219. int ret = tdm_get_port_idx(kcontrol, &port);
  2220. if (ret) {
  2221. pr_err("%s: unsupported control: %s",
  2222. __func__, kcontrol->id.name);
  2223. } else {
  2224. tdm_tx_cfg[port.mode][port.channel].channels =
  2225. ucontrol->value.enumerated.item[0] + 1;
  2226. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2227. tdm_tx_cfg[port.mode][port.channel].channels,
  2228. ucontrol->value.enumerated.item[0] + 1);
  2229. }
  2230. return ret;
  2231. }
  2232. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2233. {
  2234. int idx;
  2235. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2236. sizeof("PRIM_AUX_PCM")))
  2237. idx = PRIM_AUX_PCM;
  2238. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2239. sizeof("SEC_AUX_PCM")))
  2240. idx = SEC_AUX_PCM;
  2241. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2242. sizeof("TERT_AUX_PCM")))
  2243. idx = TERT_AUX_PCM;
  2244. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2245. sizeof("QUAT_AUX_PCM")))
  2246. idx = QUAT_AUX_PCM;
  2247. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2248. sizeof("QUIN_AUX_PCM")))
  2249. idx = QUIN_AUX_PCM;
  2250. else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  2251. sizeof("SENN_AUX_PCM")))
  2252. idx = SEN_AUX_PCM;
  2253. else {
  2254. pr_err("%s: unsupported port: %s",
  2255. __func__, kcontrol->id.name);
  2256. idx = -EINVAL;
  2257. }
  2258. return idx;
  2259. }
  2260. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2261. struct snd_ctl_elem_value *ucontrol)
  2262. {
  2263. int idx = aux_pcm_get_port_idx(kcontrol);
  2264. if (idx < 0)
  2265. return idx;
  2266. aux_pcm_rx_cfg[idx].sample_rate =
  2267. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2268. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2269. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2270. ucontrol->value.enumerated.item[0]);
  2271. return 0;
  2272. }
  2273. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2274. struct snd_ctl_elem_value *ucontrol)
  2275. {
  2276. int idx = aux_pcm_get_port_idx(kcontrol);
  2277. if (idx < 0)
  2278. return idx;
  2279. ucontrol->value.enumerated.item[0] =
  2280. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2281. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2282. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2283. ucontrol->value.enumerated.item[0]);
  2284. return 0;
  2285. }
  2286. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2287. struct snd_ctl_elem_value *ucontrol)
  2288. {
  2289. int idx = aux_pcm_get_port_idx(kcontrol);
  2290. if (idx < 0)
  2291. return idx;
  2292. aux_pcm_tx_cfg[idx].sample_rate =
  2293. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2294. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2295. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2296. ucontrol->value.enumerated.item[0]);
  2297. return 0;
  2298. }
  2299. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2300. struct snd_ctl_elem_value *ucontrol)
  2301. {
  2302. int idx = aux_pcm_get_port_idx(kcontrol);
  2303. if (idx < 0)
  2304. return idx;
  2305. ucontrol->value.enumerated.item[0] =
  2306. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2307. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2308. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2309. ucontrol->value.enumerated.item[0]);
  2310. return 0;
  2311. }
  2312. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2313. {
  2314. int idx;
  2315. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2316. sizeof("PRIM_MI2S_RX")))
  2317. idx = PRIM_MI2S;
  2318. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2319. sizeof("SEC_MI2S_RX")))
  2320. idx = SEC_MI2S;
  2321. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2322. sizeof("TERT_MI2S_RX")))
  2323. idx = TERT_MI2S;
  2324. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2325. sizeof("QUAT_MI2S_RX")))
  2326. idx = QUAT_MI2S;
  2327. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2328. sizeof("QUIN_MI2S_RX")))
  2329. idx = QUIN_MI2S;
  2330. else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2331. sizeof("SEN_MI2S_RX")))
  2332. idx = SEN_MI2S;
  2333. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2334. sizeof("PRIM_MI2S_TX")))
  2335. idx = PRIM_MI2S;
  2336. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2337. sizeof("SEC_MI2S_TX")))
  2338. idx = SEC_MI2S;
  2339. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2340. sizeof("TERT_MI2S_TX")))
  2341. idx = TERT_MI2S;
  2342. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2343. sizeof("QUAT_MI2S_TX")))
  2344. idx = QUAT_MI2S;
  2345. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2346. sizeof("QUIN_MI2S_TX")))
  2347. idx = QUIN_MI2S;
  2348. else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2349. sizeof("SEN_MI2S_TX")))
  2350. idx = SEN_MI2S;
  2351. else {
  2352. pr_err("%s: unsupported channel: %s",
  2353. __func__, kcontrol->id.name);
  2354. idx = -EINVAL;
  2355. }
  2356. return idx;
  2357. }
  2358. static int mi2s_get_sample_rate_val(int sample_rate)
  2359. {
  2360. int sample_rate_val;
  2361. switch (sample_rate) {
  2362. case SAMPLING_RATE_8KHZ:
  2363. sample_rate_val = 0;
  2364. break;
  2365. case SAMPLING_RATE_11P025KHZ:
  2366. sample_rate_val = 1;
  2367. break;
  2368. case SAMPLING_RATE_16KHZ:
  2369. sample_rate_val = 2;
  2370. break;
  2371. case SAMPLING_RATE_22P05KHZ:
  2372. sample_rate_val = 3;
  2373. break;
  2374. case SAMPLING_RATE_32KHZ:
  2375. sample_rate_val = 4;
  2376. break;
  2377. case SAMPLING_RATE_44P1KHZ:
  2378. sample_rate_val = 5;
  2379. break;
  2380. case SAMPLING_RATE_48KHZ:
  2381. sample_rate_val = 6;
  2382. break;
  2383. case SAMPLING_RATE_96KHZ:
  2384. sample_rate_val = 7;
  2385. break;
  2386. case SAMPLING_RATE_192KHZ:
  2387. sample_rate_val = 8;
  2388. break;
  2389. case SAMPLING_RATE_384KHZ:
  2390. sample_rate_val = 9;
  2391. break;
  2392. default:
  2393. sample_rate_val = 6;
  2394. break;
  2395. }
  2396. return sample_rate_val;
  2397. }
  2398. static int mi2s_get_sample_rate(int value)
  2399. {
  2400. int sample_rate;
  2401. switch (value) {
  2402. case 0:
  2403. sample_rate = SAMPLING_RATE_8KHZ;
  2404. break;
  2405. case 1:
  2406. sample_rate = SAMPLING_RATE_11P025KHZ;
  2407. break;
  2408. case 2:
  2409. sample_rate = SAMPLING_RATE_16KHZ;
  2410. break;
  2411. case 3:
  2412. sample_rate = SAMPLING_RATE_22P05KHZ;
  2413. break;
  2414. case 4:
  2415. sample_rate = SAMPLING_RATE_32KHZ;
  2416. break;
  2417. case 5:
  2418. sample_rate = SAMPLING_RATE_44P1KHZ;
  2419. break;
  2420. case 6:
  2421. sample_rate = SAMPLING_RATE_48KHZ;
  2422. break;
  2423. case 7:
  2424. sample_rate = SAMPLING_RATE_96KHZ;
  2425. break;
  2426. case 8:
  2427. sample_rate = SAMPLING_RATE_192KHZ;
  2428. break;
  2429. case 9:
  2430. sample_rate = SAMPLING_RATE_384KHZ;
  2431. break;
  2432. default:
  2433. sample_rate = SAMPLING_RATE_48KHZ;
  2434. break;
  2435. }
  2436. return sample_rate;
  2437. }
  2438. static int mi2s_auxpcm_get_format(int value)
  2439. {
  2440. int format;
  2441. switch (value) {
  2442. case 0:
  2443. format = SNDRV_PCM_FORMAT_S16_LE;
  2444. break;
  2445. case 1:
  2446. format = SNDRV_PCM_FORMAT_S24_LE;
  2447. break;
  2448. case 2:
  2449. format = SNDRV_PCM_FORMAT_S24_3LE;
  2450. break;
  2451. case 3:
  2452. format = SNDRV_PCM_FORMAT_S32_LE;
  2453. break;
  2454. default:
  2455. format = SNDRV_PCM_FORMAT_S16_LE;
  2456. break;
  2457. }
  2458. return format;
  2459. }
  2460. static int mi2s_auxpcm_get_format_value(int format)
  2461. {
  2462. int value;
  2463. switch (format) {
  2464. case SNDRV_PCM_FORMAT_S16_LE:
  2465. value = 0;
  2466. break;
  2467. case SNDRV_PCM_FORMAT_S24_LE:
  2468. value = 1;
  2469. break;
  2470. case SNDRV_PCM_FORMAT_S24_3LE:
  2471. value = 2;
  2472. break;
  2473. case SNDRV_PCM_FORMAT_S32_LE:
  2474. value = 3;
  2475. break;
  2476. default:
  2477. value = 0;
  2478. break;
  2479. }
  2480. return value;
  2481. }
  2482. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2483. struct snd_ctl_elem_value *ucontrol)
  2484. {
  2485. int idx = mi2s_get_port_idx(kcontrol);
  2486. if (idx < 0)
  2487. return idx;
  2488. mi2s_rx_cfg[idx].sample_rate =
  2489. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2490. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2491. idx, mi2s_rx_cfg[idx].sample_rate,
  2492. ucontrol->value.enumerated.item[0]);
  2493. return 0;
  2494. }
  2495. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2496. struct snd_ctl_elem_value *ucontrol)
  2497. {
  2498. int idx = mi2s_get_port_idx(kcontrol);
  2499. if (idx < 0)
  2500. return idx;
  2501. ucontrol->value.enumerated.item[0] =
  2502. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2503. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2504. idx, mi2s_rx_cfg[idx].sample_rate,
  2505. ucontrol->value.enumerated.item[0]);
  2506. return 0;
  2507. }
  2508. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2509. struct snd_ctl_elem_value *ucontrol)
  2510. {
  2511. int idx = mi2s_get_port_idx(kcontrol);
  2512. if (idx < 0)
  2513. return idx;
  2514. mi2s_tx_cfg[idx].sample_rate =
  2515. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2516. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2517. idx, mi2s_tx_cfg[idx].sample_rate,
  2518. ucontrol->value.enumerated.item[0]);
  2519. return 0;
  2520. }
  2521. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2522. struct snd_ctl_elem_value *ucontrol)
  2523. {
  2524. int idx = mi2s_get_port_idx(kcontrol);
  2525. if (idx < 0)
  2526. return idx;
  2527. ucontrol->value.enumerated.item[0] =
  2528. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2529. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2530. idx, mi2s_tx_cfg[idx].sample_rate,
  2531. ucontrol->value.enumerated.item[0]);
  2532. return 0;
  2533. }
  2534. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2535. struct snd_ctl_elem_value *ucontrol)
  2536. {
  2537. int idx = mi2s_get_port_idx(kcontrol);
  2538. if (idx < 0)
  2539. return idx;
  2540. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2541. idx, mi2s_rx_cfg[idx].channels);
  2542. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2543. return 0;
  2544. }
  2545. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2546. struct snd_ctl_elem_value *ucontrol)
  2547. {
  2548. int idx = mi2s_get_port_idx(kcontrol);
  2549. if (idx < 0)
  2550. return idx;
  2551. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2552. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2553. idx, mi2s_rx_cfg[idx].channels);
  2554. return 1;
  2555. }
  2556. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2557. struct snd_ctl_elem_value *ucontrol)
  2558. {
  2559. int idx = mi2s_get_port_idx(kcontrol);
  2560. if (idx < 0)
  2561. return idx;
  2562. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2563. idx, mi2s_tx_cfg[idx].channels);
  2564. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2565. return 0;
  2566. }
  2567. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2568. struct snd_ctl_elem_value *ucontrol)
  2569. {
  2570. int idx = mi2s_get_port_idx(kcontrol);
  2571. if (idx < 0)
  2572. return idx;
  2573. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2574. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2575. idx, mi2s_tx_cfg[idx].channels);
  2576. return 1;
  2577. }
  2578. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2579. struct snd_ctl_elem_value *ucontrol)
  2580. {
  2581. int idx = mi2s_get_port_idx(kcontrol);
  2582. if (idx < 0)
  2583. return idx;
  2584. ucontrol->value.enumerated.item[0] =
  2585. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2586. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2587. idx, mi2s_rx_cfg[idx].bit_format,
  2588. ucontrol->value.enumerated.item[0]);
  2589. return 0;
  2590. }
  2591. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2592. struct snd_ctl_elem_value *ucontrol)
  2593. {
  2594. struct msm_asoc_mach_data *pdata = NULL;
  2595. struct snd_soc_component *component = NULL;
  2596. struct snd_soc_card *card = NULL;
  2597. int idx = mi2s_get_port_idx(kcontrol);
  2598. component = snd_soc_kcontrol_component(kcontrol);
  2599. card = kcontrol->private_data;
  2600. pdata = snd_soc_card_get_drvdata(card);
  2601. if (idx < 0)
  2602. return idx;
  2603. /* check for PRIM_MI2S and CSRAx config to allow 24bit BE config only */
  2604. if ((PRIM_MI2S == idx) && (true==pdata->codec_is_csra))
  2605. {
  2606. mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2607. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  2608. __func__, idx, mi2s_rx_cfg[idx].bit_format,
  2609. ucontrol->value.enumerated.item[0]);
  2610. } else {
  2611. mi2s_rx_cfg[idx].bit_format =
  2612. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2613. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2614. idx, mi2s_rx_cfg[idx].bit_format,
  2615. ucontrol->value.enumerated.item[0]);
  2616. }
  2617. return 0;
  2618. }
  2619. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2620. struct snd_ctl_elem_value *ucontrol)
  2621. {
  2622. int idx = mi2s_get_port_idx(kcontrol);
  2623. if (idx < 0)
  2624. return idx;
  2625. ucontrol->value.enumerated.item[0] =
  2626. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2627. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2628. idx, mi2s_tx_cfg[idx].bit_format,
  2629. ucontrol->value.enumerated.item[0]);
  2630. return 0;
  2631. }
  2632. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2633. struct snd_ctl_elem_value *ucontrol)
  2634. {
  2635. int idx = mi2s_get_port_idx(kcontrol);
  2636. if (idx < 0)
  2637. return idx;
  2638. mi2s_tx_cfg[idx].bit_format =
  2639. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2640. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2641. idx, mi2s_tx_cfg[idx].bit_format,
  2642. ucontrol->value.enumerated.item[0]);
  2643. return 0;
  2644. }
  2645. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2646. struct snd_ctl_elem_value *ucontrol)
  2647. {
  2648. int idx = aux_pcm_get_port_idx(kcontrol);
  2649. if (idx < 0)
  2650. return idx;
  2651. ucontrol->value.enumerated.item[0] =
  2652. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2653. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2654. idx, aux_pcm_rx_cfg[idx].bit_format,
  2655. ucontrol->value.enumerated.item[0]);
  2656. return 0;
  2657. }
  2658. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2659. struct snd_ctl_elem_value *ucontrol)
  2660. {
  2661. int idx = aux_pcm_get_port_idx(kcontrol);
  2662. if (idx < 0)
  2663. return idx;
  2664. aux_pcm_rx_cfg[idx].bit_format =
  2665. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2666. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2667. idx, aux_pcm_rx_cfg[idx].bit_format,
  2668. ucontrol->value.enumerated.item[0]);
  2669. return 0;
  2670. }
  2671. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2672. struct snd_ctl_elem_value *ucontrol)
  2673. {
  2674. int idx = aux_pcm_get_port_idx(kcontrol);
  2675. if (idx < 0)
  2676. return idx;
  2677. ucontrol->value.enumerated.item[0] =
  2678. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2679. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2680. idx, aux_pcm_tx_cfg[idx].bit_format,
  2681. ucontrol->value.enumerated.item[0]);
  2682. return 0;
  2683. }
  2684. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2685. struct snd_ctl_elem_value *ucontrol)
  2686. {
  2687. int idx = aux_pcm_get_port_idx(kcontrol);
  2688. if (idx < 0)
  2689. return idx;
  2690. aux_pcm_tx_cfg[idx].bit_format =
  2691. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2692. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2693. idx, aux_pcm_tx_cfg[idx].bit_format,
  2694. ucontrol->value.enumerated.item[0]);
  2695. return 0;
  2696. }
  2697. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2698. {
  2699. int idx;
  2700. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2701. sizeof("PRIM_SPDIF_RX")))
  2702. idx = PRIM_SPDIF_RX;
  2703. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2704. sizeof("SEC_SPDIF_RX")))
  2705. idx = SEC_SPDIF_RX;
  2706. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2707. sizeof("PRIM_SPDIF_TX")))
  2708. idx = PRIM_SPDIF_TX;
  2709. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2710. sizeof("SEC_SPDIF_TX")))
  2711. idx = SEC_SPDIF_TX;
  2712. else {
  2713. pr_err("%s: unsupported channel: %s",
  2714. __func__, kcontrol->id.name);
  2715. idx = -EINVAL;
  2716. }
  2717. return idx;
  2718. }
  2719. static int spdif_get_sample_rate_val(int sample_rate)
  2720. {
  2721. int sample_rate_val;
  2722. switch (sample_rate) {
  2723. case SAMPLING_RATE_32KHZ:
  2724. sample_rate_val = 0;
  2725. break;
  2726. case SAMPLING_RATE_44P1KHZ:
  2727. sample_rate_val = 1;
  2728. break;
  2729. case SAMPLING_RATE_48KHZ:
  2730. sample_rate_val = 2;
  2731. break;
  2732. case SAMPLING_RATE_88P2KHZ:
  2733. sample_rate_val = 3;
  2734. break;
  2735. case SAMPLING_RATE_96KHZ:
  2736. sample_rate_val = 4;
  2737. break;
  2738. case SAMPLING_RATE_176P4KHZ:
  2739. sample_rate_val = 5;
  2740. break;
  2741. case SAMPLING_RATE_192KHZ:
  2742. sample_rate_val = 6;
  2743. break;
  2744. default:
  2745. sample_rate_val = 2;
  2746. break;
  2747. }
  2748. return sample_rate_val;
  2749. }
  2750. static int spdif_get_sample_rate(int value)
  2751. {
  2752. int sample_rate;
  2753. switch (value) {
  2754. case 0:
  2755. sample_rate = SAMPLING_RATE_32KHZ;
  2756. break;
  2757. case 1:
  2758. sample_rate = SAMPLING_RATE_44P1KHZ;
  2759. break;
  2760. case 2:
  2761. sample_rate = SAMPLING_RATE_48KHZ;
  2762. break;
  2763. case 3:
  2764. sample_rate = SAMPLING_RATE_88P2KHZ;
  2765. break;
  2766. case 4:
  2767. sample_rate = SAMPLING_RATE_96KHZ;
  2768. break;
  2769. case 5:
  2770. sample_rate = SAMPLING_RATE_176P4KHZ;
  2771. break;
  2772. case 6:
  2773. sample_rate = SAMPLING_RATE_192KHZ;
  2774. break;
  2775. default:
  2776. sample_rate = SAMPLING_RATE_48KHZ;
  2777. break;
  2778. }
  2779. return sample_rate;
  2780. }
  2781. static int spdif_get_format(int value)
  2782. {
  2783. int format;
  2784. switch (value) {
  2785. case 0:
  2786. format = SNDRV_PCM_FORMAT_S16_LE;
  2787. break;
  2788. case 1:
  2789. format = SNDRV_PCM_FORMAT_S24_LE;
  2790. break;
  2791. default:
  2792. format = SNDRV_PCM_FORMAT_S16_LE;
  2793. break;
  2794. }
  2795. return format;
  2796. }
  2797. static int spdif_get_format_value(int format)
  2798. {
  2799. int value;
  2800. switch (format) {
  2801. case SNDRV_PCM_FORMAT_S16_LE:
  2802. value = 0;
  2803. break;
  2804. case SNDRV_PCM_FORMAT_S24_LE:
  2805. value = 1;
  2806. break;
  2807. default:
  2808. value = 0;
  2809. break;
  2810. }
  2811. return value;
  2812. }
  2813. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2814. struct snd_ctl_elem_value *ucontrol)
  2815. {
  2816. int idx = spdif_get_port_idx(kcontrol);
  2817. if (idx < 0)
  2818. return idx;
  2819. spdif_rx_cfg[idx].sample_rate =
  2820. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2821. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2822. idx, spdif_rx_cfg[idx].sample_rate,
  2823. ucontrol->value.enumerated.item[0]);
  2824. return 0;
  2825. }
  2826. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2827. struct snd_ctl_elem_value *ucontrol)
  2828. {
  2829. int idx = spdif_get_port_idx(kcontrol);
  2830. if (idx < 0)
  2831. return idx;
  2832. ucontrol->value.enumerated.item[0] =
  2833. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2834. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2835. idx, spdif_rx_cfg[idx].sample_rate,
  2836. ucontrol->value.enumerated.item[0]);
  2837. return 0;
  2838. }
  2839. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2840. struct snd_ctl_elem_value *ucontrol)
  2841. {
  2842. int idx = spdif_get_port_idx(kcontrol);
  2843. if (idx < 0)
  2844. return idx;
  2845. spdif_tx_cfg[idx].sample_rate =
  2846. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2847. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2848. idx, spdif_tx_cfg[idx].sample_rate,
  2849. ucontrol->value.enumerated.item[0]);
  2850. return 0;
  2851. }
  2852. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2853. struct snd_ctl_elem_value *ucontrol)
  2854. {
  2855. int idx = spdif_get_port_idx(kcontrol);
  2856. if (idx < 0)
  2857. return idx;
  2858. ucontrol->value.enumerated.item[0] =
  2859. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2860. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2861. idx, spdif_tx_cfg[idx].sample_rate,
  2862. ucontrol->value.enumerated.item[0]);
  2863. return 0;
  2864. }
  2865. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2866. struct snd_ctl_elem_value *ucontrol)
  2867. {
  2868. int idx = spdif_get_port_idx(kcontrol);
  2869. if (idx < 0)
  2870. return idx;
  2871. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2872. idx, spdif_rx_cfg[idx].channels);
  2873. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2874. return 0;
  2875. }
  2876. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2877. struct snd_ctl_elem_value *ucontrol)
  2878. {
  2879. int idx = spdif_get_port_idx(kcontrol);
  2880. if (idx < 0)
  2881. return idx;
  2882. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2883. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2884. idx, spdif_rx_cfg[idx].channels);
  2885. return 1;
  2886. }
  2887. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2888. struct snd_ctl_elem_value *ucontrol)
  2889. {
  2890. int idx = spdif_get_port_idx(kcontrol);
  2891. if (idx < 0)
  2892. return idx;
  2893. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2894. idx, spdif_tx_cfg[idx].channels);
  2895. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2896. return 0;
  2897. }
  2898. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2899. struct snd_ctl_elem_value *ucontrol)
  2900. {
  2901. int idx = spdif_get_port_idx(kcontrol);
  2902. if (idx < 0)
  2903. return idx;
  2904. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2905. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2906. idx, spdif_tx_cfg[idx].channels);
  2907. return 1;
  2908. }
  2909. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2910. struct snd_ctl_elem_value *ucontrol)
  2911. {
  2912. int idx = spdif_get_port_idx(kcontrol);
  2913. if (idx < 0)
  2914. return idx;
  2915. ucontrol->value.enumerated.item[0] =
  2916. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2917. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2918. idx, spdif_rx_cfg[idx].bit_format,
  2919. ucontrol->value.enumerated.item[0]);
  2920. return 0;
  2921. }
  2922. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2923. struct snd_ctl_elem_value *ucontrol)
  2924. {
  2925. int idx = spdif_get_port_idx(kcontrol);
  2926. if (idx < 0)
  2927. return idx;
  2928. spdif_rx_cfg[idx].bit_format =
  2929. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2930. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2931. idx, spdif_rx_cfg[idx].bit_format,
  2932. ucontrol->value.enumerated.item[0]);
  2933. return 0;
  2934. }
  2935. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  2936. struct snd_ctl_elem_value *ucontrol)
  2937. {
  2938. int idx = spdif_get_port_idx(kcontrol);
  2939. if (idx < 0)
  2940. return idx;
  2941. ucontrol->value.enumerated.item[0] =
  2942. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  2943. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2944. idx, spdif_tx_cfg[idx].bit_format,
  2945. ucontrol->value.enumerated.item[0]);
  2946. return 0;
  2947. }
  2948. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  2949. struct snd_ctl_elem_value *ucontrol)
  2950. {
  2951. int idx = spdif_get_port_idx(kcontrol);
  2952. if (idx < 0)
  2953. return idx;
  2954. spdif_tx_cfg[idx].bit_format =
  2955. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2956. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2957. idx, spdif_tx_cfg[idx].bit_format,
  2958. ucontrol->value.enumerated.item[0]);
  2959. return 0;
  2960. }
  2961. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2962. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2963. slim_rx_ch_get, slim_rx_ch_put),
  2964. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2965. slim_rx_ch_get, slim_rx_ch_put),
  2966. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2967. slim_tx_ch_get, slim_tx_ch_put),
  2968. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2969. slim_tx_ch_get, slim_tx_ch_put),
  2970. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2971. slim_rx_ch_get, slim_rx_ch_put),
  2972. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2973. slim_rx_ch_get, slim_rx_ch_put),
  2974. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2975. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2976. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2977. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2978. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2979. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2980. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2981. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2982. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2983. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2984. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2985. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2986. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2987. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2988. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2989. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2990. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2991. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2992. };
  2993. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2994. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2995. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2996. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2997. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2998. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2999. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3000. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  3001. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3002. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3003. va_cdc_dma_tx_0_sample_rate,
  3004. cdc_dma_tx_sample_rate_get,
  3005. cdc_dma_tx_sample_rate_put),
  3006. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3007. va_cdc_dma_tx_1_sample_rate,
  3008. cdc_dma_tx_sample_rate_get,
  3009. cdc_dma_tx_sample_rate_put),
  3010. };
  3011. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  3012. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3013. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3014. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3015. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3016. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3017. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3018. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3019. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3020. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3021. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3022. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3023. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3024. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3025. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3026. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3027. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3028. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3029. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3030. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3031. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3032. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3033. wsa_cdc_dma_rx_0_sample_rate,
  3034. cdc_dma_rx_sample_rate_get,
  3035. cdc_dma_rx_sample_rate_put),
  3036. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3037. wsa_cdc_dma_rx_1_sample_rate,
  3038. cdc_dma_rx_sample_rate_get,
  3039. cdc_dma_rx_sample_rate_put),
  3040. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3041. wsa_cdc_dma_tx_0_sample_rate,
  3042. cdc_dma_tx_sample_rate_get,
  3043. cdc_dma_tx_sample_rate_put),
  3044. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3045. wsa_cdc_dma_tx_1_sample_rate,
  3046. cdc_dma_tx_sample_rate_get,
  3047. cdc_dma_tx_sample_rate_put),
  3048. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3049. wsa_cdc_dma_tx_2_sample_rate,
  3050. cdc_dma_tx_sample_rate_get,
  3051. cdc_dma_tx_sample_rate_put),
  3052. };
  3053. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3054. SOC_ENUM_EXT("BT_TX SampleRate", bt_sample_rate_sink,
  3055. msm_bt_sample_rate_sink_get,
  3056. msm_bt_sample_rate_sink_put),
  3057. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3058. msm_bt_sample_rate_get,
  3059. msm_bt_sample_rate_put),
  3060. SOC_ENUM_EXT("BT_RX SampleRate", bt_sample_rate,
  3061. msm_bt_sample_rate_get,
  3062. msm_bt_sample_rate_put),
  3063. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3064. proxy_rx_ch_get, proxy_rx_ch_put),
  3065. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3066. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3067. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3068. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3069. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3070. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3071. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3072. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3073. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3074. usb_audio_rx_sample_rate_get,
  3075. usb_audio_rx_sample_rate_put),
  3076. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3077. usb_audio_tx_sample_rate_get,
  3078. usb_audio_tx_sample_rate_put),
  3079. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3080. tdm_rx_sample_rate_get,
  3081. tdm_rx_sample_rate_put),
  3082. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3083. tdm_tx_sample_rate_get,
  3084. tdm_tx_sample_rate_put),
  3085. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3086. tdm_rx_format_get,
  3087. tdm_rx_format_put),
  3088. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3089. tdm_tx_format_get,
  3090. tdm_tx_format_put),
  3091. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3092. tdm_rx_ch_get,
  3093. tdm_rx_ch_put),
  3094. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3095. tdm_tx_ch_get,
  3096. tdm_tx_ch_put),
  3097. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3098. tdm_rx_sample_rate_get,
  3099. tdm_rx_sample_rate_put),
  3100. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3101. tdm_tx_sample_rate_get,
  3102. tdm_tx_sample_rate_put),
  3103. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3104. tdm_rx_format_get,
  3105. tdm_rx_format_put),
  3106. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3107. tdm_tx_format_get,
  3108. tdm_tx_format_put),
  3109. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3110. tdm_rx_ch_get,
  3111. tdm_rx_ch_put),
  3112. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3113. tdm_tx_ch_get,
  3114. tdm_tx_ch_put),
  3115. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3116. tdm_rx_sample_rate_get,
  3117. tdm_rx_sample_rate_put),
  3118. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3119. tdm_tx_sample_rate_get,
  3120. tdm_tx_sample_rate_put),
  3121. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3122. tdm_rx_format_get,
  3123. tdm_rx_format_put),
  3124. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3125. tdm_tx_format_get,
  3126. tdm_tx_format_put),
  3127. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3128. tdm_rx_ch_get,
  3129. tdm_rx_ch_put),
  3130. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3131. tdm_tx_ch_get,
  3132. tdm_tx_ch_put),
  3133. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3134. tdm_rx_sample_rate_get,
  3135. tdm_rx_sample_rate_put),
  3136. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3137. tdm_tx_sample_rate_get,
  3138. tdm_tx_sample_rate_put),
  3139. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3140. tdm_rx_format_get,
  3141. tdm_rx_format_put),
  3142. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3143. tdm_tx_format_get,
  3144. tdm_tx_format_put),
  3145. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3146. tdm_rx_ch_get,
  3147. tdm_rx_ch_put),
  3148. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3149. tdm_tx_ch_get,
  3150. tdm_tx_ch_put),
  3151. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3152. tdm_rx_sample_rate_get,
  3153. tdm_rx_sample_rate_put),
  3154. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3155. tdm_tx_sample_rate_get,
  3156. tdm_tx_sample_rate_put),
  3157. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3158. tdm_rx_format_get,
  3159. tdm_rx_format_put),
  3160. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3161. tdm_tx_format_get,
  3162. tdm_tx_format_put),
  3163. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3164. tdm_rx_ch_get,
  3165. tdm_rx_ch_put),
  3166. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3167. tdm_tx_ch_get,
  3168. tdm_tx_ch_put),
  3169. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3170. aux_pcm_rx_sample_rate_get,
  3171. aux_pcm_rx_sample_rate_put),
  3172. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3173. aux_pcm_rx_sample_rate_get,
  3174. aux_pcm_rx_sample_rate_put),
  3175. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3176. aux_pcm_rx_sample_rate_get,
  3177. aux_pcm_rx_sample_rate_put),
  3178. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3179. aux_pcm_rx_sample_rate_get,
  3180. aux_pcm_rx_sample_rate_put),
  3181. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3182. aux_pcm_rx_sample_rate_get,
  3183. aux_pcm_rx_sample_rate_put),
  3184. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3185. aux_pcm_tx_sample_rate_get,
  3186. aux_pcm_tx_sample_rate_put),
  3187. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3188. aux_pcm_tx_sample_rate_get,
  3189. aux_pcm_tx_sample_rate_put),
  3190. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3191. aux_pcm_tx_sample_rate_get,
  3192. aux_pcm_tx_sample_rate_put),
  3193. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3194. aux_pcm_tx_sample_rate_get,
  3195. aux_pcm_tx_sample_rate_put),
  3196. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3197. aux_pcm_tx_sample_rate_get,
  3198. aux_pcm_tx_sample_rate_put),
  3199. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3200. aux_pcm_tx_sample_rate_get,
  3201. aux_pcm_tx_sample_rate_put),
  3202. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3203. mi2s_rx_sample_rate_get,
  3204. mi2s_rx_sample_rate_put),
  3205. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3206. mi2s_rx_sample_rate_get,
  3207. mi2s_rx_sample_rate_put),
  3208. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3209. mi2s_rx_sample_rate_get,
  3210. mi2s_rx_sample_rate_put),
  3211. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3212. mi2s_rx_sample_rate_get,
  3213. mi2s_rx_sample_rate_put),
  3214. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3215. mi2s_rx_sample_rate_get,
  3216. mi2s_rx_sample_rate_put),
  3217. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3218. mi2s_rx_sample_rate_get,
  3219. mi2s_rx_sample_rate_put),
  3220. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3221. mi2s_tx_sample_rate_get,
  3222. mi2s_tx_sample_rate_put),
  3223. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3224. mi2s_tx_sample_rate_get,
  3225. mi2s_tx_sample_rate_put),
  3226. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3227. mi2s_tx_sample_rate_get,
  3228. mi2s_tx_sample_rate_put),
  3229. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3230. mi2s_tx_sample_rate_get,
  3231. mi2s_tx_sample_rate_put),
  3232. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3233. mi2s_tx_sample_rate_get,
  3234. mi2s_tx_sample_rate_put),
  3235. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3236. mi2s_tx_sample_rate_get,
  3237. mi2s_tx_sample_rate_put),
  3238. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3239. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3240. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3241. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3242. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3243. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3244. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3245. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3246. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3247. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3248. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3249. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3250. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3251. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3252. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3253. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3254. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3255. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3256. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3257. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3258. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3259. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3260. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3261. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3262. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3263. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3264. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3265. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3266. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3267. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3268. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3269. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3270. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3271. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3272. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3273. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3274. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3275. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3276. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3277. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3278. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3279. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3280. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3281. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3282. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3283. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3284. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3285. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3286. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3287. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3288. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3289. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3290. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3291. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3292. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3293. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3294. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3295. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3296. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3297. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3298. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3299. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3300. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3301. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3302. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3303. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3304. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3305. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3306. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3307. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3308. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3309. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3310. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3311. msm_snd_vad_cfg_put),
  3312. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3313. msm_spdif_rx_sample_rate_get,
  3314. msm_spdif_rx_sample_rate_put),
  3315. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3316. msm_spdif_tx_sample_rate_get,
  3317. msm_spdif_tx_sample_rate_put),
  3318. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3319. msm_spdif_rx_sample_rate_get,
  3320. msm_spdif_rx_sample_rate_put),
  3321. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3322. msm_spdif_tx_sample_rate_get,
  3323. msm_spdif_tx_sample_rate_put),
  3324. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3325. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3326. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3327. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3328. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3329. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3330. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3331. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3332. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3333. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3334. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3335. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3336. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3337. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3338. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3339. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3340. };
  3341. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  3342. int enable, bool dapm)
  3343. {
  3344. int ret = 0;
  3345. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3346. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  3347. } else {
  3348. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  3349. __func__);
  3350. ret = -EINVAL;
  3351. }
  3352. return ret;
  3353. }
  3354. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  3355. int enable, bool dapm)
  3356. {
  3357. int ret = 0;
  3358. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  3359. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  3360. } else {
  3361. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  3362. __func__);
  3363. ret = -EINVAL;
  3364. }
  3365. return ret;
  3366. }
  3367. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3368. struct snd_kcontrol *kcontrol, int event)
  3369. {
  3370. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3371. pr_debug("%s: event = %d\n", __func__, event);
  3372. switch (event) {
  3373. case SND_SOC_DAPM_PRE_PMU:
  3374. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  3375. case SND_SOC_DAPM_POST_PMD:
  3376. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  3377. }
  3378. return 0;
  3379. }
  3380. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3381. struct snd_kcontrol *kcontrol, int event)
  3382. {
  3383. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3384. pr_debug("%s: event = %d\n", __func__, event);
  3385. switch (event) {
  3386. case SND_SOC_DAPM_PRE_PMU:
  3387. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  3388. case SND_SOC_DAPM_POST_PMD:
  3389. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  3390. }
  3391. return 0;
  3392. }
  3393. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3394. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3395. msm_mclk_event,
  3396. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3397. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3398. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3399. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3400. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3401. };
  3402. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3403. struct snd_kcontrol *kcontrol, int event)
  3404. {
  3405. struct msm_asoc_mach_data *pdata = NULL;
  3406. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  3407. int ret = 0;
  3408. uint32_t dmic_idx;
  3409. int *dmic_gpio_cnt;
  3410. struct device_node *dmic_gpio;
  3411. char *wname;
  3412. wname = strpbrk(w->name, "01234567");
  3413. if (!wname) {
  3414. dev_err(codec->dev, "%s: widget not found\n", __func__);
  3415. return -EINVAL;
  3416. }
  3417. ret = kstrtouint(wname, 10, &dmic_idx);
  3418. if (ret < 0) {
  3419. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  3420. __func__);
  3421. return -EINVAL;
  3422. }
  3423. pdata = snd_soc_card_get_drvdata(codec->component.card);
  3424. switch (dmic_idx) {
  3425. case 0:
  3426. case 1:
  3427. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3428. dmic_gpio = pdata->dmic_01_gpio_p;
  3429. break;
  3430. case 2:
  3431. case 3:
  3432. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3433. dmic_gpio = pdata->dmic_23_gpio_p;
  3434. break;
  3435. case 4:
  3436. case 5:
  3437. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3438. dmic_gpio = pdata->dmic_45_gpio_p;
  3439. break;
  3440. case 6:
  3441. case 7:
  3442. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3443. dmic_gpio = pdata->dmic_67_gpio_p;
  3444. break;
  3445. default:
  3446. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  3447. __func__);
  3448. return -EINVAL;
  3449. }
  3450. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3451. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3452. switch (event) {
  3453. case SND_SOC_DAPM_PRE_PMU:
  3454. (*dmic_gpio_cnt)++;
  3455. if (*dmic_gpio_cnt == 1) {
  3456. ret = msm_cdc_pinctrl_select_active_state(
  3457. dmic_gpio);
  3458. if (ret < 0) {
  3459. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  3460. __func__, "dmic_gpio");
  3461. return ret;
  3462. }
  3463. }
  3464. break;
  3465. case SND_SOC_DAPM_POST_PMD:
  3466. (*dmic_gpio_cnt)--;
  3467. if (*dmic_gpio_cnt == 0) {
  3468. ret = msm_cdc_pinctrl_select_sleep_state(
  3469. dmic_gpio);
  3470. if (ret < 0) {
  3471. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  3472. __func__, "dmic_gpio");
  3473. return ret;
  3474. }
  3475. }
  3476. break;
  3477. default:
  3478. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3479. __func__, event);
  3480. return -EINVAL;
  3481. }
  3482. return 0;
  3483. }
  3484. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3485. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3486. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3487. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3488. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3489. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3490. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3491. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3492. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3493. };
  3494. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3495. };
  3496. static inline int param_is_mask(int p)
  3497. {
  3498. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3499. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3500. }
  3501. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3502. int n)
  3503. {
  3504. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3505. }
  3506. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3507. unsigned int bit)
  3508. {
  3509. if (bit >= SNDRV_MASK_MAX)
  3510. return;
  3511. if (param_is_mask(n)) {
  3512. struct snd_mask *m = param_to_mask(p, n);
  3513. m->bits[0] = 0;
  3514. m->bits[1] = 0;
  3515. m->bits[bit >> 5] |= (1 << (bit & 31));
  3516. }
  3517. }
  3518. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3519. {
  3520. int ch_id = 0;
  3521. switch (be_id) {
  3522. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3523. ch_id = SLIM_RX_0;
  3524. break;
  3525. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3526. ch_id = SLIM_RX_1;
  3527. break;
  3528. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3529. ch_id = SLIM_RX_2;
  3530. break;
  3531. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3532. ch_id = SLIM_RX_3;
  3533. break;
  3534. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3535. ch_id = SLIM_RX_4;
  3536. break;
  3537. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3538. ch_id = SLIM_RX_6;
  3539. break;
  3540. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3541. ch_id = SLIM_TX_0;
  3542. break;
  3543. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3544. ch_id = SLIM_TX_3;
  3545. break;
  3546. default:
  3547. ch_id = SLIM_RX_0;
  3548. break;
  3549. }
  3550. return ch_id;
  3551. }
  3552. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3553. {
  3554. *port_id = 0xFFFF;
  3555. switch (be_id) {
  3556. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3557. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3558. break;
  3559. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3560. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3561. break;
  3562. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3563. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3564. break;
  3565. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3566. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3567. break;
  3568. default:
  3569. return -EINVAL;
  3570. }
  3571. return 0;
  3572. }
  3573. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3574. {
  3575. int idx = 0;
  3576. switch (be_id) {
  3577. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3578. idx = WSA_CDC_DMA_RX_0;
  3579. break;
  3580. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3581. idx = WSA_CDC_DMA_TX_0;
  3582. break;
  3583. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3584. idx = WSA_CDC_DMA_RX_1;
  3585. break;
  3586. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3587. idx = WSA_CDC_DMA_TX_1;
  3588. break;
  3589. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3590. idx = WSA_CDC_DMA_TX_2;
  3591. break;
  3592. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3593. idx = VA_CDC_DMA_TX_0;
  3594. break;
  3595. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3596. idx = VA_CDC_DMA_TX_1;
  3597. break;
  3598. default:
  3599. idx = VA_CDC_DMA_TX_0;
  3600. break;
  3601. }
  3602. return idx;
  3603. }
  3604. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3605. struct snd_pcm_hw_params *params)
  3606. {
  3607. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3608. struct snd_interval *rate = hw_param_interval(params,
  3609. SNDRV_PCM_HW_PARAM_RATE);
  3610. struct snd_interval *channels = hw_param_interval(params,
  3611. SNDRV_PCM_HW_PARAM_CHANNELS);
  3612. int rc = 0;
  3613. int idx;
  3614. void *config = NULL;
  3615. struct snd_soc_codec *codec = NULL;
  3616. pr_debug("%s: format = %d, rate = %d\n",
  3617. __func__, params_format(params), params_rate(params));
  3618. switch (dai_link->id) {
  3619. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3620. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3621. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3622. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3623. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3624. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3625. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3626. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3627. slim_rx_cfg[idx].bit_format);
  3628. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3629. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3630. break;
  3631. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3632. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3633. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3634. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3635. slim_tx_cfg[idx].bit_format);
  3636. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3637. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3638. break;
  3639. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3640. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3641. slim_tx_cfg[1].bit_format);
  3642. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3643. channels->min = channels->max = slim_tx_cfg[1].channels;
  3644. break;
  3645. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3646. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3647. SNDRV_PCM_FORMAT_S32_LE);
  3648. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3649. channels->min = channels->max = msm_vi_feed_tx_ch;
  3650. break;
  3651. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3652. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3653. slim_rx_cfg[5].bit_format);
  3654. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3655. channels->min = channels->max = slim_rx_cfg[5].channels;
  3656. break;
  3657. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3658. codec = rtd->codec;
  3659. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3660. channels->min = channels->max = 1;
  3661. config = msm_codec_fn.get_afe_config_fn(codec,
  3662. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3663. if (config) {
  3664. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3665. config, SLIMBUS_5_TX);
  3666. if (rc)
  3667. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3668. __func__, rc);
  3669. }
  3670. break;
  3671. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3672. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3673. slim_rx_cfg[SLIM_RX_7].bit_format);
  3674. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3675. channels->min = channels->max =
  3676. slim_rx_cfg[SLIM_RX_7].channels;
  3677. break;
  3678. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3679. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3680. channels->min = channels->max =
  3681. slim_tx_cfg[SLIM_TX_7].channels;
  3682. break;
  3683. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3684. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3685. channels->min = channels->max =
  3686. slim_tx_cfg[SLIM_TX_8].channels;
  3687. break;
  3688. case MSM_BACKEND_DAI_SLIMBUS_9_TX:
  3689. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3690. slim_tx_cfg[SLIM_TX_9].bit_format);
  3691. rate->min = rate->max = slim_tx_cfg[SLIM_TX_9].sample_rate;
  3692. channels->min = channels->max =
  3693. slim_tx_cfg[SLIM_TX_9].channels;
  3694. break;
  3695. case MSM_BACKEND_DAI_USB_RX:
  3696. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3697. usb_rx_cfg.bit_format);
  3698. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3699. channels->min = channels->max = usb_rx_cfg.channels;
  3700. break;
  3701. case MSM_BACKEND_DAI_USB_TX:
  3702. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3703. usb_tx_cfg.bit_format);
  3704. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3705. channels->min = channels->max = usb_tx_cfg.channels;
  3706. break;
  3707. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3708. channels->min = channels->max = proxy_rx_cfg.channels;
  3709. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3710. break;
  3711. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3712. channels->min = channels->max =
  3713. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3714. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3715. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3716. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3717. break;
  3718. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3719. channels->min = channels->max =
  3720. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3721. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3722. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3723. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3724. break;
  3725. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3726. channels->min = channels->max =
  3727. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3728. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3729. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3730. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3731. break;
  3732. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3733. channels->min = channels->max =
  3734. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3735. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3736. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3737. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3738. break;
  3739. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3740. channels->min = channels->max =
  3741. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3742. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3743. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3744. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3745. break;
  3746. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3747. channels->min = channels->max =
  3748. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3749. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3750. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3751. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3752. break;
  3753. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3754. channels->min = channels->max =
  3755. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3756. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3757. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3758. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3759. break;
  3760. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3761. channels->min = channels->max =
  3762. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3763. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3764. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3765. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3766. break;
  3767. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3768. channels->min = channels->max =
  3769. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3770. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3771. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3772. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3773. break;
  3774. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3775. channels->min = channels->max =
  3776. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3777. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3778. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3779. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3780. break;
  3781. case MSM_BACKEND_DAI_AUXPCM_RX:
  3782. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3783. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3784. rate->min = rate->max =
  3785. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3786. channels->min = channels->max =
  3787. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3788. break;
  3789. case MSM_BACKEND_DAI_AUXPCM_TX:
  3790. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3791. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3792. rate->min = rate->max =
  3793. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3794. channels->min = channels->max =
  3795. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3796. break;
  3797. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3798. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3799. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3800. rate->min = rate->max =
  3801. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3802. channels->min = channels->max =
  3803. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3804. break;
  3805. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3806. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3807. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3808. rate->min = rate->max =
  3809. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3810. channels->min = channels->max =
  3811. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3812. break;
  3813. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3814. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3815. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3816. rate->min = rate->max =
  3817. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3818. channels->min = channels->max =
  3819. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3820. break;
  3821. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3822. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3823. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3824. rate->min = rate->max =
  3825. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3826. channels->min = channels->max =
  3827. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3828. break;
  3829. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3830. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3831. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3832. rate->min = rate->max =
  3833. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3834. channels->min = channels->max =
  3835. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3836. break;
  3837. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3838. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3839. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3840. rate->min = rate->max =
  3841. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3842. channels->min = channels->max =
  3843. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3844. break;
  3845. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3846. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3847. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3848. rate->min = rate->max =
  3849. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3850. channels->min = channels->max =
  3851. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3852. break;
  3853. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3854. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3855. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3856. rate->min = rate->max =
  3857. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3858. channels->min = channels->max =
  3859. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3860. break;
  3861. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3862. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3863. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3864. rate->min = rate->max =
  3865. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3866. channels->min = channels->max =
  3867. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3868. break;
  3869. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3870. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3871. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3872. rate->min = rate->max =
  3873. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3874. channels->min = channels->max =
  3875. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3876. break;
  3877. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3878. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3879. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3880. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3881. channels->min = channels->max =
  3882. mi2s_rx_cfg[PRIM_MI2S].channels;
  3883. break;
  3884. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3885. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3886. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3887. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3888. channels->min = channels->max =
  3889. mi2s_tx_cfg[PRIM_MI2S].channels;
  3890. break;
  3891. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3892. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3893. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3894. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3895. channels->min = channels->max =
  3896. mi2s_rx_cfg[SEC_MI2S].channels;
  3897. break;
  3898. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3899. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3900. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3901. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3902. channels->min = channels->max =
  3903. mi2s_tx_cfg[SEC_MI2S].channels;
  3904. break;
  3905. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3906. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3907. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3908. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3909. channels->min = channels->max =
  3910. mi2s_rx_cfg[TERT_MI2S].channels;
  3911. break;
  3912. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3913. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3914. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3915. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3916. channels->min = channels->max =
  3917. mi2s_tx_cfg[TERT_MI2S].channels;
  3918. break;
  3919. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3920. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3921. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3922. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3923. channels->min = channels->max =
  3924. mi2s_rx_cfg[QUAT_MI2S].channels;
  3925. break;
  3926. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3927. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3928. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3929. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3930. channels->min = channels->max =
  3931. mi2s_tx_cfg[QUAT_MI2S].channels;
  3932. break;
  3933. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3934. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3935. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3936. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3937. channels->min = channels->max =
  3938. mi2s_rx_cfg[QUIN_MI2S].channels;
  3939. break;
  3940. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3941. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3942. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3943. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3944. channels->min = channels->max =
  3945. mi2s_tx_cfg[QUIN_MI2S].channels;
  3946. break;
  3947. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3948. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3949. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3950. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3951. channels->min = channels->max =
  3952. mi2s_rx_cfg[SEN_MI2S].channels;
  3953. break;
  3954. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3955. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3956. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3957. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3958. channels->min = channels->max =
  3959. mi2s_tx_cfg[SEN_MI2S].channels;
  3960. break;
  3961. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3962. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3963. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3964. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3965. cdc_dma_rx_cfg[idx].bit_format);
  3966. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3967. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3968. break;
  3969. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3970. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3971. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3972. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3973. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3974. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3975. cdc_dma_tx_cfg[idx].bit_format);
  3976. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3977. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3978. break;
  3979. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3980. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3981. SNDRV_PCM_FORMAT_S32_LE);
  3982. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3983. channels->min = channels->max = msm_vi_feed_tx_ch;
  3984. break;
  3985. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  3986. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3987. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  3988. rate->min = rate->max =
  3989. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  3990. channels->min = channels->max =
  3991. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  3992. break;
  3993. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  3994. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3995. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  3996. rate->min = rate->max =
  3997. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  3998. channels->min = channels->max =
  3999. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  4000. break;
  4001. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  4002. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4003. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  4004. rate->min = rate->max =
  4005. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  4006. channels->min = channels->max =
  4007. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  4008. break;
  4009. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  4010. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4011. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  4012. rate->min = rate->max =
  4013. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  4014. channels->min = channels->max =
  4015. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  4016. break;
  4017. default:
  4018. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4019. break;
  4020. }
  4021. return rc;
  4022. }
  4023. static int msm_afe_set_config(struct snd_soc_codec *codec)
  4024. {
  4025. int ret = 0;
  4026. void *config_data = NULL;
  4027. if (!msm_codec_fn.get_afe_config_fn) {
  4028. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  4029. __func__);
  4030. return -EINVAL;
  4031. }
  4032. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4033. AFE_CDC_REGISTERS_CONFIG);
  4034. if (config_data) {
  4035. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  4036. if (ret) {
  4037. dev_err(codec->dev,
  4038. "%s: Failed to set codec registers config %d\n",
  4039. __func__, ret);
  4040. return ret;
  4041. }
  4042. }
  4043. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4044. AFE_CDC_REGISTER_PAGE_CONFIG);
  4045. if (config_data) {
  4046. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  4047. 0);
  4048. if (ret)
  4049. dev_err(codec->dev,
  4050. "%s: Failed to set cdc register page config\n",
  4051. __func__);
  4052. }
  4053. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4054. AFE_SLIMBUS_SLAVE_CONFIG);
  4055. if (config_data) {
  4056. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  4057. if (ret) {
  4058. dev_err(codec->dev,
  4059. "%s: Failed to set slimbus slave config %d\n",
  4060. __func__, ret);
  4061. return ret;
  4062. }
  4063. }
  4064. return 0;
  4065. }
  4066. static void msm_afe_clear_config(void)
  4067. {
  4068. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  4069. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  4070. }
  4071. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  4072. struct snd_card *card)
  4073. {
  4074. int ret = 0;
  4075. unsigned long timeout;
  4076. int adsp_ready = 0;
  4077. bool snd_card_online = 0;
  4078. timeout = jiffies +
  4079. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  4080. do {
  4081. if (!snd_card_online) {
  4082. snd_card_online = snd_card_is_online_state(card);
  4083. pr_debug("%s: Sound card is %s\n", __func__,
  4084. snd_card_online ? "Online" : "Offline");
  4085. }
  4086. if (!adsp_ready) {
  4087. adsp_ready = q6core_is_adsp_ready();
  4088. pr_debug("%s: ADSP Audio is %s\n", __func__,
  4089. adsp_ready ? "ready" : "not ready");
  4090. }
  4091. if (snd_card_online && adsp_ready)
  4092. break;
  4093. /*
  4094. * Sound card/ADSP will be coming up after subsystem restart and
  4095. * it might not be fully up when the control reaches
  4096. * here. So, wait for 50msec before checking ADSP state
  4097. */
  4098. msleep(50);
  4099. } while (time_after(timeout, jiffies));
  4100. if (!snd_card_online || !adsp_ready) {
  4101. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  4102. __func__,
  4103. snd_card_online ? "Online" : "Offline",
  4104. adsp_ready ? "ready" : "not ready");
  4105. ret = -ETIMEDOUT;
  4106. goto err;
  4107. }
  4108. ret = msm_afe_set_config(codec);
  4109. if (ret)
  4110. pr_err("%s: Failed to set AFE config. err %d\n",
  4111. __func__, ret);
  4112. return 0;
  4113. err:
  4114. return ret;
  4115. }
  4116. static int qcs405_notifier_service_cb(struct notifier_block *this,
  4117. unsigned long opcode, void *ptr)
  4118. {
  4119. int ret;
  4120. struct snd_soc_card *card = NULL;
  4121. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  4122. struct snd_soc_pcm_runtime *rtd;
  4123. struct snd_soc_codec *codec;
  4124. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  4125. switch (opcode) {
  4126. case AUDIO_NOTIFIER_SERVICE_DOWN:
  4127. /*
  4128. * Use flag to ignore initial boot notifications
  4129. * On initial boot msm_adsp_power_up_config is
  4130. * called on init. There is no need to clear
  4131. * and set the config again on initial boot.
  4132. */
  4133. if (is_initial_boot)
  4134. break;
  4135. msm_afe_clear_config();
  4136. break;
  4137. case AUDIO_NOTIFIER_SERVICE_UP:
  4138. if (is_initial_boot) {
  4139. is_initial_boot = false;
  4140. break;
  4141. }
  4142. if (!spdev)
  4143. return -EINVAL;
  4144. card = platform_get_drvdata(spdev);
  4145. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  4146. if (!rtd) {
  4147. dev_err(card->dev,
  4148. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  4149. __func__, be_dl_name);
  4150. ret = -EINVAL;
  4151. goto err;
  4152. }
  4153. codec = rtd->codec;
  4154. ret = msm_adsp_power_up_config(codec, card->snd_card);
  4155. if (ret < 0) {
  4156. dev_err(card->dev,
  4157. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  4158. __func__, ret);
  4159. goto err;
  4160. }
  4161. break;
  4162. default:
  4163. break;
  4164. }
  4165. err:
  4166. return NOTIFY_OK;
  4167. }
  4168. static struct notifier_block service_nb = {
  4169. .notifier_call = qcs405_notifier_service_cb,
  4170. .priority = -INT_MAX,
  4171. };
  4172. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4173. {
  4174. int ret = 0;
  4175. void *config_data;
  4176. struct snd_soc_codec *codec = rtd->codec;
  4177. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4178. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4179. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4180. struct snd_card *card;
  4181. struct msm_asoc_mach_data *pdata =
  4182. snd_soc_card_get_drvdata(rtd->card);
  4183. /*
  4184. * Codec SLIMBUS configuration
  4185. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4186. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4187. * TX14, TX15, TX16
  4188. */
  4189. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4190. 151, 152, 153, 154, 155, 156};
  4191. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4192. 134, 135, 136, 137, 138, 139,
  4193. 140, 141, 142, 143};
  4194. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4195. rtd->pmdown_time = 0;
  4196. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  4197. ARRAY_SIZE(msm_snd_sb_controls));
  4198. if (ret < 0) {
  4199. pr_err("%s: add_codec_controls failed, err %d\n",
  4200. __func__, ret);
  4201. return ret;
  4202. }
  4203. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4204. ARRAY_SIZE(msm_dapm_widgets));
  4205. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4206. ARRAY_SIZE(wcd_audio_paths));
  4207. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4208. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4209. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4210. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4211. snd_soc_dapm_sync(dapm);
  4212. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4213. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4214. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4215. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  4216. if (ret) {
  4217. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  4218. __func__, ret);
  4219. goto err;
  4220. }
  4221. config_data = msm_codec_fn.get_afe_config_fn(codec,
  4222. AFE_AANC_VERSION);
  4223. if (config_data) {
  4224. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4225. if (ret) {
  4226. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  4227. __func__, ret);
  4228. goto err;
  4229. }
  4230. }
  4231. card = rtd->card->snd_card;
  4232. if (!pdata->codec_root)
  4233. pdata->codec_root = snd_info_create_subdir(card->module,
  4234. "codecs", card->proc_root);
  4235. if (!pdata->codec_root) {
  4236. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4237. __func__);
  4238. ret = 0;
  4239. goto err;
  4240. }
  4241. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  4242. codec_reg_done = true;
  4243. return 0;
  4244. err:
  4245. return ret;
  4246. }
  4247. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4248. {
  4249. int ret = 0;
  4250. struct snd_soc_codec *codec = rtd->codec;
  4251. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4252. struct snd_card *card;
  4253. struct msm_asoc_mach_data *pdata =
  4254. snd_soc_card_get_drvdata(rtd->card);
  4255. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  4256. ARRAY_SIZE(msm_snd_va_controls));
  4257. if (ret < 0) {
  4258. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  4259. __func__, ret);
  4260. return ret;
  4261. }
  4262. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4263. ARRAY_SIZE(msm_va_dapm_widgets));
  4264. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4265. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4266. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4267. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4268. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4269. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4270. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4271. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4272. snd_soc_dapm_sync(dapm);
  4273. card = rtd->card->snd_card;
  4274. if (!pdata->codec_root)
  4275. pdata->codec_root = snd_info_create_subdir(card->module,
  4276. "codecs", card->proc_root);
  4277. if (!pdata->codec_root) {
  4278. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4279. __func__);
  4280. ret = 0;
  4281. goto done;
  4282. }
  4283. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4284. done:
  4285. return ret;
  4286. }
  4287. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4288. {
  4289. int ret = 0;
  4290. struct snd_soc_codec *codec = rtd->codec;
  4291. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  4292. struct snd_soc_component *aux_comp;
  4293. struct snd_card *card;
  4294. struct msm_asoc_mach_data *pdata =
  4295. snd_soc_card_get_drvdata(rtd->card);
  4296. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  4297. ARRAY_SIZE(msm_snd_wsa_controls));
  4298. if (ret < 0) {
  4299. dev_err(codec->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4300. __func__, ret);
  4301. return ret;
  4302. }
  4303. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4304. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4305. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4306. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4307. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4308. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4309. snd_soc_dapm_sync(dapm);
  4310. /*
  4311. * Send speaker configuration only for WSA8810.
  4312. * Default configuration is for WSA8815.
  4313. */
  4314. dev_dbg(codec->dev, "%s: Number of aux devices: %d\n",
  4315. __func__, rtd->card->num_aux_devs);
  4316. if (rtd->card->num_aux_devs &&
  4317. !list_empty(&rtd->card->component_dev_list)) {
  4318. aux_comp = list_first_entry(
  4319. &rtd->card->component_dev_list,
  4320. struct snd_soc_component,
  4321. card_aux_list);
  4322. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4323. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4324. wsa_macro_set_spkr_mode(rtd->codec,
  4325. WSA_MACRO_SPKR_MODE_1);
  4326. wsa_macro_set_spkr_gain_offset(rtd->codec,
  4327. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4328. }
  4329. }
  4330. card = rtd->card->snd_card;
  4331. if (!pdata->codec_root)
  4332. pdata->codec_root = snd_info_create_subdir(card->module,
  4333. "codecs", card->proc_root);
  4334. if (!pdata->codec_root) {
  4335. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4336. __func__);
  4337. ret = 0;
  4338. goto done;
  4339. }
  4340. bolero_info_create_codec_entry(pdata->codec_root, codec);
  4341. done:
  4342. return ret;
  4343. }
  4344. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4345. {
  4346. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4347. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161, 162};
  4348. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4349. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4350. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4351. }
  4352. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4353. struct snd_pcm_hw_params *params)
  4354. {
  4355. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4356. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4357. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4358. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4359. int ret = 0;
  4360. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4361. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4362. u32 user_set_tx_ch = 0;
  4363. u32 rx_ch_count;
  4364. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4365. ret = snd_soc_dai_get_channel_map(codec_dai,
  4366. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4367. if (ret < 0) {
  4368. pr_err("%s: failed to get codec chan map, err:%d\n",
  4369. __func__, ret);
  4370. goto err;
  4371. }
  4372. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4373. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4374. slim_rx_cfg[5].channels);
  4375. rx_ch_count = slim_rx_cfg[5].channels;
  4376. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4377. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4378. slim_rx_cfg[2].channels);
  4379. rx_ch_count = slim_rx_cfg[2].channels;
  4380. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4381. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4382. slim_rx_cfg[6].channels);
  4383. rx_ch_count = slim_rx_cfg[6].channels;
  4384. } else {
  4385. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4386. slim_rx_cfg[0].channels);
  4387. rx_ch_count = slim_rx_cfg[0].channels;
  4388. }
  4389. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4390. rx_ch_count, rx_ch);
  4391. if (ret < 0) {
  4392. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4393. __func__, ret);
  4394. goto err;
  4395. }
  4396. } else {
  4397. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4398. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4399. ret = snd_soc_dai_get_channel_map(codec_dai,
  4400. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4401. if (ret < 0) {
  4402. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4403. __func__, ret);
  4404. goto err;
  4405. }
  4406. /* For <codec>_tx1 case */
  4407. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4408. user_set_tx_ch = slim_tx_cfg[0].channels;
  4409. /* For <codec>_tx3 case */
  4410. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4411. user_set_tx_ch = slim_tx_cfg[1].channels;
  4412. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4413. user_set_tx_ch = msm_vi_feed_tx_ch;
  4414. else
  4415. user_set_tx_ch = tx_ch_cnt;
  4416. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4417. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4418. tx_ch_cnt, dai_link->id);
  4419. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4420. user_set_tx_ch, tx_ch, 0, 0);
  4421. if (ret < 0)
  4422. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4423. __func__, ret);
  4424. }
  4425. err:
  4426. return ret;
  4427. }
  4428. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4429. struct snd_pcm_hw_params *params)
  4430. {
  4431. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4432. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4433. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4434. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4435. int ret = 0;
  4436. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4437. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4438. u32 user_set_tx_ch = 0;
  4439. u32 user_set_rx_ch = 0;
  4440. u32 ch_id;
  4441. ret = snd_soc_dai_get_channel_map(codec_dai,
  4442. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4443. &rx_ch_cdc_dma);
  4444. if (ret < 0) {
  4445. pr_err("%s: failed to get codec chan map, err:%d\n",
  4446. __func__, ret);
  4447. goto err;
  4448. }
  4449. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4450. switch (dai_link->id) {
  4451. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4452. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4453. {
  4454. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4455. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4456. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4457. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4458. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4459. user_set_rx_ch, &rx_ch_cdc_dma);
  4460. if (ret < 0) {
  4461. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4462. __func__, ret);
  4463. goto err;
  4464. }
  4465. }
  4466. break;
  4467. }
  4468. } else {
  4469. switch (dai_link->id) {
  4470. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4471. {
  4472. user_set_tx_ch = msm_vi_feed_tx_ch;
  4473. }
  4474. break;
  4475. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4476. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4477. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4478. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4479. {
  4480. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4481. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4482. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4483. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4484. }
  4485. break;
  4486. }
  4487. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4488. &tx_ch_cdc_dma, 0, 0);
  4489. if (ret < 0) {
  4490. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4491. __func__, ret);
  4492. goto err;
  4493. }
  4494. }
  4495. err:
  4496. return ret;
  4497. }
  4498. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4499. struct snd_pcm_hw_params *params)
  4500. {
  4501. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4502. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4503. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4504. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4505. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4506. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4507. int ret;
  4508. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4509. codec_dai->name, codec_dai->id);
  4510. ret = snd_soc_dai_get_channel_map(codec_dai,
  4511. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4512. if (ret) {
  4513. dev_err(rtd->dev,
  4514. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4515. __func__, ret);
  4516. goto err;
  4517. }
  4518. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4519. __func__, tx_ch_cnt, dai_link->id);
  4520. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4521. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4522. if (ret)
  4523. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4524. __func__, ret);
  4525. err:
  4526. return ret;
  4527. }
  4528. static int msm_get_port_id(int be_id)
  4529. {
  4530. int afe_port_id;
  4531. switch (be_id) {
  4532. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4533. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4534. break;
  4535. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4536. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4537. break;
  4538. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4539. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4540. break;
  4541. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4542. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4543. break;
  4544. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4545. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4546. break;
  4547. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4548. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4549. break;
  4550. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4551. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4552. break;
  4553. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4554. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4555. break;
  4556. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4557. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4558. break;
  4559. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4560. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4561. break;
  4562. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4563. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  4564. break;
  4565. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4566. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  4567. break;
  4568. default:
  4569. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4570. afe_port_id = -EINVAL;
  4571. }
  4572. return afe_port_id;
  4573. }
  4574. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4575. {
  4576. u32 bit_per_sample;
  4577. switch (bit_format) {
  4578. case SNDRV_PCM_FORMAT_S32_LE:
  4579. case SNDRV_PCM_FORMAT_S24_3LE:
  4580. case SNDRV_PCM_FORMAT_S24_LE:
  4581. bit_per_sample = 32;
  4582. break;
  4583. case SNDRV_PCM_FORMAT_S16_LE:
  4584. default:
  4585. bit_per_sample = 16;
  4586. break;
  4587. }
  4588. return bit_per_sample;
  4589. }
  4590. static void update_mi2s_clk_val(int dai_id, int stream)
  4591. {
  4592. u32 bit_per_sample;
  4593. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4594. bit_per_sample =
  4595. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4596. mi2s_clk[dai_id].clk_freq_in_hz =
  4597. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4598. } else {
  4599. bit_per_sample =
  4600. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4601. mi2s_clk[dai_id].clk_freq_in_hz =
  4602. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4603. }
  4604. }
  4605. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4606. {
  4607. int ret = 0;
  4608. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4609. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4610. int port_id = 0;
  4611. int index = cpu_dai->id;
  4612. port_id = msm_get_port_id(rtd->dai_link->id);
  4613. if (port_id < 0) {
  4614. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4615. ret = port_id;
  4616. goto err;
  4617. }
  4618. if (enable) {
  4619. update_mi2s_clk_val(index, substream->stream);
  4620. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4621. mi2s_clk[index].clk_freq_in_hz);
  4622. }
  4623. mi2s_clk[index].enable = enable;
  4624. ret = afe_set_lpass_clock_v2(port_id,
  4625. &mi2s_clk[index]);
  4626. if (ret < 0) {
  4627. dev_err(rtd->card->dev,
  4628. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4629. __func__, port_id, ret);
  4630. goto err;
  4631. }
  4632. err:
  4633. return ret;
  4634. }
  4635. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4636. struct snd_pcm_hw_params *params)
  4637. {
  4638. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4639. struct snd_interval *rate = hw_param_interval(params,
  4640. SNDRV_PCM_HW_PARAM_RATE);
  4641. struct snd_interval *channels = hw_param_interval(params,
  4642. SNDRV_PCM_HW_PARAM_CHANNELS);
  4643. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4644. channels->min = channels->max =
  4645. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4646. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4647. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4648. rate->min = rate->max =
  4649. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4650. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4651. channels->min = channels->max =
  4652. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4653. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4654. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4655. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4656. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4657. channels->min = channels->max =
  4658. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4659. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4660. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4661. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4662. } else {
  4663. pr_err("%s: dai id 0x%x not supported\n",
  4664. __func__, cpu_dai->id);
  4665. return -EINVAL;
  4666. }
  4667. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4668. __func__, cpu_dai->id, channels->max, rate->max,
  4669. params_format(params));
  4670. return 0;
  4671. }
  4672. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4673. struct snd_pcm_hw_params *params)
  4674. {
  4675. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4676. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4677. int ret = 0;
  4678. int slot_width = 32;
  4679. int channels, slots = 8;
  4680. unsigned int slot_mask, rate, clk_freq;
  4681. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4682. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4683. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4684. switch (cpu_dai->id) {
  4685. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4686. channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4687. break;
  4688. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4689. channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4690. break;
  4691. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4692. channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4693. break;
  4694. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4695. channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4696. break;
  4697. case AFE_PORT_ID_QUINARY_TDM_RX:
  4698. channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4699. break;
  4700. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4701. channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4702. break;
  4703. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4704. channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4705. break;
  4706. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4707. channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4708. break;
  4709. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4710. channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4711. break;
  4712. case AFE_PORT_ID_QUINARY_TDM_TX:
  4713. channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4714. break;
  4715. default:
  4716. pr_err("%s: dai id 0x%x not supported\n",
  4717. __func__, cpu_dai->id);
  4718. return -EINVAL;
  4719. }
  4720. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4721. /*2 slot config - bits 0 and 1 set for the first two slots */
  4722. slot_mask = 0x0000FFFF >> (16-channels);
  4723. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4724. __func__, slot_width, slots);
  4725. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4726. slots, slot_width);
  4727. if (ret < 0) {
  4728. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4729. __func__, ret);
  4730. goto end;
  4731. }
  4732. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4733. 0, NULL, channels, slot_offset);
  4734. if (ret < 0) {
  4735. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4736. __func__, ret);
  4737. goto end;
  4738. }
  4739. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4740. /*2 slot config - bits 0 and 1 set for the first two slots */
  4741. slot_mask = 0x0000FFFF >> (16-channels);
  4742. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4743. __func__, slot_width, slots);
  4744. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4745. slots, slot_width);
  4746. if (ret < 0) {
  4747. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4748. __func__, ret);
  4749. goto end;
  4750. }
  4751. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4752. channels, slot_offset, 0, NULL);
  4753. if (ret < 0) {
  4754. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4755. __func__, ret);
  4756. goto end;
  4757. }
  4758. } else {
  4759. ret = -EINVAL;
  4760. pr_err("%s: invalid use case, err:%d\n",
  4761. __func__, ret);
  4762. goto end;
  4763. }
  4764. rate = params_rate(params);
  4765. clk_freq = rate * slot_width * slots;
  4766. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4767. if (ret < 0)
  4768. pr_err("%s: failed to set tdm clk, err:%d\n",
  4769. __func__, ret);
  4770. end:
  4771. return ret;
  4772. }
  4773. static int msm_get_tdm_mode(u32 port_id)
  4774. {
  4775. u32 tdm_mode;
  4776. switch (port_id) {
  4777. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4778. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4779. tdm_mode = TDM_PRI;
  4780. break;
  4781. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4782. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4783. tdm_mode = TDM_SEC;
  4784. break;
  4785. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4786. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4787. tdm_mode = TDM_TERT;
  4788. break;
  4789. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4790. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4791. tdm_mode = TDM_QUAT;
  4792. break;
  4793. case AFE_PORT_ID_QUINARY_TDM_RX:
  4794. case AFE_PORT_ID_QUINARY_TDM_TX:
  4795. tdm_mode = TDM_QUIN;
  4796. break;
  4797. default:
  4798. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  4799. tdm_mode = -EINVAL;
  4800. }
  4801. return tdm_mode;
  4802. }
  4803. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4804. {
  4805. int ret = 0;
  4806. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4807. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4808. struct snd_soc_card *card = rtd->card;
  4809. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4810. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4811. if (tdm_mode >= TDM_INTERFACE_MAX) {
  4812. ret = -EINVAL;
  4813. pr_err("%s: Invalid TDM interface %d\n",
  4814. __func__, ret);
  4815. return ret;
  4816. }
  4817. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4818. ret = msm_cdc_pinctrl_select_active_state(
  4819. pdata->mi2s_gpio_p[tdm_mode]);
  4820. if (ret)
  4821. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  4822. __func__, ret);
  4823. }
  4824. /* Enable Mic bias for TDM Mics */
  4825. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4826. if (pdata->tdm_micb_supply) {
  4827. ret = regulator_set_voltage(pdata->tdm_micb_supply,
  4828. pdata->tdm_micb_voltage,
  4829. pdata->tdm_micb_voltage);
  4830. if (ret) {
  4831. pr_err("%s: Setting voltage failed, err = %d\n",
  4832. __func__, ret);
  4833. return ret;
  4834. }
  4835. ret = regulator_set_load(pdata->tdm_micb_supply,
  4836. pdata->tdm_micb_current);
  4837. if (ret) {
  4838. pr_err("%s: Setting current failed, err = %d\n",
  4839. __func__, ret);
  4840. return ret;
  4841. }
  4842. ret = regulator_enable(pdata->tdm_micb_supply);
  4843. if (ret) {
  4844. pr_err("%s: regulator enable failed, err = %d\n",
  4845. __func__, ret);
  4846. return ret;
  4847. }
  4848. }
  4849. }
  4850. return ret;
  4851. }
  4852. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4853. {
  4854. int ret = 0;
  4855. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4856. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4857. struct snd_soc_card *card = rtd->card;
  4858. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4859. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4860. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  4861. if (pdata->tdm_micb_supply) {
  4862. ret = regulator_disable(pdata->tdm_micb_supply);
  4863. if (ret)
  4864. pr_err("%s: regulator disable failed, err = %d\n",
  4865. __func__, ret);
  4866. regulator_set_voltage(pdata->tdm_micb_supply, 0,
  4867. pdata->tdm_micb_voltage);
  4868. regulator_set_load(pdata->tdm_micb_supply, 0);
  4869. }
  4870. }
  4871. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4872. ret = msm_cdc_pinctrl_select_sleep_state(
  4873. pdata->mi2s_gpio_p[tdm_mode]);
  4874. if (ret)
  4875. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  4876. __func__, ret);
  4877. }
  4878. }
  4879. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4880. .hw_params = qcs405_tdm_snd_hw_params,
  4881. .startup = qcs405_tdm_snd_startup,
  4882. .shutdown = qcs405_tdm_snd_shutdown
  4883. };
  4884. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4885. {
  4886. cpumask_t mask;
  4887. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4888. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4889. cpumask_clear(&mask);
  4890. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4891. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4892. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4893. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4894. pm_qos_add_request(&substream->latency_pm_qos_req,
  4895. PM_QOS_CPU_DMA_LATENCY,
  4896. MSM_LL_QOS_VALUE);
  4897. return 0;
  4898. }
  4899. static struct snd_soc_ops msm_fe_qos_ops = {
  4900. .prepare = msm_fe_qos_prepare,
  4901. };
  4902. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4903. {
  4904. int ret = 0;
  4905. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4906. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4907. int index = cpu_dai->id;
  4908. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4909. struct snd_soc_card *card = rtd->card;
  4910. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4911. dev_dbg(rtd->card->dev,
  4912. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4913. __func__, substream->name, substream->stream,
  4914. cpu_dai->name, cpu_dai->id);
  4915. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4916. ret = -EINVAL;
  4917. dev_err(rtd->card->dev,
  4918. "%s: CPU DAI id (%d) out of range\n",
  4919. __func__, cpu_dai->id);
  4920. goto err;
  4921. }
  4922. /*
  4923. * Mutex protection in case the same MI2S
  4924. * interface using for both TX and RX so
  4925. * that the same clock won't be enable twice.
  4926. */
  4927. mutex_lock(&mi2s_intf_conf[index].lock);
  4928. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4929. /* Check if msm needs to provide the clock to the interface */
  4930. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4931. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4932. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4933. }
  4934. ret = msm_mi2s_set_sclk(substream, true);
  4935. if (ret < 0) {
  4936. dev_err(rtd->card->dev,
  4937. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4938. __func__, ret);
  4939. goto clean_up;
  4940. }
  4941. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4942. if (ret < 0) {
  4943. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4944. __func__, index, ret);
  4945. goto clk_off;
  4946. }
  4947. if (pdata->mi2s_gpio_p[index])
  4948. msm_cdc_pinctrl_select_active_state(
  4949. pdata->mi2s_gpio_p[index]);
  4950. }
  4951. clk_off:
  4952. if (ret < 0)
  4953. msm_mi2s_set_sclk(substream, false);
  4954. clean_up:
  4955. if (ret < 0)
  4956. mi2s_intf_conf[index].ref_cnt--;
  4957. mutex_unlock(&mi2s_intf_conf[index].lock);
  4958. err:
  4959. return ret;
  4960. }
  4961. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4962. {
  4963. int ret;
  4964. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4965. int index = rtd->cpu_dai->id;
  4966. struct snd_soc_card *card = rtd->card;
  4967. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4968. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4969. substream->name, substream->stream);
  4970. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4971. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4972. return;
  4973. }
  4974. mutex_lock(&mi2s_intf_conf[index].lock);
  4975. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4976. if (pdata->mi2s_gpio_p[index])
  4977. msm_cdc_pinctrl_select_sleep_state(
  4978. pdata->mi2s_gpio_p[index]);
  4979. ret = msm_mi2s_set_sclk(substream, false);
  4980. if (ret < 0)
  4981. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4982. __func__, index, ret);
  4983. }
  4984. mutex_unlock(&mi2s_intf_conf[index].lock);
  4985. }
  4986. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  4987. {
  4988. int ret = 0;
  4989. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4990. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4991. int port_id = cpu_dai->id;
  4992. struct afe_clk_set clk_cfg;
  4993. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  4994. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  4995. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  4996. clk_cfg.enable = enable;
  4997. /* Set core clock (based on sample rate for RX, fixed for TX) */
  4998. switch (port_id) {
  4999. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5000. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  5001. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  5002. clk_cfg.clk_freq_in_hz =
  5003. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5004. break;
  5005. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5006. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  5007. clk_cfg.clk_freq_in_hz =
  5008. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5009. break;
  5010. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  5011. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  5012. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5013. break;
  5014. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  5015. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  5016. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5017. break;
  5018. }
  5019. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5020. if (ret < 0) {
  5021. dev_err(rtd->card->dev,
  5022. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5023. __func__, port_id, ret);
  5024. goto err;
  5025. }
  5026. /* Set NPL clock for RX in addition */
  5027. switch (port_id) {
  5028. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5029. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  5030. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5031. if (ret < 0) {
  5032. dev_err(rtd->card->dev,
  5033. "%s: afe NPL failed port 0x%x, err:%d\n",
  5034. __func__, port_id, ret);
  5035. goto err;
  5036. }
  5037. break;
  5038. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5039. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  5040. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5041. if (ret < 0) {
  5042. dev_err(rtd->card->dev,
  5043. "%s: afe NPL failed for port 0x%x, err:%d\n",
  5044. __func__, port_id, ret);
  5045. goto err;
  5046. }
  5047. break;
  5048. }
  5049. if (enable) {
  5050. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5051. clk_cfg.clk_freq_in_hz);
  5052. }
  5053. err:
  5054. return ret;
  5055. }
  5056. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  5057. {
  5058. int ret = 0;
  5059. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5060. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5061. int port_id = cpu_dai->id;
  5062. dev_dbg(rtd->card->dev,
  5063. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5064. __func__, substream->name, substream->stream,
  5065. cpu_dai->name, cpu_dai->id);
  5066. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5067. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5068. ret = -EINVAL;
  5069. dev_err(rtd->card->dev,
  5070. "%s: CPU DAI id (%d) out of range\n",
  5071. __func__, cpu_dai->id);
  5072. goto err;
  5073. }
  5074. ret = msm_spdif_set_clk(substream, true);
  5075. if (ret < 0) {
  5076. dev_err(rtd->card->dev,
  5077. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  5078. __func__, port_id, ret);
  5079. }
  5080. err:
  5081. return ret;
  5082. }
  5083. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  5084. {
  5085. int ret;
  5086. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5087. int port_id = rtd->cpu_dai->id;
  5088. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5089. substream->name, substream->stream);
  5090. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5091. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5092. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  5093. return;
  5094. }
  5095. ret = msm_spdif_set_clk(substream, false);
  5096. if (ret < 0)
  5097. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  5098. __func__, port_id, ret);
  5099. }
  5100. static struct snd_soc_ops msm_mi2s_be_ops = {
  5101. .startup = msm_mi2s_snd_startup,
  5102. .shutdown = msm_mi2s_snd_shutdown,
  5103. };
  5104. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5105. .hw_params = msm_snd_cdc_dma_hw_params,
  5106. };
  5107. static struct snd_soc_ops msm_be_ops = {
  5108. .hw_params = msm_snd_hw_params,
  5109. };
  5110. static struct snd_soc_ops msm_wcn_ops = {
  5111. .hw_params = msm_wcn_hw_params,
  5112. };
  5113. static struct snd_soc_ops msm_spdif_be_ops = {
  5114. .startup = msm_spdif_snd_startup,
  5115. .shutdown = msm_spdif_snd_shutdown,
  5116. };
  5117. /* Digital audio interface glue - connects codec <---> CPU */
  5118. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5119. /* FrontEnd DAI Links */
  5120. {
  5121. .name = MSM_DAILINK_NAME(Media1),
  5122. .stream_name = "MultiMedia1",
  5123. .cpu_dai_name = "MultiMedia1",
  5124. .platform_name = "msm-pcm-dsp.0",
  5125. .dynamic = 1,
  5126. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5127. .dpcm_playback = 1,
  5128. .dpcm_capture = 1,
  5129. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5130. SND_SOC_DPCM_TRIGGER_POST},
  5131. .codec_dai_name = "snd-soc-dummy-dai",
  5132. .codec_name = "snd-soc-dummy",
  5133. .ignore_suspend = 1,
  5134. /* this dainlink has playback support */
  5135. .ignore_pmdown_time = 1,
  5136. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5137. },
  5138. {
  5139. .name = MSM_DAILINK_NAME(Media2),
  5140. .stream_name = "MultiMedia2",
  5141. .cpu_dai_name = "MultiMedia2",
  5142. .platform_name = "msm-pcm-dsp.0",
  5143. .dynamic = 1,
  5144. .dpcm_playback = 1,
  5145. .dpcm_capture = 1,
  5146. .codec_dai_name = "snd-soc-dummy-dai",
  5147. .codec_name = "snd-soc-dummy",
  5148. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5149. SND_SOC_DPCM_TRIGGER_POST},
  5150. .ignore_suspend = 1,
  5151. /* this dainlink has playback support */
  5152. .ignore_pmdown_time = 1,
  5153. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5154. },
  5155. {
  5156. .name = "VoiceMMode1",
  5157. .stream_name = "VoiceMMode1",
  5158. .cpu_dai_name = "VoiceMMode1",
  5159. .platform_name = "msm-pcm-voice",
  5160. .dynamic = 1,
  5161. .dpcm_playback = 1,
  5162. .dpcm_capture = 1,
  5163. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5164. SND_SOC_DPCM_TRIGGER_POST},
  5165. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5166. .ignore_suspend = 1,
  5167. .ignore_pmdown_time = 1,
  5168. .codec_dai_name = "snd-soc-dummy-dai",
  5169. .codec_name = "snd-soc-dummy",
  5170. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5171. },
  5172. {
  5173. .name = "MSM VoIP",
  5174. .stream_name = "VoIP",
  5175. .cpu_dai_name = "VoIP",
  5176. .platform_name = "msm-voip-dsp",
  5177. .dynamic = 1,
  5178. .dpcm_playback = 1,
  5179. .dpcm_capture = 1,
  5180. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5181. SND_SOC_DPCM_TRIGGER_POST},
  5182. .codec_dai_name = "snd-soc-dummy-dai",
  5183. .codec_name = "snd-soc-dummy",
  5184. .ignore_suspend = 1,
  5185. /* this dainlink has playback support */
  5186. .ignore_pmdown_time = 1,
  5187. .id = MSM_FRONTEND_DAI_VOIP,
  5188. },
  5189. {
  5190. .name = MSM_DAILINK_NAME(ULL),
  5191. .stream_name = "MultiMedia3",
  5192. .cpu_dai_name = "MultiMedia3",
  5193. .platform_name = "msm-pcm-dsp.2",
  5194. .dynamic = 1,
  5195. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5196. .dpcm_playback = 1,
  5197. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5198. SND_SOC_DPCM_TRIGGER_POST},
  5199. .codec_dai_name = "snd-soc-dummy-dai",
  5200. .codec_name = "snd-soc-dummy",
  5201. .ignore_suspend = 1,
  5202. /* this dainlink has playback support */
  5203. .ignore_pmdown_time = 1,
  5204. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5205. },
  5206. /* Hostless PCM purpose */
  5207. {
  5208. .name = "SLIMBUS_0 Hostless",
  5209. .stream_name = "SLIMBUS_0 Hostless",
  5210. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5211. .platform_name = "msm-pcm-hostless",
  5212. .dynamic = 1,
  5213. .dpcm_playback = 1,
  5214. .dpcm_capture = 1,
  5215. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5216. SND_SOC_DPCM_TRIGGER_POST},
  5217. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5218. .ignore_suspend = 1,
  5219. /* this dailink has playback support */
  5220. .ignore_pmdown_time = 1,
  5221. .codec_dai_name = "snd-soc-dummy-dai",
  5222. .codec_name = "snd-soc-dummy",
  5223. },
  5224. {
  5225. .name = "MSM AFE-PCM RX",
  5226. .stream_name = "AFE-PROXY RX",
  5227. .cpu_dai_name = "msm-dai-q6-dev.241",
  5228. .codec_name = "msm-stub-codec.1",
  5229. .codec_dai_name = "msm-stub-rx",
  5230. .platform_name = "msm-pcm-afe",
  5231. .dpcm_playback = 1,
  5232. .ignore_suspend = 1,
  5233. /* this dainlink has playback support */
  5234. .ignore_pmdown_time = 1,
  5235. },
  5236. {
  5237. .name = "MSM AFE-PCM TX",
  5238. .stream_name = "AFE-PROXY TX",
  5239. .cpu_dai_name = "msm-dai-q6-dev.240",
  5240. .codec_name = "msm-stub-codec.1",
  5241. .codec_dai_name = "msm-stub-tx",
  5242. .platform_name = "msm-pcm-afe",
  5243. .dpcm_capture = 1,
  5244. .ignore_suspend = 1,
  5245. },
  5246. {
  5247. .name = MSM_DAILINK_NAME(Compress1),
  5248. .stream_name = "Compress1",
  5249. .cpu_dai_name = "MultiMedia4",
  5250. .platform_name = "msm-compress-dsp",
  5251. .dynamic = 1,
  5252. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5253. .dpcm_playback = 1,
  5254. .dpcm_capture = 1,
  5255. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5256. SND_SOC_DPCM_TRIGGER_POST},
  5257. .codec_dai_name = "snd-soc-dummy-dai",
  5258. .codec_name = "snd-soc-dummy",
  5259. .ignore_suspend = 1,
  5260. .ignore_pmdown_time = 1,
  5261. /* this dainlink has playback support */
  5262. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5263. },
  5264. {
  5265. .name = "AUXPCM Hostless",
  5266. .stream_name = "AUXPCM Hostless",
  5267. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5268. .platform_name = "msm-pcm-hostless",
  5269. .dynamic = 1,
  5270. .dpcm_playback = 1,
  5271. .dpcm_capture = 1,
  5272. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5273. SND_SOC_DPCM_TRIGGER_POST},
  5274. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5275. .ignore_suspend = 1,
  5276. /* this dainlink has playback support */
  5277. .ignore_pmdown_time = 1,
  5278. .codec_dai_name = "snd-soc-dummy-dai",
  5279. .codec_name = "snd-soc-dummy",
  5280. },
  5281. {
  5282. .name = "SLIMBUS_1 Hostless",
  5283. .stream_name = "SLIMBUS_1 Hostless",
  5284. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5285. .platform_name = "msm-pcm-hostless",
  5286. .dynamic = 1,
  5287. .dpcm_playback = 1,
  5288. .dpcm_capture = 1,
  5289. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5290. SND_SOC_DPCM_TRIGGER_POST},
  5291. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5292. .ignore_suspend = 1,
  5293. /* this dailink has playback support */
  5294. .ignore_pmdown_time = 1,
  5295. .codec_dai_name = "snd-soc-dummy-dai",
  5296. .codec_name = "snd-soc-dummy",
  5297. },
  5298. {
  5299. .name = "SLIMBUS_3 Hostless",
  5300. .stream_name = "SLIMBUS_3 Hostless",
  5301. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5302. .platform_name = "msm-pcm-hostless",
  5303. .dynamic = 1,
  5304. .dpcm_playback = 1,
  5305. .dpcm_capture = 1,
  5306. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5307. SND_SOC_DPCM_TRIGGER_POST},
  5308. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5309. .ignore_suspend = 1,
  5310. /* this dailink has playback support */
  5311. .ignore_pmdown_time = 1,
  5312. .codec_dai_name = "snd-soc-dummy-dai",
  5313. .codec_name = "snd-soc-dummy",
  5314. },
  5315. {
  5316. .name = "SLIMBUS_4 Hostless",
  5317. .stream_name = "SLIMBUS_4 Hostless",
  5318. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5319. .platform_name = "msm-pcm-hostless",
  5320. .dynamic = 1,
  5321. .dpcm_playback = 1,
  5322. .dpcm_capture = 1,
  5323. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5324. SND_SOC_DPCM_TRIGGER_POST},
  5325. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5326. .ignore_suspend = 1,
  5327. /* this dailink has playback support */
  5328. .ignore_pmdown_time = 1,
  5329. .codec_dai_name = "snd-soc-dummy-dai",
  5330. .codec_name = "snd-soc-dummy",
  5331. },
  5332. {
  5333. .name = MSM_DAILINK_NAME(LowLatency),
  5334. .stream_name = "MultiMedia5",
  5335. .cpu_dai_name = "MultiMedia5",
  5336. .platform_name = "msm-pcm-dsp.1",
  5337. .dynamic = 1,
  5338. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5339. .dpcm_playback = 1,
  5340. .dpcm_capture = 1,
  5341. .codec_dai_name = "snd-soc-dummy-dai",
  5342. .codec_name = "snd-soc-dummy",
  5343. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5344. SND_SOC_DPCM_TRIGGER_POST},
  5345. .ignore_suspend = 1,
  5346. /* this dainlink has playback support */
  5347. .ignore_pmdown_time = 1,
  5348. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5349. .ops = &msm_fe_qos_ops,
  5350. },
  5351. {
  5352. .name = "Listen 1 Audio Service",
  5353. .stream_name = "Listen 1 Audio Service",
  5354. .cpu_dai_name = "LSM1",
  5355. .platform_name = "msm-lsm-client",
  5356. .dynamic = 1,
  5357. .dpcm_capture = 1,
  5358. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5359. SND_SOC_DPCM_TRIGGER_POST },
  5360. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5361. .ignore_suspend = 1,
  5362. .codec_dai_name = "snd-soc-dummy-dai",
  5363. .codec_name = "snd-soc-dummy",
  5364. .id = MSM_FRONTEND_DAI_LSM1,
  5365. },
  5366. /* Multiple Tunnel instances */
  5367. {
  5368. .name = MSM_DAILINK_NAME(Compress2),
  5369. .stream_name = "Compress2",
  5370. .cpu_dai_name = "MultiMedia7",
  5371. .platform_name = "msm-compress-dsp",
  5372. .dynamic = 1,
  5373. .dpcm_playback = 1,
  5374. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5375. SND_SOC_DPCM_TRIGGER_POST},
  5376. .codec_dai_name = "snd-soc-dummy-dai",
  5377. .codec_name = "snd-soc-dummy",
  5378. .ignore_suspend = 1,
  5379. .ignore_pmdown_time = 1,
  5380. /* this dainlink has playback support */
  5381. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5382. },
  5383. {
  5384. .name = MSM_DAILINK_NAME(MultiMedia10),
  5385. .stream_name = "MultiMedia10",
  5386. .cpu_dai_name = "MultiMedia10",
  5387. .platform_name = "msm-pcm-dsp.1",
  5388. .dynamic = 1,
  5389. .dpcm_playback = 1,
  5390. .dpcm_capture = 1,
  5391. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5392. SND_SOC_DPCM_TRIGGER_POST},
  5393. .codec_dai_name = "snd-soc-dummy-dai",
  5394. .codec_name = "snd-soc-dummy",
  5395. .ignore_suspend = 1,
  5396. .ignore_pmdown_time = 1,
  5397. /* this dainlink has playback support */
  5398. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5399. },
  5400. {
  5401. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5402. .stream_name = "MM_NOIRQ",
  5403. .cpu_dai_name = "MultiMedia8",
  5404. .platform_name = "msm-pcm-dsp-noirq",
  5405. .dynamic = 1,
  5406. .dpcm_playback = 1,
  5407. .dpcm_capture = 1,
  5408. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5409. SND_SOC_DPCM_TRIGGER_POST},
  5410. .codec_dai_name = "snd-soc-dummy-dai",
  5411. .codec_name = "snd-soc-dummy",
  5412. .ignore_suspend = 1,
  5413. .ignore_pmdown_time = 1,
  5414. /* this dainlink has playback support */
  5415. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5416. .ops = &msm_fe_qos_ops,
  5417. },
  5418. /* HDMI Hostless */
  5419. {
  5420. .name = "HDMI_RX_HOSTLESS",
  5421. .stream_name = "HDMI_RX_HOSTLESS",
  5422. .cpu_dai_name = "HDMI_HOSTLESS",
  5423. .platform_name = "msm-pcm-hostless",
  5424. .dynamic = 1,
  5425. .dpcm_playback = 1,
  5426. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5427. SND_SOC_DPCM_TRIGGER_POST},
  5428. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5429. .ignore_suspend = 1,
  5430. .ignore_pmdown_time = 1,
  5431. .codec_dai_name = "snd-soc-dummy-dai",
  5432. .codec_name = "snd-soc-dummy",
  5433. },
  5434. {
  5435. .name = "VoiceMMode2",
  5436. .stream_name = "VoiceMMode2",
  5437. .cpu_dai_name = "VoiceMMode2",
  5438. .platform_name = "msm-pcm-voice",
  5439. .dynamic = 1,
  5440. .dpcm_playback = 1,
  5441. .dpcm_capture = 1,
  5442. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5443. SND_SOC_DPCM_TRIGGER_POST},
  5444. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5445. .ignore_suspend = 1,
  5446. .ignore_pmdown_time = 1,
  5447. .codec_dai_name = "snd-soc-dummy-dai",
  5448. .codec_name = "snd-soc-dummy",
  5449. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5450. },
  5451. /* LSM FE */
  5452. {
  5453. .name = "Listen 2 Audio Service",
  5454. .stream_name = "Listen 2 Audio Service",
  5455. .cpu_dai_name = "LSM2",
  5456. .platform_name = "msm-lsm-client",
  5457. .dynamic = 1,
  5458. .dpcm_capture = 1,
  5459. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5460. SND_SOC_DPCM_TRIGGER_POST },
  5461. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5462. .ignore_suspend = 1,
  5463. .codec_dai_name = "snd-soc-dummy-dai",
  5464. .codec_name = "snd-soc-dummy",
  5465. .id = MSM_FRONTEND_DAI_LSM2,
  5466. },
  5467. {
  5468. .name = "Listen 3 Audio Service",
  5469. .stream_name = "Listen 3 Audio Service",
  5470. .cpu_dai_name = "LSM3",
  5471. .platform_name = "msm-lsm-client",
  5472. .dynamic = 1,
  5473. .dpcm_capture = 1,
  5474. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5475. SND_SOC_DPCM_TRIGGER_POST },
  5476. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5477. .ignore_suspend = 1,
  5478. .codec_dai_name = "snd-soc-dummy-dai",
  5479. .codec_name = "snd-soc-dummy",
  5480. .id = MSM_FRONTEND_DAI_LSM3,
  5481. },
  5482. {
  5483. .name = "Listen 4 Audio Service",
  5484. .stream_name = "Listen 4 Audio Service",
  5485. .cpu_dai_name = "LSM4",
  5486. .platform_name = "msm-lsm-client",
  5487. .dynamic = 1,
  5488. .dpcm_capture = 1,
  5489. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5490. SND_SOC_DPCM_TRIGGER_POST },
  5491. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5492. .ignore_suspend = 1,
  5493. .codec_dai_name = "snd-soc-dummy-dai",
  5494. .codec_name = "snd-soc-dummy",
  5495. .id = MSM_FRONTEND_DAI_LSM4,
  5496. },
  5497. {
  5498. .name = "Listen 5 Audio Service",
  5499. .stream_name = "Listen 5 Audio Service",
  5500. .cpu_dai_name = "LSM5",
  5501. .platform_name = "msm-lsm-client",
  5502. .dynamic = 1,
  5503. .dpcm_capture = 1,
  5504. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5505. SND_SOC_DPCM_TRIGGER_POST },
  5506. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5507. .ignore_suspend = 1,
  5508. .codec_dai_name = "snd-soc-dummy-dai",
  5509. .codec_name = "snd-soc-dummy",
  5510. .id = MSM_FRONTEND_DAI_LSM5,
  5511. },
  5512. {
  5513. .name = "Listen 6 Audio Service",
  5514. .stream_name = "Listen 6 Audio Service",
  5515. .cpu_dai_name = "LSM6",
  5516. .platform_name = "msm-lsm-client",
  5517. .dynamic = 1,
  5518. .dpcm_capture = 1,
  5519. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5520. SND_SOC_DPCM_TRIGGER_POST },
  5521. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5522. .ignore_suspend = 1,
  5523. .codec_dai_name = "snd-soc-dummy-dai",
  5524. .codec_name = "snd-soc-dummy",
  5525. .id = MSM_FRONTEND_DAI_LSM6,
  5526. },
  5527. {
  5528. .name = "Listen 7 Audio Service",
  5529. .stream_name = "Listen 7 Audio Service",
  5530. .cpu_dai_name = "LSM7",
  5531. .platform_name = "msm-lsm-client",
  5532. .dynamic = 1,
  5533. .dpcm_capture = 1,
  5534. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5535. SND_SOC_DPCM_TRIGGER_POST },
  5536. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5537. .ignore_suspend = 1,
  5538. .codec_dai_name = "snd-soc-dummy-dai",
  5539. .codec_name = "snd-soc-dummy",
  5540. .id = MSM_FRONTEND_DAI_LSM7,
  5541. },
  5542. {
  5543. .name = "Listen 8 Audio Service",
  5544. .stream_name = "Listen 8 Audio Service",
  5545. .cpu_dai_name = "LSM8",
  5546. .platform_name = "msm-lsm-client",
  5547. .dynamic = 1,
  5548. .dpcm_capture = 1,
  5549. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5550. SND_SOC_DPCM_TRIGGER_POST },
  5551. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5552. .ignore_suspend = 1,
  5553. .codec_dai_name = "snd-soc-dummy-dai",
  5554. .codec_name = "snd-soc-dummy",
  5555. .id = MSM_FRONTEND_DAI_LSM8,
  5556. },
  5557. {
  5558. .name = MSM_DAILINK_NAME(Media9),
  5559. .stream_name = "MultiMedia9",
  5560. .cpu_dai_name = "MultiMedia9",
  5561. .platform_name = "msm-pcm-dsp.0",
  5562. .dynamic = 1,
  5563. .dpcm_playback = 1,
  5564. .dpcm_capture = 1,
  5565. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5566. SND_SOC_DPCM_TRIGGER_POST},
  5567. .codec_dai_name = "snd-soc-dummy-dai",
  5568. .codec_name = "snd-soc-dummy",
  5569. .ignore_suspend = 1,
  5570. /* this dainlink has playback support */
  5571. .ignore_pmdown_time = 1,
  5572. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5573. },
  5574. {
  5575. .name = MSM_DAILINK_NAME(Compress4),
  5576. .stream_name = "Compress4",
  5577. .cpu_dai_name = "MultiMedia11",
  5578. .platform_name = "msm-compress-dsp",
  5579. .dynamic = 1,
  5580. .dpcm_playback = 1,
  5581. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5582. SND_SOC_DPCM_TRIGGER_POST},
  5583. .codec_dai_name = "snd-soc-dummy-dai",
  5584. .codec_name = "snd-soc-dummy",
  5585. .ignore_suspend = 1,
  5586. .ignore_pmdown_time = 1,
  5587. /* this dainlink has playback support */
  5588. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5589. },
  5590. {
  5591. .name = MSM_DAILINK_NAME(Compress5),
  5592. .stream_name = "Compress5",
  5593. .cpu_dai_name = "MultiMedia12",
  5594. .platform_name = "msm-compress-dsp",
  5595. .dynamic = 1,
  5596. .dpcm_playback = 1,
  5597. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5598. SND_SOC_DPCM_TRIGGER_POST},
  5599. .codec_dai_name = "snd-soc-dummy-dai",
  5600. .codec_name = "snd-soc-dummy",
  5601. .ignore_suspend = 1,
  5602. .ignore_pmdown_time = 1,
  5603. /* this dainlink has playback support */
  5604. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5605. },
  5606. {
  5607. .name = MSM_DAILINK_NAME(Compress6),
  5608. .stream_name = "Compress6",
  5609. .cpu_dai_name = "MultiMedia13",
  5610. .platform_name = "msm-compress-dsp",
  5611. .dynamic = 1,
  5612. .dpcm_playback = 1,
  5613. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5614. SND_SOC_DPCM_TRIGGER_POST},
  5615. .codec_dai_name = "snd-soc-dummy-dai",
  5616. .codec_name = "snd-soc-dummy",
  5617. .ignore_suspend = 1,
  5618. .ignore_pmdown_time = 1,
  5619. /* this dainlink has playback support */
  5620. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5621. },
  5622. {
  5623. .name = MSM_DAILINK_NAME(Compress7),
  5624. .stream_name = "Compress7",
  5625. .cpu_dai_name = "MultiMedia14",
  5626. .platform_name = "msm-compress-dsp",
  5627. .dynamic = 1,
  5628. .dpcm_playback = 1,
  5629. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5630. SND_SOC_DPCM_TRIGGER_POST},
  5631. .codec_dai_name = "snd-soc-dummy-dai",
  5632. .codec_name = "snd-soc-dummy",
  5633. .ignore_suspend = 1,
  5634. .ignore_pmdown_time = 1,
  5635. /* this dainlink has playback support */
  5636. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5637. },
  5638. {
  5639. .name = MSM_DAILINK_NAME(Compress8),
  5640. .stream_name = "Compress8",
  5641. .cpu_dai_name = "MultiMedia15",
  5642. .platform_name = "msm-compress-dsp",
  5643. .dynamic = 1,
  5644. .dpcm_playback = 1,
  5645. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5646. SND_SOC_DPCM_TRIGGER_POST},
  5647. .codec_dai_name = "snd-soc-dummy-dai",
  5648. .codec_name = "snd-soc-dummy",
  5649. .ignore_suspend = 1,
  5650. .ignore_pmdown_time = 1,
  5651. /* this dainlink has playback support */
  5652. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5653. },
  5654. {
  5655. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5656. .stream_name = "MM_NOIRQ_2",
  5657. .cpu_dai_name = "MultiMedia16",
  5658. .platform_name = "msm-pcm-dsp-noirq",
  5659. .dynamic = 1,
  5660. .dpcm_playback = 1,
  5661. .dpcm_capture = 1,
  5662. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5663. SND_SOC_DPCM_TRIGGER_POST},
  5664. .codec_dai_name = "snd-soc-dummy-dai",
  5665. .codec_name = "snd-soc-dummy",
  5666. .ignore_suspend = 1,
  5667. .ignore_pmdown_time = 1,
  5668. /* this dainlink has playback support */
  5669. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5670. },
  5671. {
  5672. .name = "SLIMBUS_8 Hostless",
  5673. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5674. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5675. .platform_name = "msm-pcm-hostless",
  5676. .dynamic = 1,
  5677. .dpcm_capture = 1,
  5678. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5679. SND_SOC_DPCM_TRIGGER_POST},
  5680. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5681. .ignore_suspend = 1,
  5682. .codec_dai_name = "snd-soc-dummy-dai",
  5683. .codec_name = "snd-soc-dummy",
  5684. },
  5685. /* Hostless PCM purpose */
  5686. {
  5687. .name = "CDC_DMA Hostless",
  5688. .stream_name = "CDC_DMA Hostless",
  5689. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5690. .platform_name = "msm-pcm-hostless",
  5691. .dynamic = 1,
  5692. .dpcm_playback = 1,
  5693. .dpcm_capture = 1,
  5694. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5695. SND_SOC_DPCM_TRIGGER_POST},
  5696. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5697. .ignore_suspend = 1,
  5698. /* this dailink has playback support */
  5699. .ignore_pmdown_time = 1,
  5700. .codec_dai_name = "snd-soc-dummy-dai",
  5701. .codec_name = "snd-soc-dummy",
  5702. },
  5703. };
  5704. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5705. {
  5706. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5707. .stream_name = "WSA CDC DMA0 Capture",
  5708. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5709. .platform_name = "msm-pcm-hostless",
  5710. .codec_name = "bolero_codec",
  5711. .codec_dai_name = "wsa_macro_vifeedback",
  5712. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5713. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5714. .ignore_suspend = 1,
  5715. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5716. .ops = &msm_cdc_dma_be_ops,
  5717. },
  5718. };
  5719. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5720. {
  5721. .name = MSM_DAILINK_NAME(ASM Loopback),
  5722. .stream_name = "MultiMedia6",
  5723. .cpu_dai_name = "MultiMedia6",
  5724. .platform_name = "msm-pcm-loopback",
  5725. .dynamic = 1,
  5726. .dpcm_playback = 1,
  5727. .dpcm_capture = 1,
  5728. .codec_dai_name = "snd-soc-dummy-dai",
  5729. .codec_name = "snd-soc-dummy",
  5730. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5731. SND_SOC_DPCM_TRIGGER_POST},
  5732. .ignore_suspend = 1,
  5733. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5734. .ignore_pmdown_time = 1,
  5735. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5736. },
  5737. {
  5738. .name = "USB Audio Hostless",
  5739. .stream_name = "USB Audio Hostless",
  5740. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5741. .platform_name = "msm-pcm-hostless",
  5742. .dynamic = 1,
  5743. .dpcm_playback = 1,
  5744. .dpcm_capture = 1,
  5745. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5746. SND_SOC_DPCM_TRIGGER_POST},
  5747. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5748. .ignore_suspend = 1,
  5749. .ignore_pmdown_time = 1,
  5750. .codec_dai_name = "snd-soc-dummy-dai",
  5751. .codec_name = "snd-soc-dummy",
  5752. },
  5753. {
  5754. .name = "SLIMBUS_7 Hostless",
  5755. .stream_name = "SLIMBUS_7 Hostless",
  5756. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5757. .platform_name = "msm-pcm-hostless",
  5758. .dynamic = 1,
  5759. .dpcm_capture = 1,
  5760. .dpcm_playback = 1,
  5761. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5762. SND_SOC_DPCM_TRIGGER_POST},
  5763. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5764. .ignore_suspend = 1,
  5765. .ignore_pmdown_time = 1,
  5766. .codec_dai_name = "snd-soc-dummy-dai",
  5767. .codec_name = "snd-soc-dummy",
  5768. },
  5769. {
  5770. .name = MSM_DAILINK_NAME(Compr Capture),
  5771. .stream_name = "Compr Capture",
  5772. .cpu_dai_name = "MultiMedia18",
  5773. .platform_name = "msm-compress-dsp",
  5774. .dynamic = 1,
  5775. .dpcm_capture = 1,
  5776. .codec_dai_name = "snd-soc-dummy-dai",
  5777. .codec_name = "snd-soc-dummy",
  5778. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5779. SND_SOC_DPCM_TRIGGER_POST},
  5780. .ignore_pmdown_time = 1,
  5781. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  5782. },
  5783. {
  5784. .name = MSM_DAILINK_NAME(Transcode Loopback Playback),
  5785. .stream_name = "Transcode Loopback Playback",
  5786. .cpu_dai_name = "MultiMedia26",
  5787. .platform_name = "msm-transcode-loopback",
  5788. .dynamic = 1,
  5789. .dpcm_playback = 1,
  5790. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5791. SND_SOC_DPCM_TRIGGER_POST},
  5792. .codec_dai_name = "snd-soc-dummy-dai",
  5793. .codec_name = "snd-soc-dummy",
  5794. .ignore_suspend = 1,
  5795. .ignore_pmdown_time = 1,
  5796. /* this dailink has playback support */
  5797. .id = MSM_FRONTEND_DAI_MULTIMEDIA26,
  5798. },
  5799. {
  5800. .name = MSM_DAILINK_NAME(Transcode Loopback Capture),
  5801. .stream_name = "Transcode Loopback Capture",
  5802. .cpu_dai_name = "MultiMedia27",
  5803. .platform_name = "msm-transcode-loopback",
  5804. .dynamic = 1,
  5805. .dpcm_capture = 1,
  5806. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5807. SND_SOC_DPCM_TRIGGER_POST},
  5808. .codec_dai_name = "snd-soc-dummy-dai",
  5809. .codec_name = "snd-soc-dummy",
  5810. .ignore_suspend = 1,
  5811. .ignore_pmdown_time = 1,
  5812. .id = MSM_FRONTEND_DAI_MULTIMEDIA27,
  5813. },
  5814. };
  5815. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5816. /* Backend AFE DAI Links */
  5817. {
  5818. .name = LPASS_BE_AFE_PCM_RX,
  5819. .stream_name = "AFE Playback",
  5820. .cpu_dai_name = "msm-dai-q6-dev.224",
  5821. .platform_name = "msm-pcm-routing",
  5822. .codec_name = "msm-stub-codec.1",
  5823. .codec_dai_name = "msm-stub-rx",
  5824. .no_pcm = 1,
  5825. .dpcm_playback = 1,
  5826. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5827. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5828. /* this dainlink has playback support */
  5829. .ignore_pmdown_time = 1,
  5830. .ignore_suspend = 1,
  5831. },
  5832. {
  5833. .name = LPASS_BE_AFE_PCM_TX,
  5834. .stream_name = "AFE Capture",
  5835. .cpu_dai_name = "msm-dai-q6-dev.225",
  5836. .platform_name = "msm-pcm-routing",
  5837. .codec_name = "msm-stub-codec.1",
  5838. .codec_dai_name = "msm-stub-tx",
  5839. .no_pcm = 1,
  5840. .dpcm_capture = 1,
  5841. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5842. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5843. .ignore_suspend = 1,
  5844. },
  5845. /* Incall Record Uplink BACK END DAI Link */
  5846. {
  5847. .name = LPASS_BE_INCALL_RECORD_TX,
  5848. .stream_name = "Voice Uplink Capture",
  5849. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5850. .platform_name = "msm-pcm-routing",
  5851. .codec_name = "msm-stub-codec.1",
  5852. .codec_dai_name = "msm-stub-tx",
  5853. .no_pcm = 1,
  5854. .dpcm_capture = 1,
  5855. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5856. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5857. .ignore_suspend = 1,
  5858. },
  5859. /* Incall Record Downlink BACK END DAI Link */
  5860. {
  5861. .name = LPASS_BE_INCALL_RECORD_RX,
  5862. .stream_name = "Voice Downlink Capture",
  5863. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5864. .platform_name = "msm-pcm-routing",
  5865. .codec_name = "msm-stub-codec.1",
  5866. .codec_dai_name = "msm-stub-tx",
  5867. .no_pcm = 1,
  5868. .dpcm_capture = 1,
  5869. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5870. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5871. .ignore_suspend = 1,
  5872. },
  5873. /* Incall Music BACK END DAI Link */
  5874. {
  5875. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5876. .stream_name = "Voice Farend Playback",
  5877. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5878. .platform_name = "msm-pcm-routing",
  5879. .codec_name = "msm-stub-codec.1",
  5880. .codec_dai_name = "msm-stub-rx",
  5881. .no_pcm = 1,
  5882. .dpcm_playback = 1,
  5883. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5884. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5885. .ignore_suspend = 1,
  5886. .ignore_pmdown_time = 1,
  5887. },
  5888. /* Incall Music 2 BACK END DAI Link */
  5889. {
  5890. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5891. .stream_name = "Voice2 Farend Playback",
  5892. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5893. .platform_name = "msm-pcm-routing",
  5894. .codec_name = "msm-stub-codec.1",
  5895. .codec_dai_name = "msm-stub-rx",
  5896. .no_pcm = 1,
  5897. .dpcm_playback = 1,
  5898. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5899. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5900. .ignore_suspend = 1,
  5901. .ignore_pmdown_time = 1,
  5902. },
  5903. {
  5904. .name = LPASS_BE_USB_AUDIO_RX,
  5905. .stream_name = "USB Audio Playback",
  5906. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5907. .platform_name = "msm-pcm-routing",
  5908. .codec_name = "msm-stub-codec.1",
  5909. .codec_dai_name = "msm-stub-rx",
  5910. .no_pcm = 1,
  5911. .dpcm_playback = 1,
  5912. .id = MSM_BACKEND_DAI_USB_RX,
  5913. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5914. .ignore_pmdown_time = 1,
  5915. .ignore_suspend = 1,
  5916. },
  5917. {
  5918. .name = LPASS_BE_USB_AUDIO_TX,
  5919. .stream_name = "USB Audio Capture",
  5920. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5921. .platform_name = "msm-pcm-routing",
  5922. .codec_name = "msm-stub-codec.1",
  5923. .codec_dai_name = "msm-stub-tx",
  5924. .no_pcm = 1,
  5925. .dpcm_capture = 1,
  5926. .id = MSM_BACKEND_DAI_USB_TX,
  5927. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5928. .ignore_suspend = 1,
  5929. },
  5930. {
  5931. .name = LPASS_BE_PRI_TDM_RX_0,
  5932. .stream_name = "Primary TDM0 Playback",
  5933. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5934. .platform_name = "msm-pcm-routing",
  5935. .codec_name = "msm-stub-codec.1",
  5936. .codec_dai_name = "msm-stub-rx",
  5937. .no_pcm = 1,
  5938. .dpcm_playback = 1,
  5939. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5940. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5941. .ops = &qcs405_tdm_be_ops,
  5942. .ignore_suspend = 1,
  5943. .ignore_pmdown_time = 1,
  5944. },
  5945. {
  5946. .name = LPASS_BE_PRI_TDM_TX_0,
  5947. .stream_name = "Primary TDM0 Capture",
  5948. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5949. .platform_name = "msm-pcm-routing",
  5950. .codec_name = "msm-stub-codec.1",
  5951. .codec_dai_name = "msm-stub-tx",
  5952. .no_pcm = 1,
  5953. .dpcm_capture = 1,
  5954. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5955. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5956. .ops = &qcs405_tdm_be_ops,
  5957. .ignore_suspend = 1,
  5958. },
  5959. {
  5960. .name = LPASS_BE_SEC_TDM_RX_0,
  5961. .stream_name = "Secondary TDM0 Playback",
  5962. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5963. .platform_name = "msm-pcm-routing",
  5964. .codec_name = "msm-stub-codec.1",
  5965. .codec_dai_name = "msm-stub-rx",
  5966. .no_pcm = 1,
  5967. .dpcm_playback = 1,
  5968. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5969. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5970. .ops = &qcs405_tdm_be_ops,
  5971. .ignore_suspend = 1,
  5972. .ignore_pmdown_time = 1,
  5973. },
  5974. {
  5975. .name = LPASS_BE_SEC_TDM_TX_0,
  5976. .stream_name = "Secondary TDM0 Capture",
  5977. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5978. .platform_name = "msm-pcm-routing",
  5979. .codec_name = "msm-stub-codec.1",
  5980. .codec_dai_name = "msm-stub-tx",
  5981. .no_pcm = 1,
  5982. .dpcm_capture = 1,
  5983. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5984. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5985. .ops = &qcs405_tdm_be_ops,
  5986. .ignore_suspend = 1,
  5987. },
  5988. {
  5989. .name = LPASS_BE_TERT_TDM_RX_0,
  5990. .stream_name = "Tertiary TDM0 Playback",
  5991. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5992. .platform_name = "msm-pcm-routing",
  5993. .codec_name = "msm-stub-codec.1",
  5994. .codec_dai_name = "msm-stub-rx",
  5995. .no_pcm = 1,
  5996. .dpcm_playback = 1,
  5997. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5998. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5999. .ops = &qcs405_tdm_be_ops,
  6000. .ignore_suspend = 1,
  6001. .ignore_pmdown_time = 1,
  6002. },
  6003. {
  6004. .name = LPASS_BE_TERT_TDM_TX_0,
  6005. .stream_name = "Tertiary TDM0 Capture",
  6006. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  6007. .platform_name = "msm-pcm-routing",
  6008. .codec_name = "msm-stub-codec.1",
  6009. .codec_dai_name = "msm-stub-tx",
  6010. .no_pcm = 1,
  6011. .dpcm_capture = 1,
  6012. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  6013. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6014. .ops = &qcs405_tdm_be_ops,
  6015. .ignore_suspend = 1,
  6016. },
  6017. {
  6018. .name = LPASS_BE_QUAT_TDM_RX_0,
  6019. .stream_name = "Quaternary TDM0 Playback",
  6020. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  6021. .platform_name = "msm-pcm-routing",
  6022. .codec_name = "msm-stub-codec.1",
  6023. .codec_dai_name = "msm-stub-rx",
  6024. .no_pcm = 1,
  6025. .dpcm_playback = 1,
  6026. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  6027. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6028. .ops = &qcs405_tdm_be_ops,
  6029. .ignore_suspend = 1,
  6030. .ignore_pmdown_time = 1,
  6031. },
  6032. {
  6033. .name = LPASS_BE_QUAT_TDM_TX_0,
  6034. .stream_name = "Quaternary TDM0 Capture",
  6035. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  6036. .platform_name = "msm-pcm-routing",
  6037. .codec_name = "msm-stub-codec.1",
  6038. .codec_dai_name = "msm-stub-tx",
  6039. .no_pcm = 1,
  6040. .dpcm_capture = 1,
  6041. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  6042. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6043. .ops = &qcs405_tdm_be_ops,
  6044. .ignore_suspend = 1,
  6045. },
  6046. {
  6047. .name = LPASS_BE_QUIN_TDM_RX_0,
  6048. .stream_name = "Quinary TDM0 Playback",
  6049. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  6050. .platform_name = "msm-pcm-routing",
  6051. .codec_name = "msm-stub-codec.1",
  6052. .codec_dai_name = "msm-stub-rx",
  6053. .no_pcm = 1,
  6054. .dpcm_playback = 1,
  6055. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  6056. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6057. .ops = &qcs405_tdm_be_ops,
  6058. .ignore_suspend = 1,
  6059. .ignore_pmdown_time = 1,
  6060. },
  6061. {
  6062. .name = LPASS_BE_QUIN_TDM_TX_0,
  6063. .stream_name = "Quinary TDM0 Capture",
  6064. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  6065. .platform_name = "msm-pcm-routing",
  6066. .codec_name = "msm-stub-codec.1",
  6067. .codec_dai_name = "msm-stub-tx",
  6068. .no_pcm = 1,
  6069. .dpcm_capture = 1,
  6070. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  6071. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6072. .ops = &qcs405_tdm_be_ops,
  6073. .ignore_suspend = 1,
  6074. },
  6075. };
  6076. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  6077. {
  6078. .name = LPASS_BE_SLIMBUS_0_RX,
  6079. .stream_name = "Slimbus Playback",
  6080. .cpu_dai_name = "msm-dai-q6-dev.16384",
  6081. .platform_name = "msm-pcm-routing",
  6082. .codec_name = "tasha_codec",
  6083. .codec_dai_name = "tasha_mix_rx1",
  6084. .no_pcm = 1,
  6085. .dpcm_playback = 1,
  6086. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  6087. .init = &msm_audrx_init,
  6088. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6089. /* this dainlink has playback support */
  6090. .ignore_pmdown_time = 1,
  6091. .ignore_suspend = 1,
  6092. .ops = &msm_be_ops,
  6093. },
  6094. {
  6095. .name = LPASS_BE_SLIMBUS_0_TX,
  6096. .stream_name = "Slimbus Capture",
  6097. .cpu_dai_name = "msm-dai-q6-dev.16385",
  6098. .platform_name = "msm-pcm-routing",
  6099. .codec_name = "tasha_codec",
  6100. .codec_dai_name = "tasha_tx1",
  6101. .no_pcm = 1,
  6102. .dpcm_capture = 1,
  6103. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  6104. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6105. .ignore_suspend = 1,
  6106. .ops = &msm_be_ops,
  6107. },
  6108. {
  6109. .name = LPASS_BE_SLIMBUS_1_RX,
  6110. .stream_name = "Slimbus1 Playback",
  6111. .cpu_dai_name = "msm-dai-q6-dev.16386",
  6112. .platform_name = "msm-pcm-routing",
  6113. .codec_name = "tasha_codec",
  6114. .codec_dai_name = "tasha_mix_rx1",
  6115. .no_pcm = 1,
  6116. .dpcm_playback = 1,
  6117. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  6118. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6119. .ops = &msm_be_ops,
  6120. /* dai link has playback support */
  6121. .ignore_pmdown_time = 1,
  6122. .ignore_suspend = 1,
  6123. },
  6124. {
  6125. .name = LPASS_BE_SLIMBUS_1_TX,
  6126. .stream_name = "Slimbus1 Capture",
  6127. .cpu_dai_name = "msm-dai-q6-dev.16387",
  6128. .platform_name = "msm-pcm-routing",
  6129. .codec_name = "tasha_codec",
  6130. .codec_dai_name = "tasha_tx3",
  6131. .no_pcm = 1,
  6132. .dpcm_capture = 1,
  6133. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  6134. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6135. .ops = &msm_be_ops,
  6136. .ignore_suspend = 1,
  6137. },
  6138. {
  6139. .name = LPASS_BE_SLIMBUS_2_RX,
  6140. .stream_name = "Slimbus2 Playback",
  6141. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6142. .platform_name = "msm-pcm-routing",
  6143. .codec_name = "tasha_codec",
  6144. .codec_dai_name = "tasha_rx2",
  6145. .no_pcm = 1,
  6146. .dpcm_playback = 1,
  6147. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6148. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6149. .ops = &msm_be_ops,
  6150. .ignore_pmdown_time = 1,
  6151. .ignore_suspend = 1,
  6152. },
  6153. {
  6154. .name = LPASS_BE_SLIMBUS_3_RX,
  6155. .stream_name = "Slimbus3 Playback",
  6156. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6157. .platform_name = "msm-pcm-routing",
  6158. .codec_name = "tasha_codec",
  6159. .codec_dai_name = "tasha_mix_rx1",
  6160. .no_pcm = 1,
  6161. .dpcm_playback = 1,
  6162. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6163. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6164. .ops = &msm_be_ops,
  6165. /* dai link has playback support */
  6166. .ignore_pmdown_time = 1,
  6167. .ignore_suspend = 1,
  6168. },
  6169. {
  6170. .name = LPASS_BE_SLIMBUS_3_TX,
  6171. .stream_name = "Slimbus3 Capture",
  6172. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6173. .platform_name = "msm-pcm-routing",
  6174. .codec_name = "tasha_codec",
  6175. .codec_dai_name = "tasha_tx1",
  6176. .no_pcm = 1,
  6177. .dpcm_capture = 1,
  6178. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6179. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6180. .ops = &msm_be_ops,
  6181. .ignore_suspend = 1,
  6182. },
  6183. {
  6184. .name = LPASS_BE_SLIMBUS_4_RX,
  6185. .stream_name = "Slimbus4 Playback",
  6186. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6187. .platform_name = "msm-pcm-routing",
  6188. .codec_name = "tasha_codec",
  6189. .codec_dai_name = "tasha_mix_rx1",
  6190. .no_pcm = 1,
  6191. .dpcm_playback = 1,
  6192. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6193. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6194. .ops = &msm_be_ops,
  6195. /* dai link has playback support */
  6196. .ignore_pmdown_time = 1,
  6197. .ignore_suspend = 1,
  6198. },
  6199. {
  6200. .name = LPASS_BE_SLIMBUS_5_RX,
  6201. .stream_name = "Slimbus5 Playback",
  6202. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6203. .platform_name = "msm-pcm-routing",
  6204. .codec_name = "tasha_codec",
  6205. .codec_dai_name = "tasha_rx3",
  6206. .no_pcm = 1,
  6207. .dpcm_playback = 1,
  6208. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6209. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6210. .ops = &msm_be_ops,
  6211. /* dai link has playback support */
  6212. .ignore_pmdown_time = 1,
  6213. .ignore_suspend = 1,
  6214. },
  6215. {
  6216. .name = LPASS_BE_SLIMBUS_6_RX,
  6217. .stream_name = "Slimbus6 Playback",
  6218. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6219. .platform_name = "msm-pcm-routing",
  6220. .codec_name = "tasha_codec",
  6221. .codec_dai_name = "tasha_rx4",
  6222. .no_pcm = 1,
  6223. .dpcm_playback = 1,
  6224. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6225. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6226. .ops = &msm_be_ops,
  6227. /* dai link has playback support */
  6228. .ignore_pmdown_time = 1,
  6229. .ignore_suspend = 1,
  6230. },
  6231. /* Slimbus VI Recording */
  6232. {
  6233. .name = LPASS_BE_SLIMBUS_TX_VI,
  6234. .stream_name = "Slimbus4 Capture",
  6235. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6236. .platform_name = "msm-pcm-routing",
  6237. .codec_name = "tasha_codec",
  6238. .codec_dai_name = "tasha_vifeedback",
  6239. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6240. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6241. .ops = &msm_be_ops,
  6242. .ignore_suspend = 1,
  6243. .no_pcm = 1,
  6244. .dpcm_capture = 1,
  6245. .ignore_pmdown_time = 1,
  6246. },
  6247. };
  6248. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6249. {
  6250. .name = LPASS_BE_SLIMBUS_7_RX,
  6251. .stream_name = "Slimbus7 Playback",
  6252. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6253. .platform_name = "msm-pcm-routing",
  6254. .codec_name = "btfmslim_slave",
  6255. /* BT codec driver determines capabilities based on
  6256. * dai name, bt codecdai name should always contains
  6257. * supported usecase information
  6258. */
  6259. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6260. .no_pcm = 1,
  6261. .dpcm_playback = 1,
  6262. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6263. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6264. .ops = &msm_wcn_ops,
  6265. /* dai link has playback support */
  6266. .ignore_pmdown_time = 1,
  6267. .ignore_suspend = 1,
  6268. },
  6269. {
  6270. .name = LPASS_BE_SLIMBUS_7_TX,
  6271. .stream_name = "Slimbus7 Capture",
  6272. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6273. .platform_name = "msm-pcm-routing",
  6274. .codec_name = "btfmslim_slave",
  6275. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6276. .no_pcm = 1,
  6277. .dpcm_capture = 1,
  6278. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6279. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6280. .ops = &msm_wcn_ops,
  6281. .ignore_suspend = 1,
  6282. },
  6283. {
  6284. .name = LPASS_BE_SLIMBUS_8_TX,
  6285. .stream_name = "Slimbus8 Capture",
  6286. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6287. .platform_name = "msm-pcm-routing",
  6288. .codec_name = "btfmslim_slave",
  6289. .codec_dai_name = "btfm_fm_slim_tx",
  6290. .no_pcm = 1,
  6291. .dpcm_capture = 1,
  6292. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6293. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6294. .init = &msm_wcn_init,
  6295. .ops = &msm_wcn_ops,
  6296. .ignore_suspend = 1,
  6297. },
  6298. {
  6299. .name = LPASS_BE_SLIMBUS_9_TX,
  6300. .stream_name = "Slimbus9 Capture",
  6301. .cpu_dai_name = "msm-dai-q6-dev.16403",
  6302. .platform_name = "msm-pcm-routing",
  6303. .codec_name = "btfmslim_slave",
  6304. .codec_dai_name = "btfm_bt_split_a2dp_slim_tx",
  6305. .no_pcm = 1,
  6306. .dpcm_capture = 1,
  6307. .id = MSM_BACKEND_DAI_SLIMBUS_9_TX,
  6308. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6309. .ops = &msm_wcn_ops,
  6310. .ignore_suspend = 1,
  6311. },
  6312. };
  6313. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6314. {
  6315. .name = LPASS_BE_PRI_MI2S_RX,
  6316. .stream_name = "Primary MI2S Playback",
  6317. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6318. .platform_name = "msm-pcm-routing",
  6319. .codec_name = "msm-stub-codec.1",
  6320. .codec_dai_name = "msm-stub-rx",
  6321. .no_pcm = 1,
  6322. .dpcm_playback = 1,
  6323. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6324. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6325. .ops = &msm_mi2s_be_ops,
  6326. .ignore_suspend = 1,
  6327. .ignore_pmdown_time = 1,
  6328. },
  6329. {
  6330. .name = LPASS_BE_PRI_MI2S_TX,
  6331. .stream_name = "Primary MI2S Capture",
  6332. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6333. .platform_name = "msm-pcm-routing",
  6334. .codec_name = "msm-stub-codec.1",
  6335. .codec_dai_name = "msm-stub-tx",
  6336. .no_pcm = 1,
  6337. .dpcm_capture = 1,
  6338. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6339. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6340. .ops = &msm_mi2s_be_ops,
  6341. .ignore_suspend = 1,
  6342. },
  6343. {
  6344. .name = LPASS_BE_SEC_MI2S_RX,
  6345. .stream_name = "Secondary MI2S Playback",
  6346. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6347. .platform_name = "msm-pcm-routing",
  6348. .codec_name = "msm-stub-codec.1",
  6349. .codec_dai_name = "msm-stub-rx",
  6350. .no_pcm = 1,
  6351. .dpcm_playback = 1,
  6352. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6353. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6354. .ops = &msm_mi2s_be_ops,
  6355. .ignore_suspend = 1,
  6356. .ignore_pmdown_time = 1,
  6357. },
  6358. {
  6359. .name = LPASS_BE_SEC_MI2S_TX,
  6360. .stream_name = "Secondary MI2S Capture",
  6361. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6362. .platform_name = "msm-pcm-routing",
  6363. .codec_name = "msm-stub-codec.1",
  6364. .codec_dai_name = "msm-stub-tx",
  6365. .no_pcm = 1,
  6366. .dpcm_capture = 1,
  6367. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6368. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6369. .ops = &msm_mi2s_be_ops,
  6370. .ignore_suspend = 1,
  6371. },
  6372. {
  6373. .name = LPASS_BE_TERT_MI2S_RX,
  6374. .stream_name = "Tertiary MI2S Playback",
  6375. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6376. .platform_name = "msm-pcm-routing",
  6377. .codec_name = "msm-stub-codec.1",
  6378. .codec_dai_name = "msm-stub-rx",
  6379. .no_pcm = 1,
  6380. .dpcm_playback = 1,
  6381. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6382. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6383. .ops = &msm_mi2s_be_ops,
  6384. .ignore_suspend = 1,
  6385. .ignore_pmdown_time = 1,
  6386. },
  6387. {
  6388. .name = LPASS_BE_TERT_MI2S_TX,
  6389. .stream_name = "Tertiary MI2S Capture",
  6390. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6391. .platform_name = "msm-pcm-routing",
  6392. .codec_name = "msm-stub-codec.1",
  6393. .codec_dai_name = "msm-stub-tx",
  6394. .no_pcm = 1,
  6395. .dpcm_capture = 1,
  6396. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6397. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6398. .ops = &msm_mi2s_be_ops,
  6399. .ignore_suspend = 1,
  6400. },
  6401. {
  6402. .name = LPASS_BE_QUAT_MI2S_RX,
  6403. .stream_name = "Quaternary MI2S Playback",
  6404. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6405. .platform_name = "msm-pcm-routing",
  6406. .codec_name = "msm-stub-codec.1",
  6407. .codec_dai_name = "msm-stub-rx",
  6408. .no_pcm = 1,
  6409. .dpcm_playback = 1,
  6410. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6411. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6412. .ops = &msm_mi2s_be_ops,
  6413. .ignore_suspend = 1,
  6414. .ignore_pmdown_time = 1,
  6415. },
  6416. {
  6417. .name = LPASS_BE_QUAT_MI2S_TX,
  6418. .stream_name = "Quaternary MI2S Capture",
  6419. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6420. .platform_name = "msm-pcm-routing",
  6421. .codec_name = "msm-stub-codec.1",
  6422. .codec_dai_name = "msm-stub-tx",
  6423. .no_pcm = 1,
  6424. .dpcm_capture = 1,
  6425. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6426. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6427. .ops = &msm_mi2s_be_ops,
  6428. .ignore_suspend = 1,
  6429. },
  6430. {
  6431. .name = LPASS_BE_QUIN_MI2S_RX,
  6432. .stream_name = "Quinary MI2S Playback",
  6433. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6434. .platform_name = "msm-pcm-routing",
  6435. .codec_name = "msm-stub-codec.1",
  6436. .codec_dai_name = "msm-stub-rx",
  6437. .no_pcm = 1,
  6438. .dpcm_playback = 1,
  6439. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6440. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6441. .ops = &msm_mi2s_be_ops,
  6442. .ignore_suspend = 1,
  6443. .ignore_pmdown_time = 1,
  6444. },
  6445. {
  6446. .name = LPASS_BE_QUIN_MI2S_TX,
  6447. .stream_name = "Quinary MI2S Capture",
  6448. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6449. .platform_name = "msm-pcm-routing",
  6450. .codec_name = "msm-stub-codec.1",
  6451. .codec_dai_name = "msm-stub-tx",
  6452. .no_pcm = 1,
  6453. .dpcm_capture = 1,
  6454. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6455. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6456. .ops = &msm_mi2s_be_ops,
  6457. .ignore_suspend = 1,
  6458. },
  6459. };
  6460. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6461. /* Primary AUX PCM Backend DAI Links */
  6462. {
  6463. .name = LPASS_BE_AUXPCM_RX,
  6464. .stream_name = "AUX PCM Playback",
  6465. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6466. .platform_name = "msm-pcm-routing",
  6467. .codec_name = "msm-stub-codec.1",
  6468. .codec_dai_name = "msm-stub-rx",
  6469. .no_pcm = 1,
  6470. .dpcm_playback = 1,
  6471. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6472. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6473. .ignore_pmdown_time = 1,
  6474. .ignore_suspend = 1,
  6475. },
  6476. {
  6477. .name = LPASS_BE_AUXPCM_TX,
  6478. .stream_name = "AUX PCM Capture",
  6479. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6480. .platform_name = "msm-pcm-routing",
  6481. .codec_name = "msm-stub-codec.1",
  6482. .codec_dai_name = "msm-stub-tx",
  6483. .no_pcm = 1,
  6484. .dpcm_capture = 1,
  6485. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6486. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6487. .ignore_suspend = 1,
  6488. },
  6489. /* Secondary AUX PCM Backend DAI Links */
  6490. {
  6491. .name = LPASS_BE_SEC_AUXPCM_RX,
  6492. .stream_name = "Sec AUX PCM Playback",
  6493. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6494. .platform_name = "msm-pcm-routing",
  6495. .codec_name = "msm-stub-codec.1",
  6496. .codec_dai_name = "msm-stub-rx",
  6497. .no_pcm = 1,
  6498. .dpcm_playback = 1,
  6499. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6500. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6501. .ignore_pmdown_time = 1,
  6502. .ignore_suspend = 1,
  6503. },
  6504. {
  6505. .name = LPASS_BE_SEC_AUXPCM_TX,
  6506. .stream_name = "Sec AUX PCM Capture",
  6507. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6508. .platform_name = "msm-pcm-routing",
  6509. .codec_name = "msm-stub-codec.1",
  6510. .codec_dai_name = "msm-stub-tx",
  6511. .no_pcm = 1,
  6512. .dpcm_capture = 1,
  6513. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6514. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6515. .ignore_suspend = 1,
  6516. },
  6517. /* Tertiary AUX PCM Backend DAI Links */
  6518. {
  6519. .name = LPASS_BE_TERT_AUXPCM_RX,
  6520. .stream_name = "Tert AUX PCM Playback",
  6521. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6522. .platform_name = "msm-pcm-routing",
  6523. .codec_name = "msm-stub-codec.1",
  6524. .codec_dai_name = "msm-stub-rx",
  6525. .no_pcm = 1,
  6526. .dpcm_playback = 1,
  6527. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6528. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6529. .ignore_suspend = 1,
  6530. },
  6531. {
  6532. .name = LPASS_BE_TERT_AUXPCM_TX,
  6533. .stream_name = "Tert AUX PCM Capture",
  6534. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6535. .platform_name = "msm-pcm-routing",
  6536. .codec_name = "msm-stub-codec.1",
  6537. .codec_dai_name = "msm-stub-tx",
  6538. .no_pcm = 1,
  6539. .dpcm_capture = 1,
  6540. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6541. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6542. .ignore_suspend = 1,
  6543. },
  6544. /* Quaternary AUX PCM Backend DAI Links */
  6545. {
  6546. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6547. .stream_name = "Quat AUX PCM Playback",
  6548. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6549. .platform_name = "msm-pcm-routing",
  6550. .codec_name = "msm-stub-codec.1",
  6551. .codec_dai_name = "msm-stub-rx",
  6552. .no_pcm = 1,
  6553. .dpcm_playback = 1,
  6554. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6555. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6556. .ignore_pmdown_time = 1,
  6557. .ignore_suspend = 1,
  6558. },
  6559. {
  6560. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6561. .stream_name = "Quat AUX PCM Capture",
  6562. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6563. .platform_name = "msm-pcm-routing",
  6564. .codec_name = "msm-stub-codec.1",
  6565. .codec_dai_name = "msm-stub-tx",
  6566. .no_pcm = 1,
  6567. .dpcm_capture = 1,
  6568. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6569. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6570. .ignore_suspend = 1,
  6571. },
  6572. /* Quinary AUX PCM Backend DAI Links */
  6573. {
  6574. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6575. .stream_name = "Quin AUX PCM Playback",
  6576. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6577. .platform_name = "msm-pcm-routing",
  6578. .codec_name = "msm-stub-codec.1",
  6579. .codec_dai_name = "msm-stub-rx",
  6580. .no_pcm = 1,
  6581. .dpcm_playback = 1,
  6582. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6583. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6584. .ignore_pmdown_time = 1,
  6585. .ignore_suspend = 1,
  6586. },
  6587. {
  6588. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6589. .stream_name = "Quin AUX PCM Capture",
  6590. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6591. .platform_name = "msm-pcm-routing",
  6592. .codec_name = "msm-stub-codec.1",
  6593. .codec_dai_name = "msm-stub-tx",
  6594. .no_pcm = 1,
  6595. .dpcm_capture = 1,
  6596. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6597. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6598. .ignore_suspend = 1,
  6599. },
  6600. };
  6601. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6602. /* WSA CDC DMA Backend DAI Links */
  6603. {
  6604. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6605. .stream_name = "WSA CDC DMA0 Playback",
  6606. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6607. .platform_name = "msm-pcm-routing",
  6608. .codec_name = "bolero_codec",
  6609. .codec_dai_name = "wsa_macro_rx1",
  6610. .no_pcm = 1,
  6611. .dpcm_playback = 1,
  6612. .init = &msm_wsa_cdc_dma_init,
  6613. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6614. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6615. .ignore_pmdown_time = 1,
  6616. .ignore_suspend = 1,
  6617. .ops = &msm_cdc_dma_be_ops,
  6618. },
  6619. {
  6620. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6621. .stream_name = "WSA CDC DMA1 Playback",
  6622. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6623. .platform_name = "msm-pcm-routing",
  6624. .codec_name = "bolero_codec",
  6625. .codec_dai_name = "wsa_macro_rx_mix",
  6626. .no_pcm = 1,
  6627. .dpcm_playback = 1,
  6628. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6629. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6630. .ignore_pmdown_time = 1,
  6631. .ignore_suspend = 1,
  6632. .ops = &msm_cdc_dma_be_ops,
  6633. },
  6634. {
  6635. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6636. .stream_name = "WSA CDC DMA1 Capture",
  6637. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6638. .platform_name = "msm-pcm-routing",
  6639. .codec_name = "bolero_codec",
  6640. .codec_dai_name = "wsa_macro_echo",
  6641. .no_pcm = 1,
  6642. .dpcm_capture = 1,
  6643. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6644. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6645. .ignore_suspend = 1,
  6646. .ops = &msm_cdc_dma_be_ops,
  6647. },
  6648. };
  6649. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6650. {
  6651. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6652. .stream_name = "VA CDC DMA0 Capture",
  6653. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6654. .platform_name = "msm-pcm-routing",
  6655. .codec_name = "bolero_codec",
  6656. .codec_dai_name = "va_macro_tx1",
  6657. .no_pcm = 1,
  6658. .dpcm_capture = 1,
  6659. .init = &msm_va_cdc_dma_init,
  6660. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6661. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6662. .ignore_suspend = 1,
  6663. .ops = &msm_cdc_dma_be_ops,
  6664. },
  6665. {
  6666. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6667. .stream_name = "VA CDC DMA1 Capture",
  6668. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6669. .platform_name = "msm-pcm-routing",
  6670. .codec_name = "bolero_codec",
  6671. .codec_dai_name = "va_macro_tx2",
  6672. .no_pcm = 1,
  6673. .dpcm_capture = 1,
  6674. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6675. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6676. .ignore_suspend = 1,
  6677. .ops = &msm_cdc_dma_be_ops,
  6678. },
  6679. };
  6680. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  6681. {
  6682. .name = LPASS_BE_PRI_SPDIF_RX,
  6683. .stream_name = "Primary SPDIF Playback",
  6684. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  6685. .platform_name = "msm-pcm-routing",
  6686. .codec_name = "msm-stub-codec.1",
  6687. .codec_dai_name = "msm-stub-rx",
  6688. .no_pcm = 1,
  6689. .dpcm_playback = 1,
  6690. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  6691. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6692. .ops = &msm_spdif_be_ops,
  6693. .ignore_suspend = 1,
  6694. .ignore_pmdown_time = 1,
  6695. },
  6696. {
  6697. .name = LPASS_BE_PRI_SPDIF_TX,
  6698. .stream_name = "Primary SPDIF Capture",
  6699. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  6700. .platform_name = "msm-pcm-routing",
  6701. .codec_name = "msm-stub-codec.1",
  6702. .codec_dai_name = "msm-stub-tx",
  6703. .no_pcm = 1,
  6704. .dpcm_capture = 1,
  6705. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  6706. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6707. .ops = &msm_spdif_be_ops,
  6708. .ignore_suspend = 1,
  6709. },
  6710. {
  6711. .name = LPASS_BE_SEC_SPDIF_RX,
  6712. .stream_name = "Secondary SPDIF Playback",
  6713. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  6714. .platform_name = "msm-pcm-routing",
  6715. .codec_name = "msm-stub-codec.1",
  6716. .codec_dai_name = "msm-stub-rx",
  6717. .no_pcm = 1,
  6718. .dpcm_playback = 1,
  6719. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  6720. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6721. .ops = &msm_spdif_be_ops,
  6722. .ignore_suspend = 1,
  6723. .ignore_pmdown_time = 1,
  6724. },
  6725. {
  6726. .name = LPASS_BE_SEC_SPDIF_TX,
  6727. .stream_name = "Secondary SPDIF Capture",
  6728. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  6729. .platform_name = "msm-pcm-routing",
  6730. .codec_name = "msm-stub-codec.1",
  6731. .codec_dai_name = "msm-stub-tx",
  6732. .no_pcm = 1,
  6733. .dpcm_capture = 1,
  6734. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  6735. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6736. .ops = &msm_spdif_be_ops,
  6737. .ignore_suspend = 1,
  6738. },
  6739. };
  6740. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6741. ARRAY_SIZE(msm_common_dai_links) +
  6742. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6743. ARRAY_SIZE(msm_common_be_dai_links) +
  6744. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6745. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6746. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6747. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6748. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6749. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6750. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6751. ARRAY_SIZE(msm_spdif_be_dai_links)];
  6752. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6753. {
  6754. int ret = 0;
  6755. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6756. &service_nb);
  6757. if (ret < 0)
  6758. pr_err("%s: Audio notifier register failed ret = %d\n",
  6759. __func__, ret);
  6760. return ret;
  6761. }
  6762. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6763. struct snd_ctl_elem_value *ucontrol)
  6764. {
  6765. int ret = 0;
  6766. int port_id;
  6767. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6768. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6769. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6770. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6771. (vad_enable < 0) || (vad_enable > 1) ||
  6772. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6773. pr_err("%s: Invalid arguments\n", __func__);
  6774. ret = -EINVAL;
  6775. goto done;
  6776. }
  6777. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6778. vad_enable, preroll_config, vad_intf);
  6779. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6780. if (ret) {
  6781. pr_err("%s: Invalid vad interface\n", __func__);
  6782. goto done;
  6783. }
  6784. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6785. done:
  6786. return ret;
  6787. }
  6788. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6789. {
  6790. int ret = 0;
  6791. uint32_t tasha_codec = 0;
  6792. ret = afe_cal_init_hwdep(card);
  6793. if (ret) {
  6794. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6795. ret = 0;
  6796. }
  6797. /* tasha late probe when it is present */
  6798. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6799. &tasha_codec);
  6800. if (ret) {
  6801. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6802. ret = 0;
  6803. } else {
  6804. if (tasha_codec) {
  6805. ret = msm_snd_card_tasha_late_probe(card);
  6806. if (ret)
  6807. dev_err(card->dev, "%s: tasha late probe err\n",
  6808. __func__);
  6809. }
  6810. }
  6811. return ret;
  6812. }
  6813. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6814. .name = "qcs405-snd-card",
  6815. .controls = msm_snd_controls,
  6816. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6817. .late_probe = msm_snd_card_codec_late_probe,
  6818. };
  6819. static int msm_populate_dai_link_component_of_node(
  6820. struct snd_soc_card *card)
  6821. {
  6822. int i, index, ret = 0;
  6823. struct device *cdev = card->dev;
  6824. struct snd_soc_dai_link *dai_link = card->dai_link;
  6825. struct device_node *np;
  6826. if (!cdev) {
  6827. pr_err("%s: Sound card device memory NULL\n", __func__);
  6828. return -ENODEV;
  6829. }
  6830. for (i = 0; i < card->num_links; i++) {
  6831. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6832. continue;
  6833. /* populate platform_of_node for snd card dai links */
  6834. if (dai_link[i].platform_name &&
  6835. !dai_link[i].platform_of_node) {
  6836. index = of_property_match_string(cdev->of_node,
  6837. "asoc-platform-names",
  6838. dai_link[i].platform_name);
  6839. if (index < 0) {
  6840. pr_err("%s: No match found for platform name: %s\n",
  6841. __func__, dai_link[i].platform_name);
  6842. ret = index;
  6843. goto err;
  6844. }
  6845. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6846. index);
  6847. if (!np) {
  6848. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6849. __func__, dai_link[i].platform_name,
  6850. index);
  6851. ret = -ENODEV;
  6852. goto err;
  6853. }
  6854. dai_link[i].platform_of_node = np;
  6855. dai_link[i].platform_name = NULL;
  6856. }
  6857. /* populate cpu_of_node for snd card dai links */
  6858. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6859. index = of_property_match_string(cdev->of_node,
  6860. "asoc-cpu-names",
  6861. dai_link[i].cpu_dai_name);
  6862. if (index >= 0) {
  6863. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6864. index);
  6865. if (!np) {
  6866. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6867. __func__,
  6868. dai_link[i].cpu_dai_name);
  6869. ret = -ENODEV;
  6870. goto err;
  6871. }
  6872. dai_link[i].cpu_of_node = np;
  6873. dai_link[i].cpu_dai_name = NULL;
  6874. }
  6875. }
  6876. /* populate codec_of_node for snd card dai links */
  6877. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6878. index = of_property_match_string(cdev->of_node,
  6879. "asoc-codec-names",
  6880. dai_link[i].codec_name);
  6881. if (index < 0)
  6882. continue;
  6883. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6884. index);
  6885. if (!np) {
  6886. pr_err("%s: retrieving phandle for codec %s failed\n",
  6887. __func__, dai_link[i].codec_name);
  6888. ret = -ENODEV;
  6889. goto err;
  6890. }
  6891. dai_link[i].codec_of_node = np;
  6892. dai_link[i].codec_name = NULL;
  6893. }
  6894. }
  6895. err:
  6896. return ret;
  6897. }
  6898. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6899. /* FrontEnd DAI Links */
  6900. {
  6901. .name = "MSMSTUB Media1",
  6902. .stream_name = "MultiMedia1",
  6903. .cpu_dai_name = "MultiMedia1",
  6904. .platform_name = "msm-pcm-dsp.0",
  6905. .dynamic = 1,
  6906. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6907. .dpcm_playback = 1,
  6908. .dpcm_capture = 1,
  6909. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6910. SND_SOC_DPCM_TRIGGER_POST},
  6911. .codec_dai_name = "snd-soc-dummy-dai",
  6912. .codec_name = "snd-soc-dummy",
  6913. .ignore_suspend = 1,
  6914. /* this dainlink has playback support */
  6915. .ignore_pmdown_time = 1,
  6916. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6917. },
  6918. };
  6919. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6920. /* Backend DAI Links */
  6921. {
  6922. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6923. .stream_name = "VA CDC DMA0 Capture",
  6924. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6925. .platform_name = "msm-pcm-routing",
  6926. .codec_name = "bolero_codec",
  6927. .codec_dai_name = "va_macro_tx1",
  6928. .no_pcm = 1,
  6929. .dpcm_capture = 1,
  6930. .init = &msm_va_cdc_dma_init,
  6931. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6932. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6933. .ignore_suspend = 1,
  6934. .ops = &msm_cdc_dma_be_ops,
  6935. },
  6936. {
  6937. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6938. .stream_name = "VA CDC DMA1 Capture",
  6939. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6940. .platform_name = "msm-pcm-routing",
  6941. .codec_name = "bolero_codec",
  6942. .codec_dai_name = "va_macro_tx2",
  6943. .no_pcm = 1,
  6944. .dpcm_capture = 1,
  6945. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6946. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6947. .ignore_suspend = 1,
  6948. .ops = &msm_cdc_dma_be_ops,
  6949. },
  6950. };
  6951. static struct snd_soc_dai_link msm_stub_dai_links[
  6952. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6953. ARRAY_SIZE(msm_stub_be_dai_links)];
  6954. struct snd_soc_card snd_soc_card_stub_msm = {
  6955. .name = "qcs405-stub-snd-card",
  6956. };
  6957. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6958. { .compatible = "qcom,qcs405-asoc-snd",
  6959. .data = "codec"},
  6960. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6961. .data = "stub_codec"},
  6962. {},
  6963. };
  6964. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6965. {
  6966. struct snd_soc_card *card = NULL;
  6967. struct snd_soc_dai_link *dailink;
  6968. int total_links = 0;
  6969. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6970. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6971. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  6972. const struct of_device_id *match;
  6973. char __iomem *spdif_cfg, *spdif_pin_ctl;
  6974. int rc = 0;
  6975. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6976. if (!match) {
  6977. dev_err(dev, "%s: No DT match found for sound card\n",
  6978. __func__);
  6979. return NULL;
  6980. }
  6981. if (!strcmp(match->data, "codec")) {
  6982. card = &snd_soc_card_qcs405_msm;
  6983. memcpy(msm_qcs405_dai_links + total_links,
  6984. msm_common_dai_links,
  6985. sizeof(msm_common_dai_links));
  6986. total_links += ARRAY_SIZE(msm_common_dai_links);
  6987. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6988. &wsa_bolero_codec);
  6989. if (rc) {
  6990. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6991. __func__);
  6992. } else {
  6993. if (wsa_bolero_codec) {
  6994. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  6995. __func__);
  6996. memcpy(msm_qcs405_dai_links + total_links,
  6997. msm_bolero_fe_dai_links,
  6998. sizeof(msm_bolero_fe_dai_links));
  6999. total_links +=
  7000. ARRAY_SIZE(msm_bolero_fe_dai_links);
  7001. }
  7002. }
  7003. memcpy(msm_qcs405_dai_links + total_links,
  7004. msm_common_misc_fe_dai_links,
  7005. sizeof(msm_common_misc_fe_dai_links));
  7006. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  7007. memcpy(msm_qcs405_dai_links + total_links,
  7008. msm_common_be_dai_links,
  7009. sizeof(msm_common_be_dai_links));
  7010. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  7011. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  7012. &tasha_codec);
  7013. if (rc) {
  7014. dev_dbg(dev, "%s: No DT match tasha codec\n",
  7015. __func__);
  7016. } else {
  7017. if (tasha_codec) {
  7018. memcpy(msm_qcs405_dai_links + total_links,
  7019. msm_tasha_be_dai_links,
  7020. sizeof(msm_tasha_be_dai_links));
  7021. total_links +=
  7022. ARRAY_SIZE(msm_tasha_be_dai_links);
  7023. }
  7024. }
  7025. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  7026. &va_bolero_codec);
  7027. if (rc) {
  7028. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  7029. __func__);
  7030. } else {
  7031. if (va_bolero_codec) {
  7032. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  7033. __func__);
  7034. memcpy(msm_qcs405_dai_links + total_links,
  7035. msm_va_cdc_dma_be_dai_links,
  7036. sizeof(msm_va_cdc_dma_be_dai_links));
  7037. total_links +=
  7038. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  7039. }
  7040. }
  7041. if (wsa_bolero_codec) {
  7042. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  7043. __func__);
  7044. memcpy(msm_qcs405_dai_links + total_links,
  7045. msm_wsa_cdc_dma_be_dai_links,
  7046. sizeof(msm_wsa_cdc_dma_be_dai_links));
  7047. total_links +=
  7048. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  7049. }
  7050. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  7051. &mi2s_audio_intf);
  7052. if (rc) {
  7053. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  7054. __func__);
  7055. } else {
  7056. if (mi2s_audio_intf) {
  7057. memcpy(msm_qcs405_dai_links + total_links,
  7058. msm_mi2s_be_dai_links,
  7059. sizeof(msm_mi2s_be_dai_links));
  7060. total_links +=
  7061. ARRAY_SIZE(msm_mi2s_be_dai_links);
  7062. }
  7063. }
  7064. rc = of_property_read_u32(dev->of_node,
  7065. "qcom,auxpcm-audio-intf",
  7066. &auxpcm_audio_intf);
  7067. if (rc) {
  7068. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  7069. __func__);
  7070. } else {
  7071. if (auxpcm_audio_intf) {
  7072. memcpy(msm_qcs405_dai_links + total_links,
  7073. msm_auxpcm_be_dai_links,
  7074. sizeof(msm_auxpcm_be_dai_links));
  7075. total_links +=
  7076. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  7077. }
  7078. }
  7079. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  7080. &spdif_audio_intf);
  7081. if (rc) {
  7082. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  7083. __func__);
  7084. } else {
  7085. if (spdif_audio_intf) {
  7086. memcpy(msm_qcs405_dai_links + total_links,
  7087. msm_spdif_be_dai_links,
  7088. sizeof(msm_spdif_be_dai_links));
  7089. total_links +=
  7090. ARRAY_SIZE(msm_spdif_be_dai_links);
  7091. /* enable spdif coax pins */
  7092. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  7093. spdif_pin_ctl =
  7094. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  7095. iowrite32(0xc0, spdif_cfg);
  7096. iowrite32(0x2220, spdif_pin_ctl);
  7097. }
  7098. }
  7099. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  7100. &wcn_audio_intf);
  7101. if (rc) {
  7102. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  7103. __func__);
  7104. } else {
  7105. if (wcn_audio_intf) {
  7106. memcpy(msm_qcs405_dai_links + total_links,
  7107. msm_wcn_be_dai_links,
  7108. sizeof(msm_wcn_be_dai_links));
  7109. total_links +=
  7110. ARRAY_SIZE(msm_wcn_be_dai_links);
  7111. }
  7112. }
  7113. dailink = msm_qcs405_dai_links;
  7114. } else if (!strcmp(match->data, "stub_codec")) {
  7115. card = &snd_soc_card_stub_msm;
  7116. memcpy(msm_stub_dai_links + total_links,
  7117. msm_stub_fe_dai_links,
  7118. sizeof(msm_stub_fe_dai_links));
  7119. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  7120. memcpy(msm_stub_dai_links + total_links,
  7121. msm_stub_be_dai_links,
  7122. sizeof(msm_stub_be_dai_links));
  7123. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  7124. dailink = msm_stub_dai_links;
  7125. }
  7126. if (card) {
  7127. card->dai_link = dailink;
  7128. card->num_links = total_links;
  7129. }
  7130. return card;
  7131. }
  7132. static int msm_wsa881x_init(struct snd_soc_component *component)
  7133. {
  7134. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7135. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7136. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  7137. SPKR_L_BOOST, SPKR_L_VI};
  7138. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  7139. SPKR_R_BOOST, SPKR_R_VI};
  7140. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  7141. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  7142. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7143. struct msm_asoc_mach_data *pdata;
  7144. struct snd_soc_dapm_context *dapm;
  7145. int ret = 0;
  7146. if (!codec) {
  7147. pr_err("%s codec is NULL\n", __func__);
  7148. return -EINVAL;
  7149. }
  7150. dapm = snd_soc_codec_get_dapm(codec);
  7151. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  7152. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  7153. __func__, codec->component.name);
  7154. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  7155. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7156. &ch_rate[0], &spkleft_port_types[0]);
  7157. if (dapm->component) {
  7158. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  7159. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  7160. }
  7161. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  7162. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  7163. __func__, codec->component.name);
  7164. wsa881x_set_channel_map(codec, &spkright_ports[0],
  7165. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7166. &ch_rate[0], &spkright_port_types[0]);
  7167. if (dapm->component) {
  7168. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7169. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7170. }
  7171. } else {
  7172. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  7173. codec->component.name);
  7174. ret = -EINVAL;
  7175. goto err;
  7176. }
  7177. pdata = snd_soc_card_get_drvdata(component->card);
  7178. if (pdata && pdata->codec_root)
  7179. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7180. codec);
  7181. err:
  7182. return ret;
  7183. }
  7184. static int msm_init_wsa_dev(struct platform_device *pdev,
  7185. struct snd_soc_card *card)
  7186. {
  7187. struct device_node *wsa_of_node;
  7188. u32 wsa_max_devs;
  7189. u32 wsa_dev_cnt;
  7190. int i;
  7191. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7192. const char *wsa_auxdev_name_prefix[1];
  7193. char *dev_name_str = NULL;
  7194. int found = 0;
  7195. int ret = 0;
  7196. /* Get maximum WSA device count for this platform */
  7197. ret = of_property_read_u32(pdev->dev.of_node,
  7198. "qcom,wsa-max-devs", &wsa_max_devs);
  7199. if (ret) {
  7200. dev_info(&pdev->dev,
  7201. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7202. __func__, pdev->dev.of_node->full_name, ret);
  7203. card->num_aux_devs = 0;
  7204. return 0;
  7205. }
  7206. if (wsa_max_devs == 0) {
  7207. dev_warn(&pdev->dev,
  7208. "%s: Max WSA devices is 0 for this target?\n",
  7209. __func__);
  7210. card->num_aux_devs = 0;
  7211. return 0;
  7212. }
  7213. /* Get count of WSA device phandles for this platform */
  7214. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7215. "qcom,wsa-devs", NULL);
  7216. if (wsa_dev_cnt == -ENOENT) {
  7217. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7218. __func__);
  7219. goto err;
  7220. } else if (wsa_dev_cnt <= 0) {
  7221. dev_err(&pdev->dev,
  7222. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7223. __func__, wsa_dev_cnt);
  7224. ret = -EINVAL;
  7225. goto err;
  7226. }
  7227. /*
  7228. * Expect total phandles count to be NOT less than maximum possible
  7229. * WSA count. However, if it is less, then assign same value to
  7230. * max count as well.
  7231. */
  7232. if (wsa_dev_cnt < wsa_max_devs) {
  7233. dev_dbg(&pdev->dev,
  7234. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7235. __func__, wsa_max_devs, wsa_dev_cnt);
  7236. wsa_max_devs = wsa_dev_cnt;
  7237. }
  7238. /* Make sure prefix string passed for each WSA device */
  7239. ret = of_property_count_strings(pdev->dev.of_node,
  7240. "qcom,wsa-aux-dev-prefix");
  7241. if (ret != wsa_dev_cnt) {
  7242. dev_err(&pdev->dev,
  7243. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7244. __func__, wsa_dev_cnt, ret);
  7245. ret = -EINVAL;
  7246. goto err;
  7247. }
  7248. /*
  7249. * Alloc mem to store phandle and index info of WSA device, if already
  7250. * registered with ALSA core
  7251. */
  7252. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7253. sizeof(struct msm_wsa881x_dev_info),
  7254. GFP_KERNEL);
  7255. if (!wsa881x_dev_info) {
  7256. ret = -ENOMEM;
  7257. goto err;
  7258. }
  7259. /*
  7260. * search and check whether all WSA devices are already
  7261. * registered with ALSA core or not. If found a node, store
  7262. * the node and the index in a local array of struct for later
  7263. * use.
  7264. */
  7265. for (i = 0; i < wsa_dev_cnt; i++) {
  7266. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7267. "qcom,wsa-devs", i);
  7268. if (unlikely(!wsa_of_node)) {
  7269. /* we should not be here */
  7270. dev_err(&pdev->dev,
  7271. "%s: wsa dev node is not present\n",
  7272. __func__);
  7273. ret = -EINVAL;
  7274. goto err_free_dev_info;
  7275. }
  7276. if (soc_find_component(wsa_of_node, NULL)) {
  7277. /* WSA device registered with ALSA core */
  7278. wsa881x_dev_info[found].of_node = wsa_of_node;
  7279. wsa881x_dev_info[found].index = i;
  7280. found++;
  7281. if (found == wsa_max_devs)
  7282. break;
  7283. }
  7284. }
  7285. if (found < wsa_max_devs) {
  7286. dev_err(&pdev->dev,
  7287. "%s: failed to find %d components. Found only %d\n",
  7288. __func__, wsa_max_devs, found);
  7289. return -EPROBE_DEFER;
  7290. }
  7291. dev_info(&pdev->dev,
  7292. "%s: found %d wsa881x devices registered with ALSA core\n",
  7293. __func__, found);
  7294. card->num_aux_devs = wsa_max_devs;
  7295. card->num_configs = wsa_max_devs;
  7296. /* Alloc array of AUX devs struct */
  7297. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7298. sizeof(struct snd_soc_aux_dev),
  7299. GFP_KERNEL);
  7300. if (!msm_aux_dev) {
  7301. ret = -ENOMEM;
  7302. goto err_free_dev_info;
  7303. }
  7304. /* Alloc array of codec conf struct */
  7305. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7306. sizeof(struct snd_soc_codec_conf),
  7307. GFP_KERNEL);
  7308. if (!msm_codec_conf) {
  7309. ret = -ENOMEM;
  7310. goto err_free_aux_dev;
  7311. }
  7312. for (i = 0; i < card->num_aux_devs; i++) {
  7313. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7314. GFP_KERNEL);
  7315. if (!dev_name_str) {
  7316. ret = -ENOMEM;
  7317. goto err_free_cdc_conf;
  7318. }
  7319. ret = of_property_read_string_index(pdev->dev.of_node,
  7320. "qcom,wsa-aux-dev-prefix",
  7321. wsa881x_dev_info[i].index,
  7322. wsa_auxdev_name_prefix);
  7323. if (ret) {
  7324. dev_err(&pdev->dev,
  7325. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7326. __func__, ret);
  7327. ret = -EINVAL;
  7328. goto err_free_dev_name_str;
  7329. }
  7330. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7331. msm_aux_dev[i].name = dev_name_str;
  7332. msm_aux_dev[i].codec_name = NULL;
  7333. msm_aux_dev[i].codec_of_node =
  7334. wsa881x_dev_info[i].of_node;
  7335. msm_aux_dev[i].init = msm_wsa881x_init;
  7336. msm_codec_conf[i].dev_name = NULL;
  7337. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7338. msm_codec_conf[i].of_node =
  7339. wsa881x_dev_info[i].of_node;
  7340. }
  7341. card->codec_conf = msm_codec_conf;
  7342. card->aux_dev = msm_aux_dev;
  7343. return 0;
  7344. err_free_dev_name_str:
  7345. devm_kfree(&pdev->dev, dev_name_str);
  7346. err_free_cdc_conf:
  7347. devm_kfree(&pdev->dev, msm_codec_conf);
  7348. err_free_aux_dev:
  7349. devm_kfree(&pdev->dev, msm_aux_dev);
  7350. err_free_dev_info:
  7351. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7352. err:
  7353. return ret;
  7354. }
  7355. static int msm_csra66x0_init(struct snd_soc_component *component)
  7356. {
  7357. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  7358. if (!codec) {
  7359. pr_err("%s codec is NULL\n", __func__);
  7360. return -EINVAL;
  7361. }
  7362. return 0;
  7363. }
  7364. static int msm_init_csra_dev(struct platform_device *pdev,
  7365. struct snd_soc_card *card)
  7366. {
  7367. struct device_node *csra_of_node;
  7368. u32 csra_max_devs;
  7369. u32 csra_dev_cnt;
  7370. char *dev_name_str = NULL;
  7371. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7372. const char *csra_auxdev_name_prefix[1];
  7373. int i;
  7374. int found = 0;
  7375. int ret = 0;
  7376. /* Get maximum CSRA device count for this platform */
  7377. ret = of_property_read_u32(pdev->dev.of_node,
  7378. "qcom,csra-max-devs", &csra_max_devs);
  7379. if (ret) {
  7380. dev_info(&pdev->dev,
  7381. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7382. __func__, pdev->dev.of_node->full_name, ret);
  7383. card->num_aux_devs = 0;
  7384. return 0;
  7385. }
  7386. if (csra_max_devs == 0) {
  7387. dev_warn(&pdev->dev,
  7388. "%s: Max CSRA devices is 0 for this target?\n",
  7389. __func__);
  7390. return 0;
  7391. }
  7392. /* Get count of CSRA device phandles for this platform */
  7393. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7394. "qcom,csra-devs", NULL);
  7395. if (csra_dev_cnt == -ENOENT) {
  7396. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7397. __func__);
  7398. goto err;
  7399. } else if (csra_dev_cnt <= 0) {
  7400. dev_err(&pdev->dev,
  7401. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7402. __func__, csra_dev_cnt);
  7403. ret = -EINVAL;
  7404. goto err;
  7405. }
  7406. /*
  7407. * Expect total phandles count to be NOT less than maximum possible
  7408. * CSRA count. However, if it is less, then assign same value to
  7409. * max count as well.
  7410. */
  7411. if (csra_dev_cnt < csra_max_devs) {
  7412. dev_dbg(&pdev->dev,
  7413. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7414. __func__, csra_max_devs, csra_dev_cnt);
  7415. csra_max_devs = csra_dev_cnt;
  7416. }
  7417. /* Make sure prefix string passed for each CSRA device */
  7418. ret = of_property_count_strings(pdev->dev.of_node,
  7419. "qcom,csra-aux-dev-prefix");
  7420. if (ret != csra_dev_cnt) {
  7421. dev_err(&pdev->dev,
  7422. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7423. __func__, csra_dev_cnt, ret);
  7424. ret = -EINVAL;
  7425. goto err;
  7426. }
  7427. /*
  7428. * Alloc mem to store phandle and index info of CSRA device, if already
  7429. * registered with ALSA core
  7430. */
  7431. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7432. sizeof(struct msm_csra66x0_dev_info),
  7433. GFP_KERNEL);
  7434. if (!csra66x0_dev_info) {
  7435. ret = -ENOMEM;
  7436. goto err;
  7437. }
  7438. /*
  7439. * search and check whether all CSRA devices are already
  7440. * registered with ALSA core or not. If found a node, store
  7441. * the node and the index in a local array of struct for later
  7442. * use.
  7443. */
  7444. for (i = 0; i < csra_dev_cnt; i++) {
  7445. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7446. "qcom,csra-devs", i);
  7447. if (unlikely(!csra_of_node)) {
  7448. /* we should not be here */
  7449. dev_err(&pdev->dev,
  7450. "%s: csra dev node is not present\n",
  7451. __func__);
  7452. ret = -EINVAL;
  7453. goto err_free_dev_info;
  7454. }
  7455. if (soc_find_component(csra_of_node, NULL)) {
  7456. /* CSRA device registered with ALSA core */
  7457. csra66x0_dev_info[found].of_node = csra_of_node;
  7458. csra66x0_dev_info[found].index = i;
  7459. found++;
  7460. if (found == csra_max_devs)
  7461. break;
  7462. }
  7463. }
  7464. if (found < csra_max_devs) {
  7465. dev_dbg(&pdev->dev,
  7466. "%s: failed to find %d components. Found only %d\n",
  7467. __func__, csra_max_devs, found);
  7468. return -EPROBE_DEFER;
  7469. }
  7470. dev_info(&pdev->dev,
  7471. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7472. __func__, found);
  7473. card->num_aux_devs = csra_max_devs;
  7474. card->num_configs = csra_max_devs;
  7475. /* Alloc array of AUX devs struct */
  7476. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7477. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7478. if (!msm_aux_dev) {
  7479. ret = -ENOMEM;
  7480. goto err_free_dev_info;
  7481. }
  7482. /* Alloc array of codec conf struct */
  7483. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7484. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7485. if (!msm_codec_conf) {
  7486. ret = -ENOMEM;
  7487. goto err_free_aux_dev;
  7488. }
  7489. for (i = 0; i < card->num_aux_devs; i++) {
  7490. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7491. GFP_KERNEL);
  7492. if (!dev_name_str) {
  7493. ret = -ENOMEM;
  7494. goto err_free_cdc_conf;
  7495. }
  7496. ret = of_property_read_string_index(pdev->dev.of_node,
  7497. "qcom,csra-aux-dev-prefix",
  7498. csra66x0_dev_info[i].index,
  7499. csra_auxdev_name_prefix);
  7500. if (ret) {
  7501. dev_err(&pdev->dev,
  7502. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7503. __func__, ret);
  7504. ret = -EINVAL;
  7505. goto err_free_dev_name_str;
  7506. }
  7507. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7508. msm_aux_dev[i].name = dev_name_str;
  7509. msm_aux_dev[i].codec_name = NULL;
  7510. msm_aux_dev[i].codec_of_node =
  7511. csra66x0_dev_info[i].of_node;
  7512. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7513. msm_codec_conf[i].dev_name = NULL;
  7514. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7515. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7516. }
  7517. card->codec_conf = msm_codec_conf;
  7518. card->aux_dev = msm_aux_dev;
  7519. return 0;
  7520. err_free_dev_name_str:
  7521. devm_kfree(&pdev->dev, dev_name_str);
  7522. err_free_cdc_conf:
  7523. devm_kfree(&pdev->dev, msm_codec_conf);
  7524. err_free_aux_dev:
  7525. devm_kfree(&pdev->dev, msm_aux_dev);
  7526. err_free_dev_info:
  7527. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7528. err:
  7529. return ret;
  7530. }
  7531. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7532. {
  7533. int count;
  7534. u32 mi2s_master_slave[MI2S_MAX];
  7535. int ret;
  7536. for (count = 0; count < MI2S_MAX; count++) {
  7537. mutex_init(&mi2s_intf_conf[count].lock);
  7538. mi2s_intf_conf[count].ref_cnt = 0;
  7539. }
  7540. ret = of_property_read_u32_array(pdev->dev.of_node,
  7541. "qcom,msm-mi2s-master",
  7542. mi2s_master_slave, MI2S_MAX);
  7543. if (ret) {
  7544. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7545. __func__);
  7546. } else {
  7547. for (count = 0; count < MI2S_MAX; count++) {
  7548. mi2s_intf_conf[count].msm_is_mi2s_master =
  7549. mi2s_master_slave[count];
  7550. }
  7551. }
  7552. }
  7553. static void msm_i2s_auxpcm_deinit(void)
  7554. {
  7555. int count;
  7556. for (count = 0; count < MI2S_MAX; count++) {
  7557. mutex_destroy(&mi2s_intf_conf[count].lock);
  7558. mi2s_intf_conf[count].ref_cnt = 0;
  7559. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7560. }
  7561. }
  7562. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7563. uint32_t busnum, uint32_t addr)
  7564. {
  7565. struct i2c_adapter *adap;
  7566. u8 rbuf;
  7567. struct i2c_msg msg;
  7568. int status = 0;
  7569. adap = i2c_get_adapter(busnum);
  7570. if (!adap) {
  7571. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7572. __func__, busnum);
  7573. return -EBUSY;
  7574. }
  7575. /* to test presence, read one byte from device */
  7576. msg.addr = addr;
  7577. msg.flags = I2C_M_RD;
  7578. msg.len = 1;
  7579. msg.buf = &rbuf;
  7580. status = i2c_transfer(adap, &msg, 1);
  7581. i2c_put_adapter(adap);
  7582. if (status != 1) {
  7583. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  7584. __func__, addr);
  7585. return -ENODEV;
  7586. }
  7587. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  7588. __func__, addr);
  7589. return 0;
  7590. }
  7591. static int msm_detect_ep92_dev(struct platform_device *pdev,
  7592. struct snd_soc_card *card)
  7593. {
  7594. int i;
  7595. uint32_t ep92_busnum = 0;
  7596. uint32_t ep92_reg = 0;
  7597. const char *ep92_name = NULL;
  7598. struct snd_soc_dai_link *dai;
  7599. int rc = 0;
  7600. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  7601. &ep92_busnum);
  7602. if (rc) {
  7603. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  7604. return 0;
  7605. }
  7606. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  7607. &ep92_reg);
  7608. if (rc) {
  7609. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  7610. return 0;
  7611. }
  7612. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  7613. &ep92_name);
  7614. if (rc) {
  7615. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  7616. return 0;
  7617. }
  7618. /* check I2C bus for connected ep92 chip */
  7619. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7620. /* check a second time after a short delay */
  7621. msleep(20);
  7622. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  7623. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  7624. __func__);
  7625. /* continue with snd_card registration without ep92 */
  7626. return 0;
  7627. }
  7628. }
  7629. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  7630. /* update codec info in MI2S dai link */
  7631. dai = &msm_mi2s_be_dai_links[0];
  7632. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  7633. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  7634. dev_dbg(&pdev->dev,
  7635. "%s: Set Sec MI2S dai to ep92 codec\n",
  7636. __func__);
  7637. dai->codec_name = ep92_name;
  7638. dai->codec_dai_name = "ep92-hdmi";
  7639. break;
  7640. }
  7641. dai++;
  7642. }
  7643. /* update codec info in SPDIF dai link */
  7644. dai = &msm_spdif_be_dai_links[0];
  7645. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  7646. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  7647. dev_dbg(&pdev->dev,
  7648. "%s: Set Sec SPDIF dai to ep92 codec\n",
  7649. __func__);
  7650. dai->codec_name = ep92_name;
  7651. dai->codec_dai_name = "ep92-arc";
  7652. break;
  7653. }
  7654. dai++;
  7655. }
  7656. return 0;
  7657. }
  7658. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7659. {
  7660. struct snd_soc_card *card;
  7661. struct msm_asoc_mach_data *pdata;
  7662. int ret;
  7663. u32 val;
  7664. const char *micb_supply_str = "tdm-vdd-micb-supply";
  7665. const char *micb_supply_str1 = "tdm-vdd-micb";
  7666. const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
  7667. const char *micb_current_str = "qcom,tdm-vdd-micb-current";
  7668. if (!pdev->dev.of_node) {
  7669. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  7670. return -EINVAL;
  7671. }
  7672. pdata = devm_kzalloc(&pdev->dev,
  7673. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7674. if (!pdata)
  7675. return -ENOMEM;
  7676. /* test for ep92 HDMI bridge and update dai links accordingly */
  7677. ret = msm_detect_ep92_dev(pdev, card);
  7678. if (ret)
  7679. goto err;
  7680. card = populate_snd_card_dailinks(&pdev->dev);
  7681. if (!card) {
  7682. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7683. ret = -EINVAL;
  7684. goto err;
  7685. }
  7686. card->dev = &pdev->dev;
  7687. platform_set_drvdata(pdev, card);
  7688. snd_soc_card_set_drvdata(card, pdata);
  7689. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7690. if (ret) {
  7691. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  7692. ret);
  7693. goto err;
  7694. }
  7695. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7696. if (ret) {
  7697. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  7698. ret);
  7699. goto err;
  7700. }
  7701. ret = msm_populate_dai_link_component_of_node(card);
  7702. if (ret) {
  7703. ret = -EPROBE_DEFER;
  7704. goto err;
  7705. }
  7706. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  7707. if (ret) {
  7708. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  7709. val = 0;
  7710. }
  7711. if (val) {
  7712. pdata->codec_is_csra = true;
  7713. mi2s_rx_cfg[PRIM_MI2S].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  7714. ret = msm_init_csra_dev(pdev, card);
  7715. if (ret)
  7716. goto err;
  7717. } else {
  7718. pdata->codec_is_csra = false;
  7719. ret = msm_init_wsa_dev(pdev, card);
  7720. if (ret)
  7721. goto err;
  7722. }
  7723. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7724. "qcom,cdc-dmic01-gpios", 0);
  7725. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7726. "qcom,cdc-dmic23-gpios", 0);
  7727. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7728. "qcom,cdc-dmic45-gpios", 0);
  7729. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7730. "qcom,cdc-dmic67-gpios", 0);
  7731. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7732. "qcom,pri-mi2s-gpios", 0);
  7733. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7734. "qcom,sec-mi2s-gpios", 0);
  7735. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7736. "qcom,tert-mi2s-gpios", 0);
  7737. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7738. "qcom,quat-mi2s-gpios", 0);
  7739. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7740. "qcom,quin-mi2s-gpios", 0);
  7741. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  7742. pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev,
  7743. micb_supply_str1);
  7744. if (IS_ERR(pdata->tdm_micb_supply)) {
  7745. ret = PTR_ERR(pdata->tdm_micb_supply);
  7746. dev_err(&pdev->dev,
  7747. "%s:Failed to get micbias supply for TDM Mic %d\n",
  7748. __func__, ret);
  7749. }
  7750. ret = of_property_read_u32(pdev->dev.of_node,
  7751. micb_voltage_str,
  7752. &pdata->tdm_micb_voltage);
  7753. if (ret) {
  7754. dev_err(&pdev->dev,
  7755. "%s:Looking up %s property in node %s failed\n",
  7756. __func__, micb_voltage_str,
  7757. pdev->dev.of_node->full_name);
  7758. }
  7759. ret = of_property_read_u32(pdev->dev.of_node,
  7760. micb_current_str,
  7761. &pdata->tdm_micb_current);
  7762. if (ret) {
  7763. dev_err(&pdev->dev,
  7764. "%s:Looking up %s property in node %s failed\n",
  7765. __func__, micb_current_str,
  7766. pdev->dev.of_node->full_name);
  7767. }
  7768. }
  7769. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7770. if (ret == -EPROBE_DEFER) {
  7771. if (codec_reg_done)
  7772. ret = -EINVAL;
  7773. goto err;
  7774. } else if (ret) {
  7775. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  7776. ret);
  7777. goto err;
  7778. }
  7779. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  7780. spdev = pdev;
  7781. ret = msm_mdf_mem_init();
  7782. if (ret)
  7783. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  7784. ret);
  7785. msm_i2s_auxpcm_init(pdev);
  7786. is_initial_boot = true;
  7787. return 0;
  7788. err:
  7789. return ret;
  7790. }
  7791. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7792. {
  7793. audio_notifier_deregister("qcs405");
  7794. msm_i2s_auxpcm_deinit();
  7795. msm_mdf_mem_deinit();
  7796. return 0;
  7797. }
  7798. static struct platform_driver qcs405_asoc_machine_driver = {
  7799. .driver = {
  7800. .name = DRV_NAME,
  7801. .owner = THIS_MODULE,
  7802. .pm = &snd_soc_pm_ops,
  7803. .of_match_table = qcs405_asoc_machine_of_match,
  7804. },
  7805. .probe = msm_asoc_machine_probe,
  7806. .remove = msm_asoc_machine_remove,
  7807. };
  7808. module_platform_driver(qcs405_asoc_machine_driver);
  7809. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  7810. MODULE_LICENSE("GPL v2");
  7811. MODULE_ALIAS("platform:" DRV_NAME);
  7812. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);