qcs405.c 207 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/input.h>
  21. #include <linux/of_device.h>
  22. #include <linux/pm_qos.h>
  23. #include <sound/core.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/info.h>
  29. #include <dsp/audio_notifier.h>
  30. #include <dsp/q6afe-v2.h>
  31. #include <dsp/q6core.h>
  32. #include "device_event.h"
  33. #include "msm-pcm-routing-v2.h"
  34. #include "codecs/msm-cdc-pinctrl.h"
  35. #include "codecs/wcd9335.h"
  36. #include "codecs/wsa881x.h"
  37. #define DRV_NAME "qcs405-asoc-snd"
  38. #define __CHIPSET__ "QCS405 "
  39. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  40. #define DEV_NAME_STR_LEN 32
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define WSA8810_NAME_1 "wsa881x.20170211"
  55. #define WSA8810_NAME_2 "wsa881x.20170212"
  56. #define WCN_CDC_SLIM_RX_CH_MAX 2
  57. #define WCN_CDC_SLIM_TX_CH_MAX 3
  58. #define TDM_CHANNEL_MAX 8
  59. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  60. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  61. enum {
  62. SLIM_RX_0 = 0,
  63. SLIM_RX_1,
  64. SLIM_RX_2,
  65. SLIM_RX_3,
  66. SLIM_RX_4,
  67. SLIM_RX_5,
  68. SLIM_RX_6,
  69. SLIM_RX_7,
  70. SLIM_RX_MAX,
  71. };
  72. enum {
  73. SLIM_TX_0 = 0,
  74. SLIM_TX_1,
  75. SLIM_TX_2,
  76. SLIM_TX_3,
  77. SLIM_TX_4,
  78. SLIM_TX_5,
  79. SLIM_TX_6,
  80. SLIM_TX_7,
  81. SLIM_TX_8,
  82. SLIM_TX_MAX,
  83. };
  84. enum {
  85. PRIM_MI2S = 0,
  86. SEC_MI2S,
  87. TERT_MI2S,
  88. QUAT_MI2S,
  89. QUIN_MI2S,
  90. MI2S_MAX,
  91. };
  92. enum {
  93. PRIM_AUX_PCM = 0,
  94. SEC_AUX_PCM,
  95. TERT_AUX_PCM,
  96. QUAT_AUX_PCM,
  97. QUIN_AUX_PCM,
  98. AUX_PCM_MAX,
  99. };
  100. enum {
  101. WSA_CDC_DMA_RX_0 = 0,
  102. WSA_CDC_DMA_RX_1,
  103. CDC_DMA_RX_MAX,
  104. };
  105. enum {
  106. WSA_CDC_DMA_TX_0 = 0,
  107. WSA_CDC_DMA_TX_1,
  108. WSA_CDC_DMA_TX_2,
  109. VA_CDC_DMA_TX_0,
  110. VA_CDC_DMA_TX_1,
  111. CDC_DMA_TX_MAX,
  112. };
  113. struct mi2s_conf {
  114. struct mutex lock;
  115. u32 ref_cnt;
  116. u32 msm_is_mi2s_master;
  117. };
  118. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  119. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  120. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  121. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  122. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  123. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  124. };
  125. struct dev_config {
  126. u32 sample_rate;
  127. u32 bit_format;
  128. u32 channels;
  129. };
  130. struct msm_wsa881x_dev_info {
  131. struct device_node *of_node;
  132. u32 index;
  133. };
  134. enum pinctrl_pin_state {
  135. STATE_DISABLE = 0, /* All pins are in sleep state */
  136. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  137. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  138. };
  139. struct msm_pinctrl_info {
  140. struct pinctrl *pinctrl;
  141. struct pinctrl_state *mi2s_disable;
  142. struct pinctrl_state *tdm_disable;
  143. struct pinctrl_state *mi2s_active;
  144. struct pinctrl_state *tdm_active;
  145. enum pinctrl_pin_state curr_state;
  146. };
  147. struct msm_asoc_mach_data {
  148. struct snd_info_entry *codec_root;
  149. struct msm_pinctrl_info pinctrl_info;
  150. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  151. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  152. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  153. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  154. int dmic_01_gpio_cnt;
  155. int dmic_23_gpio_cnt;
  156. int dmic_45_gpio_cnt;
  157. int dmic_67_gpio_cnt;
  158. };
  159. struct msm_asoc_wcd93xx_codec {
  160. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  161. enum afe_config_type config_type);
  162. };
  163. static const char *const pin_states[] = {"sleep", "i2s-active",
  164. "tdm-active"};
  165. enum {
  166. TDM_0 = 0,
  167. TDM_1,
  168. TDM_2,
  169. TDM_3,
  170. TDM_4,
  171. TDM_5,
  172. TDM_6,
  173. TDM_7,
  174. TDM_PORT_MAX,
  175. };
  176. enum {
  177. TDM_PRI = 0,
  178. TDM_SEC,
  179. TDM_TERT,
  180. TDM_QUAT,
  181. TDM_QUIN,
  182. TDM_INTERFACE_MAX,
  183. };
  184. struct tdm_port {
  185. u32 mode;
  186. u32 channel;
  187. };
  188. /* TDM default config */
  189. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  190. { /* PRI TDM */
  191. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  192. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  193. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  194. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  195. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  196. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  197. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  198. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  199. },
  200. { /* SEC TDM */
  201. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  202. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  203. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  209. },
  210. { /* TERT TDM */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  219. },
  220. { /* QUAT TDM */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  229. },
  230. { /* QUIN TDM */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  239. }
  240. };
  241. /* TDM default config */
  242. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  243. { /* PRI TDM */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  252. },
  253. { /* SEC TDM */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  262. },
  263. { /* TERT TDM */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  272. },
  273. { /* QUAT TDM */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  282. },
  283. { /* QUIN TDM */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  292. }
  293. };
  294. /* Default configuration of slimbus channels */
  295. static struct dev_config slim_rx_cfg[] = {
  296. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  297. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  298. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  299. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  300. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  301. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  302. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  303. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  304. };
  305. static struct dev_config slim_tx_cfg[] = {
  306. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  307. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  308. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  309. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  315. };
  316. /* Default configuration of Codec DMA Interface Tx */
  317. static struct dev_config cdc_dma_rx_cfg[] = {
  318. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  319. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  320. };
  321. /* Default configuration of Codec DMA Interface Rx */
  322. static struct dev_config cdc_dma_tx_cfg[] = {
  323. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  324. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  325. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  326. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  327. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  328. };
  329. static struct dev_config usb_rx_cfg = {
  330. .sample_rate = SAMPLING_RATE_48KHZ,
  331. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  332. .channels = 2,
  333. };
  334. static struct dev_config usb_tx_cfg = {
  335. .sample_rate = SAMPLING_RATE_48KHZ,
  336. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  337. .channels = 1,
  338. };
  339. static struct dev_config proxy_rx_cfg = {
  340. .sample_rate = SAMPLING_RATE_48KHZ,
  341. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  342. .channels = 2,
  343. };
  344. /* Default configuration of MI2S channels */
  345. static struct dev_config mi2s_rx_cfg[] = {
  346. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  347. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  349. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  350. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  351. };
  352. static struct dev_config mi2s_tx_cfg[] = {
  353. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  354. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  355. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  356. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  357. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  358. };
  359. static struct dev_config aux_pcm_rx_cfg[] = {
  360. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  361. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  362. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  363. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  364. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  365. };
  366. static struct dev_config aux_pcm_tx_cfg[] = {
  367. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  368. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  369. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  370. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  371. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  372. };
  373. static int msm_vi_feed_tx_ch = 2;
  374. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  375. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  376. "Five", "Six", "Seven",
  377. "Eight"};
  378. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  379. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  380. "S32_LE"};
  381. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  382. "KHZ_32", "KHZ_44P1", "KHZ_48",
  383. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  384. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  385. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  386. "KHZ_44P1", "KHZ_48",
  387. "KHZ_88P2", "KHZ_96"};
  388. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  389. "Five", "Six", "Seven",
  390. "Eight"};
  391. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  392. "Six", "Seven", "Eight"};
  393. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  394. "KHZ_16", "KHZ_22P05",
  395. "KHZ_32", "KHZ_44P1", "KHZ_48",
  396. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  397. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  398. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  399. "Five", "Six", "Seven", "Eight"};
  400. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  401. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  402. "KHZ_48", "KHZ_176P4",
  403. "KHZ_352P8"};
  404. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  405. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  406. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  407. "KHZ_48", "KHZ_96", "KHZ_192"};
  408. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  409. "Five", "Six", "Seven",
  410. "Eight"};
  411. static const char *const qos_text[] = {"Disable", "Enable"};
  412. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  413. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  414. "Five", "Six", "Seven",
  415. "Eight"};
  416. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  417. "KHZ_32", "KHZ_44P1", "KHZ_48",
  418. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  419. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  420. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  421. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  422. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  423. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  424. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  425. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  426. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  427. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  428. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  429. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  430. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  498. cdc_dma_sample_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  500. cdc_dma_sample_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  502. cdc_dma_sample_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  504. cdc_dma_sample_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  506. cdc_dma_sample_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  508. cdc_dma_sample_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  510. cdc_dma_sample_rate_text);
  511. static struct platform_device *spdev;
  512. static bool is_initial_boot;
  513. static bool codec_reg_done;
  514. static struct snd_soc_aux_dev *msm_aux_dev;
  515. static struct snd_soc_codec_conf *msm_codec_conf;
  516. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  517. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  518. int enable, bool dapm);
  519. static int msm_wsa881x_init(struct snd_soc_component *component);
  520. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  521. {"MIC BIAS1", NULL, "MCLK TX"},
  522. {"MIC BIAS2", NULL, "MCLK TX"},
  523. {"MIC BIAS3", NULL, "MCLK TX"},
  524. {"MIC BIAS4", NULL, "MCLK TX"},
  525. };
  526. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  527. {
  528. AFE_API_VERSION_I2S_CONFIG,
  529. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  530. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  531. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  532. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  533. 0,
  534. },
  535. {
  536. AFE_API_VERSION_I2S_CONFIG,
  537. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  538. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  539. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  540. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  541. 0,
  542. },
  543. {
  544. AFE_API_VERSION_I2S_CONFIG,
  545. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  546. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  547. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  548. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  549. 0,
  550. },
  551. {
  552. AFE_API_VERSION_I2S_CONFIG,
  553. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  554. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  555. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  556. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  557. 0,
  558. },
  559. {
  560. AFE_API_VERSION_I2S_CONFIG,
  561. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  562. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  563. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  564. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  565. 0,
  566. }
  567. };
  568. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  569. static int slim_get_sample_rate_val(int sample_rate)
  570. {
  571. int sample_rate_val = 0;
  572. switch (sample_rate) {
  573. case SAMPLING_RATE_8KHZ:
  574. sample_rate_val = 0;
  575. break;
  576. case SAMPLING_RATE_16KHZ:
  577. sample_rate_val = 1;
  578. break;
  579. case SAMPLING_RATE_32KHZ:
  580. sample_rate_val = 2;
  581. break;
  582. case SAMPLING_RATE_44P1KHZ:
  583. sample_rate_val = 3;
  584. break;
  585. case SAMPLING_RATE_48KHZ:
  586. sample_rate_val = 4;
  587. break;
  588. case SAMPLING_RATE_88P2KHZ:
  589. sample_rate_val = 5;
  590. break;
  591. case SAMPLING_RATE_96KHZ:
  592. sample_rate_val = 6;
  593. break;
  594. case SAMPLING_RATE_176P4KHZ:
  595. sample_rate_val = 7;
  596. break;
  597. case SAMPLING_RATE_192KHZ:
  598. sample_rate_val = 8;
  599. break;
  600. case SAMPLING_RATE_352P8KHZ:
  601. sample_rate_val = 9;
  602. break;
  603. case SAMPLING_RATE_384KHZ:
  604. sample_rate_val = 10;
  605. break;
  606. default:
  607. sample_rate_val = 4;
  608. break;
  609. }
  610. return sample_rate_val;
  611. }
  612. static int slim_get_sample_rate(int value)
  613. {
  614. int sample_rate = 0;
  615. switch (value) {
  616. case 0:
  617. sample_rate = SAMPLING_RATE_8KHZ;
  618. break;
  619. case 1:
  620. sample_rate = SAMPLING_RATE_16KHZ;
  621. break;
  622. case 2:
  623. sample_rate = SAMPLING_RATE_32KHZ;
  624. break;
  625. case 3:
  626. sample_rate = SAMPLING_RATE_44P1KHZ;
  627. break;
  628. case 4:
  629. sample_rate = SAMPLING_RATE_48KHZ;
  630. break;
  631. case 5:
  632. sample_rate = SAMPLING_RATE_88P2KHZ;
  633. break;
  634. case 6:
  635. sample_rate = SAMPLING_RATE_96KHZ;
  636. break;
  637. case 7:
  638. sample_rate = SAMPLING_RATE_176P4KHZ;
  639. break;
  640. case 8:
  641. sample_rate = SAMPLING_RATE_192KHZ;
  642. break;
  643. case 9:
  644. sample_rate = SAMPLING_RATE_352P8KHZ;
  645. break;
  646. case 10:
  647. sample_rate = SAMPLING_RATE_384KHZ;
  648. break;
  649. default:
  650. sample_rate = SAMPLING_RATE_48KHZ;
  651. break;
  652. }
  653. return sample_rate;
  654. }
  655. static int slim_get_bit_format_val(int bit_format)
  656. {
  657. int val = 0;
  658. switch (bit_format) {
  659. case SNDRV_PCM_FORMAT_S32_LE:
  660. val = 3;
  661. break;
  662. case SNDRV_PCM_FORMAT_S24_3LE:
  663. val = 2;
  664. break;
  665. case SNDRV_PCM_FORMAT_S24_LE:
  666. val = 1;
  667. break;
  668. case SNDRV_PCM_FORMAT_S16_LE:
  669. default:
  670. val = 0;
  671. break;
  672. }
  673. return val;
  674. }
  675. static int slim_get_bit_format(int val)
  676. {
  677. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  678. switch (val) {
  679. case 0:
  680. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  681. break;
  682. case 1:
  683. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  684. break;
  685. case 2:
  686. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  687. break;
  688. case 3:
  689. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  690. break;
  691. default:
  692. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  693. break;
  694. }
  695. return bit_fmt;
  696. }
  697. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  698. {
  699. int port_id = 0;
  700. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  701. port_id = SLIM_RX_0;
  702. } else if (strnstr(kcontrol->id.name,
  703. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  704. port_id = SLIM_RX_2;
  705. } else if (strnstr(kcontrol->id.name,
  706. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  707. port_id = SLIM_RX_5;
  708. } else if (strnstr(kcontrol->id.name,
  709. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  710. port_id = SLIM_RX_6;
  711. } else if (strnstr(kcontrol->id.name,
  712. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  713. port_id = SLIM_TX_0;
  714. } else if (strnstr(kcontrol->id.name,
  715. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  716. port_id = SLIM_TX_1;
  717. } else {
  718. pr_err("%s: unsupported channel: %s",
  719. __func__, kcontrol->id.name);
  720. return -EINVAL;
  721. }
  722. return port_id;
  723. }
  724. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  725. struct snd_ctl_elem_value *ucontrol)
  726. {
  727. int ch_num = slim_get_port_idx(kcontrol);
  728. if (ch_num < 0)
  729. return ch_num;
  730. ucontrol->value.enumerated.item[0] =
  731. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  732. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  733. ch_num, slim_rx_cfg[ch_num].sample_rate,
  734. ucontrol->value.enumerated.item[0]);
  735. return 0;
  736. }
  737. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  738. struct snd_ctl_elem_value *ucontrol)
  739. {
  740. int ch_num = slim_get_port_idx(kcontrol);
  741. if (ch_num < 0)
  742. return ch_num;
  743. slim_rx_cfg[ch_num].sample_rate =
  744. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  745. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  746. ch_num, slim_rx_cfg[ch_num].sample_rate,
  747. ucontrol->value.enumerated.item[0]);
  748. return 0;
  749. }
  750. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  751. struct snd_ctl_elem_value *ucontrol)
  752. {
  753. int ch_num = slim_get_port_idx(kcontrol);
  754. if (ch_num < 0)
  755. return ch_num;
  756. ucontrol->value.enumerated.item[0] =
  757. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  758. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  759. ch_num, slim_tx_cfg[ch_num].sample_rate,
  760. ucontrol->value.enumerated.item[0]);
  761. return 0;
  762. }
  763. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  764. struct snd_ctl_elem_value *ucontrol)
  765. {
  766. int sample_rate = 0;
  767. int ch_num = slim_get_port_idx(kcontrol);
  768. if (ch_num < 0)
  769. return ch_num;
  770. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  771. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  772. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  773. __func__, sample_rate);
  774. return -EINVAL;
  775. }
  776. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  777. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  778. ch_num, slim_tx_cfg[ch_num].sample_rate,
  779. ucontrol->value.enumerated.item[0]);
  780. return 0;
  781. }
  782. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  783. struct snd_ctl_elem_value *ucontrol)
  784. {
  785. int ch_num = slim_get_port_idx(kcontrol);
  786. if (ch_num < 0)
  787. return ch_num;
  788. ucontrol->value.enumerated.item[0] =
  789. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  790. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  791. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  792. ucontrol->value.enumerated.item[0]);
  793. return 0;
  794. }
  795. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  796. struct snd_ctl_elem_value *ucontrol)
  797. {
  798. int ch_num = slim_get_port_idx(kcontrol);
  799. if (ch_num < 0)
  800. return ch_num;
  801. slim_rx_cfg[ch_num].bit_format =
  802. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  803. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  804. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  805. ucontrol->value.enumerated.item[0]);
  806. return 0;
  807. }
  808. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  809. struct snd_ctl_elem_value *ucontrol)
  810. {
  811. int ch_num = slim_get_port_idx(kcontrol);
  812. if (ch_num < 0)
  813. return ch_num;
  814. ucontrol->value.enumerated.item[0] =
  815. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  816. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  817. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  818. ucontrol->value.enumerated.item[0]);
  819. return 0;
  820. }
  821. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  822. struct snd_ctl_elem_value *ucontrol)
  823. {
  824. int ch_num = slim_get_port_idx(kcontrol);
  825. if (ch_num < 0)
  826. return ch_num;
  827. slim_tx_cfg[ch_num].bit_format =
  828. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  829. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  830. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  831. ucontrol->value.enumerated.item[0]);
  832. return 0;
  833. }
  834. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  835. struct snd_ctl_elem_value *ucontrol)
  836. {
  837. int ch_num = slim_get_port_idx(kcontrol);
  838. if (ch_num < 0)
  839. return ch_num;
  840. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  841. ch_num, slim_rx_cfg[ch_num].channels);
  842. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  843. return 0;
  844. }
  845. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  846. struct snd_ctl_elem_value *ucontrol)
  847. {
  848. int ch_num = slim_get_port_idx(kcontrol);
  849. if (ch_num < 0)
  850. return ch_num;
  851. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  852. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  853. ch_num, slim_rx_cfg[ch_num].channels);
  854. return 1;
  855. }
  856. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  857. struct snd_ctl_elem_value *ucontrol)
  858. {
  859. int ch_num = slim_get_port_idx(kcontrol);
  860. if (ch_num < 0)
  861. return ch_num;
  862. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  863. ch_num, slim_tx_cfg[ch_num].channels);
  864. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  865. return 0;
  866. }
  867. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  868. struct snd_ctl_elem_value *ucontrol)
  869. {
  870. int ch_num = slim_get_port_idx(kcontrol);
  871. if (ch_num < 0)
  872. return ch_num;
  873. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  874. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  875. ch_num, slim_tx_cfg[ch_num].channels);
  876. return 1;
  877. }
  878. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  879. struct snd_ctl_elem_value *ucontrol)
  880. {
  881. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  882. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  883. ucontrol->value.integer.value[0]);
  884. return 0;
  885. }
  886. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  887. struct snd_ctl_elem_value *ucontrol)
  888. {
  889. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  890. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  891. return 1;
  892. }
  893. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  894. struct snd_ctl_elem_value *ucontrol)
  895. {
  896. /*
  897. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  898. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  899. * value.
  900. */
  901. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  902. case SAMPLING_RATE_96KHZ:
  903. ucontrol->value.integer.value[0] = 5;
  904. break;
  905. case SAMPLING_RATE_88P2KHZ:
  906. ucontrol->value.integer.value[0] = 4;
  907. break;
  908. case SAMPLING_RATE_48KHZ:
  909. ucontrol->value.integer.value[0] = 3;
  910. break;
  911. case SAMPLING_RATE_44P1KHZ:
  912. ucontrol->value.integer.value[0] = 2;
  913. break;
  914. case SAMPLING_RATE_16KHZ:
  915. ucontrol->value.integer.value[0] = 1;
  916. break;
  917. case SAMPLING_RATE_8KHZ:
  918. default:
  919. ucontrol->value.integer.value[0] = 0;
  920. break;
  921. }
  922. pr_debug("%s: sample rate = %d", __func__,
  923. slim_rx_cfg[SLIM_RX_7].sample_rate);
  924. return 0;
  925. }
  926. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  927. struct snd_ctl_elem_value *ucontrol)
  928. {
  929. switch (ucontrol->value.integer.value[0]) {
  930. case 1:
  931. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  932. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  933. break;
  934. case 2:
  935. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  936. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  937. break;
  938. case 3:
  939. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  940. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  941. break;
  942. case 4:
  943. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  944. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  945. break;
  946. case 5:
  947. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  948. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  949. break;
  950. case 0:
  951. default:
  952. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  953. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  954. break;
  955. }
  956. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  957. __func__,
  958. slim_rx_cfg[SLIM_RX_7].sample_rate,
  959. slim_tx_cfg[SLIM_TX_7].sample_rate,
  960. ucontrol->value.enumerated.item[0]);
  961. return 0;
  962. }
  963. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  964. {
  965. int idx = 0;
  966. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  967. sizeof("WSA_CDC_DMA_RX_0")))
  968. idx = WSA_CDC_DMA_RX_0;
  969. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  970. sizeof("WSA_CDC_DMA_RX_0")))
  971. idx = WSA_CDC_DMA_RX_1;
  972. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  973. sizeof("WSA_CDC_DMA_TX_0")))
  974. idx = WSA_CDC_DMA_TX_0;
  975. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  976. sizeof("WSA_CDC_DMA_TX_1")))
  977. idx = WSA_CDC_DMA_TX_1;
  978. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  979. sizeof("WSA_CDC_DMA_TX_2")))
  980. idx = WSA_CDC_DMA_TX_2;
  981. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  982. sizeof("VA_CDC_DMA_TX_0")))
  983. idx = VA_CDC_DMA_TX_0;
  984. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  985. sizeof("VA_CDC_DMA_TX_1")))
  986. idx = VA_CDC_DMA_TX_1;
  987. else {
  988. pr_err("%s: unsupported port: %s\n",
  989. __func__, kcontrol->id.name);
  990. return -EINVAL;
  991. }
  992. return idx;
  993. }
  994. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  995. struct snd_ctl_elem_value *ucontrol)
  996. {
  997. int ch_num = cdc_dma_get_port_idx(kcontrol);
  998. if (ch_num < 0)
  999. return ch_num;
  1000. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1001. cdc_dma_rx_cfg[ch_num].channels - 1);
  1002. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1003. return 0;
  1004. }
  1005. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1006. struct snd_ctl_elem_value *ucontrol)
  1007. {
  1008. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1009. if (ch_num < 0)
  1010. return ch_num;
  1011. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1012. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1013. cdc_dma_rx_cfg[ch_num].channels);
  1014. return 1;
  1015. }
  1016. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1017. struct snd_ctl_elem_value *ucontrol)
  1018. {
  1019. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1020. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1021. case SNDRV_PCM_FORMAT_S32_LE:
  1022. ucontrol->value.integer.value[0] = 3;
  1023. break;
  1024. case SNDRV_PCM_FORMAT_S24_3LE:
  1025. ucontrol->value.integer.value[0] = 2;
  1026. break;
  1027. case SNDRV_PCM_FORMAT_S24_LE:
  1028. ucontrol->value.integer.value[0] = 1;
  1029. break;
  1030. case SNDRV_PCM_FORMAT_S16_LE:
  1031. default:
  1032. ucontrol->value.integer.value[0] = 0;
  1033. break;
  1034. }
  1035. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1036. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1037. ucontrol->value.integer.value[0]);
  1038. return 0;
  1039. }
  1040. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1041. struct snd_ctl_elem_value *ucontrol)
  1042. {
  1043. int rc = 0;
  1044. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1045. switch (ucontrol->value.integer.value[0]) {
  1046. case 3:
  1047. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1048. break;
  1049. case 2:
  1050. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1051. break;
  1052. case 1:
  1053. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1054. break;
  1055. case 0:
  1056. default:
  1057. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1058. break;
  1059. }
  1060. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1061. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1062. ucontrol->value.integer.value[0]);
  1063. return rc;
  1064. }
  1065. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1066. {
  1067. int sample_rate_val = 0;
  1068. switch (sample_rate) {
  1069. case SAMPLING_RATE_8KHZ:
  1070. sample_rate_val = 0;
  1071. break;
  1072. case SAMPLING_RATE_16KHZ:
  1073. sample_rate_val = 1;
  1074. break;
  1075. case SAMPLING_RATE_32KHZ:
  1076. sample_rate_val = 2;
  1077. break;
  1078. case SAMPLING_RATE_44P1KHZ:
  1079. sample_rate_val = 3;
  1080. break;
  1081. case SAMPLING_RATE_48KHZ:
  1082. sample_rate_val = 4;
  1083. break;
  1084. case SAMPLING_RATE_88P2KHZ:
  1085. sample_rate_val = 5;
  1086. break;
  1087. case SAMPLING_RATE_96KHZ:
  1088. sample_rate_val = 6;
  1089. break;
  1090. case SAMPLING_RATE_176P4KHZ:
  1091. sample_rate_val = 7;
  1092. break;
  1093. case SAMPLING_RATE_192KHZ:
  1094. sample_rate_val = 8;
  1095. break;
  1096. case SAMPLING_RATE_352P8KHZ:
  1097. sample_rate_val = 9;
  1098. break;
  1099. case SAMPLING_RATE_384KHZ:
  1100. sample_rate_val = 10;
  1101. break;
  1102. default:
  1103. sample_rate_val = 4;
  1104. break;
  1105. }
  1106. return sample_rate_val;
  1107. }
  1108. static int cdc_dma_get_sample_rate(int value)
  1109. {
  1110. int sample_rate = 0;
  1111. switch (value) {
  1112. case 0:
  1113. sample_rate = SAMPLING_RATE_8KHZ;
  1114. break;
  1115. case 1:
  1116. sample_rate = SAMPLING_RATE_16KHZ;
  1117. break;
  1118. case 2:
  1119. sample_rate = SAMPLING_RATE_32KHZ;
  1120. break;
  1121. case 3:
  1122. sample_rate = SAMPLING_RATE_44P1KHZ;
  1123. break;
  1124. case 4:
  1125. sample_rate = SAMPLING_RATE_48KHZ;
  1126. break;
  1127. case 5:
  1128. sample_rate = SAMPLING_RATE_88P2KHZ;
  1129. break;
  1130. case 6:
  1131. sample_rate = SAMPLING_RATE_96KHZ;
  1132. break;
  1133. case 7:
  1134. sample_rate = SAMPLING_RATE_176P4KHZ;
  1135. break;
  1136. case 8:
  1137. sample_rate = SAMPLING_RATE_192KHZ;
  1138. break;
  1139. case 9:
  1140. sample_rate = SAMPLING_RATE_352P8KHZ;
  1141. break;
  1142. case 10:
  1143. sample_rate = SAMPLING_RATE_384KHZ;
  1144. break;
  1145. default:
  1146. sample_rate = SAMPLING_RATE_48KHZ;
  1147. break;
  1148. }
  1149. return sample_rate;
  1150. }
  1151. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1152. struct snd_ctl_elem_value *ucontrol)
  1153. {
  1154. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1155. if (ch_num < 0)
  1156. return ch_num;
  1157. ucontrol->value.enumerated.item[0] =
  1158. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1159. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1160. cdc_dma_rx_cfg[ch_num].sample_rate);
  1161. return 0;
  1162. }
  1163. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1164. struct snd_ctl_elem_value *ucontrol)
  1165. {
  1166. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1167. if (ch_num < 0)
  1168. return ch_num;
  1169. cdc_dma_rx_cfg[ch_num].sample_rate =
  1170. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1171. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1172. __func__, ucontrol->value.enumerated.item[0],
  1173. cdc_dma_rx_cfg[ch_num].sample_rate);
  1174. return 0;
  1175. }
  1176. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1177. struct snd_ctl_elem_value *ucontrol)
  1178. {
  1179. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1180. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1181. cdc_dma_tx_cfg[ch_num].channels);
  1182. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1183. return 0;
  1184. }
  1185. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1186. struct snd_ctl_elem_value *ucontrol)
  1187. {
  1188. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1189. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1190. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1191. cdc_dma_tx_cfg[ch_num].channels);
  1192. return 1;
  1193. }
  1194. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1195. struct snd_ctl_elem_value *ucontrol)
  1196. {
  1197. int sample_rate_val;
  1198. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1199. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1200. case SAMPLING_RATE_384KHZ:
  1201. sample_rate_val = 12;
  1202. break;
  1203. case SAMPLING_RATE_352P8KHZ:
  1204. sample_rate_val = 11;
  1205. break;
  1206. case SAMPLING_RATE_192KHZ:
  1207. sample_rate_val = 10;
  1208. break;
  1209. case SAMPLING_RATE_176P4KHZ:
  1210. sample_rate_val = 9;
  1211. break;
  1212. case SAMPLING_RATE_96KHZ:
  1213. sample_rate_val = 8;
  1214. break;
  1215. case SAMPLING_RATE_88P2KHZ:
  1216. sample_rate_val = 7;
  1217. break;
  1218. case SAMPLING_RATE_48KHZ:
  1219. sample_rate_val = 6;
  1220. break;
  1221. case SAMPLING_RATE_44P1KHZ:
  1222. sample_rate_val = 5;
  1223. break;
  1224. case SAMPLING_RATE_32KHZ:
  1225. sample_rate_val = 4;
  1226. break;
  1227. case SAMPLING_RATE_22P05KHZ:
  1228. sample_rate_val = 3;
  1229. break;
  1230. case SAMPLING_RATE_16KHZ:
  1231. sample_rate_val = 2;
  1232. break;
  1233. case SAMPLING_RATE_11P025KHZ:
  1234. sample_rate_val = 1;
  1235. break;
  1236. case SAMPLING_RATE_8KHZ:
  1237. sample_rate_val = 0;
  1238. break;
  1239. default:
  1240. sample_rate_val = 6;
  1241. break;
  1242. }
  1243. ucontrol->value.integer.value[0] = sample_rate_val;
  1244. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1245. cdc_dma_tx_cfg[ch_num].sample_rate);
  1246. return 0;
  1247. }
  1248. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1249. struct snd_ctl_elem_value *ucontrol)
  1250. {
  1251. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1252. switch (ucontrol->value.integer.value[0]) {
  1253. case 12:
  1254. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1255. break;
  1256. case 11:
  1257. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1258. break;
  1259. case 10:
  1260. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1261. break;
  1262. case 9:
  1263. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1264. break;
  1265. case 8:
  1266. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1267. break;
  1268. case 7:
  1269. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1270. break;
  1271. case 6:
  1272. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1273. break;
  1274. case 5:
  1275. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1276. break;
  1277. case 4:
  1278. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1279. break;
  1280. case 3:
  1281. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1282. break;
  1283. case 2:
  1284. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1285. break;
  1286. case 1:
  1287. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1288. break;
  1289. case 0:
  1290. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1291. break;
  1292. default:
  1293. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1294. break;
  1295. }
  1296. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1297. __func__, ucontrol->value.integer.value[0],
  1298. cdc_dma_tx_cfg[ch_num].sample_rate);
  1299. return 0;
  1300. }
  1301. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1302. struct snd_ctl_elem_value *ucontrol)
  1303. {
  1304. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1305. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1306. case SNDRV_PCM_FORMAT_S32_LE:
  1307. ucontrol->value.integer.value[0] = 3;
  1308. break;
  1309. case SNDRV_PCM_FORMAT_S24_3LE:
  1310. ucontrol->value.integer.value[0] = 2;
  1311. break;
  1312. case SNDRV_PCM_FORMAT_S24_LE:
  1313. ucontrol->value.integer.value[0] = 1;
  1314. break;
  1315. case SNDRV_PCM_FORMAT_S16_LE:
  1316. default:
  1317. ucontrol->value.integer.value[0] = 0;
  1318. break;
  1319. }
  1320. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1321. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1322. ucontrol->value.integer.value[0]);
  1323. return 0;
  1324. }
  1325. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1326. struct snd_ctl_elem_value *ucontrol)
  1327. {
  1328. int rc = 0;
  1329. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1330. switch (ucontrol->value.integer.value[0]) {
  1331. case 3:
  1332. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1333. break;
  1334. case 2:
  1335. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1336. break;
  1337. case 1:
  1338. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1339. break;
  1340. case 0:
  1341. default:
  1342. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1343. break;
  1344. }
  1345. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1346. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1347. ucontrol->value.integer.value[0]);
  1348. return rc;
  1349. }
  1350. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1351. struct snd_ctl_elem_value *ucontrol)
  1352. {
  1353. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1354. usb_rx_cfg.channels);
  1355. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1356. return 0;
  1357. }
  1358. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1359. struct snd_ctl_elem_value *ucontrol)
  1360. {
  1361. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1362. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1363. return 1;
  1364. }
  1365. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1366. struct snd_ctl_elem_value *ucontrol)
  1367. {
  1368. int sample_rate_val;
  1369. switch (usb_rx_cfg.sample_rate) {
  1370. case SAMPLING_RATE_384KHZ:
  1371. sample_rate_val = 12;
  1372. break;
  1373. case SAMPLING_RATE_352P8KHZ:
  1374. sample_rate_val = 11;
  1375. break;
  1376. case SAMPLING_RATE_192KHZ:
  1377. sample_rate_val = 10;
  1378. break;
  1379. case SAMPLING_RATE_176P4KHZ:
  1380. sample_rate_val = 9;
  1381. break;
  1382. case SAMPLING_RATE_96KHZ:
  1383. sample_rate_val = 8;
  1384. break;
  1385. case SAMPLING_RATE_88P2KHZ:
  1386. sample_rate_val = 7;
  1387. break;
  1388. case SAMPLING_RATE_48KHZ:
  1389. sample_rate_val = 6;
  1390. break;
  1391. case SAMPLING_RATE_44P1KHZ:
  1392. sample_rate_val = 5;
  1393. break;
  1394. case SAMPLING_RATE_32KHZ:
  1395. sample_rate_val = 4;
  1396. break;
  1397. case SAMPLING_RATE_22P05KHZ:
  1398. sample_rate_val = 3;
  1399. break;
  1400. case SAMPLING_RATE_16KHZ:
  1401. sample_rate_val = 2;
  1402. break;
  1403. case SAMPLING_RATE_11P025KHZ:
  1404. sample_rate_val = 1;
  1405. break;
  1406. case SAMPLING_RATE_8KHZ:
  1407. default:
  1408. sample_rate_val = 0;
  1409. break;
  1410. }
  1411. ucontrol->value.integer.value[0] = sample_rate_val;
  1412. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1413. usb_rx_cfg.sample_rate);
  1414. return 0;
  1415. }
  1416. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1417. struct snd_ctl_elem_value *ucontrol)
  1418. {
  1419. switch (ucontrol->value.integer.value[0]) {
  1420. case 12:
  1421. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1422. break;
  1423. case 11:
  1424. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1425. break;
  1426. case 10:
  1427. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1428. break;
  1429. case 9:
  1430. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1431. break;
  1432. case 8:
  1433. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1434. break;
  1435. case 7:
  1436. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1437. break;
  1438. case 6:
  1439. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1440. break;
  1441. case 5:
  1442. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1443. break;
  1444. case 4:
  1445. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1446. break;
  1447. case 3:
  1448. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1449. break;
  1450. case 2:
  1451. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1452. break;
  1453. case 1:
  1454. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1455. break;
  1456. case 0:
  1457. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1458. break;
  1459. default:
  1460. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1461. break;
  1462. }
  1463. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1464. __func__, ucontrol->value.integer.value[0],
  1465. usb_rx_cfg.sample_rate);
  1466. return 0;
  1467. }
  1468. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1469. struct snd_ctl_elem_value *ucontrol)
  1470. {
  1471. switch (usb_rx_cfg.bit_format) {
  1472. case SNDRV_PCM_FORMAT_S32_LE:
  1473. ucontrol->value.integer.value[0] = 3;
  1474. break;
  1475. case SNDRV_PCM_FORMAT_S24_3LE:
  1476. ucontrol->value.integer.value[0] = 2;
  1477. break;
  1478. case SNDRV_PCM_FORMAT_S24_LE:
  1479. ucontrol->value.integer.value[0] = 1;
  1480. break;
  1481. case SNDRV_PCM_FORMAT_S16_LE:
  1482. default:
  1483. ucontrol->value.integer.value[0] = 0;
  1484. break;
  1485. }
  1486. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1487. __func__, usb_rx_cfg.bit_format,
  1488. ucontrol->value.integer.value[0]);
  1489. return 0;
  1490. }
  1491. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1492. struct snd_ctl_elem_value *ucontrol)
  1493. {
  1494. int rc = 0;
  1495. switch (ucontrol->value.integer.value[0]) {
  1496. case 3:
  1497. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1498. break;
  1499. case 2:
  1500. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1501. break;
  1502. case 1:
  1503. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1504. break;
  1505. case 0:
  1506. default:
  1507. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1508. break;
  1509. }
  1510. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1511. __func__, usb_rx_cfg.bit_format,
  1512. ucontrol->value.integer.value[0]);
  1513. return rc;
  1514. }
  1515. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1516. struct snd_ctl_elem_value *ucontrol)
  1517. {
  1518. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1519. usb_tx_cfg.channels);
  1520. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1521. return 0;
  1522. }
  1523. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1524. struct snd_ctl_elem_value *ucontrol)
  1525. {
  1526. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1527. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1528. return 1;
  1529. }
  1530. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1531. struct snd_ctl_elem_value *ucontrol)
  1532. {
  1533. int sample_rate_val;
  1534. switch (usb_tx_cfg.sample_rate) {
  1535. case SAMPLING_RATE_384KHZ:
  1536. sample_rate_val = 12;
  1537. break;
  1538. case SAMPLING_RATE_352P8KHZ:
  1539. sample_rate_val = 11;
  1540. break;
  1541. case SAMPLING_RATE_192KHZ:
  1542. sample_rate_val = 10;
  1543. break;
  1544. case SAMPLING_RATE_176P4KHZ:
  1545. sample_rate_val = 9;
  1546. break;
  1547. case SAMPLING_RATE_96KHZ:
  1548. sample_rate_val = 8;
  1549. break;
  1550. case SAMPLING_RATE_88P2KHZ:
  1551. sample_rate_val = 7;
  1552. break;
  1553. case SAMPLING_RATE_48KHZ:
  1554. sample_rate_val = 6;
  1555. break;
  1556. case SAMPLING_RATE_44P1KHZ:
  1557. sample_rate_val = 5;
  1558. break;
  1559. case SAMPLING_RATE_32KHZ:
  1560. sample_rate_val = 4;
  1561. break;
  1562. case SAMPLING_RATE_22P05KHZ:
  1563. sample_rate_val = 3;
  1564. break;
  1565. case SAMPLING_RATE_16KHZ:
  1566. sample_rate_val = 2;
  1567. break;
  1568. case SAMPLING_RATE_11P025KHZ:
  1569. sample_rate_val = 1;
  1570. break;
  1571. case SAMPLING_RATE_8KHZ:
  1572. sample_rate_val = 0;
  1573. break;
  1574. default:
  1575. sample_rate_val = 6;
  1576. break;
  1577. }
  1578. ucontrol->value.integer.value[0] = sample_rate_val;
  1579. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1580. usb_tx_cfg.sample_rate);
  1581. return 0;
  1582. }
  1583. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1584. struct snd_ctl_elem_value *ucontrol)
  1585. {
  1586. switch (ucontrol->value.integer.value[0]) {
  1587. case 12:
  1588. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1589. break;
  1590. case 11:
  1591. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1592. break;
  1593. case 10:
  1594. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1595. break;
  1596. case 9:
  1597. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1598. break;
  1599. case 8:
  1600. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1601. break;
  1602. case 7:
  1603. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1604. break;
  1605. case 6:
  1606. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1607. break;
  1608. case 5:
  1609. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1610. break;
  1611. case 4:
  1612. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1613. break;
  1614. case 3:
  1615. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1616. break;
  1617. case 2:
  1618. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1619. break;
  1620. case 1:
  1621. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1622. break;
  1623. case 0:
  1624. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1625. break;
  1626. default:
  1627. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1628. break;
  1629. }
  1630. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1631. __func__, ucontrol->value.integer.value[0],
  1632. usb_tx_cfg.sample_rate);
  1633. return 0;
  1634. }
  1635. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1636. struct snd_ctl_elem_value *ucontrol)
  1637. {
  1638. switch (usb_tx_cfg.bit_format) {
  1639. case SNDRV_PCM_FORMAT_S32_LE:
  1640. ucontrol->value.integer.value[0] = 3;
  1641. break;
  1642. case SNDRV_PCM_FORMAT_S24_3LE:
  1643. ucontrol->value.integer.value[0] = 2;
  1644. break;
  1645. case SNDRV_PCM_FORMAT_S24_LE:
  1646. ucontrol->value.integer.value[0] = 1;
  1647. break;
  1648. case SNDRV_PCM_FORMAT_S16_LE:
  1649. default:
  1650. ucontrol->value.integer.value[0] = 0;
  1651. break;
  1652. }
  1653. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1654. __func__, usb_tx_cfg.bit_format,
  1655. ucontrol->value.integer.value[0]);
  1656. return 0;
  1657. }
  1658. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1659. struct snd_ctl_elem_value *ucontrol)
  1660. {
  1661. int rc = 0;
  1662. switch (ucontrol->value.integer.value[0]) {
  1663. case 3:
  1664. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1665. break;
  1666. case 2:
  1667. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1668. break;
  1669. case 1:
  1670. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1671. break;
  1672. case 0:
  1673. default:
  1674. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1675. break;
  1676. }
  1677. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1678. __func__, usb_tx_cfg.bit_format,
  1679. ucontrol->value.integer.value[0]);
  1680. return rc;
  1681. }
  1682. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1683. struct snd_ctl_elem_value *ucontrol)
  1684. {
  1685. pr_debug("%s: proxy_rx channels = %d\n",
  1686. __func__, proxy_rx_cfg.channels);
  1687. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1688. return 0;
  1689. }
  1690. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1691. struct snd_ctl_elem_value *ucontrol)
  1692. {
  1693. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1694. pr_debug("%s: proxy_rx channels = %d\n",
  1695. __func__, proxy_rx_cfg.channels);
  1696. return 1;
  1697. }
  1698. static int tdm_get_sample_rate(int value)
  1699. {
  1700. int sample_rate = 0;
  1701. switch (value) {
  1702. case 0:
  1703. sample_rate = SAMPLING_RATE_8KHZ;
  1704. break;
  1705. case 1:
  1706. sample_rate = SAMPLING_RATE_16KHZ;
  1707. break;
  1708. case 2:
  1709. sample_rate = SAMPLING_RATE_32KHZ;
  1710. break;
  1711. case 3:
  1712. sample_rate = SAMPLING_RATE_48KHZ;
  1713. break;
  1714. case 4:
  1715. sample_rate = SAMPLING_RATE_176P4KHZ;
  1716. break;
  1717. case 5:
  1718. sample_rate = SAMPLING_RATE_352P8KHZ;
  1719. break;
  1720. default:
  1721. sample_rate = SAMPLING_RATE_48KHZ;
  1722. break;
  1723. }
  1724. return sample_rate;
  1725. }
  1726. static int aux_pcm_get_sample_rate(int value)
  1727. {
  1728. int sample_rate;
  1729. switch (value) {
  1730. case 1:
  1731. sample_rate = SAMPLING_RATE_16KHZ;
  1732. break;
  1733. case 0:
  1734. default:
  1735. sample_rate = SAMPLING_RATE_8KHZ;
  1736. break;
  1737. }
  1738. return sample_rate;
  1739. }
  1740. static int tdm_get_sample_rate_val(int sample_rate)
  1741. {
  1742. int sample_rate_val = 0;
  1743. switch (sample_rate) {
  1744. case SAMPLING_RATE_8KHZ:
  1745. sample_rate_val = 0;
  1746. break;
  1747. case SAMPLING_RATE_16KHZ:
  1748. sample_rate_val = 1;
  1749. break;
  1750. case SAMPLING_RATE_32KHZ:
  1751. sample_rate_val = 2;
  1752. break;
  1753. case SAMPLING_RATE_48KHZ:
  1754. sample_rate_val = 3;
  1755. break;
  1756. case SAMPLING_RATE_176P4KHZ:
  1757. sample_rate_val = 4;
  1758. break;
  1759. case SAMPLING_RATE_352P8KHZ:
  1760. sample_rate_val = 5;
  1761. break;
  1762. default:
  1763. sample_rate_val = 3;
  1764. break;
  1765. }
  1766. return sample_rate_val;
  1767. }
  1768. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1769. {
  1770. int sample_rate_val;
  1771. switch (sample_rate) {
  1772. case SAMPLING_RATE_16KHZ:
  1773. sample_rate_val = 1;
  1774. break;
  1775. case SAMPLING_RATE_8KHZ:
  1776. default:
  1777. sample_rate_val = 0;
  1778. break;
  1779. }
  1780. return sample_rate_val;
  1781. }
  1782. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1783. struct tdm_port *port)
  1784. {
  1785. if (port) {
  1786. if (strnstr(kcontrol->id.name, "PRI",
  1787. sizeof(kcontrol->id.name))) {
  1788. port->mode = TDM_PRI;
  1789. } else if (strnstr(kcontrol->id.name, "SEC",
  1790. sizeof(kcontrol->id.name))) {
  1791. port->mode = TDM_SEC;
  1792. } else if (strnstr(kcontrol->id.name, "TERT",
  1793. sizeof(kcontrol->id.name))) {
  1794. port->mode = TDM_TERT;
  1795. } else if (strnstr(kcontrol->id.name, "QUAT",
  1796. sizeof(kcontrol->id.name))) {
  1797. port->mode = TDM_QUAT;
  1798. } else if (strnstr(kcontrol->id.name, "QUIN",
  1799. sizeof(kcontrol->id.name))) {
  1800. port->mode = TDM_QUIN;
  1801. } else {
  1802. pr_err("%s: unsupported mode in: %s",
  1803. __func__, kcontrol->id.name);
  1804. return -EINVAL;
  1805. }
  1806. if (strnstr(kcontrol->id.name, "RX_0",
  1807. sizeof(kcontrol->id.name)) ||
  1808. strnstr(kcontrol->id.name, "TX_0",
  1809. sizeof(kcontrol->id.name))) {
  1810. port->channel = TDM_0;
  1811. } else if (strnstr(kcontrol->id.name, "RX_1",
  1812. sizeof(kcontrol->id.name)) ||
  1813. strnstr(kcontrol->id.name, "TX_1",
  1814. sizeof(kcontrol->id.name))) {
  1815. port->channel = TDM_1;
  1816. } else if (strnstr(kcontrol->id.name, "RX_2",
  1817. sizeof(kcontrol->id.name)) ||
  1818. strnstr(kcontrol->id.name, "TX_2",
  1819. sizeof(kcontrol->id.name))) {
  1820. port->channel = TDM_2;
  1821. } else if (strnstr(kcontrol->id.name, "RX_3",
  1822. sizeof(kcontrol->id.name)) ||
  1823. strnstr(kcontrol->id.name, "TX_3",
  1824. sizeof(kcontrol->id.name))) {
  1825. port->channel = TDM_3;
  1826. } else if (strnstr(kcontrol->id.name, "RX_4",
  1827. sizeof(kcontrol->id.name)) ||
  1828. strnstr(kcontrol->id.name, "TX_4",
  1829. sizeof(kcontrol->id.name))) {
  1830. port->channel = TDM_4;
  1831. } else if (strnstr(kcontrol->id.name, "RX_5",
  1832. sizeof(kcontrol->id.name)) ||
  1833. strnstr(kcontrol->id.name, "TX_5",
  1834. sizeof(kcontrol->id.name))) {
  1835. port->channel = TDM_5;
  1836. } else if (strnstr(kcontrol->id.name, "RX_6",
  1837. sizeof(kcontrol->id.name)) ||
  1838. strnstr(kcontrol->id.name, "TX_6",
  1839. sizeof(kcontrol->id.name))) {
  1840. port->channel = TDM_6;
  1841. } else if (strnstr(kcontrol->id.name, "RX_7",
  1842. sizeof(kcontrol->id.name)) ||
  1843. strnstr(kcontrol->id.name, "TX_7",
  1844. sizeof(kcontrol->id.name))) {
  1845. port->channel = TDM_7;
  1846. } else {
  1847. pr_err("%s: unsupported channel in: %s",
  1848. __func__, kcontrol->id.name);
  1849. return -EINVAL;
  1850. }
  1851. } else
  1852. return -EINVAL;
  1853. return 0;
  1854. }
  1855. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1856. struct snd_ctl_elem_value *ucontrol)
  1857. {
  1858. struct tdm_port port;
  1859. int ret = tdm_get_port_idx(kcontrol, &port);
  1860. if (ret) {
  1861. pr_err("%s: unsupported control: %s",
  1862. __func__, kcontrol->id.name);
  1863. } else {
  1864. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1865. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1866. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1867. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1868. ucontrol->value.enumerated.item[0]);
  1869. }
  1870. return ret;
  1871. }
  1872. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1873. struct snd_ctl_elem_value *ucontrol)
  1874. {
  1875. struct tdm_port port;
  1876. int ret = tdm_get_port_idx(kcontrol, &port);
  1877. if (ret) {
  1878. pr_err("%s: unsupported control: %s",
  1879. __func__, kcontrol->id.name);
  1880. } else {
  1881. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1882. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1883. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1884. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1885. ucontrol->value.enumerated.item[0]);
  1886. }
  1887. return ret;
  1888. }
  1889. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1890. struct snd_ctl_elem_value *ucontrol)
  1891. {
  1892. struct tdm_port port;
  1893. int ret = tdm_get_port_idx(kcontrol, &port);
  1894. if (ret) {
  1895. pr_err("%s: unsupported control: %s",
  1896. __func__, kcontrol->id.name);
  1897. } else {
  1898. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1899. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1900. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1901. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1902. ucontrol->value.enumerated.item[0]);
  1903. }
  1904. return ret;
  1905. }
  1906. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1907. struct snd_ctl_elem_value *ucontrol)
  1908. {
  1909. struct tdm_port port;
  1910. int ret = tdm_get_port_idx(kcontrol, &port);
  1911. if (ret) {
  1912. pr_err("%s: unsupported control: %s",
  1913. __func__, kcontrol->id.name);
  1914. } else {
  1915. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1916. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1917. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1918. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1919. ucontrol->value.enumerated.item[0]);
  1920. }
  1921. return ret;
  1922. }
  1923. static int tdm_get_format(int value)
  1924. {
  1925. int format = 0;
  1926. switch (value) {
  1927. case 0:
  1928. format = SNDRV_PCM_FORMAT_S16_LE;
  1929. break;
  1930. case 1:
  1931. format = SNDRV_PCM_FORMAT_S24_LE;
  1932. break;
  1933. case 2:
  1934. format = SNDRV_PCM_FORMAT_S32_LE;
  1935. break;
  1936. default:
  1937. format = SNDRV_PCM_FORMAT_S16_LE;
  1938. break;
  1939. }
  1940. return format;
  1941. }
  1942. static int tdm_get_format_val(int format)
  1943. {
  1944. int value = 0;
  1945. switch (format) {
  1946. case SNDRV_PCM_FORMAT_S16_LE:
  1947. value = 0;
  1948. break;
  1949. case SNDRV_PCM_FORMAT_S24_LE:
  1950. value = 1;
  1951. break;
  1952. case SNDRV_PCM_FORMAT_S32_LE:
  1953. value = 2;
  1954. break;
  1955. default:
  1956. value = 0;
  1957. break;
  1958. }
  1959. return value;
  1960. }
  1961. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1962. struct snd_ctl_elem_value *ucontrol)
  1963. {
  1964. struct tdm_port port;
  1965. int ret = tdm_get_port_idx(kcontrol, &port);
  1966. if (ret) {
  1967. pr_err("%s: unsupported control: %s",
  1968. __func__, kcontrol->id.name);
  1969. } else {
  1970. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1971. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1972. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1973. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1974. ucontrol->value.enumerated.item[0]);
  1975. }
  1976. return ret;
  1977. }
  1978. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1979. struct snd_ctl_elem_value *ucontrol)
  1980. {
  1981. struct tdm_port port;
  1982. int ret = tdm_get_port_idx(kcontrol, &port);
  1983. if (ret) {
  1984. pr_err("%s: unsupported control: %s",
  1985. __func__, kcontrol->id.name);
  1986. } else {
  1987. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1988. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1989. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1990. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1991. ucontrol->value.enumerated.item[0]);
  1992. }
  1993. return ret;
  1994. }
  1995. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1996. struct snd_ctl_elem_value *ucontrol)
  1997. {
  1998. struct tdm_port port;
  1999. int ret = tdm_get_port_idx(kcontrol, &port);
  2000. if (ret) {
  2001. pr_err("%s: unsupported control: %s",
  2002. __func__, kcontrol->id.name);
  2003. } else {
  2004. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2005. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2006. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2007. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2008. ucontrol->value.enumerated.item[0]);
  2009. }
  2010. return ret;
  2011. }
  2012. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2013. struct snd_ctl_elem_value *ucontrol)
  2014. {
  2015. struct tdm_port port;
  2016. int ret = tdm_get_port_idx(kcontrol, &port);
  2017. if (ret) {
  2018. pr_err("%s: unsupported control: %s",
  2019. __func__, kcontrol->id.name);
  2020. } else {
  2021. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2022. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2023. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2024. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2025. ucontrol->value.enumerated.item[0]);
  2026. }
  2027. return ret;
  2028. }
  2029. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2030. struct snd_ctl_elem_value *ucontrol)
  2031. {
  2032. struct tdm_port port;
  2033. int ret = tdm_get_port_idx(kcontrol, &port);
  2034. if (ret) {
  2035. pr_err("%s: unsupported control: %s",
  2036. __func__, kcontrol->id.name);
  2037. } else {
  2038. ucontrol->value.enumerated.item[0] =
  2039. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2040. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2041. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2042. ucontrol->value.enumerated.item[0]);
  2043. }
  2044. return ret;
  2045. }
  2046. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2047. struct snd_ctl_elem_value *ucontrol)
  2048. {
  2049. struct tdm_port port;
  2050. int ret = tdm_get_port_idx(kcontrol, &port);
  2051. if (ret) {
  2052. pr_err("%s: unsupported control: %s",
  2053. __func__, kcontrol->id.name);
  2054. } else {
  2055. tdm_rx_cfg[port.mode][port.channel].channels =
  2056. ucontrol->value.enumerated.item[0] + 1;
  2057. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2058. tdm_rx_cfg[port.mode][port.channel].channels,
  2059. ucontrol->value.enumerated.item[0] + 1);
  2060. }
  2061. return ret;
  2062. }
  2063. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2064. struct snd_ctl_elem_value *ucontrol)
  2065. {
  2066. struct tdm_port port;
  2067. int ret = tdm_get_port_idx(kcontrol, &port);
  2068. if (ret) {
  2069. pr_err("%s: unsupported control: %s",
  2070. __func__, kcontrol->id.name);
  2071. } else {
  2072. ucontrol->value.enumerated.item[0] =
  2073. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2074. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2075. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2076. ucontrol->value.enumerated.item[0]);
  2077. }
  2078. return ret;
  2079. }
  2080. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2081. struct snd_ctl_elem_value *ucontrol)
  2082. {
  2083. struct tdm_port port;
  2084. int ret = tdm_get_port_idx(kcontrol, &port);
  2085. if (ret) {
  2086. pr_err("%s: unsupported control: %s",
  2087. __func__, kcontrol->id.name);
  2088. } else {
  2089. tdm_tx_cfg[port.mode][port.channel].channels =
  2090. ucontrol->value.enumerated.item[0] + 1;
  2091. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2092. tdm_tx_cfg[port.mode][port.channel].channels,
  2093. ucontrol->value.enumerated.item[0] + 1);
  2094. }
  2095. return ret;
  2096. }
  2097. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2098. {
  2099. int idx;
  2100. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2101. sizeof("PRIM_AUX_PCM")))
  2102. idx = PRIM_AUX_PCM;
  2103. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2104. sizeof("SEC_AUX_PCM")))
  2105. idx = SEC_AUX_PCM;
  2106. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2107. sizeof("TERT_AUX_PCM")))
  2108. idx = TERT_AUX_PCM;
  2109. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2110. sizeof("QUAT_AUX_PCM")))
  2111. idx = QUAT_AUX_PCM;
  2112. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2113. sizeof("QUIN_AUX_PCM")))
  2114. idx = QUIN_AUX_PCM;
  2115. else {
  2116. pr_err("%s: unsupported port: %s",
  2117. __func__, kcontrol->id.name);
  2118. idx = -EINVAL;
  2119. }
  2120. return idx;
  2121. }
  2122. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2123. struct snd_ctl_elem_value *ucontrol)
  2124. {
  2125. int idx = aux_pcm_get_port_idx(kcontrol);
  2126. if (idx < 0)
  2127. return idx;
  2128. aux_pcm_rx_cfg[idx].sample_rate =
  2129. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2130. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2131. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2132. ucontrol->value.enumerated.item[0]);
  2133. return 0;
  2134. }
  2135. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2136. struct snd_ctl_elem_value *ucontrol)
  2137. {
  2138. int idx = aux_pcm_get_port_idx(kcontrol);
  2139. if (idx < 0)
  2140. return idx;
  2141. ucontrol->value.enumerated.item[0] =
  2142. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2143. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2144. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2145. ucontrol->value.enumerated.item[0]);
  2146. return 0;
  2147. }
  2148. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2149. struct snd_ctl_elem_value *ucontrol)
  2150. {
  2151. int idx = aux_pcm_get_port_idx(kcontrol);
  2152. if (idx < 0)
  2153. return idx;
  2154. aux_pcm_tx_cfg[idx].sample_rate =
  2155. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2156. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2157. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2158. ucontrol->value.enumerated.item[0]);
  2159. return 0;
  2160. }
  2161. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2162. struct snd_ctl_elem_value *ucontrol)
  2163. {
  2164. int idx = aux_pcm_get_port_idx(kcontrol);
  2165. if (idx < 0)
  2166. return idx;
  2167. ucontrol->value.enumerated.item[0] =
  2168. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2169. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2170. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2171. ucontrol->value.enumerated.item[0]);
  2172. return 0;
  2173. }
  2174. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2175. {
  2176. int idx;
  2177. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2178. sizeof("PRIM_MI2S_RX")))
  2179. idx = PRIM_MI2S;
  2180. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2181. sizeof("SEC_MI2S_RX")))
  2182. idx = SEC_MI2S;
  2183. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2184. sizeof("TERT_MI2S_RX")))
  2185. idx = TERT_MI2S;
  2186. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2187. sizeof("QUAT_MI2S_RX")))
  2188. idx = QUAT_MI2S;
  2189. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2190. sizeof("QUIN_MI2S_RX")))
  2191. idx = QUIN_MI2S;
  2192. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2193. sizeof("PRIM_MI2S_TX")))
  2194. idx = PRIM_MI2S;
  2195. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2196. sizeof("SEC_MI2S_TX")))
  2197. idx = SEC_MI2S;
  2198. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2199. sizeof("TERT_MI2S_TX")))
  2200. idx = TERT_MI2S;
  2201. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2202. sizeof("QUAT_MI2S_TX")))
  2203. idx = QUAT_MI2S;
  2204. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2205. sizeof("QUIN_MI2S_TX")))
  2206. idx = QUIN_MI2S;
  2207. else {
  2208. pr_err("%s: unsupported channel: %s",
  2209. __func__, kcontrol->id.name);
  2210. idx = -EINVAL;
  2211. }
  2212. return idx;
  2213. }
  2214. static int mi2s_get_sample_rate_val(int sample_rate)
  2215. {
  2216. int sample_rate_val;
  2217. switch (sample_rate) {
  2218. case SAMPLING_RATE_8KHZ:
  2219. sample_rate_val = 0;
  2220. break;
  2221. case SAMPLING_RATE_11P025KHZ:
  2222. sample_rate_val = 1;
  2223. break;
  2224. case SAMPLING_RATE_16KHZ:
  2225. sample_rate_val = 2;
  2226. break;
  2227. case SAMPLING_RATE_22P05KHZ:
  2228. sample_rate_val = 3;
  2229. break;
  2230. case SAMPLING_RATE_32KHZ:
  2231. sample_rate_val = 4;
  2232. break;
  2233. case SAMPLING_RATE_44P1KHZ:
  2234. sample_rate_val = 5;
  2235. break;
  2236. case SAMPLING_RATE_48KHZ:
  2237. sample_rate_val = 6;
  2238. break;
  2239. case SAMPLING_RATE_96KHZ:
  2240. sample_rate_val = 7;
  2241. break;
  2242. case SAMPLING_RATE_192KHZ:
  2243. sample_rate_val = 8;
  2244. break;
  2245. default:
  2246. sample_rate_val = 6;
  2247. break;
  2248. }
  2249. return sample_rate_val;
  2250. }
  2251. static int mi2s_get_sample_rate(int value)
  2252. {
  2253. int sample_rate;
  2254. switch (value) {
  2255. case 0:
  2256. sample_rate = SAMPLING_RATE_8KHZ;
  2257. break;
  2258. case 1:
  2259. sample_rate = SAMPLING_RATE_11P025KHZ;
  2260. break;
  2261. case 2:
  2262. sample_rate = SAMPLING_RATE_16KHZ;
  2263. break;
  2264. case 3:
  2265. sample_rate = SAMPLING_RATE_22P05KHZ;
  2266. break;
  2267. case 4:
  2268. sample_rate = SAMPLING_RATE_32KHZ;
  2269. break;
  2270. case 5:
  2271. sample_rate = SAMPLING_RATE_44P1KHZ;
  2272. break;
  2273. case 6:
  2274. sample_rate = SAMPLING_RATE_48KHZ;
  2275. break;
  2276. case 7:
  2277. sample_rate = SAMPLING_RATE_96KHZ;
  2278. break;
  2279. case 8:
  2280. sample_rate = SAMPLING_RATE_192KHZ;
  2281. break;
  2282. default:
  2283. sample_rate = SAMPLING_RATE_48KHZ;
  2284. break;
  2285. }
  2286. return sample_rate;
  2287. }
  2288. static int mi2s_auxpcm_get_format(int value)
  2289. {
  2290. int format;
  2291. switch (value) {
  2292. case 0:
  2293. format = SNDRV_PCM_FORMAT_S16_LE;
  2294. break;
  2295. case 1:
  2296. format = SNDRV_PCM_FORMAT_S24_LE;
  2297. break;
  2298. case 2:
  2299. format = SNDRV_PCM_FORMAT_S24_3LE;
  2300. break;
  2301. case 3:
  2302. format = SNDRV_PCM_FORMAT_S32_LE;
  2303. break;
  2304. default:
  2305. format = SNDRV_PCM_FORMAT_S16_LE;
  2306. break;
  2307. }
  2308. return format;
  2309. }
  2310. static int mi2s_auxpcm_get_format_value(int format)
  2311. {
  2312. int value;
  2313. switch (format) {
  2314. case SNDRV_PCM_FORMAT_S16_LE:
  2315. value = 0;
  2316. break;
  2317. case SNDRV_PCM_FORMAT_S24_LE:
  2318. value = 1;
  2319. break;
  2320. case SNDRV_PCM_FORMAT_S24_3LE:
  2321. value = 2;
  2322. break;
  2323. case SNDRV_PCM_FORMAT_S32_LE:
  2324. value = 3;
  2325. break;
  2326. default:
  2327. value = 0;
  2328. break;
  2329. }
  2330. return value;
  2331. }
  2332. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2333. struct snd_ctl_elem_value *ucontrol)
  2334. {
  2335. int idx = mi2s_get_port_idx(kcontrol);
  2336. if (idx < 0)
  2337. return idx;
  2338. mi2s_rx_cfg[idx].sample_rate =
  2339. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2340. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2341. idx, mi2s_rx_cfg[idx].sample_rate,
  2342. ucontrol->value.enumerated.item[0]);
  2343. return 0;
  2344. }
  2345. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2346. struct snd_ctl_elem_value *ucontrol)
  2347. {
  2348. int idx = mi2s_get_port_idx(kcontrol);
  2349. if (idx < 0)
  2350. return idx;
  2351. ucontrol->value.enumerated.item[0] =
  2352. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2353. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2354. idx, mi2s_rx_cfg[idx].sample_rate,
  2355. ucontrol->value.enumerated.item[0]);
  2356. return 0;
  2357. }
  2358. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2359. struct snd_ctl_elem_value *ucontrol)
  2360. {
  2361. int idx = mi2s_get_port_idx(kcontrol);
  2362. if (idx < 0)
  2363. return idx;
  2364. mi2s_tx_cfg[idx].sample_rate =
  2365. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2366. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2367. idx, mi2s_tx_cfg[idx].sample_rate,
  2368. ucontrol->value.enumerated.item[0]);
  2369. return 0;
  2370. }
  2371. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2372. struct snd_ctl_elem_value *ucontrol)
  2373. {
  2374. int idx = mi2s_get_port_idx(kcontrol);
  2375. if (idx < 0)
  2376. return idx;
  2377. ucontrol->value.enumerated.item[0] =
  2378. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2379. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2380. idx, mi2s_tx_cfg[idx].sample_rate,
  2381. ucontrol->value.enumerated.item[0]);
  2382. return 0;
  2383. }
  2384. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2385. struct snd_ctl_elem_value *ucontrol)
  2386. {
  2387. int idx = mi2s_get_port_idx(kcontrol);
  2388. if (idx < 0)
  2389. return idx;
  2390. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2391. idx, mi2s_rx_cfg[idx].channels);
  2392. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2393. return 0;
  2394. }
  2395. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2396. struct snd_ctl_elem_value *ucontrol)
  2397. {
  2398. int idx = mi2s_get_port_idx(kcontrol);
  2399. if (idx < 0)
  2400. return idx;
  2401. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2402. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2403. idx, mi2s_rx_cfg[idx].channels);
  2404. return 1;
  2405. }
  2406. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2407. struct snd_ctl_elem_value *ucontrol)
  2408. {
  2409. int idx = mi2s_get_port_idx(kcontrol);
  2410. if (idx < 0)
  2411. return idx;
  2412. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2413. idx, mi2s_tx_cfg[idx].channels);
  2414. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2415. return 0;
  2416. }
  2417. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2418. struct snd_ctl_elem_value *ucontrol)
  2419. {
  2420. int idx = mi2s_get_port_idx(kcontrol);
  2421. if (idx < 0)
  2422. return idx;
  2423. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2424. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2425. idx, mi2s_tx_cfg[idx].channels);
  2426. return 1;
  2427. }
  2428. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2429. struct snd_ctl_elem_value *ucontrol)
  2430. {
  2431. int idx = mi2s_get_port_idx(kcontrol);
  2432. if (idx < 0)
  2433. return idx;
  2434. ucontrol->value.enumerated.item[0] =
  2435. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2436. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2437. idx, mi2s_rx_cfg[idx].bit_format,
  2438. ucontrol->value.enumerated.item[0]);
  2439. return 0;
  2440. }
  2441. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2442. struct snd_ctl_elem_value *ucontrol)
  2443. {
  2444. int idx = mi2s_get_port_idx(kcontrol);
  2445. if (idx < 0)
  2446. return idx;
  2447. mi2s_rx_cfg[idx].bit_format =
  2448. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2449. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2450. idx, mi2s_rx_cfg[idx].bit_format,
  2451. ucontrol->value.enumerated.item[0]);
  2452. return 0;
  2453. }
  2454. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2455. struct snd_ctl_elem_value *ucontrol)
  2456. {
  2457. int idx = mi2s_get_port_idx(kcontrol);
  2458. if (idx < 0)
  2459. return idx;
  2460. ucontrol->value.enumerated.item[0] =
  2461. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2462. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2463. idx, mi2s_tx_cfg[idx].bit_format,
  2464. ucontrol->value.enumerated.item[0]);
  2465. return 0;
  2466. }
  2467. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2468. struct snd_ctl_elem_value *ucontrol)
  2469. {
  2470. int idx = mi2s_get_port_idx(kcontrol);
  2471. if (idx < 0)
  2472. return idx;
  2473. mi2s_tx_cfg[idx].bit_format =
  2474. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2475. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2476. idx, mi2s_tx_cfg[idx].bit_format,
  2477. ucontrol->value.enumerated.item[0]);
  2478. return 0;
  2479. }
  2480. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2481. struct snd_ctl_elem_value *ucontrol)
  2482. {
  2483. int idx = aux_pcm_get_port_idx(kcontrol);
  2484. if (idx < 0)
  2485. return idx;
  2486. ucontrol->value.enumerated.item[0] =
  2487. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2488. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2489. idx, aux_pcm_rx_cfg[idx].bit_format,
  2490. ucontrol->value.enumerated.item[0]);
  2491. return 0;
  2492. }
  2493. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2494. struct snd_ctl_elem_value *ucontrol)
  2495. {
  2496. int idx = aux_pcm_get_port_idx(kcontrol);
  2497. if (idx < 0)
  2498. return idx;
  2499. aux_pcm_rx_cfg[idx].bit_format =
  2500. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2501. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2502. idx, aux_pcm_rx_cfg[idx].bit_format,
  2503. ucontrol->value.enumerated.item[0]);
  2504. return 0;
  2505. }
  2506. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2507. struct snd_ctl_elem_value *ucontrol)
  2508. {
  2509. int idx = aux_pcm_get_port_idx(kcontrol);
  2510. if (idx < 0)
  2511. return idx;
  2512. ucontrol->value.enumerated.item[0] =
  2513. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2514. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2515. idx, aux_pcm_tx_cfg[idx].bit_format,
  2516. ucontrol->value.enumerated.item[0]);
  2517. return 0;
  2518. }
  2519. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2520. struct snd_ctl_elem_value *ucontrol)
  2521. {
  2522. int idx = aux_pcm_get_port_idx(kcontrol);
  2523. if (idx < 0)
  2524. return idx;
  2525. aux_pcm_tx_cfg[idx].bit_format =
  2526. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2527. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2528. idx, aux_pcm_tx_cfg[idx].bit_format,
  2529. ucontrol->value.enumerated.item[0]);
  2530. return 0;
  2531. }
  2532. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2533. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2534. slim_rx_ch_get, slim_rx_ch_put),
  2535. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2536. slim_rx_ch_get, slim_rx_ch_put),
  2537. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2538. slim_tx_ch_get, slim_tx_ch_put),
  2539. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2540. slim_tx_ch_get, slim_tx_ch_put),
  2541. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2542. slim_rx_ch_get, slim_rx_ch_put),
  2543. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2544. slim_rx_ch_get, slim_rx_ch_put),
  2545. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2546. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2547. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2548. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2549. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2550. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2551. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2552. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2553. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2554. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2555. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2556. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2557. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2558. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2559. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2560. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2561. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2562. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2563. };
  2564. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2565. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2566. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2567. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2568. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2569. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2570. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2571. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2572. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2573. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2574. va_cdc_dma_tx_0_sample_rate,
  2575. cdc_dma_tx_sample_rate_get,
  2576. cdc_dma_tx_sample_rate_put),
  2577. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2578. va_cdc_dma_tx_1_sample_rate,
  2579. cdc_dma_tx_sample_rate_get,
  2580. cdc_dma_tx_sample_rate_put),
  2581. };
  2582. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2583. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2584. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2585. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2586. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2587. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2588. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2589. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2590. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2591. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2592. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2593. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2594. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2595. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2596. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2597. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2598. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2599. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2600. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2601. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2602. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2603. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2604. wsa_cdc_dma_rx_0_sample_rate,
  2605. cdc_dma_rx_sample_rate_get,
  2606. cdc_dma_rx_sample_rate_put),
  2607. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2608. wsa_cdc_dma_rx_1_sample_rate,
  2609. cdc_dma_rx_sample_rate_get,
  2610. cdc_dma_rx_sample_rate_put),
  2611. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2612. wsa_cdc_dma_tx_0_sample_rate,
  2613. cdc_dma_tx_sample_rate_get,
  2614. cdc_dma_tx_sample_rate_put),
  2615. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2616. wsa_cdc_dma_tx_1_sample_rate,
  2617. cdc_dma_tx_sample_rate_get,
  2618. cdc_dma_tx_sample_rate_put),
  2619. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2620. wsa_cdc_dma_tx_2_sample_rate,
  2621. cdc_dma_tx_sample_rate_get,
  2622. cdc_dma_tx_sample_rate_put),
  2623. };
  2624. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2625. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2626. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2627. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2628. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2629. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2630. proxy_rx_ch_get, proxy_rx_ch_put),
  2631. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2632. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2633. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2634. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2635. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2636. msm_bt_sample_rate_get,
  2637. msm_bt_sample_rate_put),
  2638. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2639. usb_audio_rx_sample_rate_get,
  2640. usb_audio_rx_sample_rate_put),
  2641. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2642. usb_audio_tx_sample_rate_get,
  2643. usb_audio_tx_sample_rate_put),
  2644. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2645. tdm_rx_sample_rate_get,
  2646. tdm_rx_sample_rate_put),
  2647. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2648. tdm_tx_sample_rate_get,
  2649. tdm_tx_sample_rate_put),
  2650. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2651. tdm_rx_format_get,
  2652. tdm_rx_format_put),
  2653. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2654. tdm_tx_format_get,
  2655. tdm_tx_format_put),
  2656. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2657. tdm_rx_ch_get,
  2658. tdm_rx_ch_put),
  2659. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2660. tdm_tx_ch_get,
  2661. tdm_tx_ch_put),
  2662. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2663. tdm_rx_sample_rate_get,
  2664. tdm_rx_sample_rate_put),
  2665. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2666. tdm_tx_sample_rate_get,
  2667. tdm_tx_sample_rate_put),
  2668. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2669. tdm_rx_format_get,
  2670. tdm_rx_format_put),
  2671. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2672. tdm_tx_format_get,
  2673. tdm_tx_format_put),
  2674. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2675. tdm_rx_ch_get,
  2676. tdm_rx_ch_put),
  2677. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2678. tdm_tx_ch_get,
  2679. tdm_tx_ch_put),
  2680. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2681. tdm_rx_sample_rate_get,
  2682. tdm_rx_sample_rate_put),
  2683. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2684. tdm_tx_sample_rate_get,
  2685. tdm_tx_sample_rate_put),
  2686. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2687. tdm_rx_format_get,
  2688. tdm_rx_format_put),
  2689. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2690. tdm_tx_format_get,
  2691. tdm_tx_format_put),
  2692. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2693. tdm_rx_ch_get,
  2694. tdm_rx_ch_put),
  2695. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2696. tdm_tx_ch_get,
  2697. tdm_tx_ch_put),
  2698. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2699. tdm_rx_sample_rate_get,
  2700. tdm_rx_sample_rate_put),
  2701. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2702. tdm_tx_sample_rate_get,
  2703. tdm_tx_sample_rate_put),
  2704. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  2705. tdm_rx_format_get,
  2706. tdm_rx_format_put),
  2707. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  2708. tdm_tx_format_get,
  2709. tdm_tx_format_put),
  2710. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  2711. tdm_rx_ch_get,
  2712. tdm_rx_ch_put),
  2713. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  2714. tdm_tx_ch_get,
  2715. tdm_tx_ch_put),
  2716. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2717. tdm_rx_sample_rate_get,
  2718. tdm_rx_sample_rate_put),
  2719. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2720. tdm_tx_sample_rate_get,
  2721. tdm_tx_sample_rate_put),
  2722. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  2723. tdm_rx_format_get,
  2724. tdm_rx_format_put),
  2725. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  2726. tdm_tx_format_get,
  2727. tdm_tx_format_put),
  2728. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  2729. tdm_rx_ch_get,
  2730. tdm_rx_ch_put),
  2731. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  2732. tdm_tx_ch_get,
  2733. tdm_tx_ch_put),
  2734. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2735. aux_pcm_rx_sample_rate_get,
  2736. aux_pcm_rx_sample_rate_put),
  2737. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2738. aux_pcm_rx_sample_rate_get,
  2739. aux_pcm_rx_sample_rate_put),
  2740. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2741. aux_pcm_rx_sample_rate_get,
  2742. aux_pcm_rx_sample_rate_put),
  2743. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  2744. aux_pcm_rx_sample_rate_get,
  2745. aux_pcm_rx_sample_rate_put),
  2746. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  2747. aux_pcm_rx_sample_rate_get,
  2748. aux_pcm_rx_sample_rate_put),
  2749. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2750. aux_pcm_tx_sample_rate_get,
  2751. aux_pcm_tx_sample_rate_put),
  2752. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2753. aux_pcm_tx_sample_rate_get,
  2754. aux_pcm_tx_sample_rate_put),
  2755. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2756. aux_pcm_tx_sample_rate_get,
  2757. aux_pcm_tx_sample_rate_put),
  2758. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  2759. aux_pcm_tx_sample_rate_get,
  2760. aux_pcm_tx_sample_rate_put),
  2761. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  2762. aux_pcm_tx_sample_rate_get,
  2763. aux_pcm_tx_sample_rate_put),
  2764. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2765. mi2s_rx_sample_rate_get,
  2766. mi2s_rx_sample_rate_put),
  2767. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2768. mi2s_rx_sample_rate_get,
  2769. mi2s_rx_sample_rate_put),
  2770. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2771. mi2s_rx_sample_rate_get,
  2772. mi2s_rx_sample_rate_put),
  2773. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  2774. mi2s_rx_sample_rate_get,
  2775. mi2s_rx_sample_rate_put),
  2776. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  2777. mi2s_rx_sample_rate_get,
  2778. mi2s_rx_sample_rate_put),
  2779. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  2780. mi2s_tx_sample_rate_get,
  2781. mi2s_tx_sample_rate_put),
  2782. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2783. mi2s_tx_sample_rate_get,
  2784. mi2s_tx_sample_rate_put),
  2785. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2786. mi2s_tx_sample_rate_get,
  2787. mi2s_tx_sample_rate_put),
  2788. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  2789. mi2s_tx_sample_rate_get,
  2790. mi2s_tx_sample_rate_put),
  2791. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  2792. mi2s_tx_sample_rate_get,
  2793. mi2s_tx_sample_rate_put),
  2794. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2795. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2796. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2797. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2798. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2799. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2800. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2801. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2802. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2803. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2804. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2805. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2806. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  2807. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2808. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  2809. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2810. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  2811. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2812. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  2813. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2814. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2815. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2816. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2817. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2818. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2819. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2820. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2821. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2822. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2823. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2824. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2825. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2826. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  2827. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2828. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  2829. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2830. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  2831. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2832. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  2833. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2834. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2835. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2836. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2837. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2838. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2839. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2840. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2841. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2842. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2843. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2844. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2845. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2846. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2847. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2848. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2849. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2850. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  2851. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2852. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  2853. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2854. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  2855. msm_snd_vad_cfg_put),
  2856. };
  2857. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  2858. int enable, bool dapm)
  2859. {
  2860. int ret = 0;
  2861. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2862. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  2863. } else {
  2864. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  2865. __func__);
  2866. ret = -EINVAL;
  2867. }
  2868. return ret;
  2869. }
  2870. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  2871. int enable, bool dapm)
  2872. {
  2873. int ret = 0;
  2874. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2875. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  2876. } else {
  2877. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  2878. __func__);
  2879. ret = -EINVAL;
  2880. }
  2881. return ret;
  2882. }
  2883. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  2884. struct snd_kcontrol *kcontrol, int event)
  2885. {
  2886. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2887. pr_debug("%s: event = %d\n", __func__, event);
  2888. switch (event) {
  2889. case SND_SOC_DAPM_PRE_PMU:
  2890. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  2891. case SND_SOC_DAPM_POST_PMD:
  2892. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  2893. }
  2894. return 0;
  2895. }
  2896. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  2897. struct snd_kcontrol *kcontrol, int event)
  2898. {
  2899. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2900. pr_debug("%s: event = %d\n", __func__, event);
  2901. switch (event) {
  2902. case SND_SOC_DAPM_PRE_PMU:
  2903. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  2904. case SND_SOC_DAPM_POST_PMD:
  2905. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  2906. }
  2907. return 0;
  2908. }
  2909. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  2910. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  2911. msm_mclk_event,
  2912. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2913. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  2914. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2915. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  2916. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  2917. };
  2918. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  2919. struct snd_kcontrol *kcontrol, int event)
  2920. {
  2921. struct msm_asoc_mach_data *pdata = NULL;
  2922. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2923. int ret = 0;
  2924. uint32_t dmic_idx;
  2925. int *dmic_gpio_cnt;
  2926. struct device_node *dmic_gpio;
  2927. char *wname;
  2928. wname = strpbrk(w->name, "01234567");
  2929. if (!wname) {
  2930. dev_err(codec->dev, "%s: widget not found\n", __func__);
  2931. return -EINVAL;
  2932. }
  2933. ret = kstrtouint(wname, 10, &dmic_idx);
  2934. if (ret < 0) {
  2935. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  2936. __func__);
  2937. return -EINVAL;
  2938. }
  2939. pdata = snd_soc_card_get_drvdata(codec->component.card);
  2940. switch (dmic_idx) {
  2941. case 0:
  2942. case 1:
  2943. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  2944. dmic_gpio = pdata->dmic_01_gpio_p;
  2945. break;
  2946. case 2:
  2947. case 3:
  2948. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  2949. dmic_gpio = pdata->dmic_23_gpio_p;
  2950. break;
  2951. case 4:
  2952. case 5:
  2953. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  2954. dmic_gpio = pdata->dmic_45_gpio_p;
  2955. break;
  2956. case 6:
  2957. case 7:
  2958. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  2959. dmic_gpio = pdata->dmic_67_gpio_p;
  2960. break;
  2961. default:
  2962. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  2963. __func__);
  2964. return -EINVAL;
  2965. }
  2966. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  2967. __func__, event, dmic_idx, *dmic_gpio_cnt);
  2968. switch (event) {
  2969. case SND_SOC_DAPM_PRE_PMU:
  2970. (*dmic_gpio_cnt)++;
  2971. if (*dmic_gpio_cnt == 1) {
  2972. ret = msm_cdc_pinctrl_select_active_state(
  2973. dmic_gpio);
  2974. if (ret < 0) {
  2975. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  2976. __func__, "dmic_gpio");
  2977. return ret;
  2978. }
  2979. }
  2980. break;
  2981. case SND_SOC_DAPM_POST_PMD:
  2982. (*dmic_gpio_cnt)--;
  2983. if (*dmic_gpio_cnt == 0) {
  2984. ret = msm_cdc_pinctrl_select_sleep_state(
  2985. dmic_gpio);
  2986. if (ret < 0) {
  2987. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  2988. __func__, "dmic_gpio");
  2989. return ret;
  2990. }
  2991. }
  2992. break;
  2993. default:
  2994. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  2995. __func__, event);
  2996. return -EINVAL;
  2997. }
  2998. return 0;
  2999. }
  3000. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3001. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3002. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3003. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3004. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3005. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3006. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3007. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3008. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3009. };
  3010. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3011. };
  3012. static inline int param_is_mask(int p)
  3013. {
  3014. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3015. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3016. }
  3017. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3018. int n)
  3019. {
  3020. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3021. }
  3022. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3023. unsigned int bit)
  3024. {
  3025. if (bit >= SNDRV_MASK_MAX)
  3026. return;
  3027. if (param_is_mask(n)) {
  3028. struct snd_mask *m = param_to_mask(p, n);
  3029. m->bits[0] = 0;
  3030. m->bits[1] = 0;
  3031. m->bits[bit >> 5] |= (1 << (bit & 31));
  3032. }
  3033. }
  3034. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3035. {
  3036. int ch_id = 0;
  3037. switch (be_id) {
  3038. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3039. ch_id = SLIM_RX_0;
  3040. break;
  3041. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3042. ch_id = SLIM_RX_1;
  3043. break;
  3044. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3045. ch_id = SLIM_RX_2;
  3046. break;
  3047. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3048. ch_id = SLIM_RX_3;
  3049. break;
  3050. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3051. ch_id = SLIM_RX_4;
  3052. break;
  3053. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3054. ch_id = SLIM_RX_6;
  3055. break;
  3056. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3057. ch_id = SLIM_TX_0;
  3058. break;
  3059. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3060. ch_id = SLIM_TX_3;
  3061. break;
  3062. default:
  3063. ch_id = SLIM_RX_0;
  3064. break;
  3065. }
  3066. return ch_id;
  3067. }
  3068. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3069. {
  3070. *port_id = 0xFFFF;
  3071. switch (be_id) {
  3072. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3073. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3074. break;
  3075. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3076. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3077. break;
  3078. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3079. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3080. break;
  3081. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3082. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3083. break;
  3084. default:
  3085. return -EINVAL;
  3086. }
  3087. return 0;
  3088. }
  3089. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3090. {
  3091. int idx = 0;
  3092. switch (be_id) {
  3093. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3094. idx = WSA_CDC_DMA_RX_0;
  3095. break;
  3096. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3097. idx = WSA_CDC_DMA_TX_0;
  3098. break;
  3099. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3100. idx = WSA_CDC_DMA_RX_1;
  3101. break;
  3102. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3103. idx = WSA_CDC_DMA_TX_1;
  3104. break;
  3105. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3106. idx = WSA_CDC_DMA_TX_2;
  3107. break;
  3108. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3109. idx = VA_CDC_DMA_TX_0;
  3110. break;
  3111. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3112. idx = VA_CDC_DMA_TX_1;
  3113. break;
  3114. default:
  3115. idx = VA_CDC_DMA_TX_0;
  3116. break;
  3117. }
  3118. return idx;
  3119. }
  3120. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3121. struct snd_pcm_hw_params *params)
  3122. {
  3123. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3124. struct snd_interval *rate = hw_param_interval(params,
  3125. SNDRV_PCM_HW_PARAM_RATE);
  3126. struct snd_interval *channels = hw_param_interval(params,
  3127. SNDRV_PCM_HW_PARAM_CHANNELS);
  3128. int rc = 0;
  3129. int idx;
  3130. void *config = NULL;
  3131. struct snd_soc_codec *codec = NULL;
  3132. pr_debug("%s: format = %d, rate = %d\n",
  3133. __func__, params_format(params), params_rate(params));
  3134. switch (dai_link->id) {
  3135. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3136. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3137. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3138. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3139. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3140. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3141. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3142. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3143. slim_rx_cfg[idx].bit_format);
  3144. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3145. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3146. break;
  3147. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3148. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3149. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3150. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3151. slim_tx_cfg[idx].bit_format);
  3152. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3153. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3154. break;
  3155. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3156. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3157. slim_tx_cfg[1].bit_format);
  3158. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3159. channels->min = channels->max = slim_tx_cfg[1].channels;
  3160. break;
  3161. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3162. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3163. SNDRV_PCM_FORMAT_S32_LE);
  3164. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3165. channels->min = channels->max = msm_vi_feed_tx_ch;
  3166. break;
  3167. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3168. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3169. slim_rx_cfg[5].bit_format);
  3170. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3171. channels->min = channels->max = slim_rx_cfg[5].channels;
  3172. break;
  3173. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3174. codec = rtd->codec;
  3175. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3176. channels->min = channels->max = 1;
  3177. config = msm_codec_fn.get_afe_config_fn(codec,
  3178. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3179. if (config) {
  3180. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3181. config, SLIMBUS_5_TX);
  3182. if (rc)
  3183. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3184. __func__, rc);
  3185. }
  3186. break;
  3187. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3188. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3189. slim_rx_cfg[SLIM_RX_7].bit_format);
  3190. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3191. channels->min = channels->max =
  3192. slim_rx_cfg[SLIM_RX_7].channels;
  3193. break;
  3194. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3195. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3196. channels->min = channels->max =
  3197. slim_tx_cfg[SLIM_TX_7].channels;
  3198. break;
  3199. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3200. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3201. channels->min = channels->max =
  3202. slim_tx_cfg[SLIM_TX_8].channels;
  3203. break;
  3204. case MSM_BACKEND_DAI_USB_RX:
  3205. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3206. usb_rx_cfg.bit_format);
  3207. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3208. channels->min = channels->max = usb_rx_cfg.channels;
  3209. break;
  3210. case MSM_BACKEND_DAI_USB_TX:
  3211. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3212. usb_tx_cfg.bit_format);
  3213. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3214. channels->min = channels->max = usb_tx_cfg.channels;
  3215. break;
  3216. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3217. channels->min = channels->max = proxy_rx_cfg.channels;
  3218. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3219. break;
  3220. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3221. channels->min = channels->max =
  3222. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3223. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3224. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3225. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3226. break;
  3227. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3228. channels->min = channels->max =
  3229. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3230. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3231. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3232. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3233. break;
  3234. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3235. channels->min = channels->max =
  3236. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3237. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3238. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3239. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3240. break;
  3241. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3242. channels->min = channels->max =
  3243. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3244. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3245. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3246. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3247. break;
  3248. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3249. channels->min = channels->max =
  3250. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3251. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3252. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3253. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3254. break;
  3255. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3256. channels->min = channels->max =
  3257. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3258. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3259. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3260. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3261. break;
  3262. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3263. channels->min = channels->max =
  3264. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3265. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3266. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3267. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3268. break;
  3269. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3270. channels->min = channels->max =
  3271. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3272. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3273. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3274. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3275. break;
  3276. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3277. channels->min = channels->max =
  3278. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3279. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3280. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3281. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3282. break;
  3283. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3284. channels->min = channels->max =
  3285. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3286. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3287. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3288. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3289. break;
  3290. case MSM_BACKEND_DAI_AUXPCM_RX:
  3291. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3292. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3293. rate->min = rate->max =
  3294. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3295. channels->min = channels->max =
  3296. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3297. break;
  3298. case MSM_BACKEND_DAI_AUXPCM_TX:
  3299. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3300. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3301. rate->min = rate->max =
  3302. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3303. channels->min = channels->max =
  3304. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3305. break;
  3306. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3307. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3308. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3309. rate->min = rate->max =
  3310. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3311. channels->min = channels->max =
  3312. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3313. break;
  3314. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3315. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3316. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3317. rate->min = rate->max =
  3318. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3319. channels->min = channels->max =
  3320. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3321. break;
  3322. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3323. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3324. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3325. rate->min = rate->max =
  3326. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3327. channels->min = channels->max =
  3328. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3329. break;
  3330. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3331. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3332. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3333. rate->min = rate->max =
  3334. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3335. channels->min = channels->max =
  3336. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3337. break;
  3338. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3339. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3340. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3341. rate->min = rate->max =
  3342. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3343. channels->min = channels->max =
  3344. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3345. break;
  3346. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3347. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3348. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3349. rate->min = rate->max =
  3350. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3351. channels->min = channels->max =
  3352. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3353. break;
  3354. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3355. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3356. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3357. rate->min = rate->max =
  3358. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3359. channels->min = channels->max =
  3360. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3361. break;
  3362. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3363. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3364. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3365. rate->min = rate->max =
  3366. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3367. channels->min = channels->max =
  3368. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3369. break;
  3370. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3371. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3372. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3373. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3374. channels->min = channels->max =
  3375. mi2s_rx_cfg[PRIM_MI2S].channels;
  3376. break;
  3377. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3378. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3379. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3380. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3381. channels->min = channels->max =
  3382. mi2s_tx_cfg[PRIM_MI2S].channels;
  3383. break;
  3384. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3385. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3386. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3387. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3388. channels->min = channels->max =
  3389. mi2s_rx_cfg[SEC_MI2S].channels;
  3390. break;
  3391. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3392. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3393. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3394. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3395. channels->min = channels->max =
  3396. mi2s_tx_cfg[SEC_MI2S].channels;
  3397. break;
  3398. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3399. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3400. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3401. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3402. channels->min = channels->max =
  3403. mi2s_rx_cfg[TERT_MI2S].channels;
  3404. break;
  3405. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3406. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3407. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3408. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3409. channels->min = channels->max =
  3410. mi2s_tx_cfg[TERT_MI2S].channels;
  3411. break;
  3412. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3413. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3414. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3415. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3416. channels->min = channels->max =
  3417. mi2s_rx_cfg[QUAT_MI2S].channels;
  3418. break;
  3419. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3420. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3421. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3422. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3423. channels->min = channels->max =
  3424. mi2s_tx_cfg[QUAT_MI2S].channels;
  3425. break;
  3426. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3427. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3428. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3429. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3430. channels->min = channels->max =
  3431. mi2s_rx_cfg[QUIN_MI2S].channels;
  3432. break;
  3433. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3434. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3435. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3436. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3437. channels->min = channels->max =
  3438. mi2s_tx_cfg[QUIN_MI2S].channels;
  3439. break;
  3440. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3441. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3442. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3443. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3444. cdc_dma_rx_cfg[idx].bit_format);
  3445. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3446. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3447. break;
  3448. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3449. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3450. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3451. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3452. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3453. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3454. cdc_dma_tx_cfg[idx].bit_format);
  3455. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3456. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3457. break;
  3458. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3459. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3460. SNDRV_PCM_FORMAT_S32_LE);
  3461. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3462. channels->min = channels->max = msm_vi_feed_tx_ch;
  3463. break;
  3464. default:
  3465. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3466. break;
  3467. }
  3468. return rc;
  3469. }
  3470. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3471. {
  3472. int ret = 0;
  3473. void *config_data = NULL;
  3474. if (!msm_codec_fn.get_afe_config_fn) {
  3475. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3476. __func__);
  3477. return -EINVAL;
  3478. }
  3479. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3480. AFE_CDC_REGISTERS_CONFIG);
  3481. if (config_data) {
  3482. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3483. if (ret) {
  3484. dev_err(codec->dev,
  3485. "%s: Failed to set codec registers config %d\n",
  3486. __func__, ret);
  3487. return ret;
  3488. }
  3489. }
  3490. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3491. AFE_CDC_REGISTER_PAGE_CONFIG);
  3492. if (config_data) {
  3493. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3494. 0);
  3495. if (ret)
  3496. dev_err(codec->dev,
  3497. "%s: Failed to set cdc register page config\n",
  3498. __func__);
  3499. }
  3500. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3501. AFE_SLIMBUS_SLAVE_CONFIG);
  3502. if (config_data) {
  3503. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3504. if (ret) {
  3505. dev_err(codec->dev,
  3506. "%s: Failed to set slimbus slave config %d\n",
  3507. __func__, ret);
  3508. return ret;
  3509. }
  3510. }
  3511. return 0;
  3512. }
  3513. static void msm_afe_clear_config(void)
  3514. {
  3515. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3516. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3517. }
  3518. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3519. struct snd_card *card)
  3520. {
  3521. int ret = 0;
  3522. unsigned long timeout;
  3523. int adsp_ready = 0;
  3524. bool snd_card_online = 0;
  3525. timeout = jiffies +
  3526. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3527. do {
  3528. if (!snd_card_online) {
  3529. snd_card_online = snd_card_is_online_state(card);
  3530. pr_debug("%s: Sound card is %s\n", __func__,
  3531. snd_card_online ? "Online" : "Offline");
  3532. }
  3533. if (!adsp_ready) {
  3534. adsp_ready = q6core_is_adsp_ready();
  3535. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3536. adsp_ready ? "ready" : "not ready");
  3537. }
  3538. if (snd_card_online && adsp_ready)
  3539. break;
  3540. /*
  3541. * Sound card/ADSP will be coming up after subsystem restart and
  3542. * it might not be fully up when the control reaches
  3543. * here. So, wait for 50msec before checking ADSP state
  3544. */
  3545. msleep(50);
  3546. } while (time_after(timeout, jiffies));
  3547. if (!snd_card_online || !adsp_ready) {
  3548. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3549. __func__,
  3550. snd_card_online ? "Online" : "Offline",
  3551. adsp_ready ? "ready" : "not ready");
  3552. ret = -ETIMEDOUT;
  3553. goto err;
  3554. }
  3555. ret = msm_afe_set_config(codec);
  3556. if (ret)
  3557. pr_err("%s: Failed to set AFE config. err %d\n",
  3558. __func__, ret);
  3559. return 0;
  3560. err:
  3561. return ret;
  3562. }
  3563. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3564. unsigned long opcode, void *ptr)
  3565. {
  3566. int ret;
  3567. struct snd_soc_card *card = NULL;
  3568. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3569. struct snd_soc_pcm_runtime *rtd;
  3570. struct snd_soc_codec *codec;
  3571. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3572. switch (opcode) {
  3573. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3574. /*
  3575. * Use flag to ignore initial boot notifications
  3576. * On initial boot msm_adsp_power_up_config is
  3577. * called on init. There is no need to clear
  3578. * and set the config again on initial boot.
  3579. */
  3580. if (is_initial_boot)
  3581. break;
  3582. msm_afe_clear_config();
  3583. break;
  3584. case AUDIO_NOTIFIER_SERVICE_UP:
  3585. if (is_initial_boot) {
  3586. is_initial_boot = false;
  3587. break;
  3588. }
  3589. if (!spdev)
  3590. return -EINVAL;
  3591. card = platform_get_drvdata(spdev);
  3592. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3593. if (!rtd) {
  3594. dev_err(card->dev,
  3595. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3596. __func__, be_dl_name);
  3597. ret = -EINVAL;
  3598. goto err;
  3599. }
  3600. codec = rtd->codec;
  3601. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3602. if (ret < 0) {
  3603. dev_err(card->dev,
  3604. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3605. __func__, ret);
  3606. goto err;
  3607. }
  3608. break;
  3609. default:
  3610. break;
  3611. }
  3612. err:
  3613. return NOTIFY_OK;
  3614. }
  3615. static struct notifier_block service_nb = {
  3616. .notifier_call = qcs405_notifier_service_cb,
  3617. .priority = -INT_MAX,
  3618. };
  3619. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3620. {
  3621. int ret = 0;
  3622. void *config_data;
  3623. struct snd_soc_codec *codec = rtd->codec;
  3624. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3625. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3626. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3627. struct snd_card *card;
  3628. struct snd_info_entry *entry;
  3629. struct msm_asoc_mach_data *pdata =
  3630. snd_soc_card_get_drvdata(rtd->card);
  3631. /*
  3632. * Codec SLIMBUS configuration
  3633. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  3634. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  3635. * TX14, TX15, TX16
  3636. */
  3637. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  3638. 151, 152, 153, 154, 155, 156};
  3639. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  3640. 134, 135, 136, 137, 138, 139,
  3641. 140, 141, 142, 143};
  3642. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  3643. rtd->pmdown_time = 0;
  3644. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  3645. ARRAY_SIZE(msm_snd_sb_controls));
  3646. if (ret < 0) {
  3647. pr_err("%s: add_codec_controls failed, err %d\n",
  3648. __func__, ret);
  3649. return ret;
  3650. }
  3651. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  3652. ARRAY_SIZE(msm_dapm_widgets));
  3653. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  3654. ARRAY_SIZE(wcd_audio_paths));
  3655. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  3656. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  3657. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3658. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3659. snd_soc_dapm_sync(dapm);
  3660. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3661. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3662. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  3663. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  3664. if (ret) {
  3665. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  3666. __func__, ret);
  3667. goto err;
  3668. }
  3669. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3670. AFE_AANC_VERSION);
  3671. if (config_data) {
  3672. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  3673. if (ret) {
  3674. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  3675. __func__, ret);
  3676. goto err;
  3677. }
  3678. }
  3679. card = rtd->card->snd_card;
  3680. entry = snd_info_create_subdir(card->module, "codecs",
  3681. card->proc_root);
  3682. if (!entry) {
  3683. pr_debug("%s: Cannot create codecs module entry\n",
  3684. __func__);
  3685. ret = 0;
  3686. goto err;
  3687. }
  3688. pdata->codec_root = entry;
  3689. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  3690. codec_reg_done = true;
  3691. return 0;
  3692. err:
  3693. return ret;
  3694. }
  3695. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3696. {
  3697. int ret = 0;
  3698. struct snd_soc_codec *codec = rtd->codec;
  3699. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3700. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  3701. ARRAY_SIZE(msm_snd_va_controls));
  3702. if (ret < 0) {
  3703. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3704. __func__, ret);
  3705. return ret;
  3706. }
  3707. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  3708. ARRAY_SIZE(msm_va_dapm_widgets));
  3709. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3710. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3711. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3712. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3713. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  3714. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  3715. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  3716. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  3717. snd_soc_dapm_sync(dapm);
  3718. return ret;
  3719. }
  3720. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3721. {
  3722. int ret = 0;
  3723. struct snd_soc_codec *codec = rtd->codec;
  3724. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3725. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  3726. ARRAY_SIZE(msm_snd_wsa_controls));
  3727. if (ret < 0) {
  3728. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3729. __func__, ret);
  3730. return ret;
  3731. }
  3732. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  3733. ARRAY_SIZE(msm_wsa_dapm_widgets));
  3734. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  3735. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  3736. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  3737. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  3738. snd_soc_dapm_sync(dapm);
  3739. return ret;
  3740. }
  3741. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3742. {
  3743. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3744. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  3745. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3746. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3747. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3748. }
  3749. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  3750. struct snd_pcm_hw_params *params)
  3751. {
  3752. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3753. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3754. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3755. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3756. int ret = 0;
  3757. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3758. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3759. u32 user_set_tx_ch = 0;
  3760. u32 rx_ch_count;
  3761. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3762. ret = snd_soc_dai_get_channel_map(codec_dai,
  3763. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3764. if (ret < 0) {
  3765. pr_err("%s: failed to get codec chan map, err:%d\n",
  3766. __func__, ret);
  3767. goto err;
  3768. }
  3769. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  3770. pr_debug("%s: rx_5_ch=%d\n", __func__,
  3771. slim_rx_cfg[5].channels);
  3772. rx_ch_count = slim_rx_cfg[5].channels;
  3773. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  3774. pr_debug("%s: rx_2_ch=%d\n", __func__,
  3775. slim_rx_cfg[2].channels);
  3776. rx_ch_count = slim_rx_cfg[2].channels;
  3777. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  3778. pr_debug("%s: rx_6_ch=%d\n", __func__,
  3779. slim_rx_cfg[6].channels);
  3780. rx_ch_count = slim_rx_cfg[6].channels;
  3781. } else {
  3782. pr_debug("%s: rx_0_ch=%d\n", __func__,
  3783. slim_rx_cfg[0].channels);
  3784. rx_ch_count = slim_rx_cfg[0].channels;
  3785. }
  3786. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3787. rx_ch_count, rx_ch);
  3788. if (ret < 0) {
  3789. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3790. __func__, ret);
  3791. goto err;
  3792. }
  3793. } else {
  3794. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  3795. codec_dai->name, codec_dai->id, user_set_tx_ch);
  3796. ret = snd_soc_dai_get_channel_map(codec_dai,
  3797. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3798. if (ret < 0) {
  3799. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3800. __func__, ret);
  3801. goto err;
  3802. }
  3803. /* For <codec>_tx1 case */
  3804. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  3805. user_set_tx_ch = slim_tx_cfg[0].channels;
  3806. /* For <codec>_tx3 case */
  3807. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  3808. user_set_tx_ch = slim_tx_cfg[1].channels;
  3809. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  3810. user_set_tx_ch = msm_vi_feed_tx_ch;
  3811. else
  3812. user_set_tx_ch = tx_ch_cnt;
  3813. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  3814. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  3815. tx_ch_cnt, dai_link->id);
  3816. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3817. user_set_tx_ch, tx_ch, 0, 0);
  3818. if (ret < 0)
  3819. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3820. __func__, ret);
  3821. }
  3822. err:
  3823. return ret;
  3824. }
  3825. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3826. struct snd_pcm_hw_params *params)
  3827. {
  3828. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3829. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3830. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3831. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3832. int ret = 0;
  3833. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3834. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3835. u32 user_set_tx_ch = 0;
  3836. u32 user_set_rx_ch = 0;
  3837. u32 ch_id;
  3838. ret = snd_soc_dai_get_channel_map(codec_dai,
  3839. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3840. &rx_ch_cdc_dma);
  3841. if (ret < 0) {
  3842. pr_err("%s: failed to get codec chan map, err:%d\n",
  3843. __func__, ret);
  3844. goto err;
  3845. }
  3846. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3847. switch (dai_link->id) {
  3848. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3849. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3850. {
  3851. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3852. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3853. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3854. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3855. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3856. user_set_rx_ch, &rx_ch_cdc_dma);
  3857. if (ret < 0) {
  3858. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3859. __func__, ret);
  3860. goto err;
  3861. }
  3862. }
  3863. break;
  3864. }
  3865. } else {
  3866. switch (dai_link->id) {
  3867. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3868. {
  3869. user_set_tx_ch = msm_vi_feed_tx_ch;
  3870. }
  3871. break;
  3872. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3873. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3874. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3875. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3876. {
  3877. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3878. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3879. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3880. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3881. }
  3882. break;
  3883. }
  3884. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3885. &tx_ch_cdc_dma, 0, 0);
  3886. if (ret < 0) {
  3887. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3888. __func__, ret);
  3889. goto err;
  3890. }
  3891. }
  3892. err:
  3893. return ret;
  3894. }
  3895. static int msm_slimbus_2_hw_params(struct snd_pcm_substream *substream,
  3896. struct snd_pcm_hw_params *params)
  3897. {
  3898. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3899. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3900. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3901. unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3902. unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0;
  3903. unsigned int num_tx_ch = 0;
  3904. unsigned int num_rx_ch = 0;
  3905. int ret = 0;
  3906. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3907. num_rx_ch = params_channels(params);
  3908. pr_debug("%s: %s rx_dai_id = %d num_ch = %d\n", __func__,
  3909. codec_dai->name, codec_dai->id, num_rx_ch);
  3910. ret = snd_soc_dai_get_channel_map(codec_dai,
  3911. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3912. if (ret < 0) {
  3913. pr_err("%s: failed to get codec chan map, err:%d\n",
  3914. __func__, ret);
  3915. goto err;
  3916. }
  3917. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3918. num_rx_ch, rx_ch);
  3919. if (ret < 0) {
  3920. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3921. __func__, ret);
  3922. goto err;
  3923. }
  3924. } else {
  3925. num_tx_ch = params_channels(params);
  3926. pr_debug("%s: %s tx_dai_id = %d num_ch = %d\n", __func__,
  3927. codec_dai->name, codec_dai->id, num_tx_ch);
  3928. ret = snd_soc_dai_get_channel_map(codec_dai,
  3929. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3930. if (ret < 0) {
  3931. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3932. __func__, ret);
  3933. goto err;
  3934. }
  3935. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3936. num_tx_ch, tx_ch, 0, 0);
  3937. if (ret < 0) {
  3938. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3939. __func__, ret);
  3940. goto err;
  3941. }
  3942. }
  3943. err:
  3944. return ret;
  3945. }
  3946. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3947. struct snd_pcm_hw_params *params)
  3948. {
  3949. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3950. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3951. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3952. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3953. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3954. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3955. int ret;
  3956. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3957. codec_dai->name, codec_dai->id);
  3958. ret = snd_soc_dai_get_channel_map(codec_dai,
  3959. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3960. if (ret) {
  3961. dev_err(rtd->dev,
  3962. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3963. __func__, ret);
  3964. goto err;
  3965. }
  3966. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3967. __func__, tx_ch_cnt, dai_link->id);
  3968. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3969. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3970. if (ret)
  3971. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3972. __func__, ret);
  3973. err:
  3974. return ret;
  3975. }
  3976. static int msm_get_port_id(int be_id)
  3977. {
  3978. int afe_port_id;
  3979. switch (be_id) {
  3980. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3981. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  3982. break;
  3983. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3984. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  3985. break;
  3986. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3987. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  3988. break;
  3989. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3990. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  3991. break;
  3992. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3993. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  3994. break;
  3995. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3996. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  3997. break;
  3998. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3999. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4000. break;
  4001. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4002. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4003. break;
  4004. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4005. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4006. break;
  4007. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4008. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4009. break;
  4010. default:
  4011. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4012. afe_port_id = -EINVAL;
  4013. }
  4014. return afe_port_id;
  4015. }
  4016. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4017. {
  4018. u32 bit_per_sample;
  4019. switch (bit_format) {
  4020. case SNDRV_PCM_FORMAT_S32_LE:
  4021. case SNDRV_PCM_FORMAT_S24_3LE:
  4022. case SNDRV_PCM_FORMAT_S24_LE:
  4023. bit_per_sample = 32;
  4024. break;
  4025. case SNDRV_PCM_FORMAT_S16_LE:
  4026. default:
  4027. bit_per_sample = 16;
  4028. break;
  4029. }
  4030. return bit_per_sample;
  4031. }
  4032. static void update_mi2s_clk_val(int dai_id, int stream)
  4033. {
  4034. u32 bit_per_sample;
  4035. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4036. bit_per_sample =
  4037. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4038. mi2s_clk[dai_id].clk_freq_in_hz =
  4039. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4040. } else {
  4041. bit_per_sample =
  4042. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4043. mi2s_clk[dai_id].clk_freq_in_hz =
  4044. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4045. }
  4046. }
  4047. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4048. {
  4049. int ret = 0;
  4050. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4051. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4052. int port_id = 0;
  4053. int index = cpu_dai->id;
  4054. port_id = msm_get_port_id(rtd->dai_link->id);
  4055. if (port_id < 0) {
  4056. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4057. ret = port_id;
  4058. goto err;
  4059. }
  4060. if (enable) {
  4061. update_mi2s_clk_val(index, substream->stream);
  4062. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4063. mi2s_clk[index].clk_freq_in_hz);
  4064. }
  4065. mi2s_clk[index].enable = enable;
  4066. ret = afe_set_lpass_clock_v2(port_id,
  4067. &mi2s_clk[index]);
  4068. if (ret < 0) {
  4069. dev_err(rtd->card->dev,
  4070. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4071. __func__, port_id, ret);
  4072. goto err;
  4073. }
  4074. err:
  4075. return ret;
  4076. }
  4077. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4078. enum pinctrl_pin_state new_state)
  4079. {
  4080. int ret = 0;
  4081. int curr_state = 0;
  4082. if (pinctrl_info == NULL) {
  4083. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4084. ret = -EINVAL;
  4085. goto err;
  4086. }
  4087. if (pinctrl_info->pinctrl == NULL) {
  4088. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4089. ret = -EINVAL;
  4090. goto err;
  4091. }
  4092. curr_state = pinctrl_info->curr_state;
  4093. pinctrl_info->curr_state = new_state;
  4094. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4095. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4096. if (curr_state == pinctrl_info->curr_state) {
  4097. pr_debug("%s: Already in same state\n", __func__);
  4098. goto err;
  4099. }
  4100. if (curr_state != STATE_DISABLE &&
  4101. pinctrl_info->curr_state != STATE_DISABLE) {
  4102. pr_debug("%s: state already active cannot switch\n", __func__);
  4103. ret = -EIO;
  4104. goto err;
  4105. }
  4106. switch (pinctrl_info->curr_state) {
  4107. case STATE_MI2S_ACTIVE:
  4108. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4109. pinctrl_info->mi2s_active);
  4110. if (ret) {
  4111. pr_err("%s: MI2S state select failed with %d\n",
  4112. __func__, ret);
  4113. ret = -EIO;
  4114. goto err;
  4115. }
  4116. break;
  4117. case STATE_TDM_ACTIVE:
  4118. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4119. pinctrl_info->tdm_active);
  4120. if (ret) {
  4121. pr_err("%s: TDM state select failed with %d\n",
  4122. __func__, ret);
  4123. ret = -EIO;
  4124. goto err;
  4125. }
  4126. break;
  4127. case STATE_DISABLE:
  4128. if (curr_state == STATE_MI2S_ACTIVE) {
  4129. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4130. pinctrl_info->mi2s_disable);
  4131. } else {
  4132. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4133. pinctrl_info->tdm_disable);
  4134. }
  4135. if (ret) {
  4136. pr_err("%s: state disable failed with %d\n",
  4137. __func__, ret);
  4138. ret = -EIO;
  4139. goto err;
  4140. }
  4141. break;
  4142. default:
  4143. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4144. return -EINVAL;
  4145. }
  4146. err:
  4147. return ret;
  4148. }
  4149. static void msm_release_pinctrl(struct platform_device *pdev)
  4150. {
  4151. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4152. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4153. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4154. if (pinctrl_info->pinctrl) {
  4155. devm_pinctrl_put(pinctrl_info->pinctrl);
  4156. pinctrl_info->pinctrl = NULL;
  4157. }
  4158. }
  4159. static int msm_get_pinctrl(struct platform_device *pdev)
  4160. {
  4161. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4162. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4163. struct msm_pinctrl_info *pinctrl_info = NULL;
  4164. struct pinctrl *pinctrl;
  4165. int ret;
  4166. pinctrl_info = &pdata->pinctrl_info;
  4167. if (pinctrl_info == NULL) {
  4168. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4169. return -EINVAL;
  4170. }
  4171. pinctrl = devm_pinctrl_get(&pdev->dev);
  4172. if (IS_ERR_OR_NULL(pinctrl)) {
  4173. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4174. return -EINVAL;
  4175. }
  4176. pinctrl_info->pinctrl = pinctrl;
  4177. /* get all the states handles from Device Tree */
  4178. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4179. "quat-mi2s-sleep");
  4180. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4181. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4182. goto err;
  4183. }
  4184. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4185. "quat-mi2s-active");
  4186. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4187. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4188. goto err;
  4189. }
  4190. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4191. "quat-tdm-sleep");
  4192. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4193. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4194. goto err;
  4195. }
  4196. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4197. "quat-tdm-active");
  4198. if (IS_ERR(pinctrl_info->tdm_active)) {
  4199. pr_err("%s: could not get tdm_active pinstate\n",
  4200. __func__);
  4201. goto err;
  4202. }
  4203. /* Reset the TLMM pins to a default state */
  4204. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4205. pinctrl_info->mi2s_disable);
  4206. if (ret != 0) {
  4207. pr_err("%s: Disable TLMM pins failed with %d\n",
  4208. __func__, ret);
  4209. ret = -EIO;
  4210. goto err;
  4211. }
  4212. pinctrl_info->curr_state = STATE_DISABLE;
  4213. return 0;
  4214. err:
  4215. devm_pinctrl_put(pinctrl);
  4216. pinctrl_info->pinctrl = NULL;
  4217. return -EINVAL;
  4218. }
  4219. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4220. struct snd_pcm_hw_params *params)
  4221. {
  4222. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4223. struct snd_interval *rate = hw_param_interval(params,
  4224. SNDRV_PCM_HW_PARAM_RATE);
  4225. struct snd_interval *channels = hw_param_interval(params,
  4226. SNDRV_PCM_HW_PARAM_CHANNELS);
  4227. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4228. channels->min = channels->max =
  4229. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4230. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4231. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4232. rate->min = rate->max =
  4233. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4234. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4235. channels->min = channels->max =
  4236. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4237. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4238. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4239. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4240. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4241. channels->min = channels->max =
  4242. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4243. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4244. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4245. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4246. } else {
  4247. pr_err("%s: dai id 0x%x not supported\n",
  4248. __func__, cpu_dai->id);
  4249. return -EINVAL;
  4250. }
  4251. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4252. __func__, cpu_dai->id, channels->max, rate->max,
  4253. params_format(params));
  4254. return 0;
  4255. }
  4256. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4257. struct snd_pcm_hw_params *params)
  4258. {
  4259. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4260. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4261. int ret = 0;
  4262. int slot_width = 32;
  4263. int channels, slots;
  4264. unsigned int slot_mask, rate, clk_freq;
  4265. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4266. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4267. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4268. switch (cpu_dai->id) {
  4269. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4270. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4271. break;
  4272. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4273. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4274. break;
  4275. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4276. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4277. break;
  4278. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4279. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4280. break;
  4281. case AFE_PORT_ID_QUINARY_TDM_RX:
  4282. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4283. break;
  4284. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4285. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4286. break;
  4287. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4288. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4289. break;
  4290. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4291. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4292. break;
  4293. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4294. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4295. break;
  4296. case AFE_PORT_ID_QUINARY_TDM_TX:
  4297. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4298. break;
  4299. default:
  4300. pr_err("%s: dai id 0x%x not supported\n",
  4301. __func__, cpu_dai->id);
  4302. return -EINVAL;
  4303. }
  4304. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4305. /*2 slot config - bits 0 and 1 set for the first two slots */
  4306. slot_mask = 0x0000FFFF >> (16-slots);
  4307. channels = slots;
  4308. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4309. __func__, slot_width, slots);
  4310. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4311. slots, slot_width);
  4312. if (ret < 0) {
  4313. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4314. __func__, ret);
  4315. goto end;
  4316. }
  4317. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4318. 0, NULL, channels, slot_offset);
  4319. if (ret < 0) {
  4320. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4321. __func__, ret);
  4322. goto end;
  4323. }
  4324. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4325. /*2 slot config - bits 0 and 1 set for the first two slots */
  4326. slot_mask = 0x0000FFFF >> (16-slots);
  4327. channels = slots;
  4328. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4329. __func__, slot_width, slots);
  4330. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4331. slots, slot_width);
  4332. if (ret < 0) {
  4333. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4334. __func__, ret);
  4335. goto end;
  4336. }
  4337. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4338. channels, slot_offset, 0, NULL);
  4339. if (ret < 0) {
  4340. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4341. __func__, ret);
  4342. goto end;
  4343. }
  4344. } else {
  4345. ret = -EINVAL;
  4346. pr_err("%s: invalid use case, err:%d\n",
  4347. __func__, ret);
  4348. goto end;
  4349. }
  4350. rate = params_rate(params);
  4351. clk_freq = rate * slot_width * slots;
  4352. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4353. if (ret < 0)
  4354. pr_err("%s: failed to set tdm clk, err:%d\n",
  4355. __func__, ret);
  4356. end:
  4357. return ret;
  4358. }
  4359. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4360. {
  4361. int ret = 0;
  4362. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4363. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4364. struct snd_soc_card *card = rtd->card;
  4365. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4366. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4367. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4368. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4369. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4370. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4371. if (ret)
  4372. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4373. __func__, ret);
  4374. }
  4375. return ret;
  4376. }
  4377. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4378. {
  4379. int ret = 0;
  4380. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4381. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4382. struct snd_soc_card *card = rtd->card;
  4383. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4384. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4385. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4386. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4387. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4388. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4389. if (ret)
  4390. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4391. __func__, ret);
  4392. }
  4393. }
  4394. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4395. .hw_params = qcs405_tdm_snd_hw_params,
  4396. .startup = qcs405_tdm_snd_startup,
  4397. .shutdown = qcs405_tdm_snd_shutdown
  4398. };
  4399. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4400. {
  4401. cpumask_t mask;
  4402. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4403. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4404. cpumask_clear(&mask);
  4405. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4406. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4407. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4408. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4409. pm_qos_add_request(&substream->latency_pm_qos_req,
  4410. PM_QOS_CPU_DMA_LATENCY,
  4411. MSM_LL_QOS_VALUE);
  4412. return 0;
  4413. }
  4414. static struct snd_soc_ops msm_fe_qos_ops = {
  4415. .prepare = msm_fe_qos_prepare,
  4416. };
  4417. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4418. {
  4419. int ret = 0;
  4420. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4421. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4422. int index = cpu_dai->id;
  4423. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4424. struct snd_soc_card *card = rtd->card;
  4425. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4426. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4427. int ret_pinctrl = 0;
  4428. dev_dbg(rtd->card->dev,
  4429. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4430. __func__, substream->name, substream->stream,
  4431. cpu_dai->name, cpu_dai->id);
  4432. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4433. ret = -EINVAL;
  4434. dev_err(rtd->card->dev,
  4435. "%s: CPU DAI id (%d) out of range\n",
  4436. __func__, cpu_dai->id);
  4437. goto err;
  4438. }
  4439. /*
  4440. * Mutex protection in case the same MI2S
  4441. * interface using for both TX and RX so
  4442. * that the same clock won't be enable twice.
  4443. */
  4444. mutex_lock(&mi2s_intf_conf[index].lock);
  4445. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4446. /* Check if msm needs to provide the clock to the interface */
  4447. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4448. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4449. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4450. }
  4451. ret = msm_mi2s_set_sclk(substream, true);
  4452. if (ret < 0) {
  4453. dev_err(rtd->card->dev,
  4454. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4455. __func__, ret);
  4456. goto clean_up;
  4457. }
  4458. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4459. if (ret < 0) {
  4460. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4461. __func__, index, ret);
  4462. goto clk_off;
  4463. }
  4464. if (index == QUAT_MI2S) {
  4465. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4466. STATE_MI2S_ACTIVE);
  4467. if (ret_pinctrl)
  4468. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4469. __func__, ret_pinctrl);
  4470. }
  4471. }
  4472. clk_off:
  4473. if (ret < 0)
  4474. msm_mi2s_set_sclk(substream, false);
  4475. clean_up:
  4476. if (ret < 0)
  4477. mi2s_intf_conf[index].ref_cnt--;
  4478. mutex_unlock(&mi2s_intf_conf[index].lock);
  4479. err:
  4480. return ret;
  4481. }
  4482. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4483. {
  4484. int ret;
  4485. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4486. int index = rtd->cpu_dai->id;
  4487. struct snd_soc_card *card = rtd->card;
  4488. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4489. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4490. int ret_pinctrl = 0;
  4491. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4492. substream->name, substream->stream);
  4493. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4494. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4495. return;
  4496. }
  4497. mutex_lock(&mi2s_intf_conf[index].lock);
  4498. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4499. ret = msm_mi2s_set_sclk(substream, false);
  4500. if (ret < 0)
  4501. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4502. __func__, index, ret);
  4503. if (index == QUAT_MI2S) {
  4504. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4505. STATE_DISABLE);
  4506. if (ret_pinctrl)
  4507. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4508. __func__, ret_pinctrl);
  4509. }
  4510. }
  4511. mutex_unlock(&mi2s_intf_conf[index].lock);
  4512. }
  4513. static struct snd_soc_ops msm_mi2s_be_ops = {
  4514. .startup = msm_mi2s_snd_startup,
  4515. .shutdown = msm_mi2s_snd_shutdown,
  4516. };
  4517. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4518. .hw_params = msm_snd_cdc_dma_hw_params,
  4519. };
  4520. static struct snd_soc_ops msm_be_ops = {
  4521. .hw_params = msm_snd_hw_params,
  4522. };
  4523. static struct snd_soc_ops msm_slimbus_2_be_ops = {
  4524. .hw_params = msm_slimbus_2_hw_params,
  4525. };
  4526. static struct snd_soc_ops msm_wcn_ops = {
  4527. .hw_params = msm_wcn_hw_params,
  4528. };
  4529. /* Digital audio interface glue - connects codec <---> CPU */
  4530. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4531. /* FrontEnd DAI Links */
  4532. {
  4533. .name = MSM_DAILINK_NAME(Media1),
  4534. .stream_name = "MultiMedia1",
  4535. .cpu_dai_name = "MultiMedia1",
  4536. .platform_name = "msm-pcm-dsp.0",
  4537. .dynamic = 1,
  4538. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4539. .dpcm_playback = 1,
  4540. .dpcm_capture = 1,
  4541. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4542. SND_SOC_DPCM_TRIGGER_POST},
  4543. .codec_dai_name = "snd-soc-dummy-dai",
  4544. .codec_name = "snd-soc-dummy",
  4545. .ignore_suspend = 1,
  4546. /* this dainlink has playback support */
  4547. .ignore_pmdown_time = 1,
  4548. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4549. },
  4550. {
  4551. .name = MSM_DAILINK_NAME(Media2),
  4552. .stream_name = "MultiMedia2",
  4553. .cpu_dai_name = "MultiMedia2",
  4554. .platform_name = "msm-pcm-dsp.0",
  4555. .dynamic = 1,
  4556. .dpcm_playback = 1,
  4557. .dpcm_capture = 1,
  4558. .codec_dai_name = "snd-soc-dummy-dai",
  4559. .codec_name = "snd-soc-dummy",
  4560. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4561. SND_SOC_DPCM_TRIGGER_POST},
  4562. .ignore_suspend = 1,
  4563. /* this dainlink has playback support */
  4564. .ignore_pmdown_time = 1,
  4565. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4566. },
  4567. {
  4568. .name = "VoiceMMode1",
  4569. .stream_name = "VoiceMMode1",
  4570. .cpu_dai_name = "VoiceMMode1",
  4571. .platform_name = "msm-pcm-voice",
  4572. .dynamic = 1,
  4573. .dpcm_playback = 1,
  4574. .dpcm_capture = 1,
  4575. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4576. SND_SOC_DPCM_TRIGGER_POST},
  4577. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4578. .ignore_suspend = 1,
  4579. .ignore_pmdown_time = 1,
  4580. .codec_dai_name = "snd-soc-dummy-dai",
  4581. .codec_name = "snd-soc-dummy",
  4582. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4583. },
  4584. {
  4585. .name = "MSM VoIP",
  4586. .stream_name = "VoIP",
  4587. .cpu_dai_name = "VoIP",
  4588. .platform_name = "msm-voip-dsp",
  4589. .dynamic = 1,
  4590. .dpcm_playback = 1,
  4591. .dpcm_capture = 1,
  4592. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4593. SND_SOC_DPCM_TRIGGER_POST},
  4594. .codec_dai_name = "snd-soc-dummy-dai",
  4595. .codec_name = "snd-soc-dummy",
  4596. .ignore_suspend = 1,
  4597. /* this dainlink has playback support */
  4598. .ignore_pmdown_time = 1,
  4599. .id = MSM_FRONTEND_DAI_VOIP,
  4600. },
  4601. {
  4602. .name = MSM_DAILINK_NAME(ULL),
  4603. .stream_name = "MultiMedia3",
  4604. .cpu_dai_name = "MultiMedia3",
  4605. .platform_name = "msm-pcm-dsp.2",
  4606. .dynamic = 1,
  4607. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4608. .dpcm_playback = 1,
  4609. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4610. SND_SOC_DPCM_TRIGGER_POST},
  4611. .codec_dai_name = "snd-soc-dummy-dai",
  4612. .codec_name = "snd-soc-dummy",
  4613. .ignore_suspend = 1,
  4614. /* this dainlink has playback support */
  4615. .ignore_pmdown_time = 1,
  4616. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4617. },
  4618. /* Hostless PCM purpose */
  4619. {
  4620. .name = "SLIMBUS_0 Hostless",
  4621. .stream_name = "SLIMBUS_0 Hostless",
  4622. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  4623. .platform_name = "msm-pcm-hostless",
  4624. .dynamic = 1,
  4625. .dpcm_playback = 1,
  4626. .dpcm_capture = 1,
  4627. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4628. SND_SOC_DPCM_TRIGGER_POST},
  4629. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4630. .ignore_suspend = 1,
  4631. /* this dailink has playback support */
  4632. .ignore_pmdown_time = 1,
  4633. .codec_dai_name = "snd-soc-dummy-dai",
  4634. .codec_name = "snd-soc-dummy",
  4635. },
  4636. {
  4637. .name = "MSM AFE-PCM RX",
  4638. .stream_name = "AFE-PROXY RX",
  4639. .cpu_dai_name = "msm-dai-q6-dev.241",
  4640. .codec_name = "msm-stub-codec.1",
  4641. .codec_dai_name = "msm-stub-rx",
  4642. .platform_name = "msm-pcm-afe",
  4643. .dpcm_playback = 1,
  4644. .ignore_suspend = 1,
  4645. /* this dainlink has playback support */
  4646. .ignore_pmdown_time = 1,
  4647. },
  4648. {
  4649. .name = "MSM AFE-PCM TX",
  4650. .stream_name = "AFE-PROXY TX",
  4651. .cpu_dai_name = "msm-dai-q6-dev.240",
  4652. .codec_name = "msm-stub-codec.1",
  4653. .codec_dai_name = "msm-stub-tx",
  4654. .platform_name = "msm-pcm-afe",
  4655. .dpcm_capture = 1,
  4656. .ignore_suspend = 1,
  4657. },
  4658. {
  4659. .name = MSM_DAILINK_NAME(Compress1),
  4660. .stream_name = "Compress1",
  4661. .cpu_dai_name = "MultiMedia4",
  4662. .platform_name = "msm-compress-dsp",
  4663. .dynamic = 1,
  4664. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4665. .dpcm_playback = 1,
  4666. .dpcm_capture = 1,
  4667. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4668. SND_SOC_DPCM_TRIGGER_POST},
  4669. .codec_dai_name = "snd-soc-dummy-dai",
  4670. .codec_name = "snd-soc-dummy",
  4671. .ignore_suspend = 1,
  4672. .ignore_pmdown_time = 1,
  4673. /* this dainlink has playback support */
  4674. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4675. },
  4676. {
  4677. .name = "AUXPCM Hostless",
  4678. .stream_name = "AUXPCM Hostless",
  4679. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4680. .platform_name = "msm-pcm-hostless",
  4681. .dynamic = 1,
  4682. .dpcm_playback = 1,
  4683. .dpcm_capture = 1,
  4684. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4685. SND_SOC_DPCM_TRIGGER_POST},
  4686. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4687. .ignore_suspend = 1,
  4688. /* this dainlink has playback support */
  4689. .ignore_pmdown_time = 1,
  4690. .codec_dai_name = "snd-soc-dummy-dai",
  4691. .codec_name = "snd-soc-dummy",
  4692. },
  4693. {
  4694. .name = "SLIMBUS_1 Hostless",
  4695. .stream_name = "SLIMBUS_1 Hostless",
  4696. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  4697. .platform_name = "msm-pcm-hostless",
  4698. .dynamic = 1,
  4699. .dpcm_playback = 1,
  4700. .dpcm_capture = 1,
  4701. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4702. SND_SOC_DPCM_TRIGGER_POST},
  4703. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4704. .ignore_suspend = 1,
  4705. /* this dailink has playback support */
  4706. .ignore_pmdown_time = 1,
  4707. .codec_dai_name = "snd-soc-dummy-dai",
  4708. .codec_name = "snd-soc-dummy",
  4709. },
  4710. {
  4711. .name = "SLIMBUS_3 Hostless",
  4712. .stream_name = "SLIMBUS_3 Hostless",
  4713. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  4714. .platform_name = "msm-pcm-hostless",
  4715. .dynamic = 1,
  4716. .dpcm_playback = 1,
  4717. .dpcm_capture = 1,
  4718. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4719. SND_SOC_DPCM_TRIGGER_POST},
  4720. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4721. .ignore_suspend = 1,
  4722. /* this dailink has playback support */
  4723. .ignore_pmdown_time = 1,
  4724. .codec_dai_name = "snd-soc-dummy-dai",
  4725. .codec_name = "snd-soc-dummy",
  4726. },
  4727. {
  4728. .name = "SLIMBUS_4 Hostless",
  4729. .stream_name = "SLIMBUS_4 Hostless",
  4730. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  4731. .platform_name = "msm-pcm-hostless",
  4732. .dynamic = 1,
  4733. .dpcm_playback = 1,
  4734. .dpcm_capture = 1,
  4735. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4736. SND_SOC_DPCM_TRIGGER_POST},
  4737. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4738. .ignore_suspend = 1,
  4739. /* this dailink has playback support */
  4740. .ignore_pmdown_time = 1,
  4741. .codec_dai_name = "snd-soc-dummy-dai",
  4742. .codec_name = "snd-soc-dummy",
  4743. },
  4744. {
  4745. .name = MSM_DAILINK_NAME(LowLatency),
  4746. .stream_name = "MultiMedia5",
  4747. .cpu_dai_name = "MultiMedia5",
  4748. .platform_name = "msm-pcm-dsp.1",
  4749. .dynamic = 1,
  4750. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4751. .dpcm_playback = 1,
  4752. .dpcm_capture = 1,
  4753. .codec_dai_name = "snd-soc-dummy-dai",
  4754. .codec_name = "snd-soc-dummy",
  4755. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4756. SND_SOC_DPCM_TRIGGER_POST},
  4757. .ignore_suspend = 1,
  4758. /* this dainlink has playback support */
  4759. .ignore_pmdown_time = 1,
  4760. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4761. .ops = &msm_fe_qos_ops,
  4762. },
  4763. {
  4764. .name = "Listen 1 Audio Service",
  4765. .stream_name = "Listen 1 Audio Service",
  4766. .cpu_dai_name = "LSM1",
  4767. .platform_name = "msm-lsm-client",
  4768. .dynamic = 1,
  4769. .dpcm_capture = 1,
  4770. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4771. SND_SOC_DPCM_TRIGGER_POST },
  4772. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4773. .ignore_suspend = 1,
  4774. .codec_dai_name = "snd-soc-dummy-dai",
  4775. .codec_name = "snd-soc-dummy",
  4776. .id = MSM_FRONTEND_DAI_LSM1,
  4777. },
  4778. /* Multiple Tunnel instances */
  4779. {
  4780. .name = MSM_DAILINK_NAME(Compress2),
  4781. .stream_name = "Compress2",
  4782. .cpu_dai_name = "MultiMedia7",
  4783. .platform_name = "msm-compress-dsp",
  4784. .dynamic = 1,
  4785. .dpcm_playback = 1,
  4786. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4787. SND_SOC_DPCM_TRIGGER_POST},
  4788. .codec_dai_name = "snd-soc-dummy-dai",
  4789. .codec_name = "snd-soc-dummy",
  4790. .ignore_suspend = 1,
  4791. .ignore_pmdown_time = 1,
  4792. /* this dainlink has playback support */
  4793. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4794. },
  4795. {
  4796. .name = MSM_DAILINK_NAME(MultiMedia10),
  4797. .stream_name = "MultiMedia10",
  4798. .cpu_dai_name = "MultiMedia10",
  4799. .platform_name = "msm-pcm-dsp.1",
  4800. .dynamic = 1,
  4801. .dpcm_playback = 1,
  4802. .dpcm_capture = 1,
  4803. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4804. SND_SOC_DPCM_TRIGGER_POST},
  4805. .codec_dai_name = "snd-soc-dummy-dai",
  4806. .codec_name = "snd-soc-dummy",
  4807. .ignore_suspend = 1,
  4808. .ignore_pmdown_time = 1,
  4809. /* this dainlink has playback support */
  4810. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4811. },
  4812. {
  4813. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4814. .stream_name = "MM_NOIRQ",
  4815. .cpu_dai_name = "MultiMedia8",
  4816. .platform_name = "msm-pcm-dsp-noirq",
  4817. .dynamic = 1,
  4818. .dpcm_playback = 1,
  4819. .dpcm_capture = 1,
  4820. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4821. SND_SOC_DPCM_TRIGGER_POST},
  4822. .codec_dai_name = "snd-soc-dummy-dai",
  4823. .codec_name = "snd-soc-dummy",
  4824. .ignore_suspend = 1,
  4825. .ignore_pmdown_time = 1,
  4826. /* this dainlink has playback support */
  4827. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4828. .ops = &msm_fe_qos_ops,
  4829. },
  4830. /* HDMI Hostless */
  4831. {
  4832. .name = "HDMI_RX_HOSTLESS",
  4833. .stream_name = "HDMI_RX_HOSTLESS",
  4834. .cpu_dai_name = "HDMI_HOSTLESS",
  4835. .platform_name = "msm-pcm-hostless",
  4836. .dynamic = 1,
  4837. .dpcm_playback = 1,
  4838. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4839. SND_SOC_DPCM_TRIGGER_POST},
  4840. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4841. .ignore_suspend = 1,
  4842. .ignore_pmdown_time = 1,
  4843. .codec_dai_name = "snd-soc-dummy-dai",
  4844. .codec_name = "snd-soc-dummy",
  4845. },
  4846. {
  4847. .name = "VoiceMMode2",
  4848. .stream_name = "VoiceMMode2",
  4849. .cpu_dai_name = "VoiceMMode2",
  4850. .platform_name = "msm-pcm-voice",
  4851. .dynamic = 1,
  4852. .dpcm_playback = 1,
  4853. .dpcm_capture = 1,
  4854. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4855. SND_SOC_DPCM_TRIGGER_POST},
  4856. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4857. .ignore_suspend = 1,
  4858. .ignore_pmdown_time = 1,
  4859. .codec_dai_name = "snd-soc-dummy-dai",
  4860. .codec_name = "snd-soc-dummy",
  4861. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4862. },
  4863. /* LSM FE */
  4864. {
  4865. .name = "Listen 2 Audio Service",
  4866. .stream_name = "Listen 2 Audio Service",
  4867. .cpu_dai_name = "LSM2",
  4868. .platform_name = "msm-lsm-client",
  4869. .dynamic = 1,
  4870. .dpcm_capture = 1,
  4871. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4872. SND_SOC_DPCM_TRIGGER_POST },
  4873. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4874. .ignore_suspend = 1,
  4875. .codec_dai_name = "snd-soc-dummy-dai",
  4876. .codec_name = "snd-soc-dummy",
  4877. .id = MSM_FRONTEND_DAI_LSM2,
  4878. },
  4879. {
  4880. .name = "Listen 3 Audio Service",
  4881. .stream_name = "Listen 3 Audio Service",
  4882. .cpu_dai_name = "LSM3",
  4883. .platform_name = "msm-lsm-client",
  4884. .dynamic = 1,
  4885. .dpcm_capture = 1,
  4886. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4887. SND_SOC_DPCM_TRIGGER_POST },
  4888. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4889. .ignore_suspend = 1,
  4890. .codec_dai_name = "snd-soc-dummy-dai",
  4891. .codec_name = "snd-soc-dummy",
  4892. .id = MSM_FRONTEND_DAI_LSM3,
  4893. },
  4894. {
  4895. .name = "Listen 4 Audio Service",
  4896. .stream_name = "Listen 4 Audio Service",
  4897. .cpu_dai_name = "LSM4",
  4898. .platform_name = "msm-lsm-client",
  4899. .dynamic = 1,
  4900. .dpcm_capture = 1,
  4901. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4902. SND_SOC_DPCM_TRIGGER_POST },
  4903. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4904. .ignore_suspend = 1,
  4905. .codec_dai_name = "snd-soc-dummy-dai",
  4906. .codec_name = "snd-soc-dummy",
  4907. .id = MSM_FRONTEND_DAI_LSM4,
  4908. },
  4909. {
  4910. .name = "Listen 5 Audio Service",
  4911. .stream_name = "Listen 5 Audio Service",
  4912. .cpu_dai_name = "LSM5",
  4913. .platform_name = "msm-lsm-client",
  4914. .dynamic = 1,
  4915. .dpcm_capture = 1,
  4916. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4917. SND_SOC_DPCM_TRIGGER_POST },
  4918. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4919. .ignore_suspend = 1,
  4920. .codec_dai_name = "snd-soc-dummy-dai",
  4921. .codec_name = "snd-soc-dummy",
  4922. .id = MSM_FRONTEND_DAI_LSM5,
  4923. },
  4924. {
  4925. .name = "Listen 6 Audio Service",
  4926. .stream_name = "Listen 6 Audio Service",
  4927. .cpu_dai_name = "LSM6",
  4928. .platform_name = "msm-lsm-client",
  4929. .dynamic = 1,
  4930. .dpcm_capture = 1,
  4931. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4932. SND_SOC_DPCM_TRIGGER_POST },
  4933. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4934. .ignore_suspend = 1,
  4935. .codec_dai_name = "snd-soc-dummy-dai",
  4936. .codec_name = "snd-soc-dummy",
  4937. .id = MSM_FRONTEND_DAI_LSM6,
  4938. },
  4939. {
  4940. .name = "Listen 7 Audio Service",
  4941. .stream_name = "Listen 7 Audio Service",
  4942. .cpu_dai_name = "LSM7",
  4943. .platform_name = "msm-lsm-client",
  4944. .dynamic = 1,
  4945. .dpcm_capture = 1,
  4946. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4947. SND_SOC_DPCM_TRIGGER_POST },
  4948. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4949. .ignore_suspend = 1,
  4950. .codec_dai_name = "snd-soc-dummy-dai",
  4951. .codec_name = "snd-soc-dummy",
  4952. .id = MSM_FRONTEND_DAI_LSM7,
  4953. },
  4954. {
  4955. .name = "Listen 8 Audio Service",
  4956. .stream_name = "Listen 8 Audio Service",
  4957. .cpu_dai_name = "LSM8",
  4958. .platform_name = "msm-lsm-client",
  4959. .dynamic = 1,
  4960. .dpcm_capture = 1,
  4961. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4962. SND_SOC_DPCM_TRIGGER_POST },
  4963. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4964. .ignore_suspend = 1,
  4965. .codec_dai_name = "snd-soc-dummy-dai",
  4966. .codec_name = "snd-soc-dummy",
  4967. .id = MSM_FRONTEND_DAI_LSM8,
  4968. },
  4969. {
  4970. .name = MSM_DAILINK_NAME(Media9),
  4971. .stream_name = "MultiMedia9",
  4972. .cpu_dai_name = "MultiMedia9",
  4973. .platform_name = "msm-pcm-dsp.0",
  4974. .dynamic = 1,
  4975. .dpcm_playback = 1,
  4976. .dpcm_capture = 1,
  4977. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4978. SND_SOC_DPCM_TRIGGER_POST},
  4979. .codec_dai_name = "snd-soc-dummy-dai",
  4980. .codec_name = "snd-soc-dummy",
  4981. .ignore_suspend = 1,
  4982. /* this dainlink has playback support */
  4983. .ignore_pmdown_time = 1,
  4984. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4985. },
  4986. {
  4987. .name = MSM_DAILINK_NAME(Compress4),
  4988. .stream_name = "Compress4",
  4989. .cpu_dai_name = "MultiMedia11",
  4990. .platform_name = "msm-compress-dsp",
  4991. .dynamic = 1,
  4992. .dpcm_playback = 1,
  4993. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4994. SND_SOC_DPCM_TRIGGER_POST},
  4995. .codec_dai_name = "snd-soc-dummy-dai",
  4996. .codec_name = "snd-soc-dummy",
  4997. .ignore_suspend = 1,
  4998. .ignore_pmdown_time = 1,
  4999. /* this dainlink has playback support */
  5000. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5001. },
  5002. {
  5003. .name = MSM_DAILINK_NAME(Compress5),
  5004. .stream_name = "Compress5",
  5005. .cpu_dai_name = "MultiMedia12",
  5006. .platform_name = "msm-compress-dsp",
  5007. .dynamic = 1,
  5008. .dpcm_playback = 1,
  5009. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5010. SND_SOC_DPCM_TRIGGER_POST},
  5011. .codec_dai_name = "snd-soc-dummy-dai",
  5012. .codec_name = "snd-soc-dummy",
  5013. .ignore_suspend = 1,
  5014. .ignore_pmdown_time = 1,
  5015. /* this dainlink has playback support */
  5016. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5017. },
  5018. {
  5019. .name = MSM_DAILINK_NAME(Compress6),
  5020. .stream_name = "Compress6",
  5021. .cpu_dai_name = "MultiMedia13",
  5022. .platform_name = "msm-compress-dsp",
  5023. .dynamic = 1,
  5024. .dpcm_playback = 1,
  5025. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5026. SND_SOC_DPCM_TRIGGER_POST},
  5027. .codec_dai_name = "snd-soc-dummy-dai",
  5028. .codec_name = "snd-soc-dummy",
  5029. .ignore_suspend = 1,
  5030. .ignore_pmdown_time = 1,
  5031. /* this dainlink has playback support */
  5032. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5033. },
  5034. {
  5035. .name = MSM_DAILINK_NAME(Compress7),
  5036. .stream_name = "Compress7",
  5037. .cpu_dai_name = "MultiMedia14",
  5038. .platform_name = "msm-compress-dsp",
  5039. .dynamic = 1,
  5040. .dpcm_playback = 1,
  5041. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5042. SND_SOC_DPCM_TRIGGER_POST},
  5043. .codec_dai_name = "snd-soc-dummy-dai",
  5044. .codec_name = "snd-soc-dummy",
  5045. .ignore_suspend = 1,
  5046. .ignore_pmdown_time = 1,
  5047. /* this dainlink has playback support */
  5048. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5049. },
  5050. {
  5051. .name = MSM_DAILINK_NAME(Compress8),
  5052. .stream_name = "Compress8",
  5053. .cpu_dai_name = "MultiMedia15",
  5054. .platform_name = "msm-compress-dsp",
  5055. .dynamic = 1,
  5056. .dpcm_playback = 1,
  5057. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5058. SND_SOC_DPCM_TRIGGER_POST},
  5059. .codec_dai_name = "snd-soc-dummy-dai",
  5060. .codec_name = "snd-soc-dummy",
  5061. .ignore_suspend = 1,
  5062. .ignore_pmdown_time = 1,
  5063. /* this dainlink has playback support */
  5064. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5065. },
  5066. {
  5067. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5068. .stream_name = "MM_NOIRQ_2",
  5069. .cpu_dai_name = "MultiMedia16",
  5070. .platform_name = "msm-pcm-dsp-noirq",
  5071. .dynamic = 1,
  5072. .dpcm_playback = 1,
  5073. .dpcm_capture = 1,
  5074. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5075. SND_SOC_DPCM_TRIGGER_POST},
  5076. .codec_dai_name = "snd-soc-dummy-dai",
  5077. .codec_name = "snd-soc-dummy",
  5078. .ignore_suspend = 1,
  5079. .ignore_pmdown_time = 1,
  5080. /* this dainlink has playback support */
  5081. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5082. },
  5083. {
  5084. .name = "SLIMBUS_8 Hostless",
  5085. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5086. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5087. .platform_name = "msm-pcm-hostless",
  5088. .dynamic = 1,
  5089. .dpcm_capture = 1,
  5090. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5091. SND_SOC_DPCM_TRIGGER_POST},
  5092. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5093. .ignore_suspend = 1,
  5094. .codec_dai_name = "snd-soc-dummy-dai",
  5095. .codec_name = "snd-soc-dummy",
  5096. },
  5097. };
  5098. static struct snd_soc_dai_link msm_tasha_fe_dai_links[] = {
  5099. /* Ultrasound RX DAI Link */
  5100. {
  5101. .name = "SLIMBUS_2 Hostless Playback",
  5102. .stream_name = "SLIMBUS_2 Hostless Playback",
  5103. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5104. .platform_name = "msm-pcm-hostless",
  5105. .codec_name = "tasha_codec",
  5106. .codec_dai_name = "tasha_rx2",
  5107. .ignore_suspend = 1,
  5108. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5109. .ops = &msm_slimbus_2_be_ops,
  5110. },
  5111. /* Ultrasound TX DAI Link */
  5112. {
  5113. .name = "SLIMBUS_2 Hostless Capture",
  5114. .stream_name = "SLIMBUS_2 Hostless Capture",
  5115. .cpu_dai_name = "msm-dai-q6-dev.16389",
  5116. .platform_name = "msm-pcm-hostless",
  5117. .codec_name = "tasha_codec",
  5118. .codec_dai_name = "tasha_tx2",
  5119. .ignore_suspend = 1,
  5120. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5121. .ops = &msm_slimbus_2_be_ops,
  5122. },
  5123. {
  5124. .name = "SLIMBUS_6 Hostless Playback",
  5125. .stream_name = "SLIMBUS_6 Hostless",
  5126. .cpu_dai_name = "SLIMBUS6_HOSTLESS",
  5127. .platform_name = "msm-pcm-hostless",
  5128. .dynamic = 1,
  5129. .dpcm_playback = 1,
  5130. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5131. SND_SOC_DPCM_TRIGGER_POST},
  5132. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5133. .ignore_suspend = 1,
  5134. /* this dailink has playback support */
  5135. .ignore_pmdown_time = 1,
  5136. .codec_dai_name = "snd-soc-dummy-dai",
  5137. .codec_name = "snd-soc-dummy",
  5138. },
  5139. };
  5140. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5141. {
  5142. .name = MSM_DAILINK_NAME(ASM Loopback),
  5143. .stream_name = "MultiMedia6",
  5144. .cpu_dai_name = "MultiMedia6",
  5145. .platform_name = "msm-pcm-loopback",
  5146. .dynamic = 1,
  5147. .dpcm_playback = 1,
  5148. .dpcm_capture = 1,
  5149. .codec_dai_name = "snd-soc-dummy-dai",
  5150. .codec_name = "snd-soc-dummy",
  5151. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5152. SND_SOC_DPCM_TRIGGER_POST},
  5153. .ignore_suspend = 1,
  5154. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5155. .ignore_pmdown_time = 1,
  5156. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5157. },
  5158. {
  5159. .name = "USB Audio Hostless",
  5160. .stream_name = "USB Audio Hostless",
  5161. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5162. .platform_name = "msm-pcm-hostless",
  5163. .dynamic = 1,
  5164. .dpcm_playback = 1,
  5165. .dpcm_capture = 1,
  5166. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5167. SND_SOC_DPCM_TRIGGER_POST},
  5168. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5169. .ignore_suspend = 1,
  5170. .ignore_pmdown_time = 1,
  5171. .codec_dai_name = "snd-soc-dummy-dai",
  5172. .codec_name = "snd-soc-dummy",
  5173. },
  5174. {
  5175. .name = "SLIMBUS_7 Hostless",
  5176. .stream_name = "SLIMBUS_7 Hostless",
  5177. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5178. .platform_name = "msm-pcm-hostless",
  5179. .dynamic = 1,
  5180. .dpcm_capture = 1,
  5181. .dpcm_playback = 1,
  5182. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5183. SND_SOC_DPCM_TRIGGER_POST},
  5184. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5185. .ignore_suspend = 1,
  5186. .ignore_pmdown_time = 1,
  5187. .codec_dai_name = "snd-soc-dummy-dai",
  5188. .codec_name = "snd-soc-dummy",
  5189. },
  5190. };
  5191. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5192. /* Backend AFE DAI Links */
  5193. {
  5194. .name = LPASS_BE_AFE_PCM_RX,
  5195. .stream_name = "AFE Playback",
  5196. .cpu_dai_name = "msm-dai-q6-dev.224",
  5197. .platform_name = "msm-pcm-routing",
  5198. .codec_name = "msm-stub-codec.1",
  5199. .codec_dai_name = "msm-stub-rx",
  5200. .no_pcm = 1,
  5201. .dpcm_playback = 1,
  5202. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5203. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5204. /* this dainlink has playback support */
  5205. .ignore_pmdown_time = 1,
  5206. .ignore_suspend = 1,
  5207. },
  5208. {
  5209. .name = LPASS_BE_AFE_PCM_TX,
  5210. .stream_name = "AFE Capture",
  5211. .cpu_dai_name = "msm-dai-q6-dev.225",
  5212. .platform_name = "msm-pcm-routing",
  5213. .codec_name = "msm-stub-codec.1",
  5214. .codec_dai_name = "msm-stub-tx",
  5215. .no_pcm = 1,
  5216. .dpcm_capture = 1,
  5217. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5218. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5219. .ignore_suspend = 1,
  5220. },
  5221. /* Incall Record Uplink BACK END DAI Link */
  5222. {
  5223. .name = LPASS_BE_INCALL_RECORD_TX,
  5224. .stream_name = "Voice Uplink Capture",
  5225. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5226. .platform_name = "msm-pcm-routing",
  5227. .codec_name = "msm-stub-codec.1",
  5228. .codec_dai_name = "msm-stub-tx",
  5229. .no_pcm = 1,
  5230. .dpcm_capture = 1,
  5231. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5232. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5233. .ignore_suspend = 1,
  5234. },
  5235. /* Incall Record Downlink BACK END DAI Link */
  5236. {
  5237. .name = LPASS_BE_INCALL_RECORD_RX,
  5238. .stream_name = "Voice Downlink Capture",
  5239. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5240. .platform_name = "msm-pcm-routing",
  5241. .codec_name = "msm-stub-codec.1",
  5242. .codec_dai_name = "msm-stub-tx",
  5243. .no_pcm = 1,
  5244. .dpcm_capture = 1,
  5245. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5246. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5247. .ignore_suspend = 1,
  5248. },
  5249. /* Incall Music BACK END DAI Link */
  5250. {
  5251. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5252. .stream_name = "Voice Farend Playback",
  5253. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5254. .platform_name = "msm-pcm-routing",
  5255. .codec_name = "msm-stub-codec.1",
  5256. .codec_dai_name = "msm-stub-rx",
  5257. .no_pcm = 1,
  5258. .dpcm_playback = 1,
  5259. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5260. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5261. .ignore_suspend = 1,
  5262. .ignore_pmdown_time = 1,
  5263. },
  5264. /* Incall Music 2 BACK END DAI Link */
  5265. {
  5266. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5267. .stream_name = "Voice2 Farend Playback",
  5268. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5269. .platform_name = "msm-pcm-routing",
  5270. .codec_name = "msm-stub-codec.1",
  5271. .codec_dai_name = "msm-stub-rx",
  5272. .no_pcm = 1,
  5273. .dpcm_playback = 1,
  5274. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5275. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5276. .ignore_suspend = 1,
  5277. .ignore_pmdown_time = 1,
  5278. },
  5279. {
  5280. .name = LPASS_BE_USB_AUDIO_RX,
  5281. .stream_name = "USB Audio Playback",
  5282. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5283. .platform_name = "msm-pcm-routing",
  5284. .codec_name = "msm-stub-codec.1",
  5285. .codec_dai_name = "msm-stub-rx",
  5286. .no_pcm = 1,
  5287. .dpcm_playback = 1,
  5288. .id = MSM_BACKEND_DAI_USB_RX,
  5289. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5290. .ignore_pmdown_time = 1,
  5291. .ignore_suspend = 1,
  5292. },
  5293. {
  5294. .name = LPASS_BE_USB_AUDIO_TX,
  5295. .stream_name = "USB Audio Capture",
  5296. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5297. .platform_name = "msm-pcm-routing",
  5298. .codec_name = "msm-stub-codec.1",
  5299. .codec_dai_name = "msm-stub-tx",
  5300. .no_pcm = 1,
  5301. .dpcm_capture = 1,
  5302. .id = MSM_BACKEND_DAI_USB_TX,
  5303. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5304. .ignore_suspend = 1,
  5305. },
  5306. {
  5307. .name = LPASS_BE_PRI_TDM_RX_0,
  5308. .stream_name = "Primary TDM0 Playback",
  5309. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5310. .platform_name = "msm-pcm-routing",
  5311. .codec_name = "msm-stub-codec.1",
  5312. .codec_dai_name = "msm-stub-rx",
  5313. .no_pcm = 1,
  5314. .dpcm_playback = 1,
  5315. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5316. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5317. .ops = &qcs405_tdm_be_ops,
  5318. .ignore_suspend = 1,
  5319. .ignore_pmdown_time = 1,
  5320. },
  5321. {
  5322. .name = LPASS_BE_PRI_TDM_TX_0,
  5323. .stream_name = "Primary TDM0 Capture",
  5324. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5325. .platform_name = "msm-pcm-routing",
  5326. .codec_name = "msm-stub-codec.1",
  5327. .codec_dai_name = "msm-stub-tx",
  5328. .no_pcm = 1,
  5329. .dpcm_capture = 1,
  5330. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5331. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5332. .ops = &qcs405_tdm_be_ops,
  5333. .ignore_suspend = 1,
  5334. },
  5335. {
  5336. .name = LPASS_BE_SEC_TDM_RX_0,
  5337. .stream_name = "Secondary TDM0 Playback",
  5338. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5339. .platform_name = "msm-pcm-routing",
  5340. .codec_name = "msm-stub-codec.1",
  5341. .codec_dai_name = "msm-stub-rx",
  5342. .no_pcm = 1,
  5343. .dpcm_playback = 1,
  5344. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5345. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5346. .ops = &qcs405_tdm_be_ops,
  5347. .ignore_suspend = 1,
  5348. .ignore_pmdown_time = 1,
  5349. },
  5350. {
  5351. .name = LPASS_BE_SEC_TDM_TX_0,
  5352. .stream_name = "Secondary TDM0 Capture",
  5353. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5354. .platform_name = "msm-pcm-routing",
  5355. .codec_name = "msm-stub-codec.1",
  5356. .codec_dai_name = "msm-stub-tx",
  5357. .no_pcm = 1,
  5358. .dpcm_capture = 1,
  5359. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5360. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5361. .ops = &qcs405_tdm_be_ops,
  5362. .ignore_suspend = 1,
  5363. },
  5364. {
  5365. .name = LPASS_BE_TERT_TDM_RX_0,
  5366. .stream_name = "Tertiary TDM0 Playback",
  5367. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5368. .platform_name = "msm-pcm-routing",
  5369. .codec_name = "msm-stub-codec.1",
  5370. .codec_dai_name = "msm-stub-rx",
  5371. .no_pcm = 1,
  5372. .dpcm_playback = 1,
  5373. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5374. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5375. .ops = &qcs405_tdm_be_ops,
  5376. .ignore_suspend = 1,
  5377. .ignore_pmdown_time = 1,
  5378. },
  5379. {
  5380. .name = LPASS_BE_TERT_TDM_TX_0,
  5381. .stream_name = "Tertiary TDM0 Capture",
  5382. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5383. .platform_name = "msm-pcm-routing",
  5384. .codec_name = "msm-stub-codec.1",
  5385. .codec_dai_name = "msm-stub-tx",
  5386. .no_pcm = 1,
  5387. .dpcm_capture = 1,
  5388. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5389. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5390. .ops = &qcs405_tdm_be_ops,
  5391. .ignore_suspend = 1,
  5392. },
  5393. {
  5394. .name = LPASS_BE_QUAT_TDM_RX_0,
  5395. .stream_name = "Quaternary TDM0 Playback",
  5396. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5397. .platform_name = "msm-pcm-routing",
  5398. .codec_name = "msm-stub-codec.1",
  5399. .codec_dai_name = "msm-stub-rx",
  5400. .no_pcm = 1,
  5401. .dpcm_playback = 1,
  5402. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5403. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5404. .ops = &qcs405_tdm_be_ops,
  5405. .ignore_suspend = 1,
  5406. .ignore_pmdown_time = 1,
  5407. },
  5408. {
  5409. .name = LPASS_BE_QUAT_TDM_TX_0,
  5410. .stream_name = "Quaternary TDM0 Capture",
  5411. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5412. .platform_name = "msm-pcm-routing",
  5413. .codec_name = "msm-stub-codec.1",
  5414. .codec_dai_name = "msm-stub-tx",
  5415. .no_pcm = 1,
  5416. .dpcm_capture = 1,
  5417. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5418. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5419. .ops = &qcs405_tdm_be_ops,
  5420. .ignore_suspend = 1,
  5421. },
  5422. };
  5423. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5424. {
  5425. .name = LPASS_BE_SLIMBUS_0_RX,
  5426. .stream_name = "Slimbus Playback",
  5427. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5428. .platform_name = "msm-pcm-routing",
  5429. .codec_name = "tasha_codec",
  5430. .codec_dai_name = "tasha_rx1",
  5431. .no_pcm = 1,
  5432. .dpcm_playback = 1,
  5433. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5434. .init = &msm_audrx_init,
  5435. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5436. /* this dainlink has playback support */
  5437. .ignore_pmdown_time = 1,
  5438. .ignore_suspend = 1,
  5439. .ops = &msm_be_ops,
  5440. },
  5441. {
  5442. .name = LPASS_BE_SLIMBUS_0_TX,
  5443. .stream_name = "Slimbus Capture",
  5444. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5445. .platform_name = "msm-pcm-routing",
  5446. .codec_name = "tasha_codec",
  5447. .codec_dai_name = "tasha_tx1",
  5448. .no_pcm = 1,
  5449. .dpcm_capture = 1,
  5450. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5451. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5452. .ignore_suspend = 1,
  5453. .ops = &msm_be_ops,
  5454. },
  5455. {
  5456. .name = LPASS_BE_SLIMBUS_1_RX,
  5457. .stream_name = "Slimbus1 Playback",
  5458. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5459. .platform_name = "msm-pcm-routing",
  5460. .codec_name = "tasha_codec",
  5461. .codec_dai_name = "tasha_rx1",
  5462. .no_pcm = 1,
  5463. .dpcm_playback = 1,
  5464. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5465. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5466. .ops = &msm_be_ops,
  5467. /* dai link has playback support */
  5468. .ignore_pmdown_time = 1,
  5469. .ignore_suspend = 1,
  5470. },
  5471. {
  5472. .name = LPASS_BE_SLIMBUS_1_TX,
  5473. .stream_name = "Slimbus1 Capture",
  5474. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5475. .platform_name = "msm-pcm-routing",
  5476. .codec_name = "tasha_codec",
  5477. .codec_dai_name = "tasha_tx3",
  5478. .no_pcm = 1,
  5479. .dpcm_capture = 1,
  5480. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5481. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5482. .ops = &msm_be_ops,
  5483. .ignore_suspend = 1,
  5484. },
  5485. {
  5486. .name = LPASS_BE_SLIMBUS_2_RX,
  5487. .stream_name = "Slimbus2 Playback",
  5488. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5489. .platform_name = "msm-pcm-routing",
  5490. .codec_name = "tasha_codec",
  5491. .codec_dai_name = "tasha_rx2",
  5492. .no_pcm = 1,
  5493. .dpcm_playback = 1,
  5494. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  5495. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5496. .ops = &msm_be_ops,
  5497. .ignore_pmdown_time = 1,
  5498. .ignore_suspend = 1,
  5499. },
  5500. {
  5501. .name = LPASS_BE_SLIMBUS_3_RX,
  5502. .stream_name = "Slimbus3 Playback",
  5503. .cpu_dai_name = "msm-dai-q6-dev.16390",
  5504. .platform_name = "msm-pcm-routing",
  5505. .codec_name = "tasha_codec",
  5506. .codec_dai_name = "tasha_rx1",
  5507. .no_pcm = 1,
  5508. .dpcm_playback = 1,
  5509. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  5510. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5511. .ops = &msm_be_ops,
  5512. /* dai link has playback support */
  5513. .ignore_pmdown_time = 1,
  5514. .ignore_suspend = 1,
  5515. },
  5516. {
  5517. .name = LPASS_BE_SLIMBUS_3_TX,
  5518. .stream_name = "Slimbus3 Capture",
  5519. .cpu_dai_name = "msm-dai-q6-dev.16391",
  5520. .platform_name = "msm-pcm-routing",
  5521. .codec_name = "tasha_codec",
  5522. .codec_dai_name = "tasha_tx1",
  5523. .no_pcm = 1,
  5524. .dpcm_capture = 1,
  5525. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  5526. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5527. .ops = &msm_be_ops,
  5528. .ignore_suspend = 1,
  5529. },
  5530. {
  5531. .name = LPASS_BE_SLIMBUS_4_RX,
  5532. .stream_name = "Slimbus4 Playback",
  5533. .cpu_dai_name = "msm-dai-q6-dev.16392",
  5534. .platform_name = "msm-pcm-routing",
  5535. .codec_name = "tasha_codec",
  5536. .codec_dai_name = "tasha_rx1",
  5537. .no_pcm = 1,
  5538. .dpcm_playback = 1,
  5539. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  5540. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5541. .ops = &msm_be_ops,
  5542. /* dai link has playback support */
  5543. .ignore_pmdown_time = 1,
  5544. .ignore_suspend = 1,
  5545. },
  5546. {
  5547. .name = LPASS_BE_SLIMBUS_5_RX,
  5548. .stream_name = "Slimbus5 Playback",
  5549. .cpu_dai_name = "msm-dai-q6-dev.16394",
  5550. .platform_name = "msm-pcm-routing",
  5551. .codec_name = "tasha_codec",
  5552. .codec_dai_name = "tasha_rx3",
  5553. .no_pcm = 1,
  5554. .dpcm_playback = 1,
  5555. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  5556. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5557. .ops = &msm_be_ops,
  5558. /* dai link has playback support */
  5559. .ignore_pmdown_time = 1,
  5560. .ignore_suspend = 1,
  5561. },
  5562. {
  5563. .name = LPASS_BE_SLIMBUS_6_RX,
  5564. .stream_name = "Slimbus6 Playback",
  5565. .cpu_dai_name = "msm-dai-q6-dev.16396",
  5566. .platform_name = "msm-pcm-routing",
  5567. .codec_name = "tasha_codec",
  5568. .codec_dai_name = "tasha_rx4",
  5569. .no_pcm = 1,
  5570. .dpcm_playback = 1,
  5571. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  5572. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5573. .ops = &msm_be_ops,
  5574. /* dai link has playback support */
  5575. .ignore_pmdown_time = 1,
  5576. .ignore_suspend = 1,
  5577. },
  5578. /* Slimbus VI Recording */
  5579. {
  5580. .name = LPASS_BE_SLIMBUS_TX_VI,
  5581. .stream_name = "Slimbus4 Capture",
  5582. .cpu_dai_name = "msm-dai-q6-dev.16393",
  5583. .platform_name = "msm-pcm-routing",
  5584. .codec_name = "tasha_codec",
  5585. .codec_dai_name = "tasha_vifeedback",
  5586. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  5587. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5588. .ops = &msm_be_ops,
  5589. .ignore_suspend = 1,
  5590. .no_pcm = 1,
  5591. .dpcm_capture = 1,
  5592. .ignore_pmdown_time = 1,
  5593. },
  5594. };
  5595. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5596. {
  5597. .name = LPASS_BE_SLIMBUS_7_RX,
  5598. .stream_name = "Slimbus7 Playback",
  5599. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5600. .platform_name = "msm-pcm-routing",
  5601. .codec_name = "btfmslim_slave",
  5602. /* BT codec driver determines capabilities based on
  5603. * dai name, bt codecdai name should always contains
  5604. * supported usecase information
  5605. */
  5606. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5607. .no_pcm = 1,
  5608. .dpcm_playback = 1,
  5609. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5610. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5611. .ops = &msm_wcn_ops,
  5612. /* dai link has playback support */
  5613. .ignore_pmdown_time = 1,
  5614. .ignore_suspend = 1,
  5615. },
  5616. {
  5617. .name = LPASS_BE_SLIMBUS_7_TX,
  5618. .stream_name = "Slimbus7 Capture",
  5619. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5620. .platform_name = "msm-pcm-routing",
  5621. .codec_name = "btfmslim_slave",
  5622. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5623. .no_pcm = 1,
  5624. .dpcm_capture = 1,
  5625. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5626. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5627. .ops = &msm_wcn_ops,
  5628. .ignore_suspend = 1,
  5629. },
  5630. {
  5631. .name = LPASS_BE_SLIMBUS_8_TX,
  5632. .stream_name = "Slimbus8 Capture",
  5633. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5634. .platform_name = "msm-pcm-routing",
  5635. .codec_name = "btfmslim_slave",
  5636. .codec_dai_name = "btfm_fm_slim_tx",
  5637. .no_pcm = 1,
  5638. .dpcm_capture = 1,
  5639. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5640. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5641. .init = &msm_wcn_init,
  5642. .ops = &msm_wcn_ops,
  5643. .ignore_suspend = 1,
  5644. },
  5645. };
  5646. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5647. {
  5648. .name = LPASS_BE_PRI_MI2S_RX,
  5649. .stream_name = "Primary MI2S Playback",
  5650. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5651. .platform_name = "msm-pcm-routing",
  5652. .codec_name = "msm-stub-codec.1",
  5653. .codec_dai_name = "msm-stub-rx",
  5654. .no_pcm = 1,
  5655. .dpcm_playback = 1,
  5656. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5657. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5658. .ops = &msm_mi2s_be_ops,
  5659. .ignore_suspend = 1,
  5660. .ignore_pmdown_time = 1,
  5661. },
  5662. {
  5663. .name = LPASS_BE_PRI_MI2S_TX,
  5664. .stream_name = "Primary MI2S Capture",
  5665. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5666. .platform_name = "msm-pcm-routing",
  5667. .codec_name = "msm-stub-codec.1",
  5668. .codec_dai_name = "msm-stub-tx",
  5669. .no_pcm = 1,
  5670. .dpcm_capture = 1,
  5671. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5672. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5673. .ops = &msm_mi2s_be_ops,
  5674. .ignore_suspend = 1,
  5675. },
  5676. {
  5677. .name = LPASS_BE_SEC_MI2S_RX,
  5678. .stream_name = "Secondary MI2S Playback",
  5679. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5680. .platform_name = "msm-pcm-routing",
  5681. .codec_name = "msm-stub-codec.1",
  5682. .codec_dai_name = "msm-stub-rx",
  5683. .no_pcm = 1,
  5684. .dpcm_playback = 1,
  5685. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5686. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5687. .ops = &msm_mi2s_be_ops,
  5688. .ignore_suspend = 1,
  5689. .ignore_pmdown_time = 1,
  5690. },
  5691. {
  5692. .name = LPASS_BE_SEC_MI2S_TX,
  5693. .stream_name = "Secondary MI2S Capture",
  5694. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5695. .platform_name = "msm-pcm-routing",
  5696. .codec_name = "msm-stub-codec.1",
  5697. .codec_dai_name = "msm-stub-tx",
  5698. .no_pcm = 1,
  5699. .dpcm_capture = 1,
  5700. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5701. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5702. .ops = &msm_mi2s_be_ops,
  5703. .ignore_suspend = 1,
  5704. },
  5705. {
  5706. .name = LPASS_BE_TERT_MI2S_RX,
  5707. .stream_name = "Tertiary MI2S Playback",
  5708. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5709. .platform_name = "msm-pcm-routing",
  5710. .codec_name = "msm-stub-codec.1",
  5711. .codec_dai_name = "msm-stub-rx",
  5712. .no_pcm = 1,
  5713. .dpcm_playback = 1,
  5714. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5715. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5716. .ops = &msm_mi2s_be_ops,
  5717. .ignore_suspend = 1,
  5718. .ignore_pmdown_time = 1,
  5719. },
  5720. {
  5721. .name = LPASS_BE_TERT_MI2S_TX,
  5722. .stream_name = "Tertiary MI2S Capture",
  5723. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5724. .platform_name = "msm-pcm-routing",
  5725. .codec_name = "msm-stub-codec.1",
  5726. .codec_dai_name = "msm-stub-tx",
  5727. .no_pcm = 1,
  5728. .dpcm_capture = 1,
  5729. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5730. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5731. .ops = &msm_mi2s_be_ops,
  5732. .ignore_suspend = 1,
  5733. },
  5734. {
  5735. .name = LPASS_BE_QUAT_MI2S_RX,
  5736. .stream_name = "Quaternary MI2S Playback",
  5737. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5738. .platform_name = "msm-pcm-routing",
  5739. .codec_name = "msm-stub-codec.1",
  5740. .codec_dai_name = "msm-stub-rx",
  5741. .no_pcm = 1,
  5742. .dpcm_playback = 1,
  5743. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5744. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5745. .ops = &msm_mi2s_be_ops,
  5746. .ignore_suspend = 1,
  5747. .ignore_pmdown_time = 1,
  5748. },
  5749. {
  5750. .name = LPASS_BE_QUAT_MI2S_TX,
  5751. .stream_name = "Quaternary MI2S Capture",
  5752. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5753. .platform_name = "msm-pcm-routing",
  5754. .codec_name = "msm-stub-codec.1",
  5755. .codec_dai_name = "msm-stub-tx",
  5756. .no_pcm = 1,
  5757. .dpcm_capture = 1,
  5758. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5759. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5760. .ops = &msm_mi2s_be_ops,
  5761. .ignore_suspend = 1,
  5762. },
  5763. {
  5764. .name = LPASS_BE_QUIN_MI2S_RX,
  5765. .stream_name = "Quinary MI2S Playback",
  5766. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5767. .platform_name = "msm-pcm-routing",
  5768. .codec_name = "msm-stub-codec.1",
  5769. .codec_dai_name = "msm-stub-rx",
  5770. .no_pcm = 1,
  5771. .dpcm_playback = 1,
  5772. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5773. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5774. .ops = &msm_mi2s_be_ops,
  5775. .ignore_suspend = 1,
  5776. .ignore_pmdown_time = 1,
  5777. },
  5778. {
  5779. .name = LPASS_BE_QUIN_MI2S_TX,
  5780. .stream_name = "Quinary MI2S Capture",
  5781. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5782. .platform_name = "msm-pcm-routing",
  5783. .codec_name = "msm-stub-codec.1",
  5784. .codec_dai_name = "msm-stub-tx",
  5785. .no_pcm = 1,
  5786. .dpcm_capture = 1,
  5787. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5788. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5789. .ops = &msm_mi2s_be_ops,
  5790. .ignore_suspend = 1,
  5791. },
  5792. };
  5793. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5794. /* Primary AUX PCM Backend DAI Links */
  5795. {
  5796. .name = LPASS_BE_AUXPCM_RX,
  5797. .stream_name = "AUX PCM Playback",
  5798. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5799. .platform_name = "msm-pcm-routing",
  5800. .codec_name = "msm-stub-codec.1",
  5801. .codec_dai_name = "msm-stub-rx",
  5802. .no_pcm = 1,
  5803. .dpcm_playback = 1,
  5804. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5805. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5806. .ignore_pmdown_time = 1,
  5807. .ignore_suspend = 1,
  5808. },
  5809. {
  5810. .name = LPASS_BE_AUXPCM_TX,
  5811. .stream_name = "AUX PCM Capture",
  5812. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5813. .platform_name = "msm-pcm-routing",
  5814. .codec_name = "msm-stub-codec.1",
  5815. .codec_dai_name = "msm-stub-tx",
  5816. .no_pcm = 1,
  5817. .dpcm_capture = 1,
  5818. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5819. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5820. .ignore_suspend = 1,
  5821. },
  5822. /* Secondary AUX PCM Backend DAI Links */
  5823. {
  5824. .name = LPASS_BE_SEC_AUXPCM_RX,
  5825. .stream_name = "Sec AUX PCM Playback",
  5826. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5827. .platform_name = "msm-pcm-routing",
  5828. .codec_name = "msm-stub-codec.1",
  5829. .codec_dai_name = "msm-stub-rx",
  5830. .no_pcm = 1,
  5831. .dpcm_playback = 1,
  5832. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5833. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5834. .ignore_pmdown_time = 1,
  5835. .ignore_suspend = 1,
  5836. },
  5837. {
  5838. .name = LPASS_BE_SEC_AUXPCM_TX,
  5839. .stream_name = "Sec AUX PCM Capture",
  5840. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5841. .platform_name = "msm-pcm-routing",
  5842. .codec_name = "msm-stub-codec.1",
  5843. .codec_dai_name = "msm-stub-tx",
  5844. .no_pcm = 1,
  5845. .dpcm_capture = 1,
  5846. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5847. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5848. .ignore_suspend = 1,
  5849. },
  5850. /* Tertiary AUX PCM Backend DAI Links */
  5851. {
  5852. .name = LPASS_BE_TERT_AUXPCM_RX,
  5853. .stream_name = "Tert AUX PCM Playback",
  5854. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5855. .platform_name = "msm-pcm-routing",
  5856. .codec_name = "msm-stub-codec.1",
  5857. .codec_dai_name = "msm-stub-rx",
  5858. .no_pcm = 1,
  5859. .dpcm_playback = 1,
  5860. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5861. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5862. .ignore_suspend = 1,
  5863. },
  5864. {
  5865. .name = LPASS_BE_TERT_AUXPCM_TX,
  5866. .stream_name = "Tert AUX PCM Capture",
  5867. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5868. .platform_name = "msm-pcm-routing",
  5869. .codec_name = "msm-stub-codec.1",
  5870. .codec_dai_name = "msm-stub-tx",
  5871. .no_pcm = 1,
  5872. .dpcm_capture = 1,
  5873. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5874. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5875. .ignore_suspend = 1,
  5876. },
  5877. /* Quaternary AUX PCM Backend DAI Links */
  5878. {
  5879. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5880. .stream_name = "Quat AUX PCM Playback",
  5881. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5882. .platform_name = "msm-pcm-routing",
  5883. .codec_name = "msm-stub-codec.1",
  5884. .codec_dai_name = "msm-stub-rx",
  5885. .no_pcm = 1,
  5886. .dpcm_playback = 1,
  5887. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5888. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5889. .ignore_pmdown_time = 1,
  5890. .ignore_suspend = 1,
  5891. },
  5892. {
  5893. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5894. .stream_name = "Quat AUX PCM Capture",
  5895. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5896. .platform_name = "msm-pcm-routing",
  5897. .codec_name = "msm-stub-codec.1",
  5898. .codec_dai_name = "msm-stub-tx",
  5899. .no_pcm = 1,
  5900. .dpcm_capture = 1,
  5901. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5902. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5903. .ignore_suspend = 1,
  5904. },
  5905. /* Quinary AUX PCM Backend DAI Links */
  5906. {
  5907. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5908. .stream_name = "Quin AUX PCM Playback",
  5909. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5910. .platform_name = "msm-pcm-routing",
  5911. .codec_name = "msm-stub-codec.1",
  5912. .codec_dai_name = "msm-stub-rx",
  5913. .no_pcm = 1,
  5914. .dpcm_playback = 1,
  5915. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5916. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5917. .ignore_pmdown_time = 1,
  5918. .ignore_suspend = 1,
  5919. },
  5920. {
  5921. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5922. .stream_name = "Quin AUX PCM Capture",
  5923. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5924. .platform_name = "msm-pcm-routing",
  5925. .codec_name = "msm-stub-codec.1",
  5926. .codec_dai_name = "msm-stub-tx",
  5927. .no_pcm = 1,
  5928. .dpcm_capture = 1,
  5929. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5930. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5931. .ignore_suspend = 1,
  5932. },
  5933. };
  5934. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  5935. /* WSA CDC DMA Backend DAI Links */
  5936. {
  5937. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  5938. .stream_name = "WSA CDC DMA0 Playback",
  5939. .cpu_dai_name = "msm-dai-cdc-dma.45056",
  5940. .platform_name = "msm-pcm-routing",
  5941. .codec_name = "bolero_codec",
  5942. .codec_dai_name = "wsa_macro_rx1",
  5943. .no_pcm = 1,
  5944. .dpcm_playback = 1,
  5945. .init = &msm_wsa_cdc_dma_init,
  5946. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  5947. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5948. .ignore_pmdown_time = 1,
  5949. .ignore_suspend = 1,
  5950. .ops = &msm_cdc_dma_be_ops,
  5951. },
  5952. {
  5953. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5954. .stream_name = "WSA CDC DMA0 Capture",
  5955. .cpu_dai_name = "msm-dai-cdc-dma.45057",
  5956. .platform_name = "msm-pcm-hostless",
  5957. .codec_name = "bolero_codec",
  5958. .codec_dai_name = "wsa_macro_vifeedback",
  5959. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5960. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5961. .ignore_suspend = 1,
  5962. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5963. .ops = &msm_cdc_dma_be_ops,
  5964. },
  5965. {
  5966. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  5967. .stream_name = "WSA CDC DMA1 Playback",
  5968. .cpu_dai_name = "msm-dai-cdc-dma.45058",
  5969. .platform_name = "msm-pcm-routing",
  5970. .codec_name = "bolero_codec",
  5971. .codec_dai_name = "wsa_macro_rx_mix",
  5972. .no_pcm = 1,
  5973. .dpcm_playback = 1,
  5974. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  5975. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5976. .ignore_pmdown_time = 1,
  5977. .ignore_suspend = 1,
  5978. .ops = &msm_cdc_dma_be_ops,
  5979. },
  5980. {
  5981. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  5982. .stream_name = "WSA CDC DMA1 Capture",
  5983. .cpu_dai_name = "msm-dai-cdc-dma.45059",
  5984. .platform_name = "msm-pcm-routing",
  5985. .codec_name = "bolero_codec",
  5986. .codec_dai_name = "wsa_macro_echo",
  5987. .no_pcm = 1,
  5988. .dpcm_capture = 1,
  5989. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  5990. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5991. .ignore_suspend = 1,
  5992. .ops = &msm_cdc_dma_be_ops,
  5993. },
  5994. {
  5995. .name = LPASS_BE_WSA_CDC_DMA_TX_2,
  5996. .stream_name = "WSA CDC DMA2 Capture",
  5997. .cpu_dai_name = "msm-dai-cdc-dma.45061",
  5998. .platform_name = "msm-pcm-routing",
  5999. .codec_name = "bolero_codec",
  6000. .codec_dai_name = "msm-stub-tx",
  6001. .no_pcm = 1,
  6002. .dpcm_capture = 1,
  6003. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2,
  6004. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6005. .ignore_suspend = 1,
  6006. .ops = &msm_cdc_dma_be_ops,
  6007. },
  6008. };
  6009. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6010. {
  6011. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6012. .stream_name = "VA CDC DMA0 Capture",
  6013. .cpu_dai_name = "msm-dai-cdc-dma.49153",
  6014. .platform_name = "msm-pcm-routing",
  6015. .codec_name = "bolero_codec",
  6016. .codec_dai_name = "va_macro_tx1",
  6017. .no_pcm = 1,
  6018. .dpcm_capture = 1,
  6019. .init = &msm_va_cdc_dma_init,
  6020. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6021. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6022. .ignore_suspend = 1,
  6023. .ops = &msm_cdc_dma_be_ops,
  6024. },
  6025. {
  6026. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6027. .stream_name = "VA CDC DMA1 Capture",
  6028. .cpu_dai_name = "msm-dai-cdc-dma.49155",
  6029. .platform_name = "msm-pcm-routing",
  6030. .codec_name = "bolero_codec",
  6031. .codec_dai_name = "va_macro_tx2",
  6032. .no_pcm = 1,
  6033. .dpcm_capture = 1,
  6034. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6035. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6036. .ignore_suspend = 1,
  6037. .ops = &msm_cdc_dma_be_ops,
  6038. },
  6039. };
  6040. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6041. ARRAY_SIZE(msm_common_dai_links) +
  6042. ARRAY_SIZE(msm_tasha_fe_dai_links) +
  6043. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6044. ARRAY_SIZE(msm_common_be_dai_links) +
  6045. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6046. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6047. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6048. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6049. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6050. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links)];
  6051. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6052. {
  6053. int ret = 0;
  6054. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6055. &service_nb);
  6056. if (ret < 0)
  6057. pr_err("%s: Audio notifier register failed ret = %d\n",
  6058. __func__, ret);
  6059. return ret;
  6060. }
  6061. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6062. struct snd_ctl_elem_value *ucontrol)
  6063. {
  6064. int ret = 0;
  6065. int port_id;
  6066. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6067. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6068. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6069. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6070. (vad_enable < 0) || (vad_enable > 1) ||
  6071. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6072. pr_err("%s: Invalid arguments\n", __func__);
  6073. ret = -EINVAL;
  6074. goto done;
  6075. }
  6076. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6077. vad_enable, preroll_config, vad_intf);
  6078. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6079. if (ret) {
  6080. pr_err("%s: Invalid vad interface\n", __func__);
  6081. goto done;
  6082. }
  6083. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6084. done:
  6085. return ret;
  6086. }
  6087. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6088. {
  6089. int ret = 0;
  6090. uint32_t tasha_codec = 0;
  6091. ret = afe_cal_init_hwdep(card);
  6092. if (ret) {
  6093. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6094. ret = 0;
  6095. }
  6096. /* tasha late probe when it is present */
  6097. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6098. &tasha_codec);
  6099. if (ret) {
  6100. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6101. ret = 0;
  6102. } else {
  6103. if (tasha_codec) {
  6104. ret = msm_snd_card_tasha_late_probe(card);
  6105. if (ret)
  6106. dev_err(card->dev, "%s: tasha late probe err\n",
  6107. __func__);
  6108. }
  6109. }
  6110. return ret;
  6111. }
  6112. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6113. .name = "qcs405-snd-card",
  6114. .controls = msm_snd_controls,
  6115. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6116. .late_probe = msm_snd_card_codec_late_probe,
  6117. };
  6118. static int msm_populate_dai_link_component_of_node(
  6119. struct snd_soc_card *card)
  6120. {
  6121. int i, index, ret = 0;
  6122. struct device *cdev = card->dev;
  6123. struct snd_soc_dai_link *dai_link = card->dai_link;
  6124. struct device_node *np;
  6125. if (!cdev) {
  6126. pr_err("%s: Sound card device memory NULL\n", __func__);
  6127. return -ENODEV;
  6128. }
  6129. for (i = 0; i < card->num_links; i++) {
  6130. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6131. continue;
  6132. /* populate platform_of_node for snd card dai links */
  6133. if (dai_link[i].platform_name &&
  6134. !dai_link[i].platform_of_node) {
  6135. index = of_property_match_string(cdev->of_node,
  6136. "asoc-platform-names",
  6137. dai_link[i].platform_name);
  6138. if (index < 0) {
  6139. pr_err("%s: No match found for platform name: %s\n",
  6140. __func__, dai_link[i].platform_name);
  6141. ret = index;
  6142. goto err;
  6143. }
  6144. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6145. index);
  6146. if (!np) {
  6147. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6148. __func__, dai_link[i].platform_name,
  6149. index);
  6150. ret = -ENODEV;
  6151. goto err;
  6152. }
  6153. dai_link[i].platform_of_node = np;
  6154. dai_link[i].platform_name = NULL;
  6155. }
  6156. /* populate cpu_of_node for snd card dai links */
  6157. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6158. index = of_property_match_string(cdev->of_node,
  6159. "asoc-cpu-names",
  6160. dai_link[i].cpu_dai_name);
  6161. if (index >= 0) {
  6162. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6163. index);
  6164. if (!np) {
  6165. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6166. __func__,
  6167. dai_link[i].cpu_dai_name);
  6168. ret = -ENODEV;
  6169. goto err;
  6170. }
  6171. dai_link[i].cpu_of_node = np;
  6172. dai_link[i].cpu_dai_name = NULL;
  6173. }
  6174. }
  6175. /* populate codec_of_node for snd card dai links */
  6176. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6177. index = of_property_match_string(cdev->of_node,
  6178. "asoc-codec-names",
  6179. dai_link[i].codec_name);
  6180. if (index < 0)
  6181. continue;
  6182. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6183. index);
  6184. if (!np) {
  6185. pr_err("%s: retrieving phandle for codec %s failed\n",
  6186. __func__, dai_link[i].codec_name);
  6187. ret = -ENODEV;
  6188. goto err;
  6189. }
  6190. dai_link[i].codec_of_node = np;
  6191. dai_link[i].codec_name = NULL;
  6192. }
  6193. }
  6194. err:
  6195. return ret;
  6196. }
  6197. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  6198. {
  6199. return 0;
  6200. }
  6201. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  6202. struct snd_pcm_hw_params *params)
  6203. {
  6204. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  6205. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  6206. int ret = 0;
  6207. unsigned int rx_ch[] = {144, 145, 146, 147, 148, 149, 150,
  6208. 151};
  6209. unsigned int tx_ch[] = {128, 129, 130, 131, 132, 133,
  6210. 134, 135, 136, 137, 138, 139,
  6211. 140, 141, 142, 143};
  6212. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  6213. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  6214. slim_rx_cfg[SLIM_RX_0].channels,
  6215. rx_ch);
  6216. if (ret < 0)
  6217. pr_err("%s: RX failed to set cpu chan map error %d\n",
  6218. __func__, ret);
  6219. } else {
  6220. ret = snd_soc_dai_set_channel_map(cpu_dai,
  6221. slim_tx_cfg[SLIM_TX_0].channels,
  6222. tx_ch, 0, 0);
  6223. if (ret < 0)
  6224. pr_err("%s: TX failed to set cpu chan map error %d\n",
  6225. __func__, ret);
  6226. }
  6227. return ret;
  6228. }
  6229. static struct snd_soc_ops msm_stub_be_ops = {
  6230. .hw_params = msm_snd_stub_hw_params,
  6231. };
  6232. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6233. /* FrontEnd DAI Links */
  6234. {
  6235. .name = "MSMSTUB Media1",
  6236. .stream_name = "MultiMedia1",
  6237. .cpu_dai_name = "MultiMedia1",
  6238. .platform_name = "msm-pcm-dsp.0",
  6239. .dynamic = 1,
  6240. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6241. .dpcm_playback = 1,
  6242. .dpcm_capture = 1,
  6243. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6244. SND_SOC_DPCM_TRIGGER_POST},
  6245. .codec_dai_name = "snd-soc-dummy-dai",
  6246. .codec_name = "snd-soc-dummy",
  6247. .ignore_suspend = 1,
  6248. /* this dainlink has playback support */
  6249. .ignore_pmdown_time = 1,
  6250. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6251. },
  6252. };
  6253. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6254. /* Backend DAI Links */
  6255. {
  6256. .name = LPASS_BE_SLIMBUS_0_RX,
  6257. .stream_name = "Slimbus Playback",
  6258. .cpu_dai_name = "msm-dai-q6-dev.16384",
  6259. .platform_name = "msm-pcm-routing",
  6260. .codec_name = "msm-stub-codec.1",
  6261. .codec_dai_name = "msm-stub-rx",
  6262. .no_pcm = 1,
  6263. .dpcm_playback = 1,
  6264. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  6265. .init = &msm_audrx_stub_init,
  6266. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6267. .ignore_pmdown_time = 1, /* dai link has playback support */
  6268. .ignore_suspend = 1,
  6269. .ops = &msm_stub_be_ops,
  6270. },
  6271. {
  6272. .name = LPASS_BE_SLIMBUS_0_TX,
  6273. .stream_name = "Slimbus Capture",
  6274. .cpu_dai_name = "msm-dai-q6-dev.16385",
  6275. .platform_name = "msm-pcm-routing",
  6276. .codec_name = "msm-stub-codec.1",
  6277. .codec_dai_name = "msm-stub-tx",
  6278. .no_pcm = 1,
  6279. .dpcm_capture = 1,
  6280. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  6281. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6282. .ignore_suspend = 1,
  6283. .ops = &msm_stub_be_ops,
  6284. },
  6285. };
  6286. static struct snd_soc_dai_link msm_stub_dai_links[
  6287. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6288. ARRAY_SIZE(msm_stub_be_dai_links)];
  6289. struct snd_soc_card snd_soc_card_stub_msm = {
  6290. .name = "qcs405-stub-snd-card",
  6291. };
  6292. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6293. { .compatible = "qcom,qcs405-asoc-snd",
  6294. .data = "codec"},
  6295. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6296. .data = "stub_codec"},
  6297. {},
  6298. };
  6299. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6300. {
  6301. struct snd_soc_card *card = NULL;
  6302. struct snd_soc_dai_link *dailink;
  6303. int total_links = 0;
  6304. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6305. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6306. const struct of_device_id *match;
  6307. int rc = 0;
  6308. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6309. if (!match) {
  6310. dev_err(dev, "%s: No DT match found for sound card\n",
  6311. __func__);
  6312. return NULL;
  6313. }
  6314. if (!strcmp(match->data, "codec")) {
  6315. card = &snd_soc_card_qcs405_msm;
  6316. memcpy(msm_qcs405_dai_links + total_links,
  6317. msm_common_dai_links,
  6318. sizeof(msm_common_dai_links));
  6319. total_links += ARRAY_SIZE(msm_common_dai_links);
  6320. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6321. &tasha_codec);
  6322. if (rc) {
  6323. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6324. __func__);
  6325. } else {
  6326. if (tasha_codec) {
  6327. dev_dbg(dev, "%s(): Tasha codec is present\n",
  6328. __func__);
  6329. memcpy(msm_qcs405_dai_links + total_links,
  6330. msm_tasha_fe_dai_links,
  6331. sizeof(msm_tasha_fe_dai_links));
  6332. total_links +=
  6333. ARRAY_SIZE(msm_tasha_fe_dai_links);
  6334. }
  6335. }
  6336. memcpy(msm_qcs405_dai_links + total_links,
  6337. msm_common_misc_fe_dai_links,
  6338. sizeof(msm_common_misc_fe_dai_links));
  6339. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6340. memcpy(msm_qcs405_dai_links + total_links,
  6341. msm_common_be_dai_links,
  6342. sizeof(msm_common_be_dai_links));
  6343. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6344. if (tasha_codec) {
  6345. memcpy(msm_qcs405_dai_links + total_links,
  6346. msm_tasha_be_dai_links,
  6347. sizeof(msm_tasha_be_dai_links));
  6348. total_links += ARRAY_SIZE(msm_tasha_be_dai_links);
  6349. }
  6350. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6351. &va_bolero_codec);
  6352. if (rc) {
  6353. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6354. __func__);
  6355. } else {
  6356. if (va_bolero_codec) {
  6357. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6358. __func__);
  6359. memcpy(msm_qcs405_dai_links + total_links,
  6360. msm_va_cdc_dma_be_dai_links,
  6361. sizeof(msm_va_cdc_dma_be_dai_links));
  6362. total_links +=
  6363. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6364. }
  6365. }
  6366. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6367. &wsa_bolero_codec);
  6368. if (rc) {
  6369. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6370. __func__);
  6371. } else {
  6372. if (wsa_bolero_codec) {
  6373. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6374. __func__);
  6375. memcpy(msm_qcs405_dai_links + total_links,
  6376. msm_wsa_cdc_dma_be_dai_links,
  6377. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6378. total_links +=
  6379. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6380. }
  6381. }
  6382. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6383. &mi2s_audio_intf);
  6384. if (rc) {
  6385. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6386. __func__);
  6387. } else {
  6388. if (mi2s_audio_intf) {
  6389. memcpy(msm_qcs405_dai_links + total_links,
  6390. msm_mi2s_be_dai_links,
  6391. sizeof(msm_mi2s_be_dai_links));
  6392. total_links +=
  6393. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6394. }
  6395. }
  6396. rc = of_property_read_u32(dev->of_node,
  6397. "qcom,auxpcm-audio-intf",
  6398. &auxpcm_audio_intf);
  6399. if (rc) {
  6400. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6401. __func__);
  6402. } else {
  6403. if (auxpcm_audio_intf) {
  6404. memcpy(msm_qcs405_dai_links + total_links,
  6405. msm_auxpcm_be_dai_links,
  6406. sizeof(msm_auxpcm_be_dai_links));
  6407. total_links +=
  6408. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6409. }
  6410. }
  6411. dailink = msm_qcs405_dai_links;
  6412. } else if (!strcmp(match->data, "stub_codec")) {
  6413. card = &snd_soc_card_stub_msm;
  6414. memcpy(msm_stub_dai_links + total_links,
  6415. msm_stub_fe_dai_links,
  6416. sizeof(msm_stub_fe_dai_links));
  6417. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6418. memcpy(msm_stub_dai_links + total_links,
  6419. msm_stub_be_dai_links,
  6420. sizeof(msm_stub_be_dai_links));
  6421. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6422. dailink = msm_stub_dai_links;
  6423. }
  6424. if (card) {
  6425. card->dai_link = dailink;
  6426. card->num_links = total_links;
  6427. }
  6428. return card;
  6429. }
  6430. static int msm_wsa881x_init(struct snd_soc_component *component)
  6431. {
  6432. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106};
  6433. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107};
  6434. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6435. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6436. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6437. struct msm_asoc_mach_data *pdata;
  6438. struct snd_soc_dapm_context *dapm;
  6439. int ret = 0;
  6440. if (!codec) {
  6441. pr_err("%s codec is NULL\n", __func__);
  6442. return -EINVAL;
  6443. }
  6444. dapm = snd_soc_codec_get_dapm(codec);
  6445. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6446. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6447. __func__, codec->component.name);
  6448. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6449. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6450. &ch_rate[0]);
  6451. if (dapm->component) {
  6452. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6453. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6454. }
  6455. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6456. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  6457. __func__, codec->component.name);
  6458. wsa881x_set_channel_map(codec, &spkright_ports[0],
  6459. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6460. &ch_rate[0]);
  6461. if (dapm->component) {
  6462. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6463. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6464. }
  6465. } else {
  6466. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  6467. codec->component.name);
  6468. ret = -EINVAL;
  6469. goto err;
  6470. }
  6471. pdata = snd_soc_card_get_drvdata(component->card);
  6472. if (pdata && pdata->codec_root)
  6473. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6474. codec);
  6475. err:
  6476. return ret;
  6477. }
  6478. static int msm_init_wsa_dev(struct platform_device *pdev,
  6479. struct snd_soc_card *card)
  6480. {
  6481. struct device_node *wsa_of_node;
  6482. u32 wsa_max_devs;
  6483. u32 wsa_dev_cnt;
  6484. int i;
  6485. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6486. const char *wsa_auxdev_name_prefix[1];
  6487. char *dev_name_str = NULL;
  6488. int found = 0;
  6489. int ret = 0;
  6490. /* Get maximum WSA device count for this platform */
  6491. ret = of_property_read_u32(pdev->dev.of_node,
  6492. "qcom,wsa-max-devs", &wsa_max_devs);
  6493. if (ret) {
  6494. dev_info(&pdev->dev,
  6495. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6496. __func__, pdev->dev.of_node->full_name, ret);
  6497. card->num_aux_devs = 0;
  6498. return 0;
  6499. }
  6500. if (wsa_max_devs == 0) {
  6501. dev_warn(&pdev->dev,
  6502. "%s: Max WSA devices is 0 for this target?\n",
  6503. __func__);
  6504. card->num_aux_devs = 0;
  6505. return 0;
  6506. }
  6507. /* Get count of WSA device phandles for this platform */
  6508. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6509. "qcom,wsa-devs", NULL);
  6510. if (wsa_dev_cnt == -ENOENT) {
  6511. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6512. __func__);
  6513. goto err;
  6514. } else if (wsa_dev_cnt <= 0) {
  6515. dev_err(&pdev->dev,
  6516. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6517. __func__, wsa_dev_cnt);
  6518. ret = -EINVAL;
  6519. goto err;
  6520. }
  6521. /*
  6522. * Expect total phandles count to be NOT less than maximum possible
  6523. * WSA count. However, if it is less, then assign same value to
  6524. * max count as well.
  6525. */
  6526. if (wsa_dev_cnt < wsa_max_devs) {
  6527. dev_dbg(&pdev->dev,
  6528. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6529. __func__, wsa_max_devs, wsa_dev_cnt);
  6530. wsa_max_devs = wsa_dev_cnt;
  6531. }
  6532. /* Make sure prefix string passed for each WSA device */
  6533. ret = of_property_count_strings(pdev->dev.of_node,
  6534. "qcom,wsa-aux-dev-prefix");
  6535. if (ret != wsa_dev_cnt) {
  6536. dev_err(&pdev->dev,
  6537. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6538. __func__, wsa_dev_cnt, ret);
  6539. ret = -EINVAL;
  6540. goto err;
  6541. }
  6542. /*
  6543. * Alloc mem to store phandle and index info of WSA device, if already
  6544. * registered with ALSA core
  6545. */
  6546. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6547. sizeof(struct msm_wsa881x_dev_info),
  6548. GFP_KERNEL);
  6549. if (!wsa881x_dev_info) {
  6550. ret = -ENOMEM;
  6551. goto err;
  6552. }
  6553. /*
  6554. * search and check whether all WSA devices are already
  6555. * registered with ALSA core or not. If found a node, store
  6556. * the node and the index in a local array of struct for later
  6557. * use.
  6558. */
  6559. for (i = 0; i < wsa_dev_cnt; i++) {
  6560. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6561. "qcom,wsa-devs", i);
  6562. if (unlikely(!wsa_of_node)) {
  6563. /* we should not be here */
  6564. dev_err(&pdev->dev,
  6565. "%s: wsa dev node is not present\n",
  6566. __func__);
  6567. ret = -EINVAL;
  6568. goto err_free_dev_info;
  6569. }
  6570. if (soc_find_component(wsa_of_node, NULL)) {
  6571. /* WSA device registered with ALSA core */
  6572. wsa881x_dev_info[found].of_node = wsa_of_node;
  6573. wsa881x_dev_info[found].index = i;
  6574. found++;
  6575. if (found == wsa_max_devs)
  6576. break;
  6577. }
  6578. }
  6579. if (found < wsa_max_devs) {
  6580. dev_dbg(&pdev->dev,
  6581. "%s: failed to find %d components. Found only %d\n",
  6582. __func__, wsa_max_devs, found);
  6583. return -EPROBE_DEFER;
  6584. }
  6585. dev_info(&pdev->dev,
  6586. "%s: found %d wsa881x devices registered with ALSA core\n",
  6587. __func__, found);
  6588. card->num_aux_devs = wsa_max_devs;
  6589. card->num_configs = wsa_max_devs;
  6590. /* Alloc array of AUX devs struct */
  6591. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6592. sizeof(struct snd_soc_aux_dev),
  6593. GFP_KERNEL);
  6594. if (!msm_aux_dev) {
  6595. ret = -ENOMEM;
  6596. goto err_free_dev_info;
  6597. }
  6598. /* Alloc array of codec conf struct */
  6599. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6600. sizeof(struct snd_soc_codec_conf),
  6601. GFP_KERNEL);
  6602. if (!msm_codec_conf) {
  6603. ret = -ENOMEM;
  6604. goto err_free_aux_dev;
  6605. }
  6606. for (i = 0; i < card->num_aux_devs; i++) {
  6607. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6608. GFP_KERNEL);
  6609. if (!dev_name_str) {
  6610. ret = -ENOMEM;
  6611. goto err_free_cdc_conf;
  6612. }
  6613. ret = of_property_read_string_index(pdev->dev.of_node,
  6614. "qcom,wsa-aux-dev-prefix",
  6615. wsa881x_dev_info[i].index,
  6616. wsa_auxdev_name_prefix);
  6617. if (ret) {
  6618. dev_err(&pdev->dev,
  6619. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6620. __func__, ret);
  6621. ret = -EINVAL;
  6622. goto err_free_dev_name_str;
  6623. }
  6624. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6625. msm_aux_dev[i].name = dev_name_str;
  6626. msm_aux_dev[i].codec_name = NULL;
  6627. msm_aux_dev[i].codec_of_node =
  6628. wsa881x_dev_info[i].of_node;
  6629. msm_aux_dev[i].init = msm_wsa881x_init;
  6630. msm_codec_conf[i].dev_name = NULL;
  6631. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  6632. msm_codec_conf[i].of_node =
  6633. wsa881x_dev_info[i].of_node;
  6634. }
  6635. card->codec_conf = msm_codec_conf;
  6636. card->aux_dev = msm_aux_dev;
  6637. return 0;
  6638. err_free_dev_name_str:
  6639. devm_kfree(&pdev->dev, dev_name_str);
  6640. err_free_cdc_conf:
  6641. devm_kfree(&pdev->dev, msm_codec_conf);
  6642. err_free_aux_dev:
  6643. devm_kfree(&pdev->dev, msm_aux_dev);
  6644. err_free_dev_info:
  6645. devm_kfree(&pdev->dev, wsa881x_dev_info);
  6646. err:
  6647. return ret;
  6648. }
  6649. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6650. {
  6651. int count;
  6652. u32 mi2s_master_slave[MI2S_MAX];
  6653. int ret;
  6654. for (count = 0; count < MI2S_MAX; count++) {
  6655. mutex_init(&mi2s_intf_conf[count].lock);
  6656. mi2s_intf_conf[count].ref_cnt = 0;
  6657. }
  6658. ret = of_property_read_u32_array(pdev->dev.of_node,
  6659. "qcom,msm-mi2s-master",
  6660. mi2s_master_slave, MI2S_MAX);
  6661. if (ret) {
  6662. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6663. __func__);
  6664. } else {
  6665. for (count = 0; count < MI2S_MAX; count++) {
  6666. mi2s_intf_conf[count].msm_is_mi2s_master =
  6667. mi2s_master_slave[count];
  6668. }
  6669. }
  6670. }
  6671. static void msm_i2s_auxpcm_deinit(void)
  6672. {
  6673. int count;
  6674. for (count = 0; count < MI2S_MAX; count++) {
  6675. mutex_destroy(&mi2s_intf_conf[count].lock);
  6676. mi2s_intf_conf[count].ref_cnt = 0;
  6677. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6678. }
  6679. }
  6680. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6681. {
  6682. struct snd_soc_card *card;
  6683. struct msm_asoc_mach_data *pdata;
  6684. int ret;
  6685. if (!pdev->dev.of_node) {
  6686. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  6687. return -EINVAL;
  6688. }
  6689. pdata = devm_kzalloc(&pdev->dev,
  6690. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6691. if (!pdata)
  6692. return -ENOMEM;
  6693. card = populate_snd_card_dailinks(&pdev->dev);
  6694. if (!card) {
  6695. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6696. ret = -EINVAL;
  6697. goto err;
  6698. }
  6699. card->dev = &pdev->dev;
  6700. platform_set_drvdata(pdev, card);
  6701. snd_soc_card_set_drvdata(card, pdata);
  6702. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6703. if (ret) {
  6704. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  6705. ret);
  6706. goto err;
  6707. }
  6708. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6709. if (ret) {
  6710. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  6711. ret);
  6712. goto err;
  6713. }
  6714. ret = msm_populate_dai_link_component_of_node(card);
  6715. if (ret) {
  6716. ret = -EPROBE_DEFER;
  6717. goto err;
  6718. }
  6719. ret = msm_init_wsa_dev(pdev, card);
  6720. if (ret)
  6721. goto err;
  6722. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6723. "qcom,cdc-dmic01-gpios",
  6724. 0);
  6725. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6726. "qcom,cdc-dmic23-gpios",
  6727. 0);
  6728. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6729. "qcom,cdc-dmic45-gpios",
  6730. 0);
  6731. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6732. "qcom,cdc-dmic67-gpios",
  6733. 0);
  6734. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6735. if (ret == -EPROBE_DEFER) {
  6736. if (codec_reg_done)
  6737. ret = -EINVAL;
  6738. goto err;
  6739. } else if (ret) {
  6740. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  6741. ret);
  6742. goto err;
  6743. }
  6744. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  6745. spdev = pdev;
  6746. /* Parse pinctrl info from devicetree */
  6747. ret = msm_get_pinctrl(pdev);
  6748. if (!ret) {
  6749. pr_debug("%s: pinctrl parsing successful\n", __func__);
  6750. } else {
  6751. dev_dbg(&pdev->dev,
  6752. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  6753. __func__, ret);
  6754. ret = 0;
  6755. }
  6756. msm_i2s_auxpcm_init(pdev);
  6757. is_initial_boot = true;
  6758. return 0;
  6759. err:
  6760. msm_release_pinctrl(pdev);
  6761. return ret;
  6762. }
  6763. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6764. {
  6765. audio_notifier_deregister("qcs405");
  6766. msm_i2s_auxpcm_deinit();
  6767. msm_release_pinctrl(pdev);
  6768. return 0;
  6769. }
  6770. static struct platform_driver qcs405_asoc_machine_driver = {
  6771. .driver = {
  6772. .name = DRV_NAME,
  6773. .owner = THIS_MODULE,
  6774. .pm = &snd_soc_pm_ops,
  6775. .of_match_table = qcs405_asoc_machine_of_match,
  6776. },
  6777. .probe = msm_asoc_machine_probe,
  6778. .remove = msm_asoc_machine_remove,
  6779. };
  6780. module_platform_driver(qcs405_asoc_machine_driver);
  6781. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  6782. MODULE_LICENSE("GPL v2");
  6783. MODULE_ALIAS("platform:" DRV_NAME);
  6784. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);