cam_sync_dma_fence.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include "cam_sync_dma_fence.h"
  6. #include "cam_sync_util.h"
  7. extern unsigned long cam_sync_monitor_mask;
  8. /**
  9. * struct cam_dma_fence_row - DMA fence row
  10. */
  11. struct cam_dma_fence_row {
  12. char name[CAM_DMA_FENCE_NAME_LEN];
  13. struct dma_fence *fence;
  14. int32_t fd;
  15. enum cam_dma_fence_state state;
  16. struct dma_fence_cb fence_cb;
  17. int32_t sync_obj;
  18. cam_sync_callback_for_dma_fence sync_cb;
  19. bool cb_registered_for_sync;
  20. bool ext_dma_fence;
  21. bool sync_signal_dma;
  22. };
  23. /**
  24. * struct cam_dma_fence_device - DMA fence device
  25. */
  26. struct cam_dma_fence_device {
  27. uint64_t dma_fence_context;
  28. struct cam_dma_fence_row rows[CAM_DMA_FENCE_MAX_FENCES];
  29. spinlock_t row_spinlocks[CAM_DMA_FENCE_MAX_FENCES];
  30. struct mutex dev_lock;
  31. DECLARE_BITMAP(bitmap, CAM_DMA_FENCE_MAX_FENCES);
  32. struct cam_generic_fence_monitor_data **monitor_data;
  33. };
  34. static atomic64_t g_cam_dma_fence_seq_no;
  35. static struct cam_dma_fence_device *g_cam_dma_fence_dev;
  36. bool __cam_dma_fence_enable_signaling(
  37. struct dma_fence *fence)
  38. {
  39. return true;
  40. }
  41. const char *__cam_dma_fence_get_driver_name(
  42. struct dma_fence *fence)
  43. {
  44. return "Camera DMA fence driver";
  45. }
  46. void __cam_dma_fence_free(struct dma_fence *fence)
  47. {
  48. CAM_DBG(CAM_DMA_FENCE,
  49. "Free memory for dma fence context: %llu seqno: %llu",
  50. fence->context, fence->seqno);
  51. kfree(fence->lock);
  52. kfree(fence);
  53. }
  54. static struct dma_fence_ops cam_sync_dma_fence_ops = {
  55. .enable_signaling = __cam_dma_fence_enable_signaling,
  56. .get_driver_name = __cam_dma_fence_get_driver_name,
  57. .get_timeline_name = __cam_dma_fence_get_driver_name,
  58. .release = __cam_dma_fence_free,
  59. };
  60. static inline struct cam_generic_fence_monitor_entry *
  61. __cam_dma_fence_get_monitor_entries(int idx)
  62. {
  63. struct cam_generic_fence_monitor_data *monitor_data;
  64. monitor_data = CAM_GENERIC_MONITOR_GET_DATA(g_cam_dma_fence_dev->monitor_data, idx);
  65. if (monitor_data->swap_monitor_entries)
  66. return monitor_data->prev_monitor_entries;
  67. else
  68. return monitor_data->monitor_entries;
  69. }
  70. static inline struct cam_generic_fence_monitor_entry *
  71. __cam_dma_fence_get_prev_monitor_entries(int idx)
  72. {
  73. struct cam_generic_fence_monitor_data *monitor_data;
  74. monitor_data = CAM_GENERIC_MONITOR_GET_DATA(g_cam_dma_fence_dev->monitor_data, idx);
  75. if (monitor_data->swap_monitor_entries)
  76. return monitor_data->monitor_entries;
  77. else
  78. return monitor_data->prev_monitor_entries;
  79. }
  80. static void __cam_dma_fence_print_table(void)
  81. {
  82. int i;
  83. struct cam_dma_fence_row *row;
  84. struct dma_fence *fence;
  85. for (i = 0; i < CAM_DMA_FENCE_MAX_FENCES; i++) {
  86. spin_lock_bh(&g_cam_dma_fence_dev->row_spinlocks[i]);
  87. row = &g_cam_dma_fence_dev->rows[i];
  88. fence = row->fence;
  89. CAM_INFO(CAM_DMA_FENCE,
  90. "Idx: %d seqno: %llu name: %s state: %d",
  91. i, fence->seqno, row->name, row->state);
  92. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[i]);
  93. }
  94. }
  95. static int __cam_dma_fence_find_free_idx(uint32_t *idx)
  96. {
  97. int rc = 0;
  98. bool bit;
  99. do {
  100. *idx = find_first_zero_bit(g_cam_dma_fence_dev->bitmap, CAM_DMA_FENCE_MAX_FENCES);
  101. if (*idx >= CAM_DMA_FENCE_MAX_FENCES) {
  102. rc = -ENOMEM;
  103. break;
  104. }
  105. bit = test_and_set_bit(*idx, g_cam_dma_fence_dev->bitmap);
  106. } while (bit);
  107. if (rc) {
  108. CAM_ERR(CAM_DMA_FENCE, "No free idx, printing dma fence table......");
  109. __cam_dma_fence_print_table();
  110. }
  111. return rc;
  112. }
  113. static struct dma_fence *__cam_dma_fence_find_fence_in_table(
  114. int32_t fd, int32_t *idx)
  115. {
  116. int i;
  117. struct dma_fence *fence = NULL;
  118. struct cam_dma_fence_row *row = NULL;
  119. for (i = 0; i < CAM_DMA_FENCE_MAX_FENCES; i++) {
  120. spin_lock_bh(&g_cam_dma_fence_dev->row_spinlocks[i]);
  121. row = &g_cam_dma_fence_dev->rows[i];
  122. if ((row->state != CAM_DMA_FENCE_STATE_INVALID) && (row->fd == fd)) {
  123. *idx = i;
  124. fence = row->fence;
  125. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[i]);
  126. break;
  127. }
  128. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[i]);
  129. }
  130. return fence;
  131. }
  132. static void __cam_dma_fence_init_row(const char *name,
  133. struct dma_fence *dma_fence, int32_t fd, uint32_t idx,
  134. bool ext_dma_fence)
  135. {
  136. struct cam_dma_fence_row *row;
  137. spin_lock_bh(&g_cam_dma_fence_dev->row_spinlocks[idx]);
  138. row = &g_cam_dma_fence_dev->rows[idx];
  139. row->fence = dma_fence;
  140. row->fd = fd;
  141. row->state = CAM_DMA_FENCE_STATE_ACTIVE;
  142. row->ext_dma_fence = ext_dma_fence;
  143. strscpy(row->name, name, CAM_DMA_FENCE_NAME_LEN);
  144. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE, &cam_sync_monitor_mask)) {
  145. cam_generic_fence_update_monitor_array(idx,
  146. &g_cam_dma_fence_dev->dev_lock, g_cam_dma_fence_dev->monitor_data,
  147. CAM_FENCE_OP_CREATE);
  148. }
  149. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[idx]);
  150. }
  151. void __cam_dma_fence_signal_cb(
  152. struct dma_fence *fence, struct dma_fence_cb *cb)
  153. {
  154. struct cam_dma_fence_signal_sync_obj signal_sync_obj;
  155. struct cam_dma_fence_row *dma_fence_row =
  156. container_of(cb, struct cam_dma_fence_row, fence_cb);
  157. uint32_t idx;
  158. if (dma_fence_row->state == CAM_DMA_FENCE_STATE_INVALID) {
  159. CAM_ERR(CAM_DMA_FENCE, "dma fence seqno: %llu is in invalid state: %d",
  160. fence->seqno, dma_fence_row->state);
  161. return;
  162. }
  163. /* If this dma fence is signaled by sync obj, skip cb */
  164. if (dma_fence_row->sync_signal_dma)
  165. return;
  166. CAM_DBG(CAM_DMA_FENCE, "dma fence seqno: %llu fd: %d signaled, signal sync obj: %d",
  167. fence->seqno, dma_fence_row->fd, dma_fence_row->sync_obj);
  168. if ((dma_fence_row->cb_registered_for_sync) && (dma_fence_row->sync_cb)) {
  169. signal_sync_obj.fd = dma_fence_row->fd;
  170. /*
  171. * Signal is invoked with the fence lock held,
  172. * lock not needed to query status
  173. */
  174. signal_sync_obj.status = dma_fence_get_status_locked(fence);
  175. dma_fence_row->state = CAM_DMA_FENCE_STATE_SIGNALED;
  176. dma_fence_row->sync_cb(dma_fence_row->sync_obj, &signal_sync_obj);
  177. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE,
  178. &cam_sync_monitor_mask)) {
  179. __cam_dma_fence_find_fence_in_table(dma_fence_row->fd, &idx);
  180. cam_generic_fence_update_monitor_array(idx,
  181. &g_cam_dma_fence_dev->dev_lock,
  182. g_cam_dma_fence_dev->monitor_data,
  183. CAM_FENCE_OP_UNREGISTER_ON_SIGNAL);
  184. }
  185. }
  186. }
  187. static void __cam_dma_fence_dump_monitor_array(int dma_row_idx)
  188. {
  189. struct dma_fence *fence;
  190. struct cam_generic_fence_monitor_obj_info obj_info;
  191. struct cam_dma_fence_row *row;
  192. if (!g_cam_dma_fence_dev->monitor_data ||
  193. !test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE, &cam_sync_monitor_mask))
  194. return;
  195. if (!CAM_GENERIC_MONITOR_GET_DATA(g_cam_dma_fence_dev->monitor_data,
  196. dma_row_idx)->prev_obj_id)
  197. return;
  198. row = &g_cam_dma_fence_dev->rows[dma_row_idx];
  199. fence = row->fence;
  200. obj_info.name = row->name;
  201. obj_info.obj_id = row->fd;
  202. obj_info.state = row->state;
  203. obj_info.ref_cnt = kref_read(&fence->refcount);
  204. obj_info.monitor_data = CAM_GENERIC_MONITOR_GET_DATA(
  205. g_cam_dma_fence_dev->monitor_data, dma_row_idx);
  206. obj_info.fence_type = CAM_GENERIC_FENCE_TYPE_DMA_FENCE;
  207. obj_info.sync_id = row->sync_obj;
  208. obj_info.monitor_entries =
  209. __cam_dma_fence_get_monitor_entries(dma_row_idx);
  210. obj_info.prev_monitor_entries =
  211. __cam_dma_fence_get_prev_monitor_entries(dma_row_idx);
  212. cam_generic_fence_dump_monitor_array(&obj_info);
  213. }
  214. int cam_dma_fence_get_put_ref(
  215. bool get_or_put, int32_t dma_fence_row_idx)
  216. {
  217. struct dma_fence *dma_fence;
  218. struct cam_dma_fence_row *row;
  219. int rc = 0;
  220. if ((dma_fence_row_idx < 0) ||
  221. (dma_fence_row_idx >= CAM_DMA_FENCE_MAX_FENCES)) {
  222. CAM_ERR(CAM_DMA_FENCE, "dma fence idx: %d is invalid",
  223. dma_fence_row_idx);
  224. return -EINVAL;
  225. }
  226. spin_lock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_fence_row_idx]);
  227. row = &g_cam_dma_fence_dev->rows[dma_fence_row_idx];
  228. if (row->state == CAM_DMA_FENCE_STATE_INVALID) {
  229. CAM_ERR(CAM_DMA_FENCE,
  230. "dma fence at idx: %d is in invalid state: %d",
  231. dma_fence_row_idx, row->state);
  232. rc = -EINVAL;
  233. goto monitor_dump;
  234. }
  235. dma_fence = row->fence;
  236. if (get_or_put)
  237. dma_fence_get(dma_fence);
  238. else
  239. dma_fence_put(dma_fence);
  240. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_fence_row_idx]);
  241. CAM_DBG(CAM_DMA_FENCE, "Refcnt: %u after %s for dma fence with seqno: %llu",
  242. kref_read(&dma_fence->refcount), (get_or_put ? "getref" : "putref"),
  243. dma_fence->seqno);
  244. return rc;
  245. monitor_dump:
  246. __cam_dma_fence_dump_monitor_array(dma_fence_row_idx);
  247. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_fence_row_idx]);
  248. return rc;
  249. }
  250. static struct dma_fence *cam_dma_fence_get_fence_from_sync_file(
  251. int32_t fd, int32_t *dma_fence_row_idx)
  252. {
  253. uint32_t idx;
  254. struct dma_fence *dma_fence = NULL;
  255. dma_fence = sync_file_get_fence(fd);
  256. if (IS_ERR_OR_NULL(dma_fence)) {
  257. CAM_ERR(CAM_DMA_FENCE, "Invalid fd: %d no dma fence found", fd);
  258. return ERR_PTR(-EINVAL);
  259. }
  260. if (__cam_dma_fence_find_free_idx(&idx)) {
  261. CAM_ERR(CAM_DMA_FENCE, "No free idx");
  262. goto end;
  263. }
  264. __cam_dma_fence_init_row(dma_fence->ops->get_driver_name(dma_fence),
  265. dma_fence, fd, idx, true);
  266. *dma_fence_row_idx = idx;
  267. CAM_DBG(CAM_DMA_FENCE,
  268. "External dma fence with fd: %d seqno: %llu ref_cnt: %u updated in tbl",
  269. fd, dma_fence->seqno, kref_read(&dma_fence->refcount));
  270. return dma_fence;
  271. end:
  272. dma_fence_put(dma_fence);
  273. return NULL;
  274. }
  275. struct dma_fence *cam_dma_fence_get_fence_from_fd(
  276. int32_t fd, int32_t *dma_fence_row_idx)
  277. {
  278. struct dma_fence *dma_fence = NULL;
  279. dma_fence = __cam_dma_fence_find_fence_in_table(fd, dma_fence_row_idx);
  280. if (IS_ERR_OR_NULL(dma_fence)) {
  281. CAM_WARN(CAM_DMA_FENCE,
  282. "dma fence with fd: %d is an external fence, querying sync file",
  283. fd);
  284. return cam_dma_fence_get_fence_from_sync_file(fd, dma_fence_row_idx);
  285. }
  286. dma_fence_get(dma_fence);
  287. CAM_DBG(CAM_DMA_FENCE, "dma fence found for fd: %d with seqno: %llu ref_cnt: %u",
  288. fd, dma_fence->seqno, kref_read(&dma_fence->refcount));
  289. return dma_fence;
  290. }
  291. int cam_dma_fence_register_cb(int32_t *sync_obj, int32_t *dma_fence_idx,
  292. cam_sync_callback_for_dma_fence sync_cb)
  293. {
  294. int rc = 0;
  295. int dma_fence_row_idx = 0;
  296. struct cam_dma_fence_row *row = NULL;
  297. struct dma_fence *dma_fence = NULL;
  298. if (!sync_obj || !dma_fence_idx || !sync_cb) {
  299. CAM_ERR(CAM_DMA_FENCE,
  300. "Invalid args sync_obj: %p dma_fence_idx: %p sync_cb: %p",
  301. sync_obj, dma_fence_idx, sync_cb);
  302. return -EINVAL;
  303. }
  304. dma_fence_row_idx = *dma_fence_idx;
  305. if ((dma_fence_row_idx < 0) ||
  306. (dma_fence_row_idx >= CAM_DMA_FENCE_MAX_FENCES)) {
  307. CAM_ERR(CAM_DMA_FENCE, "dma fence idx: %d is invalid",
  308. dma_fence_row_idx);
  309. return -EINVAL;
  310. }
  311. spin_lock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_fence_row_idx]);
  312. row = &g_cam_dma_fence_dev->rows[dma_fence_row_idx];
  313. dma_fence = row->fence;
  314. if (row->state != CAM_DMA_FENCE_STATE_ACTIVE) {
  315. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE,
  316. &cam_sync_monitor_mask))
  317. cam_generic_fence_update_monitor_array(dma_fence_row_idx,
  318. &g_cam_dma_fence_dev->dev_lock,
  319. g_cam_dma_fence_dev->monitor_data,
  320. CAM_FENCE_OP_SKIP_REGISTER_CB);
  321. CAM_ERR(CAM_DMA_FENCE,
  322. "dma fence at idx: %d fd: %d seqno: %llu is not active, current state: %d",
  323. dma_fence_row_idx, row->fd, dma_fence->seqno, row->state);
  324. rc = -EINVAL;
  325. goto monitor_dump;
  326. }
  327. /**
  328. * If the cb is already registered, return
  329. * If a fd is closed by userspace without releasing the dma fence, it is
  330. * possible that same fd is returned to a new fence.
  331. */
  332. if (row->cb_registered_for_sync) {
  333. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE,
  334. &cam_sync_monitor_mask))
  335. cam_generic_fence_update_monitor_array(dma_fence_row_idx,
  336. &g_cam_dma_fence_dev->dev_lock, g_cam_dma_fence_dev->monitor_data,
  337. CAM_FENCE_OP_ALREADY_REGISTERED_CB);
  338. CAM_WARN(CAM_DMA_FENCE,
  339. "dma fence at idx: %d fd: %d seqno: %llu has already registered a cb for sync: %d - same fd for 2 fences?",
  340. dma_fence_row_idx, row->fd, dma_fence->seqno, row->sync_obj);
  341. goto end;
  342. }
  343. rc = dma_fence_add_callback(row->fence, &row->fence_cb,
  344. __cam_dma_fence_signal_cb);
  345. if (rc) {
  346. CAM_ERR(CAM_DMA_FENCE,
  347. "Failed to register cb for dma fence fd: %d seqno: %llu rc: %d",
  348. row->fd, dma_fence->seqno, rc);
  349. goto monitor_dump;
  350. }
  351. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE, &cam_sync_monitor_mask))
  352. cam_generic_fence_update_monitor_array(dma_fence_row_idx,
  353. &g_cam_dma_fence_dev->dev_lock, g_cam_dma_fence_dev->monitor_data,
  354. CAM_FENCE_OP_REGISTER_CB);
  355. row->cb_registered_for_sync = true;
  356. row->sync_obj = *sync_obj;
  357. row->sync_cb = sync_cb;
  358. CAM_DBG(CAM_DMA_FENCE,
  359. "CB successfully registered for dma fence fd: %d seqno: %llu for sync_obj: %d",
  360. row->fd, dma_fence->seqno, *sync_obj);
  361. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_fence_row_idx]);
  362. return rc;
  363. monitor_dump:
  364. __cam_dma_fence_dump_monitor_array(dma_fence_row_idx);
  365. end:
  366. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_fence_row_idx]);
  367. return rc;
  368. }
  369. static int __cam_dma_fence_signal_fence(
  370. struct dma_fence *dma_fence,
  371. int32_t status)
  372. {
  373. int rc;
  374. unsigned long flags;
  375. bool fence_signaled = false;
  376. spin_lock_irqsave(dma_fence->lock, flags);
  377. fence_signaled = dma_fence_is_signaled_locked(dma_fence);
  378. if (fence_signaled) {
  379. rc = -EPERM;
  380. goto end;
  381. }
  382. if (status)
  383. dma_fence_set_error(dma_fence, status);
  384. rc = dma_fence_signal_locked(dma_fence);
  385. end:
  386. spin_unlock_irqrestore(dma_fence->lock, flags);
  387. if (fence_signaled)
  388. CAM_DBG(CAM_DMA_FENCE, "dma fence seqno: %llu is already signaled",
  389. dma_fence->seqno);
  390. return rc;
  391. }
  392. int cam_dma_fence_internal_signal(
  393. int32_t dma_fence_row_idx,
  394. struct cam_dma_fence_signal *signal_dma_fence)
  395. {
  396. int rc;
  397. struct dma_fence *dma_fence = NULL;
  398. struct cam_dma_fence_row *row = NULL;
  399. if ((dma_fence_row_idx < 0) ||
  400. (dma_fence_row_idx >= CAM_DMA_FENCE_MAX_FENCES)) {
  401. CAM_ERR(CAM_DMA_FENCE, "dma fence idx: %d is invalid",
  402. dma_fence_row_idx);
  403. return -EINVAL;
  404. }
  405. spin_lock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_fence_row_idx]);
  406. row = &g_cam_dma_fence_dev->rows[dma_fence_row_idx];
  407. /* Ensures sync obj cb is not invoked */
  408. row->sync_signal_dma = true;
  409. dma_fence = row->fence;
  410. if (IS_ERR_OR_NULL(dma_fence)) {
  411. CAM_ERR(CAM_DMA_FENCE, "DMA fence in row: %d is invalid",
  412. dma_fence_row_idx);
  413. rc = -EINVAL;
  414. goto monitor_dump;
  415. }
  416. if (row->state == CAM_DMA_FENCE_STATE_SIGNALED) {
  417. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_fence_row_idx]);
  418. CAM_WARN(CAM_DMA_FENCE,
  419. "dma fence fd: %d[seqno: %llu] already in signaled state",
  420. signal_dma_fence->dma_fence_fd, dma_fence->seqno);
  421. return 0;
  422. }
  423. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE, &cam_sync_monitor_mask))
  424. cam_generic_fence_update_monitor_array(dma_fence_row_idx,
  425. &g_cam_dma_fence_dev->dev_lock, g_cam_dma_fence_dev->monitor_data,
  426. CAM_FENCE_OP_SIGNAL);
  427. if (row->cb_registered_for_sync) {
  428. if (!dma_fence_remove_callback(row->fence, &row->fence_cb)) {
  429. CAM_ERR(CAM_DMA_FENCE,
  430. "Failed to remove cb for dma fence seqno: %llu fd: %d",
  431. dma_fence->seqno, row->fd);
  432. rc = -EINVAL;
  433. goto monitor_dump;
  434. }
  435. }
  436. rc = __cam_dma_fence_signal_fence(dma_fence, signal_dma_fence->status);
  437. if (rc)
  438. CAM_WARN(CAM_DMA_FENCE,
  439. "dma fence seqno: %llu fd: %d already signaled rc: %d",
  440. dma_fence->seqno, row->fd, rc);
  441. row->state = CAM_DMA_FENCE_STATE_SIGNALED;
  442. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_fence_row_idx]);
  443. CAM_DBG(CAM_DMA_FENCE,
  444. "dma fence fd: %d[seqno: %llu] signaled with status: %d rc: %d",
  445. signal_dma_fence->dma_fence_fd, dma_fence->seqno,
  446. signal_dma_fence->status, rc);
  447. return rc;
  448. monitor_dump:
  449. __cam_dma_fence_dump_monitor_array(dma_fence_row_idx);
  450. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_fence_row_idx]);
  451. return rc;
  452. }
  453. int cam_dma_fence_signal_fd(struct cam_dma_fence_signal *signal_dma_fence)
  454. {
  455. uint32_t idx;
  456. struct dma_fence *dma_fence = NULL;
  457. dma_fence = __cam_dma_fence_find_fence_in_table(
  458. signal_dma_fence->dma_fence_fd, &idx);
  459. if (IS_ERR_OR_NULL(dma_fence)) {
  460. CAM_ERR(CAM_DMA_FENCE, "Failed to find dma fence for fd: %d",
  461. signal_dma_fence->dma_fence_fd);
  462. return -EINVAL;
  463. }
  464. return cam_dma_fence_internal_signal(idx, signal_dma_fence);
  465. }
  466. static int __cam_dma_fence_get_fd(int32_t *row_idx,
  467. const char *name)
  468. {
  469. int fd = -1;
  470. uint32_t idx;
  471. struct dma_fence *dma_fence = NULL;
  472. spinlock_t *dma_fence_lock = NULL;
  473. struct sync_file *sync_file = NULL;
  474. if (__cam_dma_fence_find_free_idx(&idx))
  475. goto end;
  476. dma_fence_lock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
  477. if (!dma_fence_lock)
  478. goto free_idx;
  479. dma_fence = kzalloc(sizeof(struct dma_fence), GFP_KERNEL);
  480. if (!dma_fence) {
  481. kfree(dma_fence_lock);
  482. goto free_idx;
  483. }
  484. spin_lock_init(dma_fence_lock);
  485. dma_fence_init(dma_fence, &cam_sync_dma_fence_ops, dma_fence_lock,
  486. g_cam_dma_fence_dev->dma_fence_context,
  487. atomic64_inc_return(&g_cam_dma_fence_seq_no));
  488. fd = get_unused_fd_flags(O_CLOEXEC);
  489. if (fd < 0) {
  490. CAM_ERR(CAM_DMA_FENCE, "failed to get a unused fd: %d", fd);
  491. dma_fence_put(dma_fence);
  492. goto free_idx;
  493. }
  494. sync_file = sync_file_create(dma_fence);
  495. if (!sync_file) {
  496. put_unused_fd(fd);
  497. fd = -1;
  498. dma_fence_put(dma_fence);
  499. goto free_idx;
  500. }
  501. fd_install(fd, sync_file->file);
  502. *row_idx = idx;
  503. __cam_dma_fence_init_row(name, dma_fence, fd, idx, false);
  504. CAM_DBG(CAM_DMA_FENCE, "Created dma fence fd: %d[%s] seqno: %llu row_idx: %u ref_cnt: %u",
  505. fd, name, dma_fence->seqno, idx, kref_read(&dma_fence->refcount));
  506. return fd;
  507. free_idx:
  508. clear_bit(idx, g_cam_dma_fence_dev->bitmap);
  509. end:
  510. return fd;
  511. }
  512. int cam_dma_fence_create_fd(
  513. int32_t *dma_fence_fd, int32_t *dma_fence_row_idx, const char *name)
  514. {
  515. int fd = -1, rc = 0;
  516. if (!dma_fence_fd || !dma_fence_row_idx) {
  517. CAM_ERR(CAM_DMA_FENCE, "Invalid args fd: %pK dma_fence_row_idx: %pK",
  518. dma_fence_fd, dma_fence_row_idx);
  519. return -EINVAL;
  520. }
  521. fd = __cam_dma_fence_get_fd(dma_fence_row_idx, name);
  522. if (fd < 0) {
  523. rc = -EBADFD;
  524. goto end;
  525. }
  526. *dma_fence_fd = fd;
  527. end:
  528. return rc;
  529. }
  530. void __cam_dma_fence_save_previous_monitor_data(int dma_row_idx)
  531. {
  532. struct cam_generic_fence_monitor_data *row_mon_data;
  533. struct cam_dma_fence_row *row;
  534. if (!g_cam_dma_fence_dev->monitor_data)
  535. return;
  536. row = &g_cam_dma_fence_dev->rows[dma_row_idx];
  537. row_mon_data = CAM_GENERIC_MONITOR_GET_DATA(
  538. g_cam_dma_fence_dev->monitor_data, dma_row_idx);
  539. /* save current usage details into prev variables */
  540. strscpy(row_mon_data->prev_name, row->name, CAM_DMA_FENCE_NAME_LEN);
  541. row_mon_data->prev_obj_id = row->fd;
  542. row_mon_data->prev_sync_id = row->sync_obj;
  543. row_mon_data->prev_state = row->state;
  544. row_mon_data->swap_monitor_entries = !row_mon_data->swap_monitor_entries;
  545. row_mon_data->prev_monitor_head = atomic64_read(&row_mon_data->monitor_head);
  546. }
  547. static int __cam_dma_fence_release(int32_t dma_row_idx)
  548. {
  549. struct dma_fence *dma_fence = NULL;
  550. struct cam_dma_fence_row *row = NULL;
  551. int rc;
  552. spin_lock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_row_idx]);
  553. row = &g_cam_dma_fence_dev->rows[dma_row_idx];
  554. dma_fence = row->fence;
  555. if (row->state == CAM_DMA_FENCE_STATE_INVALID) {
  556. CAM_ERR(CAM_DMA_FENCE, "Invalid row index: %u, state: %u",
  557. dma_row_idx, row->state);
  558. rc = -EINVAL;
  559. goto monitor_dump;
  560. }
  561. if (row->state == CAM_DMA_FENCE_STATE_ACTIVE) {
  562. CAM_WARN(CAM_DMA_FENCE,
  563. "Unsignaled fence being released name: %s seqno: %llu fd:%d",
  564. row->name, dma_fence->seqno, row->fd);
  565. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE,
  566. &cam_sync_monitor_mask))
  567. cam_generic_fence_update_monitor_array(dma_row_idx,
  568. &g_cam_dma_fence_dev->dev_lock, g_cam_dma_fence_dev->monitor_data,
  569. CAM_FENCE_OP_SIGNAL);
  570. __cam_dma_fence_signal_fence(dma_fence, -ECANCELED);
  571. }
  572. CAM_DBG(CAM_DMA_FENCE,
  573. "Releasing dma fence with fd: %d[%s] row_idx: %u current ref_cnt: %u",
  574. row->fd, row->name, dma_row_idx, kref_read(&dma_fence->refcount));
  575. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE, &cam_sync_monitor_mask)) {
  576. /* Update monitor entries & save data before row memset to 0 */
  577. cam_generic_fence_update_monitor_array(dma_row_idx,
  578. &g_cam_dma_fence_dev->dev_lock, g_cam_dma_fence_dev->monitor_data,
  579. CAM_FENCE_OP_DESTROY);
  580. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE_DUMP, &cam_sync_monitor_mask))
  581. __cam_dma_fence_dump_monitor_array(dma_row_idx);
  582. __cam_dma_fence_save_previous_monitor_data(dma_row_idx);
  583. }
  584. /* putref on dma fence */
  585. dma_fence_put(dma_fence);
  586. /* deinit row */
  587. memset(row, 0, sizeof(struct cam_dma_fence_row));
  588. clear_bit(dma_row_idx, g_cam_dma_fence_dev->bitmap);
  589. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_row_idx]);
  590. return 0;
  591. monitor_dump:
  592. __cam_dma_fence_dump_monitor_array(dma_row_idx);
  593. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[dma_row_idx]);
  594. return rc;
  595. }
  596. static int __cam_dma_fence_release_fd(int fd)
  597. {
  598. int32_t idx;
  599. struct dma_fence *dma_fence = NULL;
  600. dma_fence = __cam_dma_fence_find_fence_in_table(fd, &idx);
  601. if (IS_ERR_OR_NULL(dma_fence)) {
  602. CAM_ERR(CAM_DMA_FENCE, "Failed to find dma fence for fd: %d", fd);
  603. return -EINVAL;
  604. }
  605. return __cam_dma_fence_release(idx);
  606. }
  607. static int __cam_dma_fence_release_row(
  608. int32_t dma_fence_row_idx)
  609. {
  610. if ((dma_fence_row_idx < 0) ||
  611. (dma_fence_row_idx >= CAM_DMA_FENCE_MAX_FENCES)) {
  612. CAM_ERR(CAM_DMA_FENCE, "dma fence idx: %d is invalid",
  613. dma_fence_row_idx);
  614. return -EINVAL;
  615. }
  616. return __cam_dma_fence_release(dma_fence_row_idx);
  617. }
  618. int cam_dma_fence_release(
  619. struct cam_dma_fence_release_params *release_params)
  620. {
  621. if (release_params->use_row_idx)
  622. return __cam_dma_fence_release_row(release_params->u.dma_row_idx);
  623. else
  624. return __cam_dma_fence_release_fd(release_params->u.dma_fence_fd);
  625. }
  626. void cam_dma_fence_close(void)
  627. {
  628. int i;
  629. struct cam_dma_fence_row *row = NULL;
  630. mutex_lock(&g_cam_dma_fence_dev->dev_lock);
  631. for (i = 0; i < CAM_DMA_FENCE_MAX_FENCES; i++) {
  632. spin_lock_bh(&g_cam_dma_fence_dev->row_spinlocks[i]);
  633. row = &g_cam_dma_fence_dev->rows[i];
  634. if (row->state != CAM_DMA_FENCE_STATE_INVALID) {
  635. CAM_DBG(CAM_DMA_FENCE,
  636. "Releasing dma fence seqno: %llu associated with fd: %d[%s] ref_cnt: %u",
  637. row->fence->seqno, row->fd, row->name,
  638. kref_read(&row->fence->refcount));
  639. /* If registered for cb, remove cb */
  640. if (row->cb_registered_for_sync) {
  641. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE,
  642. &cam_sync_monitor_mask))
  643. cam_generic_fence_update_monitor_array(i,
  644. &g_cam_dma_fence_dev->dev_lock,
  645. g_cam_dma_fence_dev->monitor_data,
  646. CAM_FENCE_OP_UNREGISTER_CB);
  647. dma_fence_remove_callback(row->fence, &row->fence_cb);
  648. }
  649. /* Signal and put if the dma fence is created from camera */
  650. if (!row->ext_dma_fence) {
  651. if (row->state != CAM_DMA_FENCE_STATE_SIGNALED) {
  652. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE,
  653. &cam_sync_monitor_mask))
  654. cam_generic_fence_update_monitor_array(i,
  655. &g_cam_dma_fence_dev->dev_lock,
  656. g_cam_dma_fence_dev->monitor_data,
  657. CAM_FENCE_OP_SIGNAL);
  658. __cam_dma_fence_signal_fence(row->fence, -EADV);
  659. }
  660. dma_fence_put(row->fence);
  661. }
  662. memset(row, 0, sizeof(struct cam_dma_fence_row));
  663. clear_bit(i, g_cam_dma_fence_dev->bitmap);
  664. }
  665. spin_unlock_bh(&g_cam_dma_fence_dev->row_spinlocks[i]);
  666. }
  667. if (g_cam_dma_fence_dev->monitor_data) {
  668. for (i = 0; i < CAM_DMA_FENCE_TABLE_SZ; i++)
  669. kfree(g_cam_dma_fence_dev->monitor_data[i]);
  670. }
  671. kfree(g_cam_dma_fence_dev->monitor_data);
  672. mutex_unlock(&g_cam_dma_fence_dev->dev_lock);
  673. CAM_DBG(CAM_DMA_FENCE, "Close on Camera DMA fence driver");
  674. }
  675. void cam_dma_fence_open(void)
  676. {
  677. mutex_lock(&g_cam_dma_fence_dev->dev_lock);
  678. if (test_bit(CAM_GENERIC_FENCE_TYPE_DMA_FENCE, &cam_sync_monitor_mask)) {
  679. g_cam_dma_fence_dev->monitor_data = kzalloc(
  680. sizeof(struct cam_generic_fence_monitor_data *) *
  681. CAM_DMA_FENCE_TABLE_SZ, GFP_KERNEL);
  682. if (!g_cam_dma_fence_dev->monitor_data) {
  683. CAM_WARN(CAM_DMA_FENCE, "Failed to allocate memory %d",
  684. sizeof(struct cam_generic_fence_monitor_data *) *
  685. CAM_DMA_FENCE_TABLE_SZ);
  686. }
  687. }
  688. /* DMA fence seqno reset */
  689. atomic64_set(&g_cam_dma_fence_seq_no, 0);
  690. mutex_unlock(&g_cam_dma_fence_dev->dev_lock);
  691. CAM_DBG(CAM_DMA_FENCE, "Camera DMA fence driver opened");
  692. }
  693. int cam_dma_fence_driver_init(void)
  694. {
  695. int i;
  696. g_cam_dma_fence_dev = kzalloc(sizeof(struct cam_dma_fence_device), GFP_KERNEL);
  697. if (!g_cam_dma_fence_dev)
  698. return -ENOMEM;
  699. mutex_init(&g_cam_dma_fence_dev->dev_lock);
  700. for (i = 0; i < CAM_DMA_FENCE_MAX_FENCES; i++)
  701. spin_lock_init(&g_cam_dma_fence_dev->row_spinlocks[i]);
  702. bitmap_zero(g_cam_dma_fence_dev->bitmap, CAM_DMA_FENCE_MAX_FENCES);
  703. /* zero will be considered an invalid slot */
  704. set_bit(0, g_cam_dma_fence_dev->bitmap);
  705. g_cam_dma_fence_dev->dma_fence_context = dma_fence_context_alloc(1);
  706. CAM_DBG(CAM_DMA_FENCE, "Camera DMA fence driver initialized");
  707. return 0;
  708. }
  709. void cam_dma_fence_driver_deinit(void)
  710. {
  711. kfree(g_cam_dma_fence_dev);
  712. g_cam_dma_fence_dev = NULL;
  713. CAM_DBG(CAM_DMA_FENCE, "Camera DMA fence driver deinitialized");
  714. }