hal_6390.c 55 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "qdf_types.h"
  20. #include "qdf_util.h"
  21. #include "qdf_types.h"
  22. #include "qdf_lock.h"
  23. #include "qdf_mem.h"
  24. #include "qdf_nbuf.h"
  25. #include "hal_li_hw_headers.h"
  26. #include "hal_internal.h"
  27. #include "hal_api.h"
  28. #include "target_type.h"
  29. #include "wcss_version.h"
  30. #include "qdf_module.h"
  31. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
  32. RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET
  33. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
  34. RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK
  35. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
  36. RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB
  37. #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
  38. PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET
  39. #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
  40. PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET
  41. #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
  42. PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET
  43. #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
  44. PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET
  45. #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
  46. PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET
  47. #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
  48. PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET
  49. #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
  50. PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET
  51. #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
  52. PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET
  53. #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
  54. PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET
  55. #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
  56. PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET
  57. #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
  58. PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET
  59. #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
  60. RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET
  61. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  62. RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
  63. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  64. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
  65. #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  66. RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
  67. #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  68. REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
  69. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
  70. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
  71. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  72. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
  73. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  74. RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
  75. #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  76. TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
  77. #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  78. TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
  79. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
  80. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
  81. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
  82. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
  83. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
  84. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
  85. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
  86. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
  87. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
  88. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
  89. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
  90. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
  91. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
  92. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
  93. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
  94. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
  95. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
  96. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
  97. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
  98. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
  99. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
  100. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
  101. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
  102. WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK
  103. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
  104. WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET
  105. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
  106. WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB
  107. #include "hal_6390_tx.h"
  108. #include "hal_6390_rx.h"
  109. #include <hal_generic_api.h>
  110. #include "hal_li_rx.h"
  111. #include "hal_li_api.h"
  112. #include "hal_li_generic_api.h"
  113. /**
  114. * hal_rx_get_rx_fragment_number_6390(): Function to retrieve rx fragment number
  115. *
  116. * @nbuf: Network buffer
  117. * Returns: rx fragment number
  118. */
  119. static
  120. uint8_t hal_rx_get_rx_fragment_number_6390(uint8_t *buf)
  121. {
  122. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  123. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  124. /* Return first 4 bits as fragment number */
  125. return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
  126. DOT11_SEQ_FRAG_MASK);
  127. }
  128. /**
  129. * hal_rx_msdu_end_da_is_mcbc_get_6390(): API to check if pkt is MCBC
  130. * from rx_msdu_end TLV
  131. *
  132. * @ buf: pointer to the start of RX PKT TLV headers
  133. * Return: da_is_mcbc
  134. */
  135. static uint8_t
  136. hal_rx_msdu_end_da_is_mcbc_get_6390(uint8_t *buf)
  137. {
  138. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  139. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  140. return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
  141. }
  142. /**
  143. * hal_rx_msdu_end_sa_is_valid_get_6390(): API to get_6390 the
  144. * sa_is_valid bit from rx_msdu_end TLV
  145. *
  146. * @ buf: pointer to the start of RX PKT TLV headers
  147. * Return: sa_is_valid bit
  148. */
  149. static uint8_t
  150. hal_rx_msdu_end_sa_is_valid_get_6390(uint8_t *buf)
  151. {
  152. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  153. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  154. uint8_t sa_is_valid;
  155. sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
  156. return sa_is_valid;
  157. }
  158. /**
  159. * hal_rx_msdu_end_sa_idx_get_6390(): API to get_6390 the
  160. * sa_idx from rx_msdu_end TLV
  161. *
  162. * @ buf: pointer to the start of RX PKT TLV headers
  163. * Return: sa_idx (SA AST index)
  164. */
  165. static
  166. uint16_t hal_rx_msdu_end_sa_idx_get_6390(uint8_t *buf)
  167. {
  168. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  169. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  170. uint16_t sa_idx;
  171. sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
  172. return sa_idx;
  173. }
  174. /**
  175. * hal_rx_desc_is_first_msdu_6390() - Check if first msdu
  176. *
  177. * @hal_soc_hdl: hal_soc handle
  178. * @hw_desc_addr: hardware descriptor address
  179. *
  180. * Return: 0 - success/ non-zero failure
  181. */
  182. static uint32_t hal_rx_desc_is_first_msdu_6390(void *hw_desc_addr)
  183. {
  184. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  185. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  186. return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
  187. }
  188. /**
  189. * hal_rx_msdu_end_l3_hdr_padding_get_6390(): API to get_6390 the
  190. * l3_header padding from rx_msdu_end TLV
  191. *
  192. * @ buf: pointer to the start of RX PKT TLV headers
  193. * Return: number of l3 header padding bytes
  194. */
  195. static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6390(uint8_t *buf)
  196. {
  197. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  198. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  199. uint32_t l3_header_padding;
  200. l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  201. return l3_header_padding;
  202. }
  203. /*
  204. * @ hal_rx_encryption_info_valid_6390: Returns encryption type.
  205. *
  206. * @ buf: rx_tlv_hdr of the received packet
  207. * @ Return: encryption type
  208. */
  209. static uint32_t hal_rx_encryption_info_valid_6390(uint8_t *buf)
  210. {
  211. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  212. struct rx_mpdu_start *mpdu_start =
  213. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  214. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  215. uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
  216. return encryption_info;
  217. }
  218. /*
  219. * @ hal_rx_print_pn_6390: Prints the PN of rx packet.
  220. *
  221. * @ buf: rx_tlv_hdr of the received packet
  222. * @ Return: void
  223. */
  224. static void hal_rx_print_pn_6390(uint8_t *buf)
  225. {
  226. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  227. struct rx_mpdu_start *mpdu_start =
  228. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  229. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  230. uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
  231. uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
  232. uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
  233. uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
  234. hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ",
  235. pn_127_96, pn_95_64, pn_63_32, pn_31_0);
  236. }
  237. /**
  238. * hal_rx_msdu_end_first_msduget_6390: API to get first msdu status
  239. * from rx_msdu_end TLV
  240. *
  241. * @ buf: pointer to the start of RX PKT TLV headers
  242. * Return: first_msdu
  243. */
  244. static uint8_t hal_rx_msdu_end_first_msdu_get_6390(uint8_t *buf)
  245. {
  246. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  247. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  248. uint8_t first_msdu;
  249. first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
  250. return first_msdu;
  251. }
  252. /**
  253. * hal_rx_msdu_end_da_is_valid_get_6390: API to check if da is valid
  254. * from rx_msdu_end TLV
  255. *
  256. * @ buf: pointer to the start of RX PKT TLV headers
  257. * Return: da_is_valid
  258. */
  259. static uint8_t hal_rx_msdu_end_da_is_valid_get_6390(uint8_t *buf)
  260. {
  261. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  262. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  263. uint8_t da_is_valid;
  264. da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
  265. return da_is_valid;
  266. }
  267. /**
  268. * hal_rx_msdu_end_last_msdu_get_6390: API to get last msdu status
  269. * from rx_msdu_end TLV
  270. *
  271. * @ buf: pointer to the start of RX PKT TLV headers
  272. * Return: last_msdu
  273. */
  274. static uint8_t hal_rx_msdu_end_last_msdu_get_6390(uint8_t *buf)
  275. {
  276. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  277. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  278. uint8_t last_msdu;
  279. last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
  280. return last_msdu;
  281. }
  282. /*
  283. * hal_rx_get_mpdu_mac_ad4_valid_6390(): Retrieves if mpdu 4th addr is valid
  284. *
  285. * @nbuf: Network buffer
  286. * Returns: value of mpdu 4th address valid field
  287. */
  288. static bool hal_rx_get_mpdu_mac_ad4_valid_6390(uint8_t *buf)
  289. {
  290. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  291. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  292. bool ad4_valid = 0;
  293. ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info);
  294. return ad4_valid;
  295. }
  296. /**
  297. * hal_rx_mpdu_start_sw_peer_id_get_6390: Retrieve sw peer_id
  298. * @buf: network buffer
  299. *
  300. * Return: sw peer_id
  301. */
  302. static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6390(uint8_t *buf)
  303. {
  304. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  305. struct rx_mpdu_start *mpdu_start =
  306. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  307. return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
  308. &mpdu_start->rx_mpdu_info_details);
  309. }
  310. /*
  311. * hal_rx_mpdu_get_to_ds_6390(): API to get the tods info
  312. * from rx_mpdu_start
  313. *
  314. * @buf: pointer to the start of RX PKT TLV header
  315. * Return: uint32_t(to_ds)
  316. */
  317. static uint32_t hal_rx_mpdu_get_to_ds_6390(uint8_t *buf)
  318. {
  319. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  320. struct rx_mpdu_start *mpdu_start =
  321. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  322. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  323. return HAL_RX_MPDU_GET_TODS(mpdu_info);
  324. }
  325. /*
  326. * hal_rx_mpdu_get_fr_ds_6390(): API to get the from ds info
  327. * from rx_mpdu_start
  328. *
  329. * @buf: pointer to the start of RX PKT TLV header
  330. * Return: uint32_t(fr_ds)
  331. */
  332. static uint32_t hal_rx_mpdu_get_fr_ds_6390(uint8_t *buf)
  333. {
  334. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  335. struct rx_mpdu_start *mpdu_start =
  336. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  337. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  338. return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
  339. }
  340. /*
  341. * hal_rx_get_mpdu_frame_control_valid_6390(): Retrieves mpdu
  342. * frame control valid
  343. *
  344. * @nbuf: Network buffer
  345. * Returns: value of frame control valid field
  346. */
  347. static uint8_t hal_rx_get_mpdu_frame_control_valid_6390(uint8_t *buf)
  348. {
  349. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  350. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  351. return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
  352. }
  353. /*
  354. * hal_rx_mpdu_get_addr1_6390(): API to check get address1 of the mpdu
  355. *
  356. * @buf: pointer to the start of RX PKT TLV headera
  357. * @mac_addr: pointer to mac address
  358. * Return: success/failure
  359. */
  360. static QDF_STATUS hal_rx_mpdu_get_addr1_6390(uint8_t *buf, uint8_t *mac_addr)
  361. {
  362. struct __attribute__((__packed__)) hal_addr1 {
  363. uint32_t ad1_31_0;
  364. uint16_t ad1_47_32;
  365. };
  366. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  367. struct rx_mpdu_start *mpdu_start =
  368. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  369. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  370. struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
  371. uint32_t mac_addr_ad1_valid;
  372. mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
  373. if (mac_addr_ad1_valid) {
  374. addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
  375. addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
  376. return QDF_STATUS_SUCCESS;
  377. }
  378. return QDF_STATUS_E_FAILURE;
  379. }
  380. /*
  381. * hal_rx_mpdu_get_addr2_6390(): API to check get address2 of the mpdu
  382. * in the packet
  383. *
  384. * @buf: pointer to the start of RX PKT TLV header
  385. * @mac_addr: pointer to mac address
  386. * Return: success/failure
  387. */
  388. static QDF_STATUS hal_rx_mpdu_get_addr2_6390(uint8_t *buf,
  389. uint8_t *mac_addr)
  390. {
  391. struct __attribute__((__packed__)) hal_addr2 {
  392. uint16_t ad2_15_0;
  393. uint32_t ad2_47_16;
  394. };
  395. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  396. struct rx_mpdu_start *mpdu_start =
  397. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  398. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  399. struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
  400. uint32_t mac_addr_ad2_valid;
  401. mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
  402. if (mac_addr_ad2_valid) {
  403. addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
  404. addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
  405. return QDF_STATUS_SUCCESS;
  406. }
  407. return QDF_STATUS_E_FAILURE;
  408. }
  409. /*
  410. * hal_rx_mpdu_get_addr3_6390(): API to get address3 of the mpdu
  411. * in the packet
  412. *
  413. * @buf: pointer to the start of RX PKT TLV header
  414. * @mac_addr: pointer to mac address
  415. * Return: success/failure
  416. */
  417. static QDF_STATUS hal_rx_mpdu_get_addr3_6390(uint8_t *buf, uint8_t *mac_addr)
  418. {
  419. struct __attribute__((__packed__)) hal_addr3 {
  420. uint32_t ad3_31_0;
  421. uint16_t ad3_47_32;
  422. };
  423. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  424. struct rx_mpdu_start *mpdu_start =
  425. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  426. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  427. struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
  428. uint32_t mac_addr_ad3_valid;
  429. mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
  430. if (mac_addr_ad3_valid) {
  431. addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
  432. addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
  433. return QDF_STATUS_SUCCESS;
  434. }
  435. return QDF_STATUS_E_FAILURE;
  436. }
  437. /*
  438. * hal_rx_mpdu_get_addr4_6390(): API to get address4 of the mpdu
  439. * in the packet
  440. *
  441. * @buf: pointer to the start of RX PKT TLV header
  442. * @mac_addr: pointer to mac address
  443. * Return: success/failure
  444. */
  445. static QDF_STATUS hal_rx_mpdu_get_addr4_6390(uint8_t *buf, uint8_t *mac_addr)
  446. {
  447. struct __attribute__((__packed__)) hal_addr4 {
  448. uint32_t ad4_31_0;
  449. uint16_t ad4_47_32;
  450. };
  451. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  452. struct rx_mpdu_start *mpdu_start =
  453. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  454. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  455. struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
  456. uint32_t mac_addr_ad4_valid;
  457. mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
  458. if (mac_addr_ad4_valid) {
  459. addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
  460. addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
  461. return QDF_STATUS_SUCCESS;
  462. }
  463. return QDF_STATUS_E_FAILURE;
  464. }
  465. /*
  466. * hal_rx_get_mpdu_sequence_control_valid_6390(): Get mpdu
  467. * sequence control valid
  468. *
  469. * @nbuf: Network buffer
  470. * Returns: value of sequence control valid field
  471. */
  472. static uint8_t hal_rx_get_mpdu_sequence_control_valid_6390(uint8_t *buf)
  473. {
  474. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  475. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  476. return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
  477. }
  478. /**
  479. * hal_rx_is_unicast_6390: check packet is unicast frame or not.
  480. *
  481. * @ buf: pointer to rx pkt TLV.
  482. *
  483. * Return: true on unicast.
  484. */
  485. static bool hal_rx_is_unicast_6390(uint8_t *buf)
  486. {
  487. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  488. struct rx_mpdu_start *mpdu_start =
  489. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  490. uint32_t grp_id;
  491. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  492. grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  493. RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
  494. RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
  495. RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
  496. return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
  497. }
  498. /**
  499. * hal_rx_tid_get_6390: get tid based on qos control valid.
  500. * @hal_soc_hdl: hal soc handle
  501. * @buf: pointer to rx pkt TLV.
  502. *
  503. * Return: tid
  504. */
  505. static uint32_t hal_rx_tid_get_6390(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  506. {
  507. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  508. struct rx_mpdu_start *mpdu_start =
  509. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  510. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  511. uint8_t qos_control_valid =
  512. (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  513. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)),
  514. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK,
  515. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB));
  516. if (qos_control_valid)
  517. return hal_rx_mpdu_start_tid_get_6390(buf);
  518. return HAL_RX_NON_QOS_TID;
  519. }
  520. /**
  521. * hal_rx_hw_desc_get_ppduid_get_6390(): retrieve ppdu id
  522. * @rx_tlv_hdr: start address of rx_pkt_tlvs
  523. * @rxdma_dst_ring_desc: Rx HW descriptor
  524. *
  525. * Return: ppdu id
  526. */
  527. static uint32_t hal_rx_hw_desc_get_ppduid_get_6390(void *rx_tlv_hdr,
  528. void *rxdma_dst_ring_desc)
  529. {
  530. struct rx_mpdu_info *rx_mpdu_info;
  531. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
  532. rx_mpdu_info =
  533. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  534. return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
  535. }
  536. /**
  537. * hal_reo_status_get_header_6390 - Process reo desc info
  538. * @ring_desc: REO status ring descriptor
  539. * @b - tlv type info
  540. * @h1 - Pointer to hal_reo_status_header where info to be stored
  541. *
  542. * Return - none.
  543. *
  544. */
  545. static void hal_reo_status_get_header_6390(hal_ring_desc_t ring_desc, int b,
  546. void *h1)
  547. {
  548. uint32_t *d = (uint32_t *)ring_desc;
  549. uint32_t val1 = 0;
  550. struct hal_reo_status_header *h =
  551. (struct hal_reo_status_header *)h1;
  552. /* Offsets of descriptor fields defined in HW headers start
  553. * from the field after TLV header
  554. */
  555. d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
  556. switch (b) {
  557. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  558. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
  559. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  560. break;
  561. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  562. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
  563. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  564. break;
  565. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  566. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
  567. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  568. break;
  569. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  570. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
  571. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  572. break;
  573. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  574. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
  575. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  576. break;
  577. case HAL_REO_DESC_THRES_STATUS_TLV:
  578. val1 =
  579. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
  580. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  581. break;
  582. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  583. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
  584. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  585. break;
  586. default:
  587. qdf_nofl_err("ERROR: Unknown tlv\n");
  588. break;
  589. }
  590. h->cmd_num =
  591. HAL_GET_FIELD(
  592. UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
  593. val1);
  594. h->exec_time =
  595. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  596. CMD_EXECUTION_TIME, val1);
  597. h->status =
  598. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  599. REO_CMD_EXECUTION_STATUS, val1);
  600. switch (b) {
  601. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  602. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
  603. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  604. break;
  605. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  606. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
  607. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  608. break;
  609. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  610. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
  611. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  612. break;
  613. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  614. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
  615. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  616. break;
  617. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  618. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
  619. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  620. break;
  621. case HAL_REO_DESC_THRES_STATUS_TLV:
  622. val1 =
  623. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
  624. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  625. break;
  626. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  627. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
  628. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  629. break;
  630. default:
  631. qdf_nofl_err("ERROR: Unknown tlv\n");
  632. break;
  633. }
  634. h->tstamp =
  635. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
  636. }
  637. /**
  638. * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390():
  639. * Retrieve qos control valid bit from the tlv.
  640. * @buf: pointer to rx pkt TLV.
  641. *
  642. * Return: qos control value.
  643. */
  644. static inline uint32_t
  645. hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(uint8_t *buf)
  646. {
  647. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  648. struct rx_mpdu_start *mpdu_start =
  649. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  650. return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
  651. &mpdu_start->rx_mpdu_info_details);
  652. }
  653. /**
  654. * hal_rx_msdu_end_sa_sw_peer_id_get_6390(): API to get the
  655. * sa_sw_peer_id from rx_msdu_end TLV
  656. * @buf: pointer to the start of RX PKT TLV headers
  657. *
  658. * Return: sa_sw_peer_id index
  659. */
  660. static inline uint32_t
  661. hal_rx_msdu_end_sa_sw_peer_id_get_6390(uint8_t *buf)
  662. {
  663. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  664. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  665. return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
  666. }
  667. /**
  668. * hal_tx_desc_set_mesh_en_6390 - Set mesh_enable flag in Tx descriptor
  669. * @desc: Handle to Tx Descriptor
  670. * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
  671. * enabling the interpretation of the 'Mesh Control Present' bit
  672. * (bit 8) of QoS Control (otherwise this bit is ignored),
  673. * For native WiFi frames, this indicates that a 'Mesh Control' field
  674. * is present between the header and the LLC.
  675. *
  676. * Return: void
  677. */
  678. static inline
  679. void hal_tx_desc_set_mesh_en_6390(void *desc, uint8_t en)
  680. {
  681. HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
  682. HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
  683. }
  684. static
  685. void *hal_rx_msdu0_buffer_addr_lsb_6390(void *link_desc_va)
  686. {
  687. return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
  688. }
  689. static
  690. void *hal_rx_msdu_desc_info_ptr_get_6390(void *msdu0)
  691. {
  692. return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
  693. }
  694. static
  695. void *hal_ent_mpdu_desc_info_6390(void *ent_ring_desc)
  696. {
  697. return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
  698. }
  699. static
  700. void *hal_dst_mpdu_desc_info_6390(void *dst_ring_desc)
  701. {
  702. return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
  703. }
  704. static
  705. uint8_t hal_rx_get_fc_valid_6390(uint8_t *buf)
  706. {
  707. return HAL_RX_GET_FC_VALID(buf);
  708. }
  709. static uint8_t hal_rx_get_to_ds_flag_6390(uint8_t *buf)
  710. {
  711. return HAL_RX_GET_TO_DS_FLAG(buf);
  712. }
  713. static uint8_t hal_rx_get_mac_addr2_valid_6390(uint8_t *buf)
  714. {
  715. return HAL_RX_GET_MAC_ADDR2_VALID(buf);
  716. }
  717. static uint8_t hal_rx_get_filter_category_6390(uint8_t *buf)
  718. {
  719. return HAL_RX_GET_FILTER_CATEGORY(buf);
  720. }
  721. static uint32_t
  722. hal_rx_get_ppdu_id_6390(uint8_t *buf)
  723. {
  724. return HAL_RX_GET_PPDU_ID(buf);
  725. }
  726. /**
  727. * hal_reo_config_6390(): Set reo config parameters
  728. * @soc: hal soc handle
  729. * @reg_val: value to be set
  730. * @reo_params: reo parameters
  731. *
  732. * Return: void
  733. */
  734. static
  735. void hal_reo_config_6390(struct hal_soc *soc,
  736. uint32_t reg_val,
  737. struct hal_reo_params *reo_params)
  738. {
  739. HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
  740. }
  741. /**
  742. * hal_rx_msdu_desc_info_get_ptr_6390() - Get msdu desc info ptr
  743. * @msdu_details_ptr - Pointer to msdu_details_ptr
  744. * Return - Pointer to rx_msdu_desc_info structure.
  745. *
  746. */
  747. static void *hal_rx_msdu_desc_info_get_ptr_6390(void *msdu_details_ptr)
  748. {
  749. return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
  750. }
  751. /**
  752. * hal_rx_link_desc_msdu0_ptr_6390 - Get pointer to rx_msdu details
  753. * @link_desc - Pointer to link desc
  754. * Return - Pointer to rx_msdu_details structure
  755. *
  756. */
  757. static void *hal_rx_link_desc_msdu0_ptr_6390(void *link_desc)
  758. {
  759. return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
  760. }
  761. /**
  762. * hal_rx_msdu_flow_idx_get_6390: API to get flow index
  763. * from rx_msdu_end TLV
  764. * @buf: pointer to the start of RX PKT TLV headers
  765. *
  766. * Return: flow index value from MSDU END TLV
  767. */
  768. static inline uint32_t hal_rx_msdu_flow_idx_get_6390(uint8_t *buf)
  769. {
  770. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  771. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  772. return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  773. }
  774. /**
  775. * hal_rx_msdu_flow_idx_invalid_6390: API to get flow index invalid
  776. * from rx_msdu_end TLV
  777. * @buf: pointer to the start of RX PKT TLV headers
  778. *
  779. * Return: flow index invalid value from MSDU END TLV
  780. */
  781. static bool hal_rx_msdu_flow_idx_invalid_6390(uint8_t *buf)
  782. {
  783. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  784. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  785. return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  786. }
  787. /**
  788. * hal_rx_msdu_flow_idx_timeout_6390: API to get flow index timeout
  789. * from rx_msdu_end TLV
  790. * @buf: pointer to the start of RX PKT TLV headers
  791. *
  792. * Return: flow index timeout value from MSDU END TLV
  793. */
  794. static bool hal_rx_msdu_flow_idx_timeout_6390(uint8_t *buf)
  795. {
  796. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  797. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  798. return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  799. }
  800. /**
  801. * hal_rx_msdu_fse_metadata_get_6390: API to get FSE metadata
  802. * from rx_msdu_end TLV
  803. * @buf: pointer to the start of RX PKT TLV headers
  804. *
  805. * Return: fse metadata value from MSDU END TLV
  806. */
  807. static uint32_t hal_rx_msdu_fse_metadata_get_6390(uint8_t *buf)
  808. {
  809. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  810. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  811. return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
  812. }
  813. /**
  814. * hal_rx_msdu_cce_metadata_get_6390: API to get CCE metadata
  815. * from rx_msdu_end TLV
  816. * @buf: pointer to the start of RX PKT TLV headers
  817. *
  818. * Return: cce metadata
  819. */
  820. static uint16_t
  821. hal_rx_msdu_cce_metadata_get_6390(uint8_t *buf)
  822. {
  823. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  824. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  825. return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
  826. }
  827. /**
  828. * hal_rx_msdu_get_flow_params_6390: API to get flow index, flow index invalid
  829. * and flow index timeout from rx_msdu_end TLV
  830. * @buf: pointer to the start of RX PKT TLV headers
  831. * @flow_invalid: pointer to return value of flow_idx_valid
  832. * @flow_timeout: pointer to return value of flow_idx_timeout
  833. * @flow_index: pointer to return value of flow_idx
  834. *
  835. * Return: none
  836. */
  837. static inline void
  838. hal_rx_msdu_get_flow_params_6390(uint8_t *buf,
  839. bool *flow_invalid,
  840. bool *flow_timeout,
  841. uint32_t *flow_index)
  842. {
  843. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  844. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  845. *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  846. *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  847. *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  848. }
  849. /**
  850. * hal_rx_tlv_get_tcp_chksum_6390() - API to get tcp checksum
  851. * @buf: rx_tlv_hdr
  852. *
  853. * Return: tcp checksum
  854. */
  855. static uint16_t
  856. hal_rx_tlv_get_tcp_chksum_6390(uint8_t *buf)
  857. {
  858. return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
  859. }
  860. /**
  861. * hal_rx_get_rx_sequence_6390(): Function to retrieve rx sequence number
  862. *
  863. * @nbuf: Network buffer
  864. * Returns: rx sequence number
  865. */
  866. static
  867. uint16_t hal_rx_get_rx_sequence_6390(uint8_t *buf)
  868. {
  869. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  870. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  871. return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
  872. }
  873. /**
  874. * hal_rx_mpdu_start_tlv_tag_valid_6390 () - API to check if RX_MPDU_START
  875. * tlv tag is valid
  876. *
  877. *@rx_tlv_hdr: start address of rx_pkt_tlvs
  878. *
  879. * Return: true if RX_MPDU_START is valied, else false.
  880. */
  881. static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6390(void *rx_tlv_hdr)
  882. {
  883. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
  884. uint32_t tlv_tag;
  885. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv);
  886. return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
  887. }
  888. /**
  889. * hal_get_window_address_6390(): Function to get hp/tp address
  890. * @hal_soc: Pointer to hal_soc
  891. * @addr: address offset of register
  892. *
  893. * Return: modified address offset of register
  894. */
  895. static inline qdf_iomem_t hal_get_window_address_6390(struct hal_soc *hal_soc,
  896. qdf_iomem_t addr)
  897. {
  898. return addr;
  899. }
  900. /**
  901. * hal_reo_set_err_dst_remap_6390(): Function to set REO error destination
  902. * ring remap register
  903. * @hal_soc: Pointer to hal_soc
  904. *
  905. * Return: none.
  906. */
  907. static void
  908. hal_reo_set_err_dst_remap_6390(void *hal_soc)
  909. {
  910. /*
  911. * Set REO error 2k jump (error code 5) / OOR (error code 7)
  912. * frame routed to REO2TCL ring.
  913. */
  914. uint32_t dst_remap_ix0 =
  915. HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) |
  916. HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) |
  917. HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) |
  918. HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) |
  919. HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) |
  920. HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) |
  921. HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) |
  922. HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7) |
  923. HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 8) |
  924. HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 9);
  925. HAL_REG_WRITE(hal_soc,
  926. HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
  927. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  928. dst_remap_ix0);
  929. hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x",
  930. HAL_REG_READ(
  931. hal_soc,
  932. HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
  933. SEQ_WCSS_UMAC_REO_REG_OFFSET)));
  934. }
  935. static
  936. void hal_compute_reo_remap_ix2_ix3_6390(uint32_t *ring, uint32_t num_rings,
  937. uint32_t *remap1, uint32_t *remap2)
  938. {
  939. switch (num_rings) {
  940. case 3:
  941. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  942. HAL_REO_REMAP_IX2(ring[1], 17) |
  943. HAL_REO_REMAP_IX2(ring[2], 18) |
  944. HAL_REO_REMAP_IX2(ring[0], 19) |
  945. HAL_REO_REMAP_IX2(ring[1], 20) |
  946. HAL_REO_REMAP_IX2(ring[2], 21) |
  947. HAL_REO_REMAP_IX2(ring[0], 22) |
  948. HAL_REO_REMAP_IX2(ring[1], 23);
  949. *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
  950. HAL_REO_REMAP_IX3(ring[0], 25) |
  951. HAL_REO_REMAP_IX3(ring[1], 26) |
  952. HAL_REO_REMAP_IX3(ring[2], 27) |
  953. HAL_REO_REMAP_IX3(ring[0], 28) |
  954. HAL_REO_REMAP_IX3(ring[1], 29) |
  955. HAL_REO_REMAP_IX3(ring[2], 30) |
  956. HAL_REO_REMAP_IX3(ring[0], 31);
  957. break;
  958. case 4:
  959. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  960. HAL_REO_REMAP_IX2(ring[1], 17) |
  961. HAL_REO_REMAP_IX2(ring[2], 18) |
  962. HAL_REO_REMAP_IX2(ring[3], 19) |
  963. HAL_REO_REMAP_IX2(ring[0], 20) |
  964. HAL_REO_REMAP_IX2(ring[1], 21) |
  965. HAL_REO_REMAP_IX2(ring[2], 22) |
  966. HAL_REO_REMAP_IX2(ring[3], 23);
  967. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  968. HAL_REO_REMAP_IX3(ring[1], 25) |
  969. HAL_REO_REMAP_IX3(ring[2], 26) |
  970. HAL_REO_REMAP_IX3(ring[3], 27) |
  971. HAL_REO_REMAP_IX3(ring[0], 28) |
  972. HAL_REO_REMAP_IX3(ring[1], 29) |
  973. HAL_REO_REMAP_IX3(ring[2], 30) |
  974. HAL_REO_REMAP_IX3(ring[3], 31);
  975. break;
  976. }
  977. }
  978. #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
  979. /**
  980. * hal_get_first_wow_wakeup_packet_6390(): Function to get if the buffer
  981. * is the first one that wakes up host from WoW.
  982. *
  983. * @buf: network buffer
  984. *
  985. * Dummy function for QCA6390
  986. *
  987. * Returns: 1 to indicate it is first packet received that wakes up host from
  988. * WoW. Otherwise 0
  989. */
  990. static inline uint8_t hal_get_first_wow_wakeup_packet_6390(uint8_t *buf)
  991. {
  992. return 0;
  993. }
  994. #endif
  995. static void hal_hw_txrx_ops_attach_qca6390(struct hal_soc *hal_soc)
  996. {
  997. /* init and setup */
  998. hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
  999. hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
  1000. hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
  1001. hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
  1002. hal_soc->ops->hal_get_window_address = hal_get_window_address_6390;
  1003. hal_soc->ops->hal_reo_set_err_dst_remap =
  1004. hal_reo_set_err_dst_remap_6390;
  1005. /* tx */
  1006. hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
  1007. hal_tx_desc_set_dscp_tid_table_id_6390;
  1008. hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6390;
  1009. hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6390;
  1010. hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6390;
  1011. hal_soc->ops->hal_tx_desc_set_buf_addr =
  1012. hal_tx_desc_set_buf_addr_generic_li;
  1013. hal_soc->ops->hal_tx_desc_set_search_type =
  1014. hal_tx_desc_set_search_type_generic_li;
  1015. hal_soc->ops->hal_tx_desc_set_search_index =
  1016. hal_tx_desc_set_search_index_generic_li;
  1017. hal_soc->ops->hal_tx_desc_set_cache_set_num =
  1018. hal_tx_desc_set_cache_set_num_generic_li;
  1019. hal_soc->ops->hal_tx_comp_get_status =
  1020. hal_tx_comp_get_status_generic_li;
  1021. hal_soc->ops->hal_tx_comp_get_release_reason =
  1022. hal_tx_comp_get_release_reason_generic_li;
  1023. hal_soc->ops->hal_get_wbm_internal_error =
  1024. hal_get_wbm_internal_error_generic_li;
  1025. hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6390;
  1026. hal_soc->ops->hal_tx_init_cmd_credit_ring =
  1027. hal_tx_init_cmd_credit_ring_6390;
  1028. /* rx */
  1029. hal_soc->ops->hal_rx_msdu_start_nss_get =
  1030. hal_rx_msdu_start_nss_get_6390;
  1031. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
  1032. hal_rx_mon_hw_desc_get_mpdu_status_6390;
  1033. hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6390;
  1034. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
  1035. hal_rx_proc_phyrx_other_receive_info_tlv_6390;
  1036. hal_soc->ops->hal_rx_dump_msdu_start_tlv =
  1037. hal_rx_dump_msdu_start_tlv_6390;
  1038. hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6390;
  1039. hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6390;
  1040. hal_soc->ops->hal_rx_mpdu_start_tid_get =
  1041. hal_rx_mpdu_start_tid_get_6390;
  1042. hal_soc->ops->hal_rx_msdu_start_reception_type_get =
  1043. hal_rx_msdu_start_reception_type_get_6390;
  1044. hal_soc->ops->hal_rx_msdu_end_da_idx_get =
  1045. hal_rx_msdu_end_da_idx_get_6390;
  1046. hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
  1047. hal_rx_msdu_desc_info_get_ptr_6390;
  1048. hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
  1049. hal_rx_link_desc_msdu0_ptr_6390;
  1050. hal_soc->ops->hal_reo_status_get_header =
  1051. hal_reo_status_get_header_6390;
  1052. hal_soc->ops->hal_rx_status_get_tlv_info =
  1053. hal_rx_status_get_tlv_info_generic_li;
  1054. hal_soc->ops->hal_rx_wbm_err_info_get =
  1055. hal_rx_wbm_err_info_get_generic_li;
  1056. hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
  1057. hal_rx_dump_mpdu_start_tlv_generic_li;
  1058. hal_soc->ops->hal_tx_set_pcp_tid_map =
  1059. hal_tx_set_pcp_tid_map_generic_li;
  1060. hal_soc->ops->hal_tx_update_pcp_tid_map =
  1061. hal_tx_update_pcp_tid_generic_li;
  1062. hal_soc->ops->hal_tx_set_tidmap_prty =
  1063. hal_tx_update_tidmap_prty_generic_li;
  1064. hal_soc->ops->hal_rx_get_rx_fragment_number =
  1065. hal_rx_get_rx_fragment_number_6390;
  1066. hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
  1067. hal_rx_msdu_end_da_is_mcbc_get_6390;
  1068. hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
  1069. hal_rx_msdu_end_sa_is_valid_get_6390;
  1070. hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
  1071. hal_rx_msdu_end_sa_idx_get_6390;
  1072. hal_soc->ops->hal_rx_desc_is_first_msdu =
  1073. hal_rx_desc_is_first_msdu_6390;
  1074. hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
  1075. hal_rx_msdu_end_l3_hdr_padding_get_6390;
  1076. hal_soc->ops->hal_rx_encryption_info_valid =
  1077. hal_rx_encryption_info_valid_6390;
  1078. hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6390;
  1079. hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
  1080. hal_rx_msdu_end_first_msdu_get_6390;
  1081. hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
  1082. hal_rx_msdu_end_da_is_valid_get_6390;
  1083. hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
  1084. hal_rx_msdu_end_last_msdu_get_6390;
  1085. hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
  1086. hal_rx_get_mpdu_mac_ad4_valid_6390;
  1087. hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
  1088. hal_rx_mpdu_start_sw_peer_id_get_6390;
  1089. hal_soc->ops->hal_rx_mpdu_peer_meta_data_get =
  1090. hal_rx_mpdu_peer_meta_data_get_li;
  1091. hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6390;
  1092. hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6390;
  1093. hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
  1094. hal_rx_get_mpdu_frame_control_valid_6390;
  1095. hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6390;
  1096. hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6390;
  1097. hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6390;
  1098. hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6390;
  1099. hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
  1100. hal_rx_get_mpdu_sequence_control_valid_6390;
  1101. hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6390;
  1102. hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6390;
  1103. hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
  1104. hal_rx_hw_desc_get_ppduid_get_6390;
  1105. hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
  1106. hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390;
  1107. hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
  1108. hal_rx_msdu_end_sa_sw_peer_id_get_6390;
  1109. hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
  1110. hal_rx_msdu0_buffer_addr_lsb_6390;
  1111. hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
  1112. hal_rx_msdu_desc_info_ptr_get_6390;
  1113. hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6390;
  1114. hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6390;
  1115. hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6390;
  1116. hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6390;
  1117. hal_soc->ops->hal_rx_get_mac_addr2_valid =
  1118. hal_rx_get_mac_addr2_valid_6390;
  1119. hal_soc->ops->hal_rx_get_filter_category =
  1120. hal_rx_get_filter_category_6390;
  1121. hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6390;
  1122. hal_soc->ops->hal_reo_config = hal_reo_config_6390;
  1123. hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6390;
  1124. hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
  1125. hal_rx_msdu_flow_idx_invalid_6390;
  1126. hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
  1127. hal_rx_msdu_flow_idx_timeout_6390;
  1128. hal_soc->ops->hal_rx_msdu_fse_metadata_get =
  1129. hal_rx_msdu_fse_metadata_get_6390;
  1130. hal_soc->ops->hal_rx_msdu_cce_match_get =
  1131. hal_rx_msdu_cce_match_get_li;
  1132. hal_soc->ops->hal_rx_msdu_cce_metadata_get =
  1133. hal_rx_msdu_cce_metadata_get_6390;
  1134. hal_soc->ops->hal_rx_msdu_get_flow_params =
  1135. hal_rx_msdu_get_flow_params_6390;
  1136. hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
  1137. hal_rx_tlv_get_tcp_chksum_6390;
  1138. hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6390;
  1139. /* rx - msdu end fast path info fields */
  1140. hal_soc->ops->hal_rx_msdu_packet_metadata_get =
  1141. hal_rx_msdu_packet_metadata_get_generic_li;
  1142. hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
  1143. hal_rx_mpdu_start_tlv_tag_valid_6390;
  1144. /* rx - TLV struct offsets */
  1145. hal_soc->ops->hal_rx_msdu_end_offset_get =
  1146. hal_rx_msdu_end_offset_get_generic;
  1147. hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
  1148. hal_soc->ops->hal_rx_msdu_start_offset_get =
  1149. hal_rx_msdu_start_offset_get_generic;
  1150. hal_soc->ops->hal_rx_mpdu_start_offset_get =
  1151. hal_rx_mpdu_start_offset_get_generic;
  1152. hal_soc->ops->hal_rx_mpdu_end_offset_get =
  1153. hal_rx_mpdu_end_offset_get_generic;
  1154. #ifndef NO_RX_PKT_HDR_TLV
  1155. hal_soc->ops->hal_rx_pkt_tlv_offset_get =
  1156. hal_rx_pkt_tlv_offset_get_generic;
  1157. #endif
  1158. hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
  1159. hal_compute_reo_remap_ix2_ix3_6390;
  1160. hal_soc->ops->hal_setup_link_idle_list =
  1161. hal_setup_link_idle_list_generic_li;
  1162. #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
  1163. hal_soc->ops->hal_get_first_wow_wakeup_packet =
  1164. hal_get_first_wow_wakeup_packet_6390;
  1165. #endif
  1166. };
  1167. struct hal_hw_srng_config hw_srng_table_6390[] = {
  1168. /* TODO: max_rings can populated by querying HW capabilities */
  1169. { /* REO_DST */
  1170. .start_ring_id = HAL_SRNG_REO2SW1,
  1171. .max_rings = 4,
  1172. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1173. .lmac_ring = FALSE,
  1174. .ring_dir = HAL_SRNG_DST_RING,
  1175. .reg_start = {
  1176. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
  1177. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1178. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
  1179. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1180. },
  1181. .reg_size = {
  1182. HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
  1183. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
  1184. HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
  1185. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
  1186. },
  1187. .max_size =
  1188. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1189. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
  1190. },
  1191. { /* REO_EXCEPTION */
  1192. /* Designating REO2TCL ring as exception ring. This ring is
  1193. * similar to other REO2SW rings though it is named as REO2TCL.
  1194. * Any of theREO2SW rings can be used as exception ring.
  1195. */
  1196. .start_ring_id = HAL_SRNG_REO2TCL,
  1197. .max_rings = 1,
  1198. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1199. .lmac_ring = FALSE,
  1200. .ring_dir = HAL_SRNG_DST_RING,
  1201. .reg_start = {
  1202. HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
  1203. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1204. HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
  1205. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1206. },
  1207. /* Single ring - provide ring size if multiple rings of this
  1208. * type are supported
  1209. */
  1210. .reg_size = {},
  1211. .max_size =
  1212. HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
  1213. HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
  1214. },
  1215. { /* REO_REINJECT */
  1216. .start_ring_id = HAL_SRNG_SW2REO,
  1217. .max_rings = 1,
  1218. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1219. .lmac_ring = FALSE,
  1220. .ring_dir = HAL_SRNG_SRC_RING,
  1221. .reg_start = {
  1222. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
  1223. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1224. HWIO_REO_R2_SW2REO_RING_HP_ADDR(
  1225. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1226. },
  1227. /* Single ring - provide ring size if multiple rings of this
  1228. * type are supported
  1229. */
  1230. .reg_size = {},
  1231. .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
  1232. HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
  1233. },
  1234. { /* REO_CMD */
  1235. .start_ring_id = HAL_SRNG_REO_CMD,
  1236. .max_rings = 1,
  1237. .entry_size = (sizeof(struct tlv_32_hdr) +
  1238. sizeof(struct reo_get_queue_stats)) >> 2,
  1239. .lmac_ring = FALSE,
  1240. .ring_dir = HAL_SRNG_SRC_RING,
  1241. .reg_start = {
  1242. HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
  1243. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1244. HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
  1245. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1246. },
  1247. /* Single ring - provide ring size if multiple rings of this
  1248. * type are supported
  1249. */
  1250. .reg_size = {},
  1251. .max_size =
  1252. HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1253. HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1254. },
  1255. { /* REO_STATUS */
  1256. .start_ring_id = HAL_SRNG_REO_STATUS,
  1257. .max_rings = 1,
  1258. .entry_size = (sizeof(struct tlv_32_hdr) +
  1259. sizeof(struct reo_get_queue_stats_status)) >> 2,
  1260. .lmac_ring = FALSE,
  1261. .ring_dir = HAL_SRNG_DST_RING,
  1262. .reg_start = {
  1263. HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
  1264. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1265. HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
  1266. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1267. },
  1268. /* Single ring - provide ring size if multiple rings of this
  1269. * type are supported
  1270. */
  1271. .reg_size = {},
  1272. .max_size =
  1273. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1274. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1275. },
  1276. { /* TCL_DATA */
  1277. .start_ring_id = HAL_SRNG_SW2TCL1,
  1278. .max_rings = 3,
  1279. .entry_size = (sizeof(struct tlv_32_hdr) +
  1280. sizeof(struct tcl_data_cmd)) >> 2,
  1281. .lmac_ring = FALSE,
  1282. .ring_dir = HAL_SRNG_SRC_RING,
  1283. .reg_start = {
  1284. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
  1285. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1286. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
  1287. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1288. },
  1289. .reg_size = {
  1290. HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
  1291. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
  1292. HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
  1293. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
  1294. },
  1295. .max_size =
  1296. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1297. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
  1298. },
  1299. { /* TCL_CMD */
  1300. .start_ring_id = HAL_SRNG_SW2TCL_CMD,
  1301. .max_rings = 1,
  1302. .entry_size = (sizeof(struct tlv_32_hdr) +
  1303. sizeof(struct tcl_gse_cmd)) >> 2,
  1304. .lmac_ring = FALSE,
  1305. .ring_dir = HAL_SRNG_SRC_RING,
  1306. .reg_start = {
  1307. HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(
  1308. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1309. HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(
  1310. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1311. },
  1312. /* Single ring - provide ring size if multiple rings of this
  1313. * type are supported
  1314. */
  1315. .reg_size = {},
  1316. .max_size =
  1317. HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1318. HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1319. },
  1320. { /* TCL_STATUS */
  1321. .start_ring_id = HAL_SRNG_TCL_STATUS,
  1322. .max_rings = 1,
  1323. .entry_size = (sizeof(struct tlv_32_hdr) +
  1324. sizeof(struct tcl_status_ring)) >> 2,
  1325. .lmac_ring = FALSE,
  1326. .ring_dir = HAL_SRNG_DST_RING,
  1327. .reg_start = {
  1328. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
  1329. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1330. HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
  1331. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1332. },
  1333. /* Single ring - provide ring size if multiple rings of this
  1334. * type are supported
  1335. */
  1336. .reg_size = {},
  1337. .max_size =
  1338. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1339. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
  1340. },
  1341. { /* CE_SRC */
  1342. .start_ring_id = HAL_SRNG_CE_0_SRC,
  1343. .max_rings = 12,
  1344. .entry_size = sizeof(struct ce_src_desc) >> 2,
  1345. .lmac_ring = FALSE,
  1346. .ring_dir = HAL_SRNG_SRC_RING,
  1347. .reg_start = {
  1348. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1349. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1350. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1351. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1352. },
  1353. .reg_size = {
  1354. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1355. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1356. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1357. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1358. },
  1359. .max_size =
  1360. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1361. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1362. },
  1363. { /* CE_DST */
  1364. .start_ring_id = HAL_SRNG_CE_0_DST,
  1365. .max_rings = 12,
  1366. .entry_size = 8 >> 2,
  1367. /*TODO: entry_size above should actually be
  1368. * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
  1369. * of struct ce_dst_desc in HW header files
  1370. */
  1371. .lmac_ring = FALSE,
  1372. .ring_dir = HAL_SRNG_SRC_RING,
  1373. .reg_start = {
  1374. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1375. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1376. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1377. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1378. },
  1379. .reg_size = {
  1380. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1381. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1382. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1383. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1384. },
  1385. .max_size =
  1386. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1387. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1388. },
  1389. { /* CE_DST_STATUS */
  1390. .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
  1391. .max_rings = 12,
  1392. .entry_size = sizeof(struct ce_stat_desc) >> 2,
  1393. .lmac_ring = FALSE,
  1394. .ring_dir = HAL_SRNG_DST_RING,
  1395. .reg_start = {
  1396. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
  1397. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1398. HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
  1399. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1400. },
  1401. /* TODO: check destination status ring registers */
  1402. .reg_size = {
  1403. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1404. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1405. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1406. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1407. },
  1408. .max_size =
  1409. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1410. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1411. },
  1412. { /* WBM_IDLE_LINK */
  1413. .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
  1414. .max_rings = 1,
  1415. .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
  1416. .lmac_ring = FALSE,
  1417. .ring_dir = HAL_SRNG_SRC_RING,
  1418. .reg_start = {
  1419. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1420. HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1421. },
  1422. /* Single ring - provide ring size if multiple rings of this
  1423. * type are supported
  1424. */
  1425. .reg_size = {},
  1426. .max_size =
  1427. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
  1428. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
  1429. },
  1430. { /* SW2WBM_RELEASE */
  1431. .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
  1432. .max_rings = 1,
  1433. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1434. .lmac_ring = FALSE,
  1435. .ring_dir = HAL_SRNG_SRC_RING,
  1436. .reg_start = {
  1437. HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1438. HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1439. },
  1440. /* Single ring - provide ring size if multiple rings of this
  1441. * type are supported
  1442. */
  1443. .reg_size = {},
  1444. .max_size =
  1445. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1446. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1447. },
  1448. { /* WBM2SW_RELEASE */
  1449. .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
  1450. #ifdef IPA_WDI3_TX_TWO_PIPES
  1451. .max_rings = 5,
  1452. #else
  1453. .max_rings = 4,
  1454. #endif
  1455. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1456. .lmac_ring = FALSE,
  1457. .ring_dir = HAL_SRNG_DST_RING,
  1458. .reg_start = {
  1459. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1460. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1461. },
  1462. .reg_size = {
  1463. HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  1464. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1465. HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  1466. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1467. },
  1468. .max_size =
  1469. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1470. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1471. },
  1472. { /* RXDMA_BUF */
  1473. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
  1474. #ifdef IPA_OFFLOAD
  1475. .max_rings = 3,
  1476. #else
  1477. .max_rings = 2,
  1478. #endif
  1479. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1480. .lmac_ring = TRUE,
  1481. .ring_dir = HAL_SRNG_SRC_RING,
  1482. /* reg_start is not set because LMAC rings are not accessed
  1483. * from host
  1484. */
  1485. .reg_start = {},
  1486. .reg_size = {},
  1487. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1488. },
  1489. { /* RXDMA_DST */
  1490. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
  1491. .max_rings = 1,
  1492. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1493. .lmac_ring = TRUE,
  1494. .ring_dir = HAL_SRNG_DST_RING,
  1495. /* reg_start is not set because LMAC rings are not accessed
  1496. * from host
  1497. */
  1498. .reg_start = {},
  1499. .reg_size = {},
  1500. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1501. },
  1502. { /* RXDMA_MONITOR_BUF */
  1503. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  1504. .max_rings = 1,
  1505. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1506. .lmac_ring = TRUE,
  1507. .ring_dir = HAL_SRNG_SRC_RING,
  1508. /* reg_start is not set because LMAC rings are not accessed
  1509. * from host
  1510. */
  1511. .reg_start = {},
  1512. .reg_size = {},
  1513. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1514. },
  1515. { /* RXDMA_MONITOR_STATUS */
  1516. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  1517. .max_rings = 1,
  1518. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1519. .lmac_ring = TRUE,
  1520. .ring_dir = HAL_SRNG_SRC_RING,
  1521. /* reg_start is not set because LMAC rings are not accessed
  1522. * from host
  1523. */
  1524. .reg_start = {},
  1525. .reg_size = {},
  1526. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1527. },
  1528. { /* RXDMA_MONITOR_DST */
  1529. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
  1530. .max_rings = 1,
  1531. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1532. .lmac_ring = TRUE,
  1533. .ring_dir = HAL_SRNG_DST_RING,
  1534. /* reg_start is not set because LMAC rings are not accessed
  1535. * from host
  1536. */
  1537. .reg_start = {},
  1538. .reg_size = {},
  1539. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1540. },
  1541. { /* RXDMA_MONITOR_DESC */
  1542. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  1543. .max_rings = 1,
  1544. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1545. .lmac_ring = TRUE,
  1546. .ring_dir = HAL_SRNG_SRC_RING,
  1547. /* reg_start is not set because LMAC rings are not accessed
  1548. * from host
  1549. */
  1550. .reg_start = {},
  1551. .reg_size = {},
  1552. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1553. },
  1554. { /* DIR_BUF_RX_DMA_SRC */
  1555. .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  1556. /*
  1557. * one ring is for spectral scan
  1558. * the other one is for cfr
  1559. */
  1560. .max_rings = 2,
  1561. .entry_size = 2,
  1562. .lmac_ring = TRUE,
  1563. .ring_dir = HAL_SRNG_SRC_RING,
  1564. /* reg_start is not set because LMAC rings are not accessed
  1565. * from host
  1566. */
  1567. .reg_start = {},
  1568. .reg_size = {},
  1569. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1570. },
  1571. #ifdef WLAN_FEATURE_CIF_CFR
  1572. { /* WIFI_POS_SRC */
  1573. .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  1574. .max_rings = 1,
  1575. .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
  1576. .lmac_ring = TRUE,
  1577. .ring_dir = HAL_SRNG_SRC_RING,
  1578. /* reg_start is not set because LMAC rings are not accessed
  1579. * from host
  1580. */
  1581. .reg_start = {},
  1582. .reg_size = {},
  1583. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1584. },
  1585. #endif
  1586. { /* REO2PPE */ 0},
  1587. { /* PPE2TCL */ 0},
  1588. { /* PPE_RELEASE */ 0},
  1589. { /* TX_MONITOR_BUF */ 0},
  1590. { /* TX_MONITOR_DST */ 0},
  1591. { /* SW2RXDMA_NEW */ 0},
  1592. };
  1593. /**
  1594. * hal_qca6390_attach() - Attach 6390 target specific hal_soc ops,
  1595. * offset and srng table
  1596. */
  1597. void hal_qca6390_attach(struct hal_soc *hal_soc)
  1598. {
  1599. hal_soc->hw_srng_table = hw_srng_table_6390;
  1600. hal_srng_hw_reg_offset_init_generic(hal_soc);
  1601. hal_hw_txrx_default_ops_attach_li(hal_soc);
  1602. hal_hw_txrx_ops_attach_qca6390(hal_soc);
  1603. }