hal_rh_rx.h 26 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_RH_RX_H_
  20. #define _HAL_RH_RX_H_
  21. #include <hal_rx.h>
  22. /*
  23. * macro to set the cookie into the rxdma ring entry
  24. */
  25. #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \
  26. ((*(((unsigned int *)buff_addr_info) + \
  27. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
  28. ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \
  29. ((*(((unsigned int *)buff_addr_info) + \
  30. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  31. ((cookie) << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
  32. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK)
  33. /*
  34. * macro to set the manager into the rxdma ring entry
  35. */
  36. #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \
  37. ((*(((unsigned int *)buff_addr_info) + \
  38. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \
  39. ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \
  40. ((*(((unsigned int *)buff_addr_info) + \
  41. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \
  42. ((manager) << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \
  43. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK)
  44. /*
  45. * NOTE: None of the following _GET macros need a right
  46. * shift by the corresponding _LSB. This is because, they are
  47. * finally taken and "OR'ed" into a single word again.
  48. */
  49. #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \
  50. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  51. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \
  52. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK)
  53. #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  54. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  55. RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \
  56. RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK)
  57. #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  58. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  59. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \
  60. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK)
  61. #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  62. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  63. RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \
  64. RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK)
  65. #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \
  66. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  67. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \
  68. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK)
  69. #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  70. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  71. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \
  72. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK)
  73. /*
  74. * Structures & Macros to obtain fields from the TLV's in the Rx packet
  75. * pre-header.
  76. */
  77. /*
  78. * Every Rx packet starts at an offset from the top of the buffer.
  79. * If the host hasn't subscribed to any specific TLV, there is
  80. * still space reserved for the following TLV's from the start of
  81. * the buffer:
  82. * -- RX ATTENTION
  83. * -- RX MPDU START
  84. * -- RX MSDU START
  85. * -- RX MSDU END
  86. * -- RX MPDU END
  87. * -- RX PACKET HEADER (802.11)
  88. * If the host subscribes to any of the TLV's above, that TLV
  89. * if populated by the HW
  90. */
  91. #define NUM_DWORDS_TAG 1
  92. /* By default the packet header TLV is 128 bytes */
  93. #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128
  94. #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \
  95. (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2)
  96. #define RX_PKT_OFFSET_WORDS \
  97. ( \
  98. NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \
  99. NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \
  100. NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \
  101. NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \
  102. NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \
  103. NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \
  104. )
  105. #define RX_PKT_OFFSET_BYTES \
  106. (RX_PKT_OFFSET_WORDS << 2)
  107. #define RX_PKT_HDR_TLV_LEN 120
  108. /*
  109. * Each RX descriptor TLV is preceded by 1 DWORD "tag"
  110. */
  111. struct rx_attention_tlv {
  112. uint32_t tag;
  113. struct rx_attention rx_attn;
  114. };
  115. struct rx_mpdu_start_tlv {
  116. uint32_t tag;
  117. struct rx_mpdu_start rx_mpdu_start;
  118. };
  119. struct rx_msdu_start_tlv {
  120. uint32_t tag;
  121. struct rx_msdu_start rx_msdu_start;
  122. };
  123. struct rx_msdu_end_tlv {
  124. uint32_t tag;
  125. struct rx_msdu_end rx_msdu_end;
  126. };
  127. struct rx_mpdu_end_tlv {
  128. uint32_t tag;
  129. struct rx_mpdu_end rx_mpdu_end;
  130. };
  131. struct rx_pkt_hdr_tlv {
  132. uint32_t tag; /* 4 B */
  133. uint32_t phy_ppdu_id; /* 4 B */
  134. char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */
  135. };
  136. /* rx_pkt_tlvs structure should be used to process Data buffers, monitor status
  137. * buffers, monitor destination buffers and monitor descriptor buffers.
  138. */
  139. #ifdef RXDMA_OPTIMIZATION
  140. /*
  141. * The RX_PADDING_BYTES is required so that the TLV's don't
  142. * spread across the 128 byte boundary
  143. * RXDMA optimization requires:
  144. * 1) MSDU_END & ATTENTION TLV's follow in that order
  145. * 2) TLV's don't span across 128 byte lines
  146. * 3) Rx Buffer is nicely aligned on the 128 byte boundary
  147. */
  148. #define RX_PADDING0_BYTES 4
  149. #define RX_PADDING1_BYTES 16
  150. struct rx_pkt_tlvs {
  151. struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
  152. struct rx_attention_tlv attn_tlv; /* 16 bytes */
  153. struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
  154. uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
  155. struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
  156. struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
  157. uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
  158. #ifndef NO_RX_PKT_HDR_TLV
  159. struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
  160. #endif
  161. };
  162. #else /* RXDMA_OPTIMIZATION */
  163. struct rx_pkt_tlvs {
  164. struct rx_attention_tlv attn_tlv;
  165. struct rx_mpdu_start_tlv mpdu_start_tlv;
  166. struct rx_msdu_start_tlv msdu_start_tlv;
  167. struct rx_msdu_end_tlv msdu_end_tlv;
  168. struct rx_mpdu_end_tlv mpdu_end_tlv;
  169. struct rx_pkt_hdr_tlv pkt_hdr_tlv;
  170. };
  171. #endif /* RXDMA_OPTIMIZATION */
  172. /* rx_mon_pkt_tlvs structure should be used to process monitor data buffers */
  173. #ifdef RXDMA_OPTIMIZATION
  174. struct rx_mon_pkt_tlvs {
  175. struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
  176. struct rx_attention_tlv attn_tlv; /* 16 bytes */
  177. struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
  178. uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
  179. struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
  180. struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
  181. uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
  182. struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
  183. };
  184. #else /* RXDMA_OPTIMIZATION */
  185. struct rx_mon_pkt_tlvs {
  186. struct rx_attention_tlv attn_tlv;
  187. struct rx_mpdu_start_tlv mpdu_start_tlv;
  188. struct rx_msdu_start_tlv msdu_start_tlv;
  189. struct rx_msdu_end_tlv msdu_end_tlv;
  190. struct rx_mpdu_end_tlv mpdu_end_tlv;
  191. struct rx_pkt_hdr_tlv pkt_hdr_tlv;
  192. };
  193. #endif
  194. #define SIZE_OF_MONITOR_TLV sizeof(struct rx_mon_pkt_tlvs)
  195. #define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs)
  196. #define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV
  197. #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field)
  198. #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \
  199. RX_PKT_TLV_OFFSET(mpdu_start_tlv)
  200. #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv)
  201. #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \
  202. RX_PKT_TLV_OFFSET(msdu_start_tlv)
  203. #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv)
  204. #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv)
  205. #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv)
  206. /**
  207. * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf
  208. *
  209. * @rx_buf_start: Pointer to data buffer field
  210. *
  211. * Returns: pointer to rx_pkt_tlvs
  212. */
  213. static inline
  214. struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start)
  215. {
  216. return (struct rx_pkt_tlvs *)rx_buf_start;
  217. }
  218. /**
  219. * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs
  220. *
  221. * @pkt_tlvs: Pointer to pkt_tlvs
  222. * Returns: pointer to rx_mpdu_info structure
  223. */
  224. static inline
  225. struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs)
  226. {
  227. return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  228. }
  229. /**
  230. * hal_rx_mon_dest_get_buffer_info_from_tlv(): Retrieve mon dest frame info
  231. * from the reserved bytes of rx_tlv_hdr.
  232. * @buf: start of rx_tlv_hdr
  233. * @buf_info: hal_rx_mon_dest_buf_info structure
  234. *
  235. * Return: void
  236. */
  237. static inline void hal_rx_mon_dest_get_buffer_info_from_tlv(
  238. uint8_t *buf,
  239. struct hal_rx_mon_dest_buf_info *buf_info)
  240. {
  241. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  242. qdf_mem_copy(buf_info, pkt_tlvs->rx_padding0,
  243. sizeof(struct hal_rx_mon_dest_buf_info));
  244. }
  245. /*
  246. * Get msdu_done bit from the RX_ATTENTION TLV
  247. */
  248. #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \
  249. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  250. RX_ATTENTION_2_MSDU_DONE_OFFSET)), \
  251. RX_ATTENTION_2_MSDU_DONE_MASK, \
  252. RX_ATTENTION_2_MSDU_DONE_LSB))
  253. #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \
  254. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  255. RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \
  256. RX_ATTENTION_1_FIRST_MPDU_MASK, \
  257. RX_ATTENTION_1_FIRST_MPDU_LSB))
  258. #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \
  259. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  260. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \
  261. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \
  262. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB))
  263. /*
  264. * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit
  265. * from rx attention
  266. * @buf: pointer to rx_pkt_tlvs
  267. *
  268. * Return: tcp_udp_cksum_fail
  269. */
  270. static inline bool
  271. hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf)
  272. {
  273. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  274. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  275. uint8_t tcp_udp_cksum_fail;
  276. tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn);
  277. return !!tcp_udp_cksum_fail;
  278. }
  279. #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \
  280. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  281. RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \
  282. RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \
  283. RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB))
  284. /*
  285. * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit
  286. * from rx attention
  287. * @buf: pointer to rx_pkt_tlvs
  288. *
  289. * Return: ip_cksum_fail
  290. */
  291. static inline bool
  292. hal_rx_attn_ip_cksum_fail_get(uint8_t *buf)
  293. {
  294. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  295. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  296. uint8_t ip_cksum_fail;
  297. ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn);
  298. return !!ip_cksum_fail;
  299. }
  300. #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \
  301. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  302. RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \
  303. RX_ATTENTION_0_PHY_PPDU_ID_MASK, \
  304. RX_ATTENTION_0_PHY_PPDU_ID_LSB))
  305. #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \
  306. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  307. RX_ATTENTION_1_CCE_MATCH_OFFSET)), \
  308. RX_ATTENTION_1_CCE_MATCH_MASK, \
  309. RX_ATTENTION_1_CCE_MATCH_LSB))
  310. /*
  311. * hal_rx_msdu_cce_match_get_rh(): get CCE match bit
  312. * from rx attention
  313. * @buf: pointer to rx_pkt_tlvs
  314. * Return: CCE match value
  315. */
  316. static inline bool
  317. hal_rx_msdu_cce_match_get_rh(uint8_t *buf)
  318. {
  319. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  320. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  321. uint8_t cce_match_val;
  322. cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn);
  323. return !!cce_match_val;
  324. }
  325. /*
  326. * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START
  327. */
  328. #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \
  329. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  330. RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \
  331. RX_MPDU_INFO_8_PEER_META_DATA_MASK, \
  332. RX_MPDU_INFO_8_PEER_META_DATA_LSB))
  333. static inline uint32_t
  334. hal_rx_mpdu_peer_meta_data_get_rh(uint8_t *buf)
  335. {
  336. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  337. struct rx_mpdu_start *mpdu_start =
  338. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  339. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  340. uint32_t peer_meta_data;
  341. peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info);
  342. return peer_meta_data;
  343. }
  344. #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \
  345. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  346. RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \
  347. RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \
  348. RX_MPDU_INFO_12_AMPDU_FLAG_LSB))
  349. /*
  350. * LRO information needed from the TLVs
  351. */
  352. #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \
  353. (_HAL_MS( \
  354. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  355. msdu_end_tlv.rx_msdu_end), \
  356. RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \
  357. RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \
  358. RX_MSDU_END_9_LRO_ELIGIBLE_LSB))
  359. #define HAL_RX_TLV_GET_TCP_ACK(buf) \
  360. (_HAL_MS( \
  361. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  362. msdu_end_tlv.rx_msdu_end), \
  363. RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \
  364. RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \
  365. RX_MSDU_END_8_TCP_ACK_NUMBER_LSB))
  366. #define HAL_RX_TLV_GET_TCP_SEQ(buf) \
  367. (_HAL_MS( \
  368. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  369. msdu_end_tlv.rx_msdu_end), \
  370. RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \
  371. RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \
  372. RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB))
  373. #define HAL_RX_TLV_GET_TCP_WIN(buf) \
  374. (_HAL_MS( \
  375. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  376. msdu_end_tlv.rx_msdu_end), \
  377. RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \
  378. RX_MSDU_END_9_WINDOW_SIZE_MASK, \
  379. RX_MSDU_END_9_WINDOW_SIZE_LSB))
  380. #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \
  381. (_HAL_MS( \
  382. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  383. msdu_start_tlv.rx_msdu_start), \
  384. RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \
  385. RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \
  386. RX_MSDU_START_2_TCP_ONLY_ACK_LSB))
  387. #define HAL_RX_TLV_GET_TCP_PROTO(buf) \
  388. (_HAL_MS( \
  389. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  390. msdu_start_tlv.rx_msdu_start), \
  391. RX_MSDU_START_2_TCP_PROTO_OFFSET)), \
  392. RX_MSDU_START_2_TCP_PROTO_MASK, \
  393. RX_MSDU_START_2_TCP_PROTO_LSB))
  394. #define HAL_RX_TLV_GET_UDP_PROTO(buf) \
  395. (_HAL_MS( \
  396. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  397. msdu_start_tlv.rx_msdu_start), \
  398. RX_MSDU_START_2_UDP_PROTO_OFFSET)), \
  399. RX_MSDU_START_2_UDP_PROTO_MASK, \
  400. RX_MSDU_START_2_UDP_PROTO_LSB))
  401. #define HAL_RX_TLV_GET_IPV6(buf) \
  402. (_HAL_MS( \
  403. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  404. msdu_start_tlv.rx_msdu_start), \
  405. RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \
  406. RX_MSDU_START_2_IPV6_PROTO_MASK, \
  407. RX_MSDU_START_2_IPV6_PROTO_LSB))
  408. #define HAL_RX_TLV_GET_IP_OFFSET(buf) \
  409. (_HAL_MS( \
  410. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  411. msdu_start_tlv.rx_msdu_start), \
  412. RX_MSDU_START_1_L3_OFFSET_OFFSET)), \
  413. RX_MSDU_START_1_L3_OFFSET_MASK, \
  414. RX_MSDU_START_1_L3_OFFSET_LSB))
  415. #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \
  416. (_HAL_MS( \
  417. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  418. msdu_start_tlv.rx_msdu_start), \
  419. RX_MSDU_START_1_L4_OFFSET_OFFSET)), \
  420. RX_MSDU_START_1_L4_OFFSET_MASK, \
  421. RX_MSDU_START_1_L4_OFFSET_LSB))
  422. #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \
  423. (_HAL_MS( \
  424. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  425. msdu_start_tlv.rx_msdu_start), \
  426. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \
  427. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \
  428. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB))
  429. #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \
  430. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  431. RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \
  432. RX_MSDU_START_1_MSDU_LENGTH_MASK, \
  433. RX_MSDU_START_1_MSDU_LENGTH_LSB))
  434. #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \
  435. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  436. RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \
  437. RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \
  438. RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB))
  439. #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \
  440. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  441. RX_MSDU_START_5_SGI_OFFSET)), \
  442. RX_MSDU_START_5_SGI_MASK, \
  443. RX_MSDU_START_5_SGI_LSB))
  444. #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \
  445. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  446. RX_MSDU_START_5_RATE_MCS_OFFSET)), \
  447. RX_MSDU_START_5_RATE_MCS_MASK, \
  448. RX_MSDU_START_5_RATE_MCS_LSB))
  449. #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \
  450. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  451. RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \
  452. RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \
  453. RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB))
  454. /*
  455. * Get key index from RX_MSDU_END
  456. */
  457. #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \
  458. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  459. RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \
  460. RX_MSDU_END_2_KEY_ID_OCTET_MASK, \
  461. RX_MSDU_END_2_KEY_ID_OCTET_LSB))
  462. #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \
  463. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  464. RX_MSDU_START_5_USER_RSSI_OFFSET)), \
  465. RX_MSDU_START_5_USER_RSSI_MASK, \
  466. RX_MSDU_START_5_USER_RSSI_LSB))
  467. #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \
  468. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  469. RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \
  470. RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \
  471. RX_MSDU_START_7_SW_PHY_META_DATA_LSB))
  472. #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \
  473. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  474. RX_MSDU_START_5_PKT_TYPE_OFFSET)), \
  475. RX_MSDU_START_5_PKT_TYPE_MASK, \
  476. RX_MSDU_START_5_PKT_TYPE_LSB))
  477. #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
  478. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  479. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
  480. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
  481. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
  482. #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
  483. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  484. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
  485. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
  486. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
  487. /*******************************************************************************
  488. * RX ERROR APIS
  489. ******************************************************************************/
  490. #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \
  491. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  492. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \
  493. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \
  494. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB))
  495. #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \
  496. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  497. RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \
  498. RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \
  499. RX_MPDU_END_1_TKIP_MIC_ERR_LSB))
  500. /**
  501. * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured
  502. * humman readable format.
  503. * @rx_attn: pointer the rx_attention TLV in pkt.
  504. * @dbg_level: log level.
  505. *
  506. * Return: void
  507. */
  508. static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn,
  509. uint8_t dbg_level)
  510. {
  511. hal_verbose_debug("rx_attention tlv (1/2) - "
  512. "rxpcu_mpdu_filter_in_category: %x "
  513. "sw_frame_group_id: %x "
  514. "reserved_0: %x "
  515. "phy_ppdu_id: %x "
  516. "first_mpdu : %x "
  517. "reserved_1a: %x "
  518. "mcast_bcast: %x "
  519. "ast_index_not_found: %x "
  520. "ast_index_timeout: %x "
  521. "power_mgmt: %x "
  522. "non_qos: %x "
  523. "null_data: %x "
  524. "mgmt_type: %x "
  525. "ctrl_type: %x "
  526. "more_data: %x "
  527. "eosp: %x "
  528. "a_msdu_error: %x "
  529. "fragment_flag: %x "
  530. "order: %x "
  531. "cce_match: %x "
  532. "overflow_err: %x "
  533. "msdu_length_err: %x "
  534. "tcp_udp_chksum_fail: %x "
  535. "ip_chksum_fail: %x "
  536. "sa_idx_invalid: %x "
  537. "da_idx_invalid: %x "
  538. "reserved_1b: %x "
  539. "rx_in_tx_decrypt_byp: %x ",
  540. rx_attn->rxpcu_mpdu_filter_in_category,
  541. rx_attn->sw_frame_group_id,
  542. rx_attn->reserved_0,
  543. rx_attn->phy_ppdu_id,
  544. rx_attn->first_mpdu,
  545. rx_attn->reserved_1a,
  546. rx_attn->mcast_bcast,
  547. rx_attn->ast_index_not_found,
  548. rx_attn->ast_index_timeout,
  549. rx_attn->power_mgmt,
  550. rx_attn->non_qos,
  551. rx_attn->null_data,
  552. rx_attn->mgmt_type,
  553. rx_attn->ctrl_type,
  554. rx_attn->more_data,
  555. rx_attn->eosp,
  556. rx_attn->a_msdu_error,
  557. rx_attn->fragment_flag,
  558. rx_attn->order,
  559. rx_attn->cce_match,
  560. rx_attn->overflow_err,
  561. rx_attn->msdu_length_err,
  562. rx_attn->tcp_udp_chksum_fail,
  563. rx_attn->ip_chksum_fail,
  564. rx_attn->sa_idx_invalid,
  565. rx_attn->da_idx_invalid,
  566. rx_attn->reserved_1b,
  567. rx_attn->rx_in_tx_decrypt_byp);
  568. hal_verbose_debug("rx_attention tlv (2/2) - "
  569. "encrypt_required: %x "
  570. "directed: %x "
  571. "buffer_fragment: %x "
  572. "mpdu_length_err: %x "
  573. "tkip_mic_err: %x "
  574. "decrypt_err: %x "
  575. "unencrypted_frame_err: %x "
  576. "fcs_err: %x "
  577. "flow_idx_timeout: %x "
  578. "flow_idx_invalid: %x "
  579. "wifi_parser_error: %x "
  580. "amsdu_parser_error: %x "
  581. "sa_idx_timeout: %x "
  582. "da_idx_timeout: %x "
  583. "msdu_limit_error: %x "
  584. "da_is_valid: %x "
  585. "da_is_mcbc: %x "
  586. "sa_is_valid: %x "
  587. "decrypt_status_code: %x "
  588. "rx_bitmap_not_updated: %x "
  589. "reserved_2: %x "
  590. "msdu_done: %x ",
  591. rx_attn->encrypt_required,
  592. rx_attn->directed,
  593. rx_attn->buffer_fragment,
  594. rx_attn->mpdu_length_err,
  595. rx_attn->tkip_mic_err,
  596. rx_attn->decrypt_err,
  597. rx_attn->unencrypted_frame_err,
  598. rx_attn->fcs_err,
  599. rx_attn->flow_idx_timeout,
  600. rx_attn->flow_idx_invalid,
  601. rx_attn->wifi_parser_error,
  602. rx_attn->amsdu_parser_error,
  603. rx_attn->sa_idx_timeout,
  604. rx_attn->da_idx_timeout,
  605. rx_attn->msdu_limit_error,
  606. rx_attn->da_is_valid,
  607. rx_attn->da_is_mcbc,
  608. rx_attn->sa_is_valid,
  609. rx_attn->decrypt_status_code,
  610. rx_attn->rx_bitmap_not_updated,
  611. rx_attn->reserved_2,
  612. rx_attn->msdu_done);
  613. }
  614. /**
  615. * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured
  616. * human readable format.
  617. * @mpdu_end: pointer the mpdu_end TLV in pkt.
  618. * @dbg_level: log level.
  619. *
  620. * Return: void
  621. */
  622. static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end,
  623. uint8_t dbg_level)
  624. {
  625. hal_verbose_debug("rx_mpdu_end tlv - "
  626. "rxpcu_mpdu_filter_in_category: %x "
  627. "sw_frame_group_id: %x "
  628. "phy_ppdu_id: %x "
  629. "unsup_ktype_short_frame: %x "
  630. "rx_in_tx_decrypt_byp: %x "
  631. "overflow_err: %x "
  632. "mpdu_length_err: %x "
  633. "tkip_mic_err: %x "
  634. "decrypt_err: %x "
  635. "unencrypted_frame_err: %x "
  636. "pn_fields_contain_valid_info: %x "
  637. "fcs_err: %x "
  638. "msdu_length_err: %x "
  639. "rxdma0_destination_ring: %x "
  640. "rxdma1_destination_ring: %x "
  641. "decrypt_status_code: %x "
  642. "rx_bitmap_not_updated: %x ",
  643. mpdu_end->rxpcu_mpdu_filter_in_category,
  644. mpdu_end->sw_frame_group_id,
  645. mpdu_end->phy_ppdu_id,
  646. mpdu_end->unsup_ktype_short_frame,
  647. mpdu_end->rx_in_tx_decrypt_byp,
  648. mpdu_end->overflow_err,
  649. mpdu_end->mpdu_length_err,
  650. mpdu_end->tkip_mic_err,
  651. mpdu_end->decrypt_err,
  652. mpdu_end->unencrypted_frame_err,
  653. mpdu_end->pn_fields_contain_valid_info,
  654. mpdu_end->fcs_err,
  655. mpdu_end->msdu_length_err,
  656. mpdu_end->rxdma0_destination_ring,
  657. mpdu_end->rxdma1_destination_ring,
  658. mpdu_end->decrypt_status_code,
  659. mpdu_end->rx_bitmap_not_updated);
  660. }
  661. #ifdef NO_RX_PKT_HDR_TLV
  662. static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs,
  663. uint8_t dbg_level)
  664. {
  665. }
  666. #else
  667. /**
  668. * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format
  669. * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt.
  670. * @dbg_level: log level.
  671. *
  672. * Return: void
  673. */
  674. static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs,
  675. uint8_t dbg_level)
  676. {
  677. struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
  678. hal_verbose_debug("\n---------------\nrx_pkt_hdr_tlv"
  679. "\n---------------\nphy_ppdu_id %d ",
  680. pkt_hdr_tlv->phy_ppdu_id);
  681. hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128);
  682. }
  683. #endif
  684. #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \
  685. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  686. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \
  687. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \
  688. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB))
  689. /**
  690. * hal_rx_attn_msdu_done_get_rh() - Get msdi done flag from RX TLV
  691. * @buf: RX tlv address
  692. *
  693. * Return: msdu done flag
  694. */
  695. static inline uint32_t hal_rx_attn_msdu_done_get_rh(uint8_t *buf)
  696. {
  697. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  698. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  699. uint32_t msdu_done;
  700. msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn);
  701. return msdu_done;
  702. }
  703. #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \
  704. (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  705. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  706. HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \
  707. HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  708. HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \
  709. HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  710. HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \
  711. HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr))
  712. /**
  713. * hal_rx_msdu_flags_get_rh() - Get msdu flags from ring desc
  714. * @msdu_desc_info_hdl: msdu desc info handle
  715. *
  716. * Return: msdu flags
  717. */
  718. static inline
  719. uint32_t hal_rx_msdu_flags_get_rh(rx_msdu_desc_info_t msdu_desc_info_hdl)
  720. {
  721. struct rx_msdu_desc_info *msdu_desc_info =
  722. (struct rx_msdu_desc_info *)msdu_desc_info_hdl;
  723. return HAL_RX_MSDU_FLAGS_GET(msdu_desc_info);
  724. }
  725. #define HAL_RX_ATTN_MSDU_LEN_ERR_GET(_rx_attn) \
  726. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  727. RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET)), \
  728. RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK, \
  729. RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB))
  730. /**
  731. * hal_rx_attn_msdu_len_err_get_rh(): Get msdu_len_err value from
  732. * rx attention tlvs
  733. * @buf: pointer to rx pkt tlvs hdr
  734. *
  735. * Return: msdu_len_err value
  736. */
  737. static inline uint32_t
  738. hal_rx_attn_msdu_len_err_get_rh(uint8_t *buf)
  739. {
  740. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  741. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  742. return HAL_RX_ATTN_MSDU_LEN_ERR_GET(rx_attn);
  743. }
  744. #endif /* _HAL_RH_RX_H_ */