hal_wbm.c 4.0 KB

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  1. /*
  2. * Copyright (c) 2016 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "hal_api.h"
  19. /**
  20. * hal_setup_link_idle_list - Setup scattered idle list using the
  21. * buffer list provided
  22. *
  23. * @hal_soc: Opaque HAL SOC handle
  24. * @scatter_bufs_base_paddr: Array of physical base addresses
  25. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  26. * @num_scatter_bufs: Number of scatter buffers in the above lists
  27. * @scatter_buf_size: Size of each scatter buffer
  28. *
  29. */
  30. void hal_setup_link_idle_list(void *hal_soc,
  31. qdf_dma_addr_t scatter_bufs_base_paddr[],
  32. void *scatter_bufs_base_vaddr[], uint32_t num_scatter_bufs,
  33. uint32_t scatter_buf_size, uint32_t last_buf_end_offset)
  34. {
  35. int i;
  36. uint32_t *prev_buf_link_ptr = NULL;
  37. struct hal_soc *soc = (struct hal_soc *)hal_soc;
  38. /* Link the scatter buffers */
  39. for (i = 0; i < num_scatter_bufs; i++) {
  40. if (i > 0) {
  41. prev_buf_link_ptr[0] =
  42. scatter_bufs_base_paddr[i] & 0xffffffff;
  43. prev_buf_link_ptr[1] =
  44. ((uint64_t)(scatter_bufs_base_paddr[i]) >> 32) &
  45. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK;
  46. }
  47. prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
  48. scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
  49. }
  50. /* TBD: Setup IDLE_LIST_CTRL and IDLE_LIST_SIZE registers - current
  51. * definitions in HW headers doesn't match those in WBM MLD document
  52. * pending confirmation from HW team
  53. */
  54. HAL_REG_WRITE(soc,
  55. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(
  56. SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  57. scatter_bufs_base_paddr[0] & 0xffffffff);
  58. HAL_REG_WRITE(soc,
  59. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  60. SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  61. ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
  62. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
  63. /* ADDRESS_MATCH_TAG field in the above register is expected to match
  64. * with the upper bits of link pointer. The above write sets this field
  65. * to zero and we are also setting the upper bits of link pointers to
  66. * zero while setting up the link list of scatter buffers above
  67. */
  68. /* Setup head and tail pointers for the idle list */
  69. HAL_REG_WRITE(soc,
  70. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  71. SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  72. scatter_bufs_base_paddr[0] & 0xffffffff);
  73. HAL_REG_WRITE(soc,
  74. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(
  75. SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  76. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  77. BUFFER_ADDRESS_39_32,
  78. ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) |
  79. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  80. HEAD_POINTER_OFFSET, 0));
  81. HAL_REG_WRITE(soc,
  82. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  83. SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  84. scatter_bufs_base_paddr[0] & 0xffffffff);
  85. HAL_REG_WRITE(soc,
  86. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(
  87. SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  88. scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff);
  89. HAL_REG_WRITE(soc,
  90. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(
  91. SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  92. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  93. BUFFER_ADDRESS_39_32,
  94. ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1]) >>
  95. 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  96. TAIL_POINTER_OFFSET, last_buf_end_offset << 2));
  97. }