sde_plane.c 148 KB

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  1. /*
  2. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <linux/debugfs.h>
  21. #include <linux/dma-buf.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/msm_drm_pp.h>
  24. #include <linux/version.h>
  25. #include <drm/drm_blend.h>
  26. #include "msm_prop.h"
  27. #include "msm_drv.h"
  28. #include "sde_kms.h"
  29. #include "sde_fence.h"
  30. #include "sde_formats.h"
  31. #include "sde_hw_sspp.h"
  32. #include "sde_hw_catalog_format.h"
  33. #include "sde_trace.h"
  34. #include "sde_crtc.h"
  35. #include "sde_vbif.h"
  36. #include "sde_plane.h"
  37. #include "sde_color_processing.h"
  38. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  39. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  40. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  41. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  42. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  43. #define PHASE_STEP_SHIFT 21
  44. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  45. #define PHASE_RESIDUAL 15
  46. #define SHARP_STRENGTH_DEFAULT 32
  47. #define SHARP_EDGE_THR_DEFAULT 112
  48. #define SHARP_SMOOTH_THR_DEFAULT 8
  49. #define SHARP_NOISE_THR_DEFAULT 2
  50. #define SDE_NAME_SIZE 12
  51. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  52. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  53. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  54. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  55. /**
  56. * enum sde_plane_qos - Different qos configurations for each pipe
  57. *
  58. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  59. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  60. * this configuration is mutually exclusive from VBLANK_CTRL.
  61. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  62. */
  63. enum sde_plane_qos {
  64. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  65. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  66. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  67. };
  68. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  69. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  70. {
  71. struct msm_drm_private *priv;
  72. if (!plane || !plane->dev)
  73. return NULL;
  74. priv = plane->dev->dev_private;
  75. if (!priv)
  76. return NULL;
  77. return to_sde_kms(priv->kms);
  78. }
  79. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  80. {
  81. struct drm_plane_state *pstate = NULL;
  82. struct drm_crtc *drm_crtc = NULL;
  83. struct sde_crtc *sde_crtc = NULL;
  84. struct sde_crtc_mixer *mixer = NULL;
  85. struct sde_hw_ctl *ctl = NULL;
  86. if (!plane) {
  87. DRM_ERROR("Invalid plane %pK\n", plane);
  88. return NULL;
  89. }
  90. pstate = plane->state;
  91. if (!pstate) {
  92. DRM_ERROR("Invalid plane state %pK\n", pstate);
  93. return NULL;
  94. }
  95. drm_crtc = pstate->crtc;
  96. if (!drm_crtc) {
  97. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  98. return NULL;
  99. }
  100. sde_crtc = to_sde_crtc(drm_crtc);
  101. if (!sde_crtc) {
  102. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  103. return NULL;
  104. }
  105. /* it will always return the first mixer and single CTL */
  106. mixer = sde_crtc->mixers;
  107. if (!mixer) {
  108. DRM_ERROR("invalid mixer %pK\n", mixer);
  109. return NULL;
  110. }
  111. ctl = mixer->hw_ctl;
  112. if (!mixer) {
  113. DRM_ERROR("invalid ctl %pK\n", ctl);
  114. return NULL;
  115. }
  116. return ctl;
  117. }
  118. static void _sde_plane_setup_panel_stacking(struct sde_plane *psde,
  119. struct sde_plane_state *pstate)
  120. {
  121. struct sde_hw_pipe_line_insertion_cfg *cfg;
  122. struct sde_crtc_state *cstate;
  123. u32 h_start = 0, h_total = 0, y_start = 0;
  124. struct drm_plane_state *dpstate = NULL;
  125. struct drm_crtc *drm_crtc = NULL;
  126. if (!psde || !psde->base.state || !psde->base.state->crtc) {
  127. SDE_ERROR("Invalid plane psde %p or drm plane state or drm crtc\n", psde);
  128. return;
  129. }
  130. dpstate = psde->base.state;
  131. drm_crtc = dpstate->crtc;
  132. cstate = to_sde_crtc_state(drm_crtc->state);
  133. pstate->lineinsertion_feature = cstate->line_insertion.panel_line_insertion_enable;
  134. if ((!test_bit(SDE_SSPP_LINE_INSERTION, (unsigned long *)&psde->features)) ||
  135. !cstate->line_insertion.panel_line_insertion_enable)
  136. return;
  137. cfg = &pstate->line_insertion_cfg;
  138. memset(cfg, 0, sizeof(*cfg));
  139. if (!cstate->line_insertion.padding_height)
  140. return;
  141. sde_crtc_calc_vpadding_param(psde->base.state->crtc->state,
  142. pstate->base.crtc_y, pstate->base.crtc_h,
  143. &y_start, &h_start, &h_total);
  144. cfg->enable = true;
  145. cfg->dummy_lines = cstate->line_insertion.padding_dummy;
  146. cfg->active_lines = cstate->line_insertion.padding_active;
  147. cfg->first_active_lines = h_start;
  148. cfg->dst_h = h_total;
  149. psde->pipe_cfg.dst_rect.y += y_start - pstate->base.crtc_y;
  150. }
  151. static bool sde_plane_enabled(const struct drm_plane_state *state)
  152. {
  153. return state && state->fb && state->crtc;
  154. }
  155. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  156. {
  157. struct sde_plane *psde;
  158. if (!plane)
  159. return false;
  160. psde = to_sde_plane(plane);
  161. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  162. }
  163. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  164. enum sde_sspp_multirect_index rect_mode, bool enable)
  165. {
  166. struct sde_plane *psde;
  167. if (!plane)
  168. return;
  169. psde = to_sde_plane(plane);
  170. if (psde->pipe_hw->ops.set_src_split_order)
  171. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  172. rect_mode, enable);
  173. }
  174. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  175. {
  176. struct sde_plane *psde;
  177. struct sde_kms *sde_kms;
  178. struct msm_drm_private *priv;
  179. if (!plane || !plane->dev) {
  180. SDE_ERROR("invalid plane\n");
  181. return;
  182. }
  183. priv = plane->dev->dev_private;
  184. if (!priv || !priv->kms) {
  185. SDE_ERROR("invalid KMS reference\n");
  186. return;
  187. }
  188. sde_kms = to_sde_kms(priv->kms);
  189. psde = to_sde_plane(plane);
  190. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm, sde_kms->catalog);
  191. }
  192. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  193. struct drm_crtc *crtc,
  194. struct drm_framebuffer *fb)
  195. {
  196. struct sde_plane *psde;
  197. const struct sde_format *fmt = NULL;
  198. u32 frame_rate, qos_count, fps_index = 0, lut_index, creq_lut_index, ds_lut_index;
  199. struct sde_perf_cfg *perf;
  200. struct sde_plane_state *pstate;
  201. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  202. bool inline_rot = false, landscape = false;
  203. struct drm_display_mode *mode;
  204. u32 fl_require0 = 0;
  205. if (!plane || !fb) {
  206. SDE_ERROR("invalid arguments\n");
  207. return;
  208. }
  209. psde = to_sde_plane(plane);
  210. pstate = to_sde_plane_state(plane->state);
  211. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  212. SDE_ERROR("invalid arguments\n");
  213. return;
  214. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  215. return;
  216. }
  217. mode = &crtc->state->adjusted_mode;
  218. landscape = mode->hdisplay > mode->vdisplay ? true : false;
  219. frame_rate = drm_mode_vrefresh(&crtc->mode);
  220. perf = &psde->catalog->perf;
  221. qos_count = perf->qos_refresh_count;
  222. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  223. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  224. (fps_index == qos_count - 1))
  225. break;
  226. fps_index++;
  227. }
  228. if (psde->is_rt_pipe) {
  229. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  230. inline_rot = (pstate->rotation & DRM_MODE_ROTATE_90);
  231. if (inline_rot && SDE_IS_IN_ROT_RESTRICTED_FMT(psde->catalog, fmt))
  232. lut_index = SDE_QOS_LUT_USAGE_INLINE_RESTRICTED_FMTS;
  233. else if (inline_rot)
  234. lut_index = SDE_QOS_LUT_USAGE_INLINE;
  235. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  236. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  237. else
  238. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  239. } else {
  240. lut_index = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB ||
  241. psde->wb_usage_type == WB_USAGE_ROT) ?
  242. SDE_QOS_LUT_USAGE_OFFLINE_WB : SDE_QOS_LUT_USAGE_NRT;
  243. }
  244. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  245. if (psde->scaler3_cfg.enable)
  246. creq_lut_index += SDE_CREQ_LUT_TYPE_QSEED;
  247. creq_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_CREQ_LUT_TYPE_MAX);
  248. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[creq_lut_index];
  249. ds_lut_index = lut_index * SDE_DANGER_SAFE_LUT_TYPE_MAX;
  250. if (landscape) {
  251. if (psde->catalog->qos_target_time_ns && sde_crtc->line_time_in_ns)
  252. fl_require0 = psde->catalog->qos_target_time_ns /
  253. (sde_crtc->line_time_in_ns * 2);
  254. if (!fl_require0 || fl_require0 < 4.5)
  255. ds_lut_index += SDE_DANGER_SAFE_LUT_TYPE_LANDSCAPE;
  256. }
  257. ds_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_DANGER_SAFE_LUT_TYPE_MAX);
  258. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[ds_lut_index];
  259. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[ds_lut_index];
  260. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0,
  261. (fmt) ? fmt->fetch_mode : 0, psde->pipe_qos_cfg.danger_lut,
  262. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut);
  263. SDE_DEBUG("plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d lut[0x%x,0x%x 0x%llx] rt:%d type:%d\n",
  264. plane->base.id, psde->pipe - SSPP_VIG0,
  265. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  266. fmt ? fmt->fetch_mode : -1, psde->pipe_qos_cfg.danger_lut,
  267. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut,
  268. psde->is_rt_pipe, psde->wb_usage_type);
  269. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  270. }
  271. /**
  272. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  273. * @plane: Pointer to drm plane
  274. * @enable: true to enable QoS control
  275. * @flags: QoS control mode (enum sde_plane_qos)
  276. */
  277. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  278. bool enable, u32 flags)
  279. {
  280. struct sde_plane *psde;
  281. if (!plane) {
  282. SDE_ERROR("invalid arguments\n");
  283. return;
  284. }
  285. psde = to_sde_plane(plane);
  286. if (!psde->pipe_hw || !psde->pipe_sblk) {
  287. SDE_ERROR("invalid arguments\n");
  288. return;
  289. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  290. return;
  291. }
  292. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  293. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  294. psde->pipe_qos_cfg.danger_vblank =
  295. psde->pipe_sblk->danger_vblank;
  296. psde->pipe_qos_cfg.vblank_en = enable;
  297. }
  298. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  299. /* this feature overrules previous VBLANK_CTRL */
  300. psde->pipe_qos_cfg.vblank_en = false;
  301. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  302. psde->pipe_qos_cfg.danger_vblank = 0;
  303. }
  304. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  305. psde->pipe_qos_cfg.danger_safe_en = enable;
  306. if (!psde->is_rt_pipe) {
  307. psde->pipe_qos_cfg.vblank_en = false;
  308. psde->pipe_qos_cfg.danger_safe_en = false;
  309. }
  310. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  311. plane->base.id,
  312. psde->pipe - SSPP_VIG0,
  313. psde->pipe_qos_cfg.danger_safe_en,
  314. psde->pipe_qos_cfg.vblank_en,
  315. psde->pipe_qos_cfg.creq_vblank,
  316. psde->pipe_qos_cfg.danger_vblank,
  317. psde->is_rt_pipe);
  318. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  319. &psde->pipe_qos_cfg);
  320. }
  321. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  322. {
  323. struct sde_plane *psde;
  324. if (!plane)
  325. return;
  326. psde = to_sde_plane(plane);
  327. psde->revalidate = enable;
  328. }
  329. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  330. {
  331. struct sde_plane *psde;
  332. int rc;
  333. if (!plane) {
  334. SDE_ERROR("invalid arguments\n");
  335. return -EINVAL;
  336. }
  337. psde = to_sde_plane(plane);
  338. if (!psde->is_rt_pipe)
  339. goto end;
  340. rc = pm_runtime_resume_and_get(plane->dev->dev);
  341. if (rc < 0) {
  342. SDE_ERROR("failed to enable power resource %d\n", rc);
  343. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  344. return rc;
  345. }
  346. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  347. pm_runtime_put_sync(plane->dev->dev);
  348. end:
  349. return 0;
  350. }
  351. /**
  352. * _sde_plane_set_ot_limit - set OT limit for the given plane
  353. * @plane: Pointer to drm plane
  354. * @crtc: Pointer to drm crtc
  355. */
  356. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  357. struct drm_crtc *crtc)
  358. {
  359. struct sde_plane *psde;
  360. struct sde_vbif_set_ot_params ot_params;
  361. struct msm_drm_private *priv;
  362. struct sde_kms *sde_kms;
  363. if (!plane || !plane->dev || !crtc) {
  364. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  365. !plane, !crtc);
  366. return;
  367. }
  368. priv = plane->dev->dev_private;
  369. if (!priv || !priv->kms) {
  370. SDE_ERROR("invalid KMS reference\n");
  371. return;
  372. }
  373. sde_kms = to_sde_kms(priv->kms);
  374. psde = to_sde_plane(plane);
  375. if (!psde->pipe_hw) {
  376. SDE_ERROR("invalid pipe reference\n");
  377. return;
  378. }
  379. memset(&ot_params, 0, sizeof(ot_params));
  380. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  381. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  382. ot_params.width = psde->pipe_cfg.src_rect.w;
  383. ot_params.height = psde->pipe_cfg.src_rect.h;
  384. ot_params.is_wfd = ((psde->is_rt_pipe)
  385. || (psde->wb_usage_type == WB_USAGE_OFFLINE_WB)) ? false : true;
  386. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  387. ot_params.vbif_idx = VBIF_RT;
  388. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  389. ot_params.rd = true;
  390. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  391. }
  392. /**
  393. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  394. * @plane: Pointer to drm plane
  395. */
  396. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  397. {
  398. struct sde_plane *psde;
  399. struct sde_vbif_set_qos_params qos_params;
  400. struct msm_drm_private *priv;
  401. struct sde_kms *sde_kms;
  402. if (!plane || !plane->dev) {
  403. SDE_ERROR("invalid arguments\n");
  404. return;
  405. }
  406. priv = plane->dev->dev_private;
  407. if (!priv || !priv->kms) {
  408. SDE_ERROR("invalid KMS reference\n");
  409. return;
  410. }
  411. sde_kms = to_sde_kms(priv->kms);
  412. psde = to_sde_plane(plane);
  413. if (!psde->pipe_hw) {
  414. SDE_ERROR("invalid pipe reference\n");
  415. return;
  416. }
  417. memset(&qos_params, 0, sizeof(qos_params));
  418. qos_params.vbif_idx = VBIF_RT;
  419. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  420. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  421. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  422. if (psde->is_rt_pipe)
  423. qos_params.client_type = VBIF_RT_CLIENT;
  424. else
  425. qos_params.client_type = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  426. VBIF_OFFLINE_WB_CLIENT : VBIF_NRT_CLIENT;
  427. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  428. plane->base.id, qos_params.num,
  429. qos_params.vbif_idx,
  430. qos_params.xin_id, qos_params.client_type,
  431. qos_params.clk_ctrl);
  432. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  433. }
  434. /**
  435. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  436. * @plane: Pointer to drm plane
  437. * @pstate: Pointer to sde plane state
  438. */
  439. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  440. struct sde_plane_state *pstate)
  441. {
  442. struct sde_plane *psde;
  443. struct sde_hw_pipe_ts_cfg cfg;
  444. struct msm_drm_private *priv;
  445. struct sde_kms *sde_kms;
  446. if (!plane || !plane->dev) {
  447. SDE_ERROR("invalid arguments");
  448. return;
  449. }
  450. priv = plane->dev->dev_private;
  451. if (!priv || !priv->kms) {
  452. SDE_ERROR("invalid KMS reference\n");
  453. return;
  454. }
  455. sde_kms = to_sde_kms(priv->kms);
  456. psde = to_sde_plane(plane);
  457. if (!psde->pipe_hw) {
  458. SDE_ERROR("invalid pipe reference\n");
  459. return;
  460. }
  461. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  462. return;
  463. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  464. memset(&cfg, 0, sizeof(cfg));
  465. cfg.size = sde_plane_get_property(pstate,
  466. PLANE_PROP_PREFILL_SIZE);
  467. cfg.time = sde_plane_get_property(pstate,
  468. PLANE_PROP_PREFILL_TIME);
  469. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  470. plane->base.id, cfg.size, cfg.time);
  471. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  472. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  473. pstate->multirect_index);
  474. }
  475. /* helper to update a state's input fence pointer from the property */
  476. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  477. struct sde_plane_state *pstate, uint64_t fd)
  478. {
  479. if (!psde || !pstate) {
  480. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  481. !psde, !pstate);
  482. return;
  483. }
  484. /* clear previous reference */
  485. if (pstate->input_fence)
  486. sde_sync_put(pstate->input_fence);
  487. /* get fence pointer for later */
  488. if (fd == 0)
  489. pstate->input_fence = NULL;
  490. else
  491. pstate->input_fence = sde_sync_get(fd);
  492. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  493. }
  494. void sde_plane_dump_input_fence(struct drm_plane *plane)
  495. {
  496. struct sde_plane *psde;
  497. struct sde_plane_state *pstate;
  498. void *input_fence;
  499. if (!plane) {
  500. SDE_ERROR("invalid plane\n");
  501. } else if (!plane->state) {
  502. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  503. } else {
  504. psde = to_sde_plane(plane);
  505. pstate = to_sde_plane_state(plane->state);
  506. input_fence = pstate->input_fence;
  507. if (input_fence)
  508. sde_fence_dump(input_fence);
  509. }
  510. }
  511. bool sde_plane_is_sw_fence_signaled(struct drm_plane *plane)
  512. {
  513. struct sde_plane *psde;
  514. struct sde_plane_state *pstate;
  515. struct dma_fence *fence;
  516. if (!plane) {
  517. SDE_ERROR("invalid plane\n");
  518. } else if (!plane->state) {
  519. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  520. } else {
  521. psde = to_sde_plane(plane);
  522. pstate = to_sde_plane_state(plane->state);
  523. if (pstate->input_fence) {
  524. fence = (struct dma_fence *)pstate->input_fence;
  525. return dma_fence_is_signaled(fence);
  526. }
  527. }
  528. return false;
  529. }
  530. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  531. {
  532. struct sde_plane *psde;
  533. struct sde_plane_state *pstate;
  534. uint32_t prefix;
  535. void *input_fence;
  536. int ret = -EINVAL;
  537. signed long rc;
  538. if (!plane) {
  539. SDE_ERROR("invalid plane\n");
  540. } else if (!plane->state) {
  541. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  542. } else {
  543. psde = to_sde_plane(plane);
  544. pstate = to_sde_plane_state(plane->state);
  545. input_fence = pstate->input_fence;
  546. if (input_fence) {
  547. prefix = sde_sync_get_name_prefix(input_fence);
  548. rc = sde_sync_wait(input_fence, wait_ms);
  549. switch (rc) {
  550. case 0:
  551. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
  552. wait_ms, prefix, sde_plane_get_property(pstate,
  553. PLANE_PROP_INPUT_FENCE));
  554. psde->is_error = true;
  555. sde_kms_timeline_status(plane->dev);
  556. ret = -ETIMEDOUT;
  557. break;
  558. case -ERESTARTSYS:
  559. SDE_ERROR_PLANE(psde,
  560. "%ums wait interrupted on %08X\n",
  561. wait_ms, prefix);
  562. psde->is_error = true;
  563. ret = -ERESTARTSYS;
  564. break;
  565. case -EINVAL:
  566. SDE_ERROR_PLANE(psde,
  567. "invalid fence param for %08X\n",
  568. prefix);
  569. psde->is_error = true;
  570. ret = -EINVAL;
  571. break;
  572. case -EBADF:
  573. SDE_INFO("plane%d spec fd signaled on bind failure fd %lld\n",
  574. plane->base.id,
  575. sde_plane_get_property(pstate, PLANE_PROP_INPUT_FENCE));
  576. psde->is_error = true;
  577. ret = 0;
  578. break;
  579. default:
  580. SDE_DEBUG_PLANE(psde, "signaled\n");
  581. ret = 0;
  582. break;
  583. }
  584. if (ret)
  585. SDE_EVT32(DRMID(plane), -ret, prefix, SDE_EVTLOG_ERROR);
  586. else
  587. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  588. } else {
  589. ret = 0;
  590. }
  591. }
  592. return ret;
  593. }
  594. /**
  595. * _sde_plane_get_aspace: gets the address space based on the
  596. * fb_translation mode property
  597. */
  598. static int _sde_plane_get_aspace(
  599. struct sde_plane *psde,
  600. struct sde_plane_state *pstate,
  601. struct msm_gem_address_space **aspace)
  602. {
  603. struct sde_kms *kms;
  604. int mode;
  605. if (!psde || !pstate || !aspace) {
  606. SDE_ERROR("invalid parameters\n");
  607. return -EINVAL;
  608. }
  609. kms = _sde_plane_get_kms(&psde->base);
  610. if (!kms) {
  611. SDE_ERROR("invalid kms\n");
  612. return -EINVAL;
  613. }
  614. mode = sde_plane_get_property(pstate,
  615. PLANE_PROP_FB_TRANSLATION_MODE);
  616. switch (mode) {
  617. case SDE_DRM_FB_NON_SEC:
  618. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  619. if (!aspace)
  620. return -EINVAL;
  621. break;
  622. case SDE_DRM_FB_SEC:
  623. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  624. if (!aspace)
  625. return -EINVAL;
  626. break;
  627. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  628. case SDE_DRM_FB_SEC_DIR_TRANS:
  629. *aspace = NULL;
  630. break;
  631. default:
  632. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  633. return -EFAULT;
  634. }
  635. return 0;
  636. }
  637. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  638. struct sde_plane_state *pstate,
  639. struct sde_hw_pipe_cfg *pipe_cfg,
  640. struct drm_framebuffer *fb)
  641. {
  642. struct sde_plane *psde;
  643. struct msm_gem_address_space *aspace = NULL;
  644. int ret, mode;
  645. bool secure = false;
  646. if (!plane || !pstate || !pipe_cfg || !fb) {
  647. SDE_ERROR(
  648. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  649. !plane, !pstate, !pipe_cfg, !fb);
  650. return;
  651. }
  652. psde = to_sde_plane(plane);
  653. if (!psde->pipe_hw) {
  654. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  655. return;
  656. }
  657. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  658. if (ret) {
  659. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  660. return;
  661. }
  662. /*
  663. * framebuffer prepare is deferred for prepare_fb calls that
  664. * happen during the transition from secure to non-secure.
  665. * Handle the prepare at this point for such cases. This can be
  666. * expected for one or two frames during the transition.
  667. */
  668. if (aspace && pstate->defer_prepare_fb) {
  669. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  670. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  671. if (ret) {
  672. SDE_ERROR_PLANE(psde,
  673. "failed to prepare framebuffer %d\n", ret);
  674. return;
  675. }
  676. pstate->defer_prepare_fb = false;
  677. }
  678. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  679. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  680. secure = true;
  681. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  682. if (ret == -EAGAIN)
  683. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  684. else if (ret) {
  685. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  686. /*
  687. * Force solid fill color on error. This is to prevent
  688. * smmu faults during secure session transition.
  689. */
  690. psde->is_error = true;
  691. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  692. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  693. pipe_cfg->layout.width,
  694. pipe_cfg->layout.height,
  695. pipe_cfg->layout.plane_addr[0],
  696. pipe_cfg->layout.plane_size[0],
  697. pipe_cfg->layout.plane_addr[1],
  698. pipe_cfg->layout.plane_size[1],
  699. pipe_cfg->layout.plane_addr[2],
  700. pipe_cfg->layout.plane_size[2],
  701. pipe_cfg->layout.plane_addr[3],
  702. pipe_cfg->layout.plane_size[3],
  703. pstate->multirect_index,
  704. secure);
  705. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  706. pstate->multirect_index);
  707. }
  708. }
  709. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  710. struct sde_plane_state *pstate)
  711. {
  712. struct sde_hw_scaler3_cfg *cfg;
  713. int ret = 0;
  714. if (!psde || !pstate) {
  715. SDE_ERROR("invalid args\n");
  716. return -EINVAL;
  717. }
  718. cfg = &psde->scaler3_cfg;
  719. cfg->dir_lut = msm_property_get_blob(
  720. &psde->property_info,
  721. &pstate->property_state, &cfg->dir_len,
  722. PLANE_PROP_SCALER_LUT_ED);
  723. cfg->cir_lut = msm_property_get_blob(
  724. &psde->property_info,
  725. &pstate->property_state, &cfg->cir_len,
  726. PLANE_PROP_SCALER_LUT_CIR);
  727. cfg->sep_lut = msm_property_get_blob(
  728. &psde->property_info,
  729. &pstate->property_state, &cfg->sep_len,
  730. PLANE_PROP_SCALER_LUT_SEP);
  731. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  732. ret = -ENODATA;
  733. return ret;
  734. }
  735. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  736. struct sde_plane_state *pstate)
  737. {
  738. struct sde_hw_scaler3_cfg *cfg;
  739. cfg = &psde->scaler3_cfg;
  740. cfg->sep_lut = msm_property_get_blob(
  741. &psde->property_info,
  742. &pstate->property_state, &cfg->sep_len,
  743. PLANE_PROP_SCALER_LUT_SEP);
  744. return cfg->sep_lut ? 0 : -ENODATA;
  745. }
  746. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  747. struct sde_plane_state *pstate, const struct sde_format *fmt,
  748. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  749. {
  750. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  751. struct sde_hw_scaler3_cfg *scale_cfg;
  752. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  753. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  754. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  755. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  756. chroma_subsmpl_h, chroma_subsmpl_v);
  757. return;
  758. }
  759. scale_cfg = &psde->scaler3_cfg;
  760. src_w = psde->pipe_cfg.src_rect.w;
  761. src_h = psde->pipe_cfg.src_rect.h;
  762. dst_w = psde->pipe_cfg.dst_rect.w;
  763. dst_h = psde->pipe_cfg.dst_rect.h;
  764. memset(scale_cfg, 0, sizeof(*scale_cfg));
  765. memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  766. /*
  767. * For inline rotation cases, scaler config is post-rotation,
  768. * so swap the dimensions here. However, pixel extension will
  769. * need pre-rotation settings, this will be corrected below
  770. * when calculating pixel extension settings.
  771. */
  772. if (inline_rotation)
  773. swap(src_w, src_h);
  774. decimated = DECIMATED_DIMENSION(src_w,
  775. psde->pipe_cfg.horz_decimation);
  776. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  777. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  778. decimated = DECIMATED_DIMENSION(src_h,
  779. psde->pipe_cfg.vert_decimation);
  780. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  781. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  782. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  783. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  784. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  785. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  786. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  787. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  788. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  789. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  790. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  791. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  792. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  793. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  794. for (i = 0; i < SDE_MAX_PLANES; i++) {
  795. /*
  796. * For inline rotation cases with pre-downscaling enabled
  797. * set x pre-downscale value if required. Only x direction
  798. * is currently supported. Use src_h as values have been swapped
  799. * and x direction corresponds to height value.
  800. */
  801. src_h_pre_down = src_h;
  802. if (pre_down_supported && inline_rotation) {
  803. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  804. src_h_pre_down = src_h / 2;
  805. }
  806. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  807. psde->pipe_cfg.horz_decimation);
  808. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  809. psde->pipe_cfg.vert_decimation);
  810. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  811. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  812. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  813. }
  814. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  815. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  816. /* For pixel extension we need the pre-rotated orientation */
  817. if (inline_rotation) {
  818. psde->pixel_ext.num_ext_pxls_top[i] =
  819. scale_cfg->src_width[i];
  820. psde->pixel_ext.num_ext_pxls_left[i] =
  821. scale_cfg->src_height[i];
  822. } else {
  823. psde->pixel_ext.num_ext_pxls_top[i] =
  824. scale_cfg->src_height[i];
  825. psde->pixel_ext.num_ext_pxls_left[i] =
  826. scale_cfg->src_width[i];
  827. }
  828. }
  829. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  830. && (src_w == dst_w) && !inline_rotation) ||
  831. pstate->multirect_mode)
  832. return;
  833. SDE_DEBUG_PLANE(psde,
  834. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  835. src_w, src_h, dst_w, dst_h,
  836. chroma_subsmpl_v, chroma_subsmpl_h,
  837. fmt->base.pixel_format);
  838. scale_cfg->dst_width = dst_w;
  839. scale_cfg->dst_height = dst_h;
  840. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  841. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  842. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  843. scale_cfg->lut_flag = 0;
  844. scale_cfg->blend_cfg = 1;
  845. scale_cfg->enable = 1;
  846. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  847. }
  848. /**
  849. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  850. * @psde: Pointer to SDE plane object
  851. * @src: Source size
  852. * @dst: Destination size
  853. * @phase_steps: Pointer to output array for phase steps
  854. * @filter: Pointer to output array for filter type
  855. * @fmt: Pointer to format definition
  856. * @chroma_subsampling: Subsampling amount for chroma channel
  857. *
  858. * Returns: 0 on success
  859. */
  860. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  861. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  862. enum sde_hw_filter *filter, const struct sde_format *fmt,
  863. uint32_t chroma_subsampling)
  864. {
  865. if (!psde || !phase_steps || !filter || !fmt) {
  866. SDE_ERROR(
  867. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  868. !psde, !phase_steps, !filter, !fmt);
  869. return -EINVAL;
  870. }
  871. /* calculate phase steps, leave init phase as zero */
  872. phase_steps[SDE_SSPP_COMP_0] =
  873. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  874. phase_steps[SDE_SSPP_COMP_1_2] =
  875. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  876. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  877. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  878. /* calculate scaler config, if necessary */
  879. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  880. filter[SDE_SSPP_COMP_3] =
  881. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  882. SDE_SCALE_FILTER_PCMN;
  883. if (SDE_FORMAT_IS_YUV(fmt)) {
  884. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  885. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  886. } else {
  887. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  888. filter[SDE_SSPP_COMP_1_2] =
  889. SDE_SCALE_FILTER_NEAREST;
  890. }
  891. } else {
  892. /* disable scaler */
  893. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  894. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  895. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  896. }
  897. return 0;
  898. }
  899. /**
  900. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  901. * @psde: Pointer to SDE plane object
  902. * @src: Source size
  903. * @dst: Destination size
  904. * @decimated_src: Source size after decimation, if any
  905. * @phase_steps: Pointer to output array for phase steps
  906. * @out_src: Output array for pixel extension values
  907. * @out_edge1: Output array for pixel extension first edge
  908. * @out_edge2: Output array for pixel extension second edge
  909. * @filter: Pointer to array for filter type
  910. * @fmt: Pointer to format definition
  911. * @chroma_subsampling: Subsampling amount for chroma channel
  912. * @post_compare: Whether to chroma subsampled source size for comparisions
  913. */
  914. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  915. uint32_t src, uint32_t dst, uint32_t decimated_src,
  916. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  917. int *out_edge2, enum sde_hw_filter *filter,
  918. const struct sde_format *fmt, uint32_t chroma_subsampling,
  919. bool post_compare)
  920. {
  921. int64_t edge1, edge2, caf;
  922. uint32_t src_work;
  923. int i, tmp;
  924. if (psde && phase_steps && out_src && out_edge1 &&
  925. out_edge2 && filter && fmt) {
  926. /* handle CAF for YUV formats */
  927. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  928. caf = PHASE_STEP_UNIT_SCALE;
  929. else
  930. caf = 0;
  931. for (i = 0; i < SDE_MAX_PLANES; i++) {
  932. src_work = decimated_src;
  933. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  934. src_work /= chroma_subsampling;
  935. if (post_compare)
  936. src = src_work;
  937. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  938. /* unity */
  939. edge1 = 0;
  940. edge2 = 0;
  941. } else if (dst >= src) {
  942. /* upscale */
  943. edge1 = (1 << PHASE_RESIDUAL);
  944. edge1 -= caf;
  945. edge2 = (1 << PHASE_RESIDUAL);
  946. edge2 += (dst - 1) * *(phase_steps + i);
  947. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  948. edge2 += caf;
  949. edge2 = -(edge2);
  950. } else {
  951. /* downscale */
  952. edge1 = 0;
  953. edge2 = (dst - 1) * *(phase_steps + i);
  954. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  955. edge2 += *(phase_steps + i);
  956. edge2 = -(edge2);
  957. }
  958. /* only enable CAF for luma plane */
  959. caf = 0;
  960. /* populate output arrays */
  961. *(out_src + i) = src_work;
  962. /* edge updates taken from __pxl_extn_helper */
  963. if (edge1 >= 0) {
  964. tmp = (uint32_t)edge1;
  965. tmp >>= PHASE_STEP_SHIFT;
  966. *(out_edge1 + i) = -tmp;
  967. } else {
  968. tmp = (uint32_t)(-edge1);
  969. *(out_edge1 + i) =
  970. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  971. PHASE_STEP_SHIFT;
  972. }
  973. if (edge2 >= 0) {
  974. tmp = (uint32_t)edge2;
  975. tmp >>= PHASE_STEP_SHIFT;
  976. *(out_edge2 + i) = -tmp;
  977. } else {
  978. tmp = (uint32_t)(-edge2);
  979. *(out_edge2 + i) =
  980. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  981. PHASE_STEP_SHIFT;
  982. }
  983. }
  984. }
  985. }
  986. static inline void _sde_plane_setup_csc(struct sde_plane *psde, struct sde_plane_state *pstate)
  987. {
  988. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  989. {
  990. /* S15.16 format */
  991. 0x00012A00, 0x00000000, 0x00019880,
  992. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  993. 0x00012A00, 0x00020480, 0x00000000,
  994. },
  995. /* signed bias */
  996. { 0xfff0, 0xff80, 0xff80,},
  997. { 0x0, 0x0, 0x0,},
  998. /* unsigned clamp */
  999. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  1000. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  1001. };
  1002. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  1003. {
  1004. /* S15.16 format */
  1005. 0x00012A00, 0x00000000, 0x00019880,
  1006. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  1007. 0x00012A00, 0x00020480, 0x00000000,
  1008. },
  1009. /* signed bias */
  1010. { 0xffc0, 0xfe00, 0xfe00,},
  1011. { 0x0, 0x0, 0x0,},
  1012. /* unsigned clamp */
  1013. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  1014. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  1015. };
  1016. if (!psde || !pstate) {
  1017. SDE_ERROR("invalid plane\n");
  1018. return;
  1019. }
  1020. /* revert to kernel default if override not available */
  1021. if (pstate->csc_usr_ptr)
  1022. pstate->csc_ptr = pstate->csc_usr_ptr;
  1023. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  1024. pstate->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  1025. else
  1026. pstate->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  1027. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  1028. pstate->csc_ptr->csc_mv[0],
  1029. pstate->csc_ptr->csc_mv[1],
  1030. pstate->csc_ptr->csc_mv[2]);
  1031. }
  1032. static void sde_color_process_plane_setup(struct drm_plane *plane)
  1033. {
  1034. struct sde_plane *psde;
  1035. struct sde_plane_state *pstate;
  1036. uint32_t hue, saturation, value, contrast;
  1037. struct drm_msm_memcol *memcol = NULL;
  1038. struct drm_msm_3d_gamut *vig_gamut = NULL;
  1039. struct drm_msm_igc_lut *igc = NULL;
  1040. struct drm_msm_pgc_lut *gc = NULL;
  1041. size_t memcol_sz = 0, size = 0;
  1042. struct sde_hw_cp_cfg hw_cfg = {};
  1043. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1044. bool fp16_igc, fp16_unmult, ucsc_unmult, ucsc_alpha_dither;
  1045. int ucsc_gc, ucsc_igc;
  1046. struct drm_msm_fp16_gc *fp16_gc = NULL;
  1047. struct drm_msm_fp16_csc *fp16_csc = NULL;
  1048. struct drm_msm_ucsc_csc *ucsc_csc = NULL;
  1049. psde = to_sde_plane(plane);
  1050. pstate = to_sde_plane_state(plane->state);
  1051. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1052. if (psde->pipe_hw->ops.setup_pa_hue)
  1053. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1054. saturation = (uint32_t) sde_plane_get_property(pstate,
  1055. PLANE_PROP_SATURATION_ADJUST);
  1056. if (psde->pipe_hw->ops.setup_pa_sat)
  1057. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1058. value = (uint32_t) sde_plane_get_property(pstate,
  1059. PLANE_PROP_VALUE_ADJUST);
  1060. if (psde->pipe_hw->ops.setup_pa_val)
  1061. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1062. contrast = (uint32_t) sde_plane_get_property(pstate,
  1063. PLANE_PROP_CONTRAST_ADJUST);
  1064. if (psde->pipe_hw->ops.setup_pa_cont)
  1065. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1066. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1067. /* Skin memory color setup */
  1068. memcol = msm_property_get_blob(&psde->property_info,
  1069. &pstate->property_state,
  1070. &memcol_sz,
  1071. PLANE_PROP_SKIN_COLOR);
  1072. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1073. MEMCOLOR_SKIN, memcol);
  1074. /* Sky memory color setup */
  1075. memcol = msm_property_get_blob(&psde->property_info,
  1076. &pstate->property_state,
  1077. &memcol_sz,
  1078. PLANE_PROP_SKY_COLOR);
  1079. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1080. MEMCOLOR_SKY, memcol);
  1081. /* Foliage memory color setup */
  1082. memcol = msm_property_get_blob(&psde->property_info,
  1083. &pstate->property_state,
  1084. &memcol_sz,
  1085. PLANE_PROP_FOLIAGE_COLOR);
  1086. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1087. MEMCOLOR_FOLIAGE, memcol);
  1088. }
  1089. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1090. psde->pipe_hw->ops.setup_vig_gamut) {
  1091. vig_gamut = msm_property_get_blob(&psde->property_info,
  1092. &pstate->property_state,
  1093. &size,
  1094. PLANE_PROP_VIG_GAMUT);
  1095. hw_cfg.last_feature = 0;
  1096. hw_cfg.ctl = ctl;
  1097. hw_cfg.len = size;
  1098. hw_cfg.payload = vig_gamut;
  1099. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1100. }
  1101. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1102. psde->pipe_hw->ops.setup_vig_igc) {
  1103. igc = msm_property_get_blob(&psde->property_info,
  1104. &pstate->property_state,
  1105. &size,
  1106. PLANE_PROP_VIG_IGC);
  1107. hw_cfg.last_feature = 0;
  1108. hw_cfg.ctl = ctl;
  1109. hw_cfg.len = size;
  1110. hw_cfg.payload = igc;
  1111. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1112. }
  1113. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1114. psde->pipe_hw->ops.setup_dma_igc) {
  1115. igc = msm_property_get_blob(&psde->property_info,
  1116. &pstate->property_state,
  1117. &size,
  1118. PLANE_PROP_DMA_IGC);
  1119. hw_cfg.last_feature = 0;
  1120. hw_cfg.ctl = ctl;
  1121. hw_cfg.len = size;
  1122. hw_cfg.payload = igc;
  1123. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1124. pstate->multirect_index);
  1125. }
  1126. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1127. psde->pipe_hw->ops.setup_dma_gc) {
  1128. gc = msm_property_get_blob(&psde->property_info,
  1129. &pstate->property_state,
  1130. &size,
  1131. PLANE_PROP_DMA_GC);
  1132. hw_cfg.last_feature = 0;
  1133. hw_cfg.ctl = ctl;
  1134. hw_cfg.len = size;
  1135. hw_cfg.payload = gc;
  1136. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1137. pstate->multirect_index);
  1138. }
  1139. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1140. psde->pipe_hw->ops.setup_fp16_igc) {
  1141. fp16_igc = !!sde_plane_get_property(pstate,
  1142. PLANE_PROP_FP16_IGC);
  1143. hw_cfg.last_feature = 0;
  1144. hw_cfg.ctl = ctl;
  1145. hw_cfg.len = sizeof(bool);
  1146. hw_cfg.payload = &fp16_igc;
  1147. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1148. pstate->multirect_index, &hw_cfg);
  1149. }
  1150. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1151. psde->pipe_hw->ops.setup_fp16_gc) {
  1152. fp16_gc = msm_property_get_blob(&psde->property_info,
  1153. &pstate->property_state,
  1154. &size,
  1155. PLANE_PROP_FP16_GC);
  1156. hw_cfg.last_feature = 0;
  1157. hw_cfg.ctl = ctl;
  1158. hw_cfg.len = size;
  1159. hw_cfg.payload = fp16_gc;
  1160. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1161. pstate->multirect_index, &hw_cfg);
  1162. }
  1163. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1164. psde->pipe_hw->ops.setup_fp16_csc) {
  1165. fp16_csc = msm_property_get_blob(&psde->property_info,
  1166. &pstate->property_state,
  1167. &size,
  1168. PLANE_PROP_FP16_CSC);
  1169. hw_cfg.last_feature = 0;
  1170. hw_cfg.ctl = ctl;
  1171. hw_cfg.len = size;
  1172. hw_cfg.payload = fp16_csc;
  1173. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1174. pstate->multirect_index, &hw_cfg);
  1175. }
  1176. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1177. psde->pipe_hw->ops.setup_fp16_unmult) {
  1178. fp16_unmult = !!sde_plane_get_property(pstate,
  1179. PLANE_PROP_FP16_UNMULT);
  1180. hw_cfg.last_feature = 0;
  1181. hw_cfg.ctl = ctl;
  1182. hw_cfg.len = sizeof(bool);
  1183. hw_cfg.payload = &fp16_unmult;
  1184. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1185. pstate->multirect_index, &hw_cfg);
  1186. }
  1187. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_IGC &&
  1188. psde->pipe_hw->ops.setup_ucsc_igc) {
  1189. ucsc_igc = sde_plane_get_property(pstate,
  1190. PLANE_PROP_UCSC_IGC);
  1191. hw_cfg.last_feature = 0;
  1192. hw_cfg.ctl = ctl;
  1193. hw_cfg.len = sizeof(int);
  1194. hw_cfg.payload = &ucsc_igc;
  1195. psde->pipe_hw->ops.setup_ucsc_igc(psde->pipe_hw,
  1196. pstate->multirect_index, &hw_cfg);
  1197. }
  1198. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_GC &&
  1199. psde->pipe_hw->ops.setup_ucsc_gc) {
  1200. ucsc_gc = sde_plane_get_property(pstate,
  1201. PLANE_PROP_UCSC_GC);
  1202. hw_cfg.last_feature = 0;
  1203. hw_cfg.ctl = ctl;
  1204. hw_cfg.len = sizeof(int);
  1205. hw_cfg.payload = &ucsc_gc;
  1206. psde->pipe_hw->ops.setup_ucsc_gc(psde->pipe_hw,
  1207. pstate->multirect_index, &hw_cfg);
  1208. }
  1209. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_CSC &&
  1210. psde->pipe_hw->ops.setup_ucsc_csc) {
  1211. ucsc_csc = msm_property_get_blob(&psde->property_info,
  1212. &pstate->property_state,
  1213. &size,
  1214. PLANE_PROP_UCSC_CSC);
  1215. hw_cfg.last_feature = 0;
  1216. hw_cfg.ctl = ctl;
  1217. hw_cfg.len = size;
  1218. hw_cfg.payload = ucsc_csc;
  1219. psde->pipe_hw->ops.setup_ucsc_csc(psde->pipe_hw,
  1220. pstate->multirect_index, &hw_cfg);
  1221. }
  1222. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_UNMULT &&
  1223. psde->pipe_hw->ops.setup_ucsc_unmult) {
  1224. ucsc_unmult = !!sde_plane_get_property(pstate,
  1225. PLANE_PROP_UCSC_UNMULT);
  1226. hw_cfg.last_feature = 0;
  1227. hw_cfg.ctl = ctl;
  1228. hw_cfg.len = sizeof(bool);
  1229. hw_cfg.payload = &ucsc_unmult;
  1230. psde->pipe_hw->ops.setup_ucsc_unmult(psde->pipe_hw,
  1231. pstate->multirect_index, &hw_cfg);
  1232. }
  1233. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_ALPHA_DITHER &&
  1234. psde->pipe_hw->ops.setup_ucsc_alpha_dither) {
  1235. ucsc_alpha_dither = !!sde_plane_get_property(pstate,
  1236. PLANE_PROP_UCSC_ALPHA_DITHER);
  1237. hw_cfg.last_feature = 0;
  1238. hw_cfg.ctl = ctl;
  1239. hw_cfg.len = sizeof(bool);
  1240. hw_cfg.payload = &ucsc_alpha_dither;
  1241. psde->pipe_hw->ops.setup_ucsc_alpha_dither(psde->pipe_hw,
  1242. pstate->multirect_index, &hw_cfg);
  1243. }
  1244. }
  1245. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1246. struct sde_plane_state *pstate,
  1247. const struct sde_format *fmt, bool color_fill)
  1248. {
  1249. struct sde_hw_pixel_ext *pe;
  1250. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1251. const struct drm_format_info *info = NULL;
  1252. if (!psde || !fmt || !pstate) {
  1253. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1254. !psde, !fmt, !pstate);
  1255. return;
  1256. }
  1257. memcpy(&psde->scaler3_cfg, &pstate->scaler3_cfg,
  1258. sizeof(psde->scaler3_cfg));
  1259. memcpy(&psde->pixel_ext, &pstate->pixel_ext,
  1260. sizeof(psde->pixel_ext));
  1261. info = drm_format_info(fmt->base.pixel_format);
  1262. pe = &psde->pixel_ext;
  1263. psde->pipe_cfg.horz_decimation =
  1264. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1265. psde->pipe_cfg.vert_decimation =
  1266. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1267. /* don't chroma subsample if decimating */
  1268. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1269. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1270. /* update scaler */
  1271. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1272. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1273. int rc = -EINVAL;
  1274. if (!color_fill && !psde->debugfs_default_scale)
  1275. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1276. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1277. _sde_plane_setup_scaler3_lut(psde, pstate);
  1278. if (rc || pstate->scaler_check_state !=
  1279. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1280. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1281. pstate->scaler_check_state,
  1282. psde->debugfs_default_scale, rc,
  1283. psde->pipe_cfg.src_rect.w,
  1284. psde->pipe_cfg.src_rect.h,
  1285. psde->pipe_cfg.dst_rect.w,
  1286. psde->pipe_cfg.dst_rect.h,
  1287. pstate->multirect_mode);
  1288. /* calculate default config for QSEED3 */
  1289. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1290. chroma_subsmpl_h, chroma_subsmpl_v);
  1291. }
  1292. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1293. color_fill || psde->debugfs_default_scale) {
  1294. uint32_t deci_dim, i;
  1295. /* calculate default configuration for QSEED2 */
  1296. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1297. SDE_DEBUG_PLANE(psde, "default config\n");
  1298. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1299. psde->pipe_cfg.horz_decimation);
  1300. _sde_plane_setup_scaler2(psde,
  1301. deci_dim,
  1302. psde->pipe_cfg.dst_rect.w,
  1303. pe->phase_step_x,
  1304. pe->horz_filter, fmt, chroma_subsmpl_h);
  1305. if (SDE_FORMAT_IS_YUV(fmt))
  1306. deci_dim &= ~0x1;
  1307. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1308. psde->pipe_cfg.dst_rect.w, deci_dim,
  1309. pe->phase_step_x,
  1310. pe->roi_w,
  1311. pe->num_ext_pxls_left,
  1312. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1313. chroma_subsmpl_h, 0);
  1314. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1315. psde->pipe_cfg.vert_decimation);
  1316. _sde_plane_setup_scaler2(psde,
  1317. deci_dim,
  1318. psde->pipe_cfg.dst_rect.h,
  1319. pe->phase_step_y,
  1320. pe->vert_filter, fmt, chroma_subsmpl_v);
  1321. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1322. psde->pipe_cfg.dst_rect.h, deci_dim,
  1323. pe->phase_step_y,
  1324. pe->roi_h,
  1325. pe->num_ext_pxls_top,
  1326. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1327. chroma_subsmpl_v, 1);
  1328. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1329. if (pe->num_ext_pxls_left[i] >= 0)
  1330. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1331. else
  1332. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1333. if (pe->num_ext_pxls_right[i] >= 0)
  1334. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1335. else
  1336. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1337. if (pe->num_ext_pxls_top[i] >= 0)
  1338. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1339. else
  1340. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1341. if (pe->num_ext_pxls_btm[i] >= 0)
  1342. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1343. else
  1344. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1345. }
  1346. }
  1347. if (psde->pipe_hw->ops.setup_pre_downscale)
  1348. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1349. &pstate->pre_down);
  1350. }
  1351. /**
  1352. * _sde_plane_color_fill - enables color fill on plane
  1353. * @psde: Pointer to SDE plane object
  1354. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1355. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1356. * Returns: 0 on success
  1357. */
  1358. static int _sde_plane_color_fill(struct sde_plane *psde,
  1359. uint32_t color, uint32_t alpha)
  1360. {
  1361. const struct sde_format *fmt;
  1362. const struct drm_plane *plane;
  1363. struct sde_plane_state *pstate;
  1364. bool blend_enable = true;
  1365. if (!psde || !psde->base.state) {
  1366. SDE_ERROR("invalid plane\n");
  1367. return -EINVAL;
  1368. }
  1369. if (!psde->pipe_hw) {
  1370. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1371. return -EINVAL;
  1372. }
  1373. plane = &psde->base;
  1374. pstate = to_sde_plane_state(plane->state);
  1375. SDE_DEBUG_PLANE(psde, "\n");
  1376. /*
  1377. * select fill format to match user property expectation,
  1378. * h/w only supports RGB variants
  1379. */
  1380. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1381. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1382. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1383. /* update sspp */
  1384. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1385. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1386. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1387. pstate->multirect_index);
  1388. /* override scaler/decimation if solid fill */
  1389. psde->pipe_cfg.src_rect.x = 0;
  1390. psde->pipe_cfg.src_rect.y = 0;
  1391. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1392. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1393. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1394. if (psde->pipe_hw->ops.setup_format)
  1395. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1396. fmt, blend_enable,
  1397. SDE_SSPP_SOLID_FILL,
  1398. pstate->multirect_index);
  1399. if (psde->pipe_hw->ops.setup_rects)
  1400. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1401. &psde->pipe_cfg,
  1402. pstate->multirect_index);
  1403. if (psde->pipe_hw->ops.setup_pe)
  1404. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1405. &psde->pixel_ext);
  1406. if (psde->pipe_hw->ops.setup_scaler &&
  1407. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1408. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1409. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1410. &psde->pipe_cfg, &psde->pixel_ext,
  1411. &psde->scaler3_cfg);
  1412. }
  1413. }
  1414. return 0;
  1415. }
  1416. /**
  1417. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1418. * @plane: Pointer to drm plane
  1419. * @state: Pointer to drm plane state to be validated
  1420. * return: 0 if success; error code otherwise
  1421. */
  1422. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1423. struct drm_plane_state *state)
  1424. {
  1425. struct sde_plane *psde;
  1426. struct sde_plane_state *pstate, *old_pstate;
  1427. int ret = 0;
  1428. u32 rotation;
  1429. if (!plane || !state) {
  1430. SDE_ERROR("invalid plane/state\n");
  1431. return -EINVAL;
  1432. }
  1433. psde = to_sde_plane(plane);
  1434. pstate = to_sde_plane_state(state);
  1435. old_pstate = to_sde_plane_state(plane->state);
  1436. /* check inline rotation and simplify the transform */
  1437. rotation = drm_rotation_simplify(
  1438. state->rotation,
  1439. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1440. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1441. if ((rotation & DRM_MODE_ROTATE_180) ||
  1442. (rotation & DRM_MODE_ROTATE_270)) {
  1443. SDE_ERROR_PLANE(psde,
  1444. "invalid rotation transform must be simplified 0x%x\n",
  1445. rotation);
  1446. ret = -EINVAL;
  1447. goto exit;
  1448. }
  1449. if (rotation & DRM_MODE_ROTATE_90) {
  1450. struct msm_drm_private *priv = plane->dev->dev_private;
  1451. struct sde_kms *sde_kms;
  1452. const struct msm_format *msm_fmt;
  1453. const struct sde_format *fmt;
  1454. struct sde_rect src;
  1455. bool q16_data = true;
  1456. POPULATE_RECT(&src, state->src_x, state->src_y,
  1457. state->src_w, state->src_h, q16_data);
  1458. /*
  1459. * DRM framework expects rotation flag in counter-clockwise
  1460. * direction and the HW expects in clockwise direction.
  1461. * Flip the flags to match with HW.
  1462. */
  1463. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1464. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1465. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1466. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1467. !psde->pipe_sblk->in_rot_maxheight ||
  1468. !psde->pipe_sblk->in_rot_format_list ||
  1469. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1470. SDE_ERROR_PLANE(psde,
  1471. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1472. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1473. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1474. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1475. !psde->pipe_sblk->in_rot_format_list,
  1476. !psde->pipe_sblk->in_rot_maxheight,
  1477. psde->features);
  1478. ret = -EINVAL;
  1479. goto exit;
  1480. }
  1481. /* check for valid height */
  1482. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1483. SDE_ERROR_PLANE(psde,
  1484. "invalid height for inline rot:%d max:%d\n",
  1485. src.h, psde->pipe_sblk->in_rot_maxheight);
  1486. ret = -EINVAL;
  1487. goto exit;
  1488. }
  1489. if (!sde_plane_enabled(state))
  1490. goto exit;
  1491. /* check for valid formats supported by inline rot */
  1492. sde_kms = to_sde_kms(priv->kms);
  1493. msm_fmt = msm_framebuffer_format(state->fb);
  1494. fmt = to_sde_format(msm_fmt);
  1495. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1496. psde->pipe_sblk->in_rot_format_list);
  1497. }
  1498. exit:
  1499. pstate->rotation = rotation;
  1500. return ret;
  1501. }
  1502. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1503. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1504. {
  1505. struct sde_plane *psde;
  1506. struct msm_drm_private *priv;
  1507. struct sde_vbif_set_xin_halt_params halt_params;
  1508. if (!plane || !plane->dev) {
  1509. SDE_ERROR("invalid arguments\n");
  1510. return false;
  1511. }
  1512. psde = to_sde_plane(plane);
  1513. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1514. SDE_ERROR("invalid pipe reference\n");
  1515. return false;
  1516. }
  1517. priv = plane->dev->dev_private;
  1518. if (!priv || !priv->kms) {
  1519. SDE_ERROR("invalid KMS reference\n");
  1520. return false;
  1521. }
  1522. memset(&halt_params, 0, sizeof(halt_params));
  1523. halt_params.vbif_idx = VBIF_RT;
  1524. halt_params.xin_id = xin_id;
  1525. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1526. halt_params.forced_on = halt_forced_clk;
  1527. halt_params.enable = enable;
  1528. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1529. }
  1530. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1531. {
  1532. struct sde_plane *psde;
  1533. if (!plane) {
  1534. SDE_ERROR("invalid plane\n");
  1535. return;
  1536. }
  1537. psde = to_sde_plane(plane);
  1538. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1539. SDE_ERROR("invalid pipe reference\n");
  1540. return;
  1541. }
  1542. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1543. psde->xin_halt_forced_clk =
  1544. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1545. psde->xin_halt_forced_clk, enable);
  1546. }
  1547. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1548. struct drm_crtc *crtc)
  1549. {
  1550. struct sde_plane *psde;
  1551. if (!plane || !crtc) {
  1552. SDE_ERROR("invalid plane/crtc\n");
  1553. return;
  1554. }
  1555. psde = to_sde_plane(plane);
  1556. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1557. return;
  1558. /* do all VBIF programming for the sec-ui allowed SSPP */
  1559. _sde_plane_set_qos_remap(plane);
  1560. _sde_plane_set_ot_limit(plane, crtc);
  1561. }
  1562. /**
  1563. * sde_plane_rot_install_properties - install plane rotator properties
  1564. * @plane: Pointer to drm plane
  1565. * @catalog: Pointer to mdss configuration
  1566. * return: none
  1567. */
  1568. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1569. struct sde_mdss_cfg *catalog)
  1570. {
  1571. struct sde_plane *psde = to_sde_plane(plane);
  1572. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1573. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1574. int ret = 0;
  1575. if (!plane || !psde) {
  1576. SDE_ERROR("invalid plane\n");
  1577. return;
  1578. } else if (!catalog) {
  1579. SDE_ERROR("invalid catalog\n");
  1580. return;
  1581. }
  1582. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1583. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1584. ret = drm_plane_create_rotation_property(plane,
  1585. DRM_MODE_ROTATE_0, supported_rotations);
  1586. if (ret) {
  1587. DRM_ERROR("create rotation property failed: %d\n", ret);
  1588. return;
  1589. }
  1590. }
  1591. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1592. {
  1593. struct sde_plane_state *pstate;
  1594. if (!drm_state)
  1595. return;
  1596. pstate = to_sde_plane_state(drm_state);
  1597. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1598. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1599. }
  1600. /**
  1601. * multi_rect validate API allows to validate only R0 and R1 RECT
  1602. * passing for each plane. Client of this API must not pass multiple
  1603. * plane which are not sharing same XIN client. Such calls will fail
  1604. * even though kernel client is passing valid multirect configuration.
  1605. */
  1606. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1607. {
  1608. struct sde_plane_state *pstate[R_MAX];
  1609. const struct drm_plane_state *drm_state[R_MAX];
  1610. struct sde_rect src[R_MAX], dst[R_MAX];
  1611. struct sde_plane *sde_plane[R_MAX];
  1612. const struct sde_format *fmt[R_MAX];
  1613. int xin_id[R_MAX];
  1614. bool q16_data = true;
  1615. int i, j, buffer_lines, width_threshold[R_MAX];
  1616. unsigned int max_tile_height = 1;
  1617. bool parallel_fetch_qualified = true;
  1618. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1619. const struct msm_format *msm_fmt;
  1620. bool const_alpha_enable = true;
  1621. for (i = 0; i < R_MAX; i++) {
  1622. drm_state[i] = i ? plane->r1 : plane->r0;
  1623. if (!drm_state[i]) {
  1624. SDE_ERROR("drm plane state is NULL\n");
  1625. return -EINVAL;
  1626. }
  1627. pstate[i] = to_sde_plane_state(drm_state[i]);
  1628. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1629. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1630. for (j = 0; j < i; j++) {
  1631. if (xin_id[i] != xin_id[j]) {
  1632. SDE_ERROR_PLANE(sde_plane[i],
  1633. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1634. j, xin_id[j], i, xin_id[i]);
  1635. return -EINVAL;
  1636. }
  1637. }
  1638. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1639. if (!msm_fmt) {
  1640. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1641. return -EINVAL;
  1642. }
  1643. fmt[i] = to_sde_format(msm_fmt);
  1644. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1645. (fmt[i]->tile_height > max_tile_height))
  1646. max_tile_height = fmt[i]->tile_height;
  1647. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1648. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1649. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1650. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1651. drm_state[i]->crtc_h, !q16_data);
  1652. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1653. SDE_ERROR_PLANE(sde_plane[i],
  1654. "scaling is not supported in multirect mode\n");
  1655. return -EINVAL;
  1656. }
  1657. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1658. SDE_ERROR_PLANE(sde_plane[i],
  1659. "inline rotation is not supported in mulirect mode\n");
  1660. return -EINVAL;
  1661. }
  1662. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1663. SDE_ERROR_PLANE(sde_plane[i],
  1664. "Unsupported format for multirect mode\n");
  1665. return -EINVAL;
  1666. }
  1667. /**
  1668. * SSPP PD_MEM is split half - one for each RECT.
  1669. * Tiled formats need 5 lines of buffering while fetching
  1670. * whereas linear formats need only 2 lines.
  1671. * So we cannot support more than half of the supported SSPP
  1672. * width for tiled formats.
  1673. */
  1674. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1675. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1676. width_threshold[i] /= 2;
  1677. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1678. parallel_fetch_qualified = false;
  1679. if (sde_plane[i]->is_virtual)
  1680. mode = sde_plane_get_property(pstate[i],
  1681. PLANE_PROP_MULTIRECT_MODE);
  1682. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1683. const_alpha_enable = false;
  1684. }
  1685. buffer_lines = 2 * max_tile_height;
  1686. /**
  1687. * fallback to driver mode selection logic if client is using
  1688. * multirect plane without setting property.
  1689. *
  1690. * validate multirect mode configuration based on rectangle
  1691. */
  1692. switch (mode) {
  1693. case SDE_SSPP_MULTIRECT_NONE:
  1694. if (parallel_fetch_qualified)
  1695. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1696. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1697. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1698. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1699. else
  1700. SDE_ERROR(
  1701. "planes(%d - %d) multirect mode selection fail\n",
  1702. drm_state[R0]->plane->base.id,
  1703. drm_state[R1]->plane->base.id);
  1704. break;
  1705. case SDE_SSPP_MULTIRECT_PARALLEL:
  1706. if (!parallel_fetch_qualified) {
  1707. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1708. drm_state[R0]->plane->base.id,
  1709. width_threshold[R0], src[R0].w);
  1710. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1711. drm_state[R1]->plane->base.id,
  1712. width_threshold[R1], src[R1].w);
  1713. SDE_ERROR("parallel fetch not qualified\n");
  1714. mode = SDE_SSPP_MULTIRECT_NONE;
  1715. }
  1716. break;
  1717. case SDE_SSPP_MULTIRECT_TIME_MX:
  1718. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1719. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1720. SDE_ERROR(
  1721. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1722. buffer_lines, drm_state[R0]->plane->base.id,
  1723. dst[R0].y, dst[R0].h);
  1724. SDE_ERROR(
  1725. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1726. buffer_lines, drm_state[R1]->plane->base.id,
  1727. dst[R1].y, dst[R1].h);
  1728. SDE_ERROR("time multiplexed fetch not qualified\n");
  1729. mode = SDE_SSPP_MULTIRECT_NONE;
  1730. }
  1731. break;
  1732. default:
  1733. SDE_ERROR("bad mode:%d selection\n", mode);
  1734. mode = SDE_SSPP_MULTIRECT_NONE;
  1735. break;
  1736. }
  1737. for (i = 0; i < R_MAX; i++) {
  1738. pstate[i]->multirect_mode = mode;
  1739. pstate[i]->const_alpha_en = const_alpha_enable;
  1740. }
  1741. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1742. return -EINVAL;
  1743. if (sde_plane[R0]->is_virtual) {
  1744. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1745. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1746. } else {
  1747. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1748. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1749. }
  1750. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1751. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1752. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1753. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1754. return 0;
  1755. }
  1756. /**
  1757. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1758. * @plane: Pointer to drm plane structure
  1759. * @ctl: Pointer to hardware control driver
  1760. * @set: set if true else clear
  1761. */
  1762. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1763. bool set)
  1764. {
  1765. if (!plane || !ctl) {
  1766. SDE_ERROR("invalid parameters\n");
  1767. return;
  1768. }
  1769. if (!ctl->ops.update_bitmask_sspp) {
  1770. SDE_ERROR("invalid ops\n");
  1771. return;
  1772. }
  1773. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1774. }
  1775. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1776. struct drm_plane_state *new_state)
  1777. {
  1778. struct drm_framebuffer *fb = new_state->fb;
  1779. struct sde_plane *psde = to_sde_plane(plane);
  1780. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1781. struct sde_hw_fmt_layout layout;
  1782. struct msm_gem_address_space *aspace;
  1783. int ret;
  1784. if (!fb)
  1785. return 0;
  1786. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1787. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1788. if (ret) {
  1789. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1790. return ret;
  1791. }
  1792. /* cache aspace */
  1793. pstate->aspace = aspace;
  1794. /*
  1795. * when transitioning from secure to non-secure,
  1796. * plane->prepare_fb happens before the commit. In such case,
  1797. * defer the prepare_fb and handled it late, during the commit
  1798. * after attaching the domains as part of the transition
  1799. */
  1800. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1801. true : false;
  1802. if (pstate->defer_prepare_fb) {
  1803. SDE_EVT32(DRMID(plane), psde->pipe);
  1804. SDE_DEBUG_PLANE(psde,
  1805. "domain not attached, prepare_fb handled later\n");
  1806. return 0;
  1807. }
  1808. if (pstate->aspace && fb) {
  1809. ret = msm_framebuffer_prepare(fb,
  1810. pstate->aspace);
  1811. if (ret) {
  1812. SDE_ERROR("failed to prepare framebuffer fb:%d plane:%d pipe:%d ret:%d\n",
  1813. fb->base.id, plane->base.id, psde->pipe, ret);
  1814. SDE_EVT32(fb->base.id, plane->base.id, psde->pipe, ret, SDE_EVTLOG_ERROR);
  1815. return ret;
  1816. }
  1817. }
  1818. /* validate framebuffer layout before commit */
  1819. ret = sde_format_populate_layout(pstate->aspace,
  1820. fb, &layout);
  1821. if (ret) {
  1822. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1823. return ret;
  1824. }
  1825. return 0;
  1826. }
  1827. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1828. struct drm_plane_state *old_state)
  1829. {
  1830. struct sde_plane *psde = to_sde_plane(plane);
  1831. struct sde_plane_state *old_pstate;
  1832. if (!old_state || !old_state->fb || !plane)
  1833. return;
  1834. old_pstate = to_sde_plane_state(old_state);
  1835. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1836. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1837. }
  1838. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1839. struct drm_plane_state *state,
  1840. struct drm_plane_state *old_state)
  1841. {
  1842. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1843. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1844. struct drm_framebuffer *fb, *old_fb;
  1845. /* no need to check it again */
  1846. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1847. return;
  1848. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1849. || psde->is_error) {
  1850. SDE_DEBUG_PLANE(psde,
  1851. "enabling/disabling full modeset required\n");
  1852. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1853. } else if (to_sde_plane_state(old_state)->pending) {
  1854. SDE_DEBUG_PLANE(psde, "still pending\n");
  1855. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1856. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1857. pstate->multirect_mode != old_pstate->multirect_mode) {
  1858. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1859. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1860. } else if (state->src_w != old_state->src_w ||
  1861. state->src_h != old_state->src_h ||
  1862. state->src_x != old_state->src_x ||
  1863. state->src_y != old_state->src_y) {
  1864. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1865. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1866. } else if (state->crtc_w != old_state->crtc_w ||
  1867. state->crtc_h != old_state->crtc_h ||
  1868. state->crtc_x != old_state->crtc_x ||
  1869. state->crtc_y != old_state->crtc_y) {
  1870. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1871. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1872. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1873. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1874. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1875. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1876. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1877. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1878. } else if (pstate->rotation != old_pstate->rotation) {
  1879. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1880. pstate->rotation, old_pstate->rotation);
  1881. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1882. }
  1883. fb = state->fb;
  1884. old_fb = old_state->fb;
  1885. if (!fb || !old_fb) {
  1886. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1887. } else if ((fb->format->format != old_fb->format->format) ||
  1888. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1889. SDE_DEBUG_PLANE(psde, "format change\n");
  1890. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1891. } else {
  1892. uint64_t new_mod = fb->modifier;
  1893. uint64_t old_mod = old_fb->modifier;
  1894. uint32_t *new_pitches = fb->pitches;
  1895. uint32_t *old_pitches = old_fb->pitches;
  1896. uint32_t *new_offset = fb->offsets;
  1897. uint32_t *old_offset = old_fb->offsets;
  1898. int i;
  1899. if (new_mod != old_mod) {
  1900. SDE_DEBUG_PLANE(psde,
  1901. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1902. new_mod, old_mod);
  1903. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1904. SDE_PLANE_DIRTY_RECTS;
  1905. }
  1906. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1907. if (new_pitches[i] != old_pitches[i]) {
  1908. SDE_DEBUG_PLANE(psde,
  1909. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1910. i, old_pitches[i], new_pitches[i]);
  1911. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1912. break;
  1913. }
  1914. }
  1915. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1916. if (new_offset[i] != old_offset[i]) {
  1917. SDE_DEBUG_PLANE(psde,
  1918. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1919. i, old_offset[i], new_offset[i]);
  1920. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1921. SDE_PLANE_DIRTY_RECTS;
  1922. break;
  1923. }
  1924. }
  1925. }
  1926. }
  1927. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1928. unsigned long base_addr, u32 size)
  1929. {
  1930. int ret = -EINVAL;
  1931. u32 addr;
  1932. struct sde_plane *psde = to_sde_plane(plane);
  1933. if (!psde || !base_addr || !size) {
  1934. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1935. return ret;
  1936. }
  1937. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1938. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1939. is_sde_plane_virtual(plane));
  1940. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1941. ret = 0;
  1942. }
  1943. return ret;
  1944. }
  1945. static inline bool _sde_plane_is_pre_downscale_enabled(
  1946. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1947. {
  1948. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1949. }
  1950. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1951. struct sde_plane_state *pstate,
  1952. const struct sde_format *fmt,
  1953. uint32_t img_w, uint32_t img_h,
  1954. uint32_t src_w, uint32_t src_h,
  1955. uint32_t deci_w, uint32_t deci_h)
  1956. {
  1957. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1958. bool pre_down_en;
  1959. int i;
  1960. if (!psde || !pstate || !fmt) {
  1961. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1962. return -EINVAL;
  1963. }
  1964. if (psde->debugfs_default_scale ||
  1965. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1966. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1967. return 0;
  1968. pd_cfg = &pstate->pre_down;
  1969. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1970. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1971. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1972. uint32_t hor_req_pixels, hor_fetch_pixels;
  1973. uint32_t vert_req_pixels, vert_fetch_pixels;
  1974. uint32_t src_w_tmp, src_h_tmp;
  1975. uint32_t scaler_w, scaler_h;
  1976. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1977. bool rot;
  1978. /* re-use color plane 1's config for plane 2 */
  1979. if (i == 2)
  1980. continue;
  1981. if (pre_down_en) {
  1982. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1983. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1984. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1985. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1986. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1987. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1988. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1989. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1990. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1991. i, pre_down_ratio_x, pre_down_ratio_y);
  1992. }
  1993. src_w_tmp = src_w;
  1994. src_h_tmp = src_h;
  1995. /*
  1996. * For chroma plane, width is half for the following sub sampled
  1997. * formats. Except in case of decimation, where hardware avoids
  1998. * 1 line of decimation instead of downsampling.
  1999. */
  2000. if (i == 1) {
  2001. if (!deci_w &&
  2002. (fmt->chroma_sample == SDE_CHROMA_420 ||
  2003. fmt->chroma_sample == SDE_CHROMA_H2V1))
  2004. src_w_tmp >>= 1;
  2005. if (!deci_h &&
  2006. (fmt->chroma_sample == SDE_CHROMA_420 ||
  2007. fmt->chroma_sample == SDE_CHROMA_H1V2))
  2008. src_h_tmp >>= 1;
  2009. }
  2010. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  2011. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  2012. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  2013. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  2014. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  2015. deci_w);
  2016. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  2017. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  2018. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  2019. deci_h);
  2020. if ((hor_req_pixels != hor_fetch_pixels) ||
  2021. (hor_fetch_pixels > img_w) ||
  2022. (vert_req_pixels != vert_fetch_pixels) ||
  2023. (vert_fetch_pixels > img_h)) {
  2024. SDE_ERROR_PLANE(psde,
  2025. "req %d/%d, fetch %d/%d, src %dx%d\n",
  2026. hor_req_pixels, vert_req_pixels,
  2027. hor_fetch_pixels, vert_fetch_pixels,
  2028. img_w, img_h);
  2029. return -EINVAL;
  2030. }
  2031. /*
  2032. * swap the scaler src width & height for inline-rotation 90
  2033. * comparison with Pixel-Extension, as PE is based on
  2034. * pre-rotation and QSEED is based on post-rotation
  2035. */
  2036. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  2037. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  2038. : pstate->scaler3_cfg.src_width[i];
  2039. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  2040. : pstate->scaler3_cfg.src_height[i];
  2041. /*
  2042. * Alpha plane can only be scaled using bilinear or pixel
  2043. * repeat/drop, src_width and src_height are only specified
  2044. * for Y and UV plane
  2045. */
  2046. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  2047. vert_req_pixels / pre_down_ratio_y !=
  2048. scaler_h)) {
  2049. SDE_ERROR_PLANE(psde,
  2050. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  2051. i, pstate->pixel_ext.roi_w[i],
  2052. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  2053. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  2054. return -EINVAL;
  2055. }
  2056. /*
  2057. * SSPP fetch , unpack output and QSEED3 input lines need
  2058. * to match for Y plane
  2059. */
  2060. if (i == 0 &&
  2061. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2062. BIT(SDE_DRM_DEINTERLACE)) &&
  2063. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  2064. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  2065. SDE_ERROR_PLANE(psde,
  2066. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  2067. i, pstate->pixel_ext.roi_w[i],
  2068. pstate->pixel_ext.roi_h[i],
  2069. pstate->scaler3_cfg.src_width[i],
  2070. pstate->scaler3_cfg.src_height[i],
  2071. src_w, src_h);
  2072. return -EINVAL;
  2073. }
  2074. }
  2075. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  2076. return 0;
  2077. }
  2078. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  2079. {
  2080. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  2081. }
  2082. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  2083. struct sde_plane_state *pstate, struct sde_rect *dst,
  2084. u32 src_w, u32 src_h)
  2085. {
  2086. int ret = 0;
  2087. u32 min_ratio_numer, min_ratio_denom;
  2088. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  2089. bool pd_x;
  2090. bool pd_y;
  2091. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  2092. return ret;
  2093. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  2094. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  2095. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  2096. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2097. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  2098. SDE_ERROR_PLANE(psde,
  2099. "hw does not support pre-downscale X: 0x%x\n",
  2100. psde->features);
  2101. ret = -EINVAL;
  2102. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  2103. SDE_ERROR_PLANE(psde,
  2104. "hw does not support pre-downscale Y: 0x%x\n",
  2105. psde->features);
  2106. ret = -EINVAL;
  2107. } else if (!min_ratio_numer || !min_ratio_denom) {
  2108. SDE_ERROR_PLANE(psde,
  2109. "min downscale ratio not set! %u / %u\n",
  2110. min_ratio_numer, min_ratio_denom);
  2111. ret = -EINVAL;
  2112. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2113. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2114. min_ratio_denom))) {
  2115. SDE_ERROR_PLANE(psde,
  2116. "failed min downscale-x check %u->%u, %u/%u\n",
  2117. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2118. ret = -EINVAL;
  2119. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2120. min_ratio_denom))) {
  2121. SDE_ERROR_PLANE(psde,
  2122. "failed min downscale-y check %u->%u, %u/%u\n",
  2123. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2124. ret = -EINVAL;
  2125. }
  2126. return ret;
  2127. }
  2128. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2129. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2130. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2131. u32 *max_numer_h, u32 *max_denom_h)
  2132. {
  2133. bool rotated, has_predown, default_scale;
  2134. const struct sde_sspp_sub_blks *sblk;
  2135. struct sde_hw_inline_pre_downscale_cfg *pd = NULL;
  2136. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2137. sblk = psde->pipe_sblk;
  2138. *max_numer_w = sblk->maxdwnscale;
  2139. *max_denom_w = 1;
  2140. *max_numer_h = sblk->maxdwnscale;
  2141. *max_denom_h = 1;
  2142. has_predown = _sde_plane_has_pre_downscale(psde);
  2143. if (has_predown)
  2144. pd = &pstate->pre_down;
  2145. default_scale = psde->debugfs_default_scale ||
  2146. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2147. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2148. /**
  2149. * Inline rotation has different max vertical downscaling limits since
  2150. * the source-width becomes the scaler's pre-downscaled source-height.
  2151. **/
  2152. if (rotated) {
  2153. if (pd != NULL && rt_client && has_predown) {
  2154. if (default_scale)
  2155. pd->pre_downscale_x_0 = (src_h >
  2156. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2157. *max_numer_h = pd->pre_downscale_x_0 ?
  2158. sblk->in_rot_maxdwnscale_rt_num :
  2159. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2160. *max_denom_h = pd->pre_downscale_x_0 ?
  2161. sblk->in_rot_maxdwnscale_rt_denom :
  2162. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2163. } else if (rt_client) {
  2164. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2165. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2166. } else {
  2167. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2168. }
  2169. }
  2170. }
  2171. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2172. struct sde_plane *psde, const struct sde_format *fmt,
  2173. struct sde_plane_state *pstate, struct sde_rect *src,
  2174. struct sde_rect *dst, u32 width, u32 height)
  2175. {
  2176. int ret = 0;
  2177. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2178. uint32_t scaler_src_w, scaler_src_h;
  2179. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2180. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2181. uint32_t max_upscale, max_linewidth;
  2182. bool inline_rotation, rt_client;
  2183. struct drm_crtc *crtc;
  2184. struct drm_crtc_state *new_cstate;
  2185. const struct sde_sspp_sub_blks *sblk;
  2186. if (!state || !state->state || !state->crtc) {
  2187. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2188. return -EINVAL;
  2189. }
  2190. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2191. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2192. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2193. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2194. /* with inline rotator, the source of the scaler is post-rotated */
  2195. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2196. if (inline_rotation) {
  2197. scaler_src_w = src_deci_h;
  2198. scaler_src_h = src_deci_w;
  2199. } else {
  2200. scaler_src_w = src_deci_w;
  2201. scaler_src_h = src_deci_h;
  2202. }
  2203. sblk = psde->pipe_sblk;
  2204. max_upscale = sblk->maxupscale;
  2205. if (inline_rotation)
  2206. max_linewidth = sblk->in_rot_maxheight;
  2207. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2208. max_linewidth = sblk->scaling_linewidth;
  2209. else
  2210. max_linewidth = sblk->maxlinewidth;
  2211. crtc = state->crtc;
  2212. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2213. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2214. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2215. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2216. &max_downscale_num_h, &max_downscale_denom_h);
  2217. /* decimation validation */
  2218. if ((deci_w || deci_h)
  2219. && ((deci_w > sblk->maxhdeciexp)
  2220. || (deci_h > sblk->maxvdeciexp))) {
  2221. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2222. ret = -EINVAL;
  2223. } else if ((deci_w || deci_h)
  2224. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2225. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2226. ret = -EINVAL;
  2227. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2228. ((src->w != dst->w) || (src->h != dst->h))) {
  2229. SDE_ERROR_PLANE(psde,
  2230. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2231. src->w, src->h, dst->w, dst->h);
  2232. ret = -EINVAL;
  2233. /* check scaler source width */
  2234. } else if (scaler_src_w > max_linewidth) {
  2235. SDE_ERROR_PLANE(psde,
  2236. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2237. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2238. ret = -E2BIG;
  2239. /* check max scaler capability */
  2240. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2241. ((scaler_src_h * max_upscale) < dst->h) ||
  2242. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2243. < scaler_src_w) ||
  2244. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2245. < scaler_src_h)) {
  2246. SDE_ERROR_PLANE(psde,
  2247. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2248. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2249. inline_rotation, max_downscale_num_w,
  2250. max_downscale_denom_w, max_downscale_num_h,
  2251. max_downscale_denom_h);
  2252. ret = -E2BIG;
  2253. /* check inline pre-downscale support */
  2254. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2255. pstate, dst, src_deci_w, src_deci_h)) {
  2256. ret = -EINVAL;
  2257. /* QSEED validation */
  2258. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2259. width, height, src->w, src->h,
  2260. deci_w, deci_h)) {
  2261. ret = -EINVAL;
  2262. }
  2263. return ret;
  2264. }
  2265. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2266. struct sde_plane_state *pstate, struct sde_rect *src,
  2267. const struct sde_format *fmt, int ret)
  2268. {
  2269. /* check excl rect configs */
  2270. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2271. struct sde_rect intersect;
  2272. /*
  2273. * Check exclusion rect against src rect.
  2274. * it must intersect with source rect.
  2275. */
  2276. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2277. if (intersect.w != pstate->excl_rect.w ||
  2278. intersect.h != pstate->excl_rect.h ||
  2279. SDE_FORMAT_IS_YUV(fmt)) {
  2280. SDE_ERROR_PLANE(psde,
  2281. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2282. pstate->excl_rect.x, pstate->excl_rect.y,
  2283. pstate->excl_rect.w, pstate->excl_rect.h,
  2284. src->x, src->y, src->w, src->h,
  2285. (char *)&fmt->base.pixel_format);
  2286. ret = -EINVAL;
  2287. }
  2288. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2289. pstate->excl_rect.x, pstate->excl_rect.y,
  2290. pstate->excl_rect.w, pstate->excl_rect.h);
  2291. }
  2292. return ret;
  2293. }
  2294. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2295. struct drm_plane_state *state)
  2296. {
  2297. struct sde_kms *sde_kms;
  2298. struct sde_splash_display *splash_display;
  2299. int i;
  2300. sde_kms = _sde_plane_get_kms(&psde->base);
  2301. if (!sde_kms || !state->crtc)
  2302. return 0;
  2303. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2304. splash_display = &sde_kms->splash_data.splash_display[i];
  2305. if (splash_display && splash_display->cont_splash_enabled &&
  2306. splash_display->encoder &&
  2307. state->crtc != splash_display->encoder->crtc) {
  2308. struct sde_sspp_index_info *pipe_info = &splash_display->pipe_info;
  2309. if (test_bit(psde->pipe, pipe_info->pipes) ||
  2310. test_bit(psde->pipe, pipe_info->virt_pipes)) {
  2311. SDE_ERROR_PLANE(psde, "pipe:%d used in cont-splash on crtc:%d\n",
  2312. psde->pipe,
  2313. splash_display->encoder->crtc->base.id);
  2314. return -EINVAL;
  2315. }
  2316. }
  2317. }
  2318. return 0;
  2319. }
  2320. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2321. const struct sde_format *fmt,
  2322. struct sde_rect src, struct sde_rect dst,
  2323. u32 width, u32 height)
  2324. {
  2325. int ret = 0;
  2326. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2327. if (SDE_FORMAT_IS_YUV(fmt) &&
  2328. (!(psde->features & SDE_SSPP_SCALER) ||
  2329. !(psde->features & (BIT(SDE_SSPP_CSC)
  2330. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2331. SDE_ERROR_PLANE(psde,
  2332. "plane doesn't have scaler/csc for yuv\n");
  2333. ret = -EINVAL;
  2334. /* check src bounds */
  2335. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2336. src.w < min_src_size || src.h < min_src_size ||
  2337. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2338. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2339. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2340. src.x, src.y, src.w, src.h);
  2341. ret = -E2BIG;
  2342. /* valid yuv image */
  2343. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2344. (src.w & 0x1) || (src.h & 0x1))) {
  2345. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2346. src.x, src.y, src.w, src.h);
  2347. ret = -EINVAL;
  2348. /* min dst support */
  2349. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2350. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2351. dst.x, dst.y, dst.w, dst.h);
  2352. ret = -EINVAL;
  2353. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2354. !psde->catalog->ubwc_rev) {
  2355. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2356. ret = -EINVAL;
  2357. }
  2358. return ret;
  2359. }
  2360. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2361. struct drm_plane_state *state)
  2362. {
  2363. int ret = 0;
  2364. struct sde_plane *psde;
  2365. struct sde_plane_state *pstate;
  2366. const struct msm_format *msm_fmt;
  2367. const struct sde_format *fmt;
  2368. struct sde_rect src, dst;
  2369. bool q16_data = true;
  2370. struct drm_framebuffer *fb;
  2371. u32 width;
  2372. u32 height;
  2373. psde = to_sde_plane(plane);
  2374. pstate = to_sde_plane_state(state);
  2375. if (!psde->pipe_sblk) {
  2376. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2377. return -EINVAL;
  2378. }
  2379. /* src values are in Q16 fixed point, convert to integer */
  2380. POPULATE_RECT(&src, state->src_x, state->src_y,
  2381. state->src_w, state->src_h, q16_data);
  2382. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2383. state->crtc_h, !q16_data);
  2384. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2385. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2386. if (!sde_plane_enabled(state))
  2387. goto modeset_update;
  2388. fb = state->fb;
  2389. width = fb ? state->fb->width : 0x0;
  2390. height = fb ? state->fb->height : 0x0;
  2391. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2392. plane->base.id,
  2393. pstate->rotation,
  2394. width, height,
  2395. fb ? (char *) &state->fb->format->format : 0x0,
  2396. fb ? state->fb->modifier : 0x0);
  2397. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2398. state->src_w >> 16, state->src_h >> 16,
  2399. state->src_x >> 16, state->src_y >> 16,
  2400. state->crtc_w, state->crtc_h,
  2401. state->crtc_x, state->crtc_y);
  2402. msm_fmt = msm_framebuffer_format(fb);
  2403. fmt = to_sde_format(msm_fmt);
  2404. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2405. height);
  2406. if (ret)
  2407. return ret;
  2408. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2409. &src, &dst, width, height);
  2410. if (ret)
  2411. return ret;
  2412. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2413. &src, fmt, ret);
  2414. if (ret)
  2415. return ret;
  2416. ret = _sde_plane_validate_shared_crtc(psde, state);
  2417. if (ret)
  2418. return ret;
  2419. pstate->const_alpha_en = fmt->alpha_enable &&
  2420. (SDE_DRM_BLEND_OP_OPAQUE !=
  2421. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2422. (pstate->stage != SDE_STAGE_0);
  2423. modeset_update:
  2424. if (!ret)
  2425. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2426. state, plane->state);
  2427. return ret;
  2428. }
  2429. static int _sde_plane_atomic_check(struct drm_plane *plane,
  2430. struct drm_plane_state *state)
  2431. {
  2432. int ret = 0;
  2433. struct sde_plane *psde;
  2434. struct sde_plane_state *pstate;
  2435. psde = to_sde_plane(plane);
  2436. pstate = to_sde_plane_state(state);
  2437. SDE_DEBUG_PLANE(psde, "\n");
  2438. ret = sde_plane_rot_atomic_check(plane, state);
  2439. if (ret)
  2440. goto exit;
  2441. ret = sde_plane_sspp_atomic_check(plane, state);
  2442. exit:
  2443. return ret;
  2444. }
  2445. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2446. static int sde_plane_atomic_check(struct drm_plane *plane,
  2447. struct drm_atomic_state *atomic_state)
  2448. {
  2449. struct drm_plane_state *state = NULL;
  2450. if (!plane || !atomic_state) {
  2451. SDE_ERROR("invalid arg(s), plane %d atomic_state %d\n",
  2452. !plane, !atomic_state);
  2453. return -EINVAL;
  2454. }
  2455. state = drm_atomic_get_new_plane_state(atomic_state, plane);
  2456. return _sde_plane_atomic_check(plane, state);
  2457. }
  2458. #else
  2459. static int sde_plane_atomic_check(struct drm_plane *plane,
  2460. struct drm_plane_state *state)
  2461. {
  2462. if (!plane || !state) {
  2463. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2464. !plane, !state);
  2465. return -EINVAL;
  2466. }
  2467. return _sde_plane_atomic_check(plane, state);
  2468. }
  2469. #endif
  2470. void sde_plane_flush(struct drm_plane *plane)
  2471. {
  2472. struct sde_plane *psde;
  2473. struct sde_plane_state *pstate;
  2474. if (!plane || !plane->state) {
  2475. SDE_ERROR("invalid plane\n");
  2476. return;
  2477. }
  2478. psde = to_sde_plane(plane);
  2479. pstate = to_sde_plane_state(plane->state);
  2480. /*
  2481. * These updates have to be done immediately before the plane flush
  2482. * timing, and may not be moved to the atomic_update/mode_set functions.
  2483. */
  2484. if (psde->is_error)
  2485. /* force white frame with 100% alpha pipe output on error */
  2486. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2487. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2488. /* force 100% alpha */
  2489. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2490. else if (psde->pipe_hw && pstate->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2491. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, pstate->csc_ptr);
  2492. /* flag h/w flush complete */
  2493. if (plane->state)
  2494. pstate->pending = false;
  2495. }
  2496. /**
  2497. * sde_plane_set_error: enable/disable error condition
  2498. * @plane: pointer to drm_plane structure
  2499. */
  2500. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2501. {
  2502. struct sde_plane *psde;
  2503. if (!plane)
  2504. return;
  2505. psde = to_sde_plane(plane);
  2506. psde->is_error = error;
  2507. }
  2508. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2509. struct sde_plane_state *pstate)
  2510. {
  2511. struct drm_plane_state *state = psde->base.state;
  2512. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2513. struct sde_hw_pipe_sc_cfg *cfg = &pstate->sc_cfg;
  2514. bool prev_rd_en = cfg->rd_en;
  2515. u32 cache_flag, cache_rd_type, cache_wr_type;
  2516. enum sde_sys_cache_state cache_state;
  2517. if (!state->fb) {
  2518. SDE_ERROR("invalid fb on plane %d\n", DRMID(&psde->base));
  2519. return;
  2520. }
  2521. cache_state = pstate->static_cache_state;
  2522. msm_framebuffer_get_cache_hint(state->fb, &cache_flag, &cache_rd_type, &cache_wr_type);
  2523. cfg->rd_en = false;
  2524. cfg->rd_scid = 0x0;
  2525. cfg->flags = SYS_CACHE_EN_FLAG | SYS_CACHE_SCID;
  2526. /*
  2527. * if condition handles static display legacy path, where internal state machine is
  2528. * transitioning the "cache_state" variable to program the LLCC cache through
  2529. * SSPP hardware using SDE_SYS_CACHE_DISP SCID.
  2530. * else condition handles static display and IWE path, were the frame is programmed to
  2531. * LLCC cache through WB/CWB path and read back by SSPP hardware. The FB cache hints are
  2532. * used to pass information on which SCID to use during read path and LLCC cache to
  2533. * keep active.
  2534. */
  2535. if (test_bit(SDE_SYS_CACHE_DISP, psde->catalog->sde_sys_cache_type_map)
  2536. && ((cache_state == CACHE_STATE_FRAME_WRITE)
  2537. || (cache_state == CACHE_STATE_FRAME_READ))) {
  2538. cfg->type = pstate->static_cache_type;
  2539. cfg->rd_en = true;
  2540. cfg->rd_scid = sc_cfg[cfg->type].llcc_scid;
  2541. if (test_bit(SDE_FEATURE_SYS_CACHE_NSE, psde->catalog->features)) {
  2542. cfg->rd_noallocate = false;
  2543. pstate->static_cache_state = CACHE_STATE_NORMAL;
  2544. } else {
  2545. cfg->rd_noallocate = (cache_state == CACHE_STATE_FRAME_READ);
  2546. }
  2547. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2548. } else if (test_bit(cache_rd_type, psde->catalog->sde_sys_cache_type_map) && cache_flag) {
  2549. cfg->rd_en = true;
  2550. cfg->type = cache_rd_type;
  2551. cfg->rd_scid = sc_cfg[cache_rd_type].llcc_scid;
  2552. cfg->rd_noallocate = false;
  2553. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2554. cache_flag = MSM_FB_CACHE_READ_EN;
  2555. msm_framebuffer_set_cache_hint(state->fb, cache_flag, cache_rd_type, cache_wr_type);
  2556. }
  2557. if (!cfg->rd_en && !prev_rd_en)
  2558. return;
  2559. SDE_EVT32(DRMID(&psde->base), cfg->type, cfg->rd_scid, cfg->rd_en, cfg->rd_noallocate,
  2560. cfg->flags, cache_state, cache_flag, cache_rd_type, cache_wr_type,
  2561. state->fb->base.id);
  2562. psde->pipe_hw->ops.setup_sys_cache(psde->pipe_hw, cfg);
  2563. }
  2564. void sde_plane_static_img_control(struct drm_plane *plane,
  2565. enum sde_sys_cache_state state, enum sde_sys_cache_type type)
  2566. {
  2567. struct sde_plane *psde;
  2568. struct sde_plane_state *pstate;
  2569. if (!plane || !plane->state) {
  2570. SDE_ERROR("invalid plane\n");
  2571. return;
  2572. }
  2573. psde = to_sde_plane(plane);
  2574. pstate = to_sde_plane_state(plane->state);
  2575. pstate->static_cache_state = state;
  2576. pstate->static_cache_type = type;
  2577. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2578. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2579. }
  2580. static void _sde_plane_map_prop_to_dirty_bits(void)
  2581. {
  2582. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2583. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2584. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2585. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2586. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2587. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2588. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2589. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2590. plane_prop_array[PLANE_PROP_ZPOS] =
  2591. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2592. plane_prop_array[PLANE_PROP_UBWC_STATS_ROI] =
  2593. SDE_PLANE_DIRTY_RECTS;
  2594. plane_prop_array[PLANE_PROP_CSC_V1] =
  2595. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2596. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2597. SDE_PLANE_DIRTY_FORMAT;
  2598. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2599. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2600. SDE_PLANE_DIRTY_ALL;
  2601. /* no special action required */
  2602. plane_prop_array[PLANE_PROP_INFO] =
  2603. plane_prop_array[PLANE_PROP_ALPHA] =
  2604. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2605. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2606. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2607. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2608. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2609. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2610. SDE_PLANE_DIRTY_PERF;
  2611. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2612. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2613. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2614. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2615. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2616. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2617. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2618. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2619. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2620. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2621. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2622. SDE_PLANE_DIRTY_ALL;
  2623. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2624. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2625. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2626. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2627. plane_prop_array[PLANE_PROP_UCSC_UNMULT] = SDE_PLANE_DIRTY_UCSC_UNMULT;
  2628. plane_prop_array[PLANE_PROP_UCSC_IGC] = SDE_PLANE_DIRTY_UCSC_IGC;
  2629. plane_prop_array[PLANE_PROP_UCSC_CSC] = SDE_PLANE_DIRTY_UCSC_CSC;
  2630. plane_prop_array[PLANE_PROP_UCSC_GC] = SDE_PLANE_DIRTY_UCSC_GC;
  2631. plane_prop_array[PLANE_PROP_UCSC_ALPHA_DITHER] = SDE_PLANE_DIRTY_UCSC_ALPHA_DITHER;
  2632. }
  2633. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2634. struct sde_rect *src, struct sde_rect *dst)
  2635. {
  2636. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2637. u32 downscale = (src->h * 1000)/dst->h;
  2638. return (downscale > max_downscale) ? false : true;
  2639. }
  2640. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2641. struct sde_plane *psde, struct sde_plane_state *pstate,
  2642. struct sde_rect *src, struct sde_rect *dst)
  2643. {
  2644. struct sde_hw_pipe_uidle_cfg cfg;
  2645. u32 line_time = sde_crtc_get_line_time(crtc);
  2646. u32 fal1_target_idle_time_ns =
  2647. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2648. u32 fal10_target_idle_time_ns =
  2649. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2650. u32 fal10_threshold =
  2651. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2652. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2653. fal1_target_idle_time_ns) {
  2654. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2655. cfg.fal10_threshold = fal10_threshold;
  2656. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2657. cfg.fal1_threshold = min(1 +
  2658. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2659. psde->catalog->uidle_cfg.fal1_max_threshold);
  2660. cfg.fal_allowed_threshold = fal10_threshold +
  2661. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2662. cfg.fill_level_scale = 0;
  2663. /*
  2664. * if uidle fill scale is supported, determing the scale value
  2665. * and adjust fal10 thresholds to their scaled values.
  2666. * fal1 thresholds and fal_allowed are not scaled.
  2667. */
  2668. if (psde->pipe_hw->ops.setup_uidle_fill_scale) {
  2669. u32 fl_require0 = psde->catalog->qos_target_time_ns / line_time * 2;
  2670. u32 fl_require = max(fal10_threshold * 1000, fl_require0);
  2671. u32 fl_scale = fl_require / fal10_threshold;
  2672. u32 fal10_threshold_noscale;
  2673. cfg.fill_level_scale = (fl_scale <= 1) ? 0 : (32 / fl_scale);
  2674. if (cfg.fill_level_scale) {
  2675. fal10_threshold_noscale = fal10_threshold *
  2676. 32/cfg.fill_level_scale;
  2677. cfg.fal_allowed_threshold = fal10_threshold_noscale +
  2678. (fal10_target_idle_time_ns * 1000 / line_time * 2) / 1000;
  2679. }
  2680. }
  2681. } else {
  2682. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2683. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2684. fal1_target_idle_time_ns);
  2685. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2686. }
  2687. SDE_DEBUG_PLANE(psde,
  2688. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d fill_scale=%d\n",
  2689. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2690. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2691. cfg.fill_level_scale);
  2692. SDE_DEBUG_PLANE(psde,
  2693. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2694. line_time, fal1_target_idle_time_ns,
  2695. fal10_target_idle_time_ns,
  2696. psde->catalog->uidle_cfg.max_dwnscale);
  2697. SDE_EVT32_VERBOSE(cfg.enable,
  2698. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2699. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2700. cfg.fill_level_scale, psde->catalog->uidle_cfg.max_dwnscale);
  2701. if (psde->pipe_hw->ops.setup_uidle_fill_scale)
  2702. psde->pipe_hw->ops.setup_uidle_fill_scale(psde->pipe_hw, &cfg);
  2703. psde->pipe_hw->ops.setup_uidle(
  2704. psde->pipe_hw, &cfg,
  2705. pstate->multirect_index);
  2706. }
  2707. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2708. struct sde_plane_state *pstate)
  2709. {
  2710. bool enable = false;
  2711. int mode = sde_plane_get_property(pstate,
  2712. PLANE_PROP_FB_TRANSLATION_MODE);
  2713. if ((mode == SDE_DRM_FB_SEC) ||
  2714. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2715. enable = true;
  2716. /* update secure session flag */
  2717. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2718. pstate->multirect_index,
  2719. enable);
  2720. }
  2721. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2722. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2723. {
  2724. const struct sde_format *fmt;
  2725. const struct msm_format *msm_fmt;
  2726. struct sde_plane *psde;
  2727. struct drm_plane_state *state;
  2728. struct sde_plane_state *pstate;
  2729. struct sde_rect src, dst;
  2730. const struct sde_rect *crtc_roi;
  2731. bool q16_data = true;
  2732. int idx;
  2733. psde = to_sde_plane(plane);
  2734. state = plane->state;
  2735. pstate = to_sde_plane_state(state);
  2736. msm_fmt = msm_framebuffer_format(fb);
  2737. if (!msm_fmt) {
  2738. SDE_ERROR("crtc%d plane%d: null format\n",
  2739. DRMID(crtc), DRMID(plane));
  2740. return;
  2741. }
  2742. fmt = to_sde_format(msm_fmt);
  2743. POPULATE_RECT(&src, state->src_x, state->src_y,
  2744. state->src_w, state->src_h, q16_data);
  2745. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2746. state->crtc_w, state->crtc_h, !q16_data);
  2747. SDE_DEBUG_PLANE(psde,
  2748. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2749. fb->base.id, src.x, src.y, src.w, src.h,
  2750. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2751. (char *)&fmt->base.pixel_format,
  2752. SDE_FORMAT_IS_UBWC(fmt));
  2753. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2754. BIT(SDE_DRM_DEINTERLACE)) {
  2755. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2756. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2757. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2758. src.h /= 2;
  2759. src.y = DIV_ROUND_UP(src.y, 2);
  2760. src.y &= ~0x1;
  2761. }
  2762. /*
  2763. * adjust layer mixer position of the sspp in the presence
  2764. * of a partial update to the active lm origin
  2765. */
  2766. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2767. dst.x -= crtc_roi->x;
  2768. dst.y -= crtc_roi->y;
  2769. /* check for UIDLE */
  2770. if (psde->pipe_hw->ops.setup_uidle)
  2771. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2772. psde->pipe_cfg.src_rect = src;
  2773. psde->pipe_cfg.dst_rect = dst;
  2774. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2775. _sde_plane_setup_panel_stacking(psde, pstate);
  2776. /* check for color fill */
  2777. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2778. PLANE_PROP_COLOR_FILL);
  2779. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2780. /* skip remaining processing on color fill */
  2781. pstate->dirty = 0x0;
  2782. } else if (psde->pipe_hw->ops.setup_rects) {
  2783. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2784. &psde->pipe_cfg,
  2785. pstate->multirect_index);
  2786. }
  2787. if (psde->pipe_hw->ops.setup_pe &&
  2788. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2789. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2790. &psde->pixel_ext);
  2791. /**
  2792. * when programmed in multirect mode, scalar block will be
  2793. * bypassed. Still we need to update alpha and bitwidth
  2794. * ONLY for RECT0
  2795. */
  2796. if (psde->pipe_hw->ops.setup_scaler &&
  2797. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2798. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2799. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2800. &psde->pipe_cfg, &psde->pixel_ext,
  2801. &psde->scaler3_cfg);
  2802. }
  2803. /* update excl rect */
  2804. if (psde->pipe_hw->ops.setup_excl_rect)
  2805. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2806. &pstate->excl_rect,
  2807. pstate->multirect_index);
  2808. /* enable multirect config of corresponding rect */
  2809. if (psde->pipe_hw->ops.update_multirect)
  2810. psde->pipe_hw->ops.update_multirect(
  2811. psde->pipe_hw,
  2812. true,
  2813. pstate->multirect_index,
  2814. pstate->multirect_mode);
  2815. /* update line insertion */
  2816. if (pstate->lineinsertion_feature && psde->pipe_hw->ops.setup_line_insertion)
  2817. psde->pipe_hw->ops.setup_line_insertion(psde->pipe_hw,
  2818. pstate->multirect_index,
  2819. &pstate->line_insertion_cfg);
  2820. }
  2821. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2822. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2823. {
  2824. uint32_t src_flags = 0;
  2825. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2826. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2827. src_flags |= SDE_SSPP_FLIP_LR;
  2828. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2829. src_flags |= SDE_SSPP_FLIP_UD;
  2830. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2831. src_flags |= SDE_SSPP_ROT_90;
  2832. /* update format */
  2833. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2834. pstate->const_alpha_en, src_flags,
  2835. pstate->multirect_index);
  2836. if (psde->pipe_hw->ops.setup_cdp) {
  2837. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2838. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2839. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2840. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2841. cdp_cfg->ubwc_meta_enable =
  2842. SDE_FORMAT_IS_UBWC(fmt);
  2843. cdp_cfg->tile_amortize_enable =
  2844. SDE_FORMAT_IS_UBWC(fmt) ||
  2845. SDE_FORMAT_IS_TILE(fmt);
  2846. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2847. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2848. pstate->multirect_index);
  2849. }
  2850. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2851. /* update csc */
  2852. if (SDE_FORMAT_IS_YUV(fmt))
  2853. _sde_plane_setup_csc(psde, pstate);
  2854. else
  2855. pstate->csc_ptr = 0;
  2856. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2857. uint32_t pma_mode = 0;
  2858. if (fmt->alpha_enable)
  2859. pma_mode = (uint32_t) sde_plane_get_property(
  2860. pstate, PLANE_PROP_INVERSE_PMA);
  2861. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2862. pstate->multirect_index, pma_mode);
  2863. }
  2864. if (psde->pipe_hw->ops.setup_dgm_csc)
  2865. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2866. pstate->multirect_index, pstate->csc_usr_ptr);
  2867. if (psde->pipe_hw->ops.set_ubwc_stats_roi) {
  2868. if (SDE_FORMAT_IS_UBWC(fmt) && !SDE_FORMAT_IS_YUV(fmt))
  2869. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2870. pstate->multirect_index, &pstate->ubwc_stats_roi);
  2871. else
  2872. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2873. pstate->multirect_index, NULL);
  2874. }
  2875. }
  2876. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2877. {
  2878. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2879. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2880. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2881. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2882. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2883. &psde->sharp_cfg);
  2884. }
  2885. static void _sde_plane_update_properties(struct drm_plane *plane,
  2886. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2887. {
  2888. uint32_t nplanes;
  2889. const struct msm_format *msm_fmt;
  2890. const struct sde_format *fmt;
  2891. struct sde_plane *psde;
  2892. struct drm_plane_state *state;
  2893. struct sde_plane_state *pstate;
  2894. psde = to_sde_plane(plane);
  2895. state = plane->state;
  2896. pstate = to_sde_plane_state(state);
  2897. if (!pstate) {
  2898. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2899. return;
  2900. }
  2901. msm_fmt = msm_framebuffer_format(fb);
  2902. if (!msm_fmt) {
  2903. SDE_ERROR("crtc%d plane%d: null format\n",
  2904. DRMID(crtc), DRMID(plane));
  2905. return;
  2906. }
  2907. fmt = to_sde_format(msm_fmt);
  2908. nplanes = fmt->num_planes;
  2909. /* update secure session flag */
  2910. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2911. _sde_plane_update_secure_session(psde, pstate);
  2912. /* update roi config */
  2913. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2914. _sde_plane_update_roi_config(plane, crtc, fb);
  2915. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2916. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2917. psde->pipe_hw->ops.setup_format)
  2918. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2919. sde_color_process_plane_setup(plane);
  2920. /* update sharpening */
  2921. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2922. psde->pipe_hw->ops.setup_sharpening)
  2923. _sde_plane_update_sharpening(psde);
  2924. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2925. SDE_PLANE_DIRTY_FORMAT))
  2926. _sde_plane_set_qos_lut(plane, crtc, fb);
  2927. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2928. _sde_plane_set_ot_limit(plane, crtc);
  2929. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2930. _sde_plane_set_ts_prefill(plane, pstate);
  2931. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2932. _sde_plane_set_qos_remap(plane);
  2933. /* clear dirty */
  2934. pstate->dirty = 0x0;
  2935. }
  2936. static void _sde_plane_check_lut_dirty(struct sde_plane *psde,
  2937. struct sde_plane_state *pstate)
  2938. {
  2939. /**
  2940. * Valid configuration if scaler is not enabled or
  2941. * lut flag is set
  2942. */
  2943. if (pstate->scaler3_cfg.lut_flag || !pstate->scaler3_cfg.enable)
  2944. return;
  2945. pstate->scaler3_cfg.lut_flag = psde->cached_lut_flag;
  2946. SDE_EVT32(DRMID(&psde->base), pstate->scaler3_cfg.lut_flag, SDE_EVTLOG_ERROR);
  2947. }
  2948. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2949. struct drm_plane_state *old_state)
  2950. {
  2951. struct sde_plane *psde;
  2952. struct drm_plane_state *state;
  2953. struct sde_plane_state *pstate;
  2954. struct sde_plane_state *old_pstate;
  2955. struct drm_crtc *crtc;
  2956. struct drm_framebuffer *fb;
  2957. int idx;
  2958. int dirty_prop_flag;
  2959. bool is_rt;
  2960. if (!plane) {
  2961. SDE_ERROR("invalid plane\n");
  2962. return -EINVAL;
  2963. } else if (!plane->state) {
  2964. SDE_ERROR("invalid plane state\n");
  2965. return -EINVAL;
  2966. } else if (!old_state) {
  2967. SDE_ERROR("invalid old state\n");
  2968. return -EINVAL;
  2969. }
  2970. psde = to_sde_plane(plane);
  2971. state = plane->state;
  2972. pstate = to_sde_plane_state(state);
  2973. old_pstate = to_sde_plane_state(old_state);
  2974. crtc = state->crtc;
  2975. fb = state->fb;
  2976. if (!crtc || !fb) {
  2977. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2978. !crtc, !fb);
  2979. return -EINVAL;
  2980. }
  2981. SDE_DEBUG(
  2982. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2983. plane->base.id,
  2984. state->fb->width, state->fb->height,
  2985. (char *) &state->fb->format->format,
  2986. state->fb->modifier,
  2987. state->src_w >> 16, state->src_h >> 16,
  2988. state->src_x >> 16, state->src_y >> 16,
  2989. pstate->rotation,
  2990. state->crtc_w, state->crtc_h,
  2991. state->crtc_x, state->crtc_y);
  2992. /* Caching the valid lut flag in sde plane */
  2993. if (pstate->scaler3_cfg.enable && pstate->scaler3_cfg.lut_flag)
  2994. psde->cached_lut_flag = pstate->scaler3_cfg.lut_flag;
  2995. /* force reprogramming of all the parameters, if the flag is set */
  2996. if (psde->revalidate) {
  2997. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2998. plane->base.id);
  2999. _sde_plane_check_lut_dirty(psde, pstate);
  3000. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  3001. psde->revalidate = false;
  3002. }
  3003. /* determine what needs to be refreshed */
  3004. mutex_lock(&psde->property_info.property_lock);
  3005. while ((idx = msm_property_pop_dirty(&psde->property_info,
  3006. &pstate->property_state)) >= 0) {
  3007. dirty_prop_flag = plane_prop_array[idx];
  3008. pstate->dirty |= dirty_prop_flag;
  3009. }
  3010. mutex_unlock(&psde->property_info.property_lock);
  3011. /**
  3012. * since plane_atomic_check is invoked before crtc_atomic_check
  3013. * in the commit sequence, all the parameters for updating the
  3014. * plane dirty flag will not be available during
  3015. * plane_atomic_check as some features params are updated
  3016. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  3017. * before sspp update.
  3018. */
  3019. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  3020. old_state);
  3021. /* re-program the output rects always if partial update roi changed */
  3022. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  3023. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  3024. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  3025. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  3026. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  3027. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  3028. if (is_rt != psde->is_rt_pipe || crtc->state->mode_changed) {
  3029. psde->is_rt_pipe = is_rt;
  3030. psde->wb_usage_type = psde->is_rt_pipe ? 0 : sde_crtc_get_wb_usage_type(crtc);
  3031. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  3032. }
  3033. /* early out if nothing dirty */
  3034. if (!pstate->dirty)
  3035. return 0;
  3036. pstate->pending = true;
  3037. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3038. _sde_plane_update_properties(plane, crtc, fb);
  3039. return 0;
  3040. }
  3041. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  3042. struct drm_plane_state *old_state)
  3043. {
  3044. struct sde_plane *psde;
  3045. struct drm_plane_state *state;
  3046. struct sde_plane_state *pstate;
  3047. u32 multirect_index = SDE_SSPP_RECT_0;
  3048. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  3049. u32 blend_type;
  3050. if (!plane) {
  3051. SDE_ERROR("invalid plane\n");
  3052. return;
  3053. } else if (!plane->state) {
  3054. SDE_ERROR("invalid plane state\n");
  3055. return;
  3056. } else if (!old_state) {
  3057. SDE_ERROR("invalid old state\n");
  3058. return;
  3059. }
  3060. psde = to_sde_plane(plane);
  3061. state = plane->state;
  3062. pstate = to_sde_plane_state(state);
  3063. blend_type = sde_plane_get_property(pstate,
  3064. PLANE_PROP_BLEND_OP);
  3065. /* some of the color features are dependent on plane with skip blend.
  3066. * if skip blend plane is being disabled, we need to disable color properties.
  3067. */
  3068. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  3069. skip_blend_plane.valid_plane = false;
  3070. skip_blend_plane.plane = SSPP_NONE;
  3071. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  3072. sde_crtc_disable_cp_features(old_state->crtc);
  3073. }
  3074. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  3075. pstate->multirect_mode);
  3076. pstate->pending = true;
  3077. pstate->static_cache_state = CACHE_STATE_DISABLED;
  3078. if (is_sde_plane_virtual(plane))
  3079. multirect_index = SDE_SSPP_RECT_1;
  3080. /* disable multirect config of corresponding rect */
  3081. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  3082. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  3083. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  3084. }
  3085. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3086. static void _sde_plane_atomic_update(struct drm_plane *plane,
  3087. struct drm_plane_state *old_state)
  3088. #else
  3089. static void sde_plane_atomic_update(struct drm_plane *plane,
  3090. struct drm_plane_state *old_state)
  3091. #endif
  3092. {
  3093. struct sde_plane *psde;
  3094. struct drm_plane_state *state;
  3095. if (!plane) {
  3096. SDE_ERROR("invalid plane\n");
  3097. return;
  3098. } else if (!plane->state) {
  3099. SDE_ERROR("invalid plane state\n");
  3100. return;
  3101. }
  3102. psde = to_sde_plane(plane);
  3103. psde->is_error = false;
  3104. state = plane->state;
  3105. SDE_DEBUG_PLANE(psde, "\n");
  3106. if (!sde_plane_enabled(state)) {
  3107. _sde_plane_atomic_disable(plane, old_state);
  3108. } else {
  3109. int ret;
  3110. ret = sde_plane_sspp_atomic_update(plane, old_state);
  3111. /* atomic_check should have ensured that this doesn't fail */
  3112. WARN_ON(ret < 0);
  3113. }
  3114. }
  3115. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3116. static void sde_plane_atomic_update(struct drm_plane *plane,
  3117. struct drm_atomic_state *atomic_state)
  3118. {
  3119. struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(atomic_state, plane);
  3120. _sde_plane_atomic_update(plane, old_state);
  3121. }
  3122. #endif
  3123. void sde_plane_restore(struct drm_plane *plane)
  3124. {
  3125. struct sde_plane *psde;
  3126. if (!plane || !plane->state) {
  3127. SDE_ERROR("invalid plane\n");
  3128. return;
  3129. }
  3130. psde = to_sde_plane(plane);
  3131. /*
  3132. * Revalidate is only true here if idle PC occurred and
  3133. * there is no plane state update in current commit cycle.
  3134. */
  3135. if (!psde->revalidate)
  3136. return;
  3137. SDE_DEBUG_PLANE(psde, "\n");
  3138. /* last plane state is same as current state */
  3139. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3140. _sde_plane_atomic_update(plane, plane->state);
  3141. #else
  3142. sde_plane_atomic_update(plane, plane->state);
  3143. #endif
  3144. }
  3145. bool sde_plane_is_cache_required(struct drm_plane *plane,
  3146. enum sde_sys_cache_type type)
  3147. {
  3148. struct sde_plane_state *pstate;
  3149. u32 cache_flag, cache_rd_type, cache_wr_type;
  3150. if (!plane || !plane->state) {
  3151. SDE_ERROR("invalid plane\n");
  3152. return false;
  3153. }
  3154. pstate = to_sde_plane_state(plane->state);
  3155. msm_framebuffer_get_cache_hint(plane->state->fb, &cache_flag, &cache_rd_type,
  3156. &cache_wr_type);
  3157. /* check if llcc is required for the plane */
  3158. if (pstate->sc_cfg.rd_en && ((pstate->sc_cfg.type == type)
  3159. || (cache_flag && (cache_rd_type == type))
  3160. || (cache_flag && (cache_wr_type == type)))) {
  3161. SDE_EVT32_VERBOSE(DRMID(plane), type, pstate->sc_cfg.rd_en, pstate->sc_cfg.type,
  3162. cache_flag, cache_rd_type, cache_wr_type,
  3163. plane->state->fb->base.id);
  3164. return true;
  3165. }
  3166. return false;
  3167. }
  3168. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  3169. {
  3170. char feature_name[256];
  3171. if (psde->pipe_sblk->maxhdeciexp) {
  3172. msm_property_install_range(&psde->property_info,
  3173. "h_decimate", 0x0, 0,
  3174. psde->pipe_sblk->maxhdeciexp, 0,
  3175. PLANE_PROP_H_DECIMATE);
  3176. }
  3177. if (psde->pipe_sblk->maxvdeciexp) {
  3178. msm_property_install_range(&psde->property_info,
  3179. "v_decimate", 0x0, 0,
  3180. psde->pipe_sblk->maxvdeciexp, 0,
  3181. PLANE_PROP_V_DECIMATE);
  3182. }
  3183. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  3184. msm_property_install_range(
  3185. &psde->property_info, "scaler_v2",
  3186. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3187. msm_property_install_blob(&psde->property_info,
  3188. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  3189. msm_property_install_blob(&psde->property_info,
  3190. "lut_cir", 0,
  3191. PLANE_PROP_SCALER_LUT_CIR);
  3192. msm_property_install_blob(&psde->property_info,
  3193. "lut_sep", 0,
  3194. PLANE_PROP_SCALER_LUT_SEP);
  3195. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  3196. msm_property_install_range(
  3197. &psde->property_info, "scaler_v2",
  3198. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3199. msm_property_install_blob(&psde->property_info,
  3200. "lut_sep", 0,
  3201. PLANE_PROP_SCALER_LUT_SEP);
  3202. } else if (psde->features & SDE_SSPP_SCALER) {
  3203. msm_property_install_range(
  3204. &psde->property_info, "scaler_v1", 0x0,
  3205. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  3206. }
  3207. if (psde->features & BIT(SDE_SSPP_CSC) ||
  3208. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  3209. msm_property_install_volatile_range(
  3210. &psde->property_info, "csc_v1", 0x0,
  3211. 0, ~0, 0, PLANE_PROP_CSC_V1);
  3212. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  3213. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3214. "SDE_SSPP_HUE_V",
  3215. psde->pipe_sblk->hsic_blk.version >> 16);
  3216. msm_property_install_range(&psde->property_info,
  3217. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3218. PLANE_PROP_HUE_ADJUST);
  3219. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3220. "SDE_SSPP_SATURATION_V",
  3221. psde->pipe_sblk->hsic_blk.version >> 16);
  3222. msm_property_install_range(&psde->property_info,
  3223. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3224. PLANE_PROP_SATURATION_ADJUST);
  3225. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3226. "SDE_SSPP_VALUE_V",
  3227. psde->pipe_sblk->hsic_blk.version >> 16);
  3228. msm_property_install_range(&psde->property_info,
  3229. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3230. PLANE_PROP_VALUE_ADJUST);
  3231. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3232. "SDE_SSPP_CONTRAST_V",
  3233. psde->pipe_sblk->hsic_blk.version >> 16);
  3234. msm_property_install_range(&psde->property_info,
  3235. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3236. PLANE_PROP_CONTRAST_ADJUST);
  3237. }
  3238. }
  3239. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3240. struct sde_kms_info *info)
  3241. {
  3242. char feature_name[256];
  3243. bool is_master = !psde->is_virtual;
  3244. static const struct drm_prop_enum_list ucsc_gc[] = {
  3245. {UCSC_GC_MODE_DISABLE, "disable"},
  3246. {UCSC_GC_MODE_SRGB, "srgb"},
  3247. {UCSC_GC_MODE_PQ, "pq"},
  3248. {UCSC_GC_MODE_GAMMA2_2, "gamma2_2"},
  3249. {UCSC_GC_MODE_HLG, "hlg"},
  3250. };
  3251. static const struct drm_prop_enum_list ucsc_igc[] = {
  3252. {UCSC_IGC_MODE_DISABLE, "disable"},
  3253. {UCSC_IGC_MODE_SRGB, "srgb"},
  3254. {UCSC_IGC_MODE_REC709, "rec709"},
  3255. {UCSC_IGC_MODE_GAMMA2_2, "gamma2_2"},
  3256. {UCSC_IGC_MODE_HLG, "hlg"},
  3257. {UCSC_IGC_MODE_PQ, "pq"},
  3258. };
  3259. if ((is_master &&
  3260. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3261. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3262. msm_property_install_range(&psde->property_info,
  3263. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3264. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3265. }
  3266. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3267. msm_property_install_volatile_range(
  3268. &psde->property_info, "csc_dma_v1", 0x0,
  3269. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3270. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3271. }
  3272. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3273. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3274. "SDE_SSPP_SKIN_COLOR_V",
  3275. psde->pipe_sblk->memcolor_blk.version >> 16);
  3276. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3277. PLANE_PROP_SKIN_COLOR);
  3278. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3279. "SDE_SSPP_SKY_COLOR_V",
  3280. psde->pipe_sblk->memcolor_blk.version >> 16);
  3281. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3282. PLANE_PROP_SKY_COLOR);
  3283. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3284. "SDE_SSPP_FOLIAGE_COLOR_V",
  3285. psde->pipe_sblk->memcolor_blk.version >> 16);
  3286. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3287. PLANE_PROP_FOLIAGE_COLOR);
  3288. }
  3289. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3290. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3291. "SDE_VIG_3D_LUT_GAMUT_V",
  3292. psde->pipe_sblk->gamut_blk.version >> 16);
  3293. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3294. PLANE_PROP_VIG_GAMUT);
  3295. }
  3296. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3297. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3298. "SDE_VIG_1D_LUT_IGC_V",
  3299. psde->pipe_sblk->igc_blk[0].version >> 16);
  3300. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3301. PLANE_PROP_VIG_IGC);
  3302. }
  3303. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3304. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3305. "SDE_DGM_1D_LUT_IGC_V",
  3306. psde->pipe_sblk->igc_blk[0].version >> 16);
  3307. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3308. PLANE_PROP_DMA_IGC);
  3309. }
  3310. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3311. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3312. "SDE_DGM_1D_LUT_GC_V",
  3313. psde->pipe_sblk->gc_blk[0].version >> 16);
  3314. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3315. PLANE_PROP_DMA_GC);
  3316. }
  3317. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3318. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3319. "SDE_SSPP_FP16_IGC_V",
  3320. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3321. msm_property_install_range(&psde->property_info, feature_name,
  3322. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3323. }
  3324. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3325. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3326. "SDE_SSPP_FP16_GC_V",
  3327. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3328. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3329. PLANE_PROP_FP16_GC);
  3330. }
  3331. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3332. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3333. "SDE_SSPP_FP16_CSC_V",
  3334. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3335. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3336. PLANE_PROP_FP16_CSC);
  3337. }
  3338. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3339. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3340. "SDE_SSPP_FP16_UNMULT_V",
  3341. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3342. msm_property_install_range(&psde->property_info, feature_name,
  3343. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3344. }
  3345. if (psde->features & BIT(SDE_SSPP_UCSC_IGC)) {
  3346. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3347. "SDE_SSPP_UCSC_IGC_V",
  3348. psde->pipe_sblk->ucsc_igc_blk[0].version >> 16);
  3349. msm_property_install_enum(&psde->property_info, feature_name,
  3350. 0x0, 0, ucsc_igc, ARRAY_SIZE(ucsc_igc), 0, PLANE_PROP_UCSC_IGC);
  3351. }
  3352. if (psde->features & BIT(SDE_SSPP_UCSC_GC)) {
  3353. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3354. "SDE_SSPP_UCSC_GC_V",
  3355. psde->pipe_sblk->ucsc_gc_blk[0].version >> 16);
  3356. msm_property_install_enum(&psde->property_info, feature_name,
  3357. 0x0, 0, ucsc_gc, ARRAY_SIZE(ucsc_gc), 0, PLANE_PROP_UCSC_GC);
  3358. }
  3359. if (psde->features & BIT(SDE_SSPP_UCSC_CSC)) {
  3360. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3361. "SDE_SSPP_UCSC_CSC_V",
  3362. psde->pipe_sblk->ucsc_csc_blk[0].version >> 16);
  3363. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3364. PLANE_PROP_UCSC_CSC);
  3365. }
  3366. if (psde->features & BIT(SDE_SSPP_UCSC_UNMULT)) {
  3367. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3368. "SDE_SSPP_UCSC_UNMULT_V",
  3369. psde->pipe_sblk->ucsc_unmult_blk[0].version >> 16);
  3370. msm_property_install_range(&psde->property_info, feature_name,
  3371. 0x0, 0, 1, 0, PLANE_PROP_UCSC_UNMULT);
  3372. }
  3373. if (psde->features & BIT(SDE_SSPP_UCSC_ALPHA_DITHER)) {
  3374. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3375. "SDE_SSPP_UCSC_ALPHA_DITHER_V",
  3376. psde->pipe_sblk->ucsc_alpha_dither_blk[0].version >> 16);
  3377. msm_property_install_range(&psde->property_info, feature_name,
  3378. 0x0, 0, 1, 0, PLANE_PROP_UCSC_ALPHA_DITHER);
  3379. }
  3380. }
  3381. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3382. u32 master_plane_id, struct sde_kms_info *info,
  3383. struct sde_mdss_cfg *catalog)
  3384. {
  3385. bool is_master = !psde->is_virtual;
  3386. const struct sde_format_extended *format_list;
  3387. u32 index;
  3388. int pipe_id;
  3389. if (is_master) {
  3390. format_list = psde->pipe_sblk->format_list;
  3391. } else {
  3392. format_list = psde->pipe_sblk->virt_format_list;
  3393. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3394. master_plane_id);
  3395. }
  3396. if (format_list) {
  3397. sde_kms_info_start(info, "pixel_formats");
  3398. while (format_list->fourcc_format) {
  3399. sde_kms_info_append_format(info,
  3400. format_list->fourcc_format,
  3401. format_list->modifier);
  3402. ++format_list;
  3403. }
  3404. sde_kms_info_stop(info);
  3405. }
  3406. if (psde->pipe_hw && catalog->qseed_hw_rev)
  3407. sde_kms_info_add_keyint(info, "scaler_step_ver", catalog->qseed_hw_rev);
  3408. sde_kms_info_add_keyint(info, "max_linewidth",
  3409. psde->pipe_sblk->maxlinewidth);
  3410. sde_kms_info_add_keyint(info, "max_upscale",
  3411. psde->pipe_sblk->maxupscale);
  3412. sde_kms_info_add_keyint(info, "max_downscale",
  3413. psde->pipe_sblk->maxdwnscale);
  3414. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3415. psde->pipe_sblk->maxhdeciexp);
  3416. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3417. psde->pipe_sblk->maxvdeciexp);
  3418. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3419. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3420. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3421. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3422. if (SDE_SSPP_VALID_VIG(psde->pipe))
  3423. pipe_id = psde->pipe - SSPP_VIG0;
  3424. else if (SDE_SSPP_VALID_DMA(psde->pipe))
  3425. pipe_id = psde->pipe - SSPP_DMA0;
  3426. else
  3427. pipe_id = -1;
  3428. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3429. index = (master_plane_id == 0) ? 0 : 1;
  3430. if (test_bit(SDE_FEATURE_DEMURA, catalog->features) &&
  3431. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3432. sde_kms_info_add_keyint(info, "demura_block",
  3433. catalog->demura_supported[psde->pipe][index]);
  3434. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3435. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3436. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3437. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3438. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3439. const struct sde_format_extended *inline_rot_fmt_list;
  3440. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3441. catalog->true_inline_rot_rev);
  3442. sde_kms_info_add_keyint(info,
  3443. "true_inline_dwnscale_rt",
  3444. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3445. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3446. sde_kms_info_add_keyint(info,
  3447. "true_inline_dwnscale_rt_numerator",
  3448. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3449. sde_kms_info_add_keyint(info,
  3450. "true_inline_dwnscale_rt_denominator",
  3451. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3452. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3453. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3454. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3455. psde->pipe_sblk->in_rot_maxheight);
  3456. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3457. if (inline_rot_fmt_list) {
  3458. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3459. while (inline_rot_fmt_list->fourcc_format) {
  3460. sde_kms_info_append_format(info,
  3461. inline_rot_fmt_list->fourcc_format,
  3462. inline_rot_fmt_list->modifier);
  3463. ++inline_rot_fmt_list;
  3464. }
  3465. sde_kms_info_stop(info);
  3466. }
  3467. }
  3468. }
  3469. /* helper to install properties which are common to planes and crtcs */
  3470. static void _sde_plane_install_properties(struct drm_plane *plane,
  3471. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3472. {
  3473. static const struct drm_prop_enum_list e_blend_op[] = {
  3474. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3475. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3476. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3477. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3478. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3479. };
  3480. static const struct drm_prop_enum_list e_src_config[] = {
  3481. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3482. };
  3483. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3484. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3485. {SDE_DRM_FB_SEC, "sec"},
  3486. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3487. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3488. };
  3489. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3490. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3491. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3492. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3493. };
  3494. struct sde_kms_info *info;
  3495. struct sde_plane *psde = to_sde_plane(plane);
  3496. bool is_master;
  3497. int zpos_max = 255;
  3498. int zpos_def = 0;
  3499. if (!plane || !psde) {
  3500. SDE_ERROR("invalid plane\n");
  3501. return;
  3502. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3503. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3504. !psde->pipe_hw, !psde->pipe_sblk);
  3505. return;
  3506. } else if (!catalog) {
  3507. SDE_ERROR("invalid catalog\n");
  3508. return;
  3509. }
  3510. psde->catalog = catalog;
  3511. is_master = !psde->is_virtual;
  3512. info = vzalloc(sizeof(struct sde_kms_info));
  3513. if (!info) {
  3514. SDE_ERROR("failed to allocate info memory\n");
  3515. return;
  3516. }
  3517. if (sde_is_custom_client()) {
  3518. if (catalog->mixer_count &&
  3519. catalog->mixer[0].sblk->maxblendstages) {
  3520. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3521. if (test_bit(SDE_FEATURE_BASE_LAYER, catalog->features) &&
  3522. (zpos_max > SDE_STAGE_MAX - 1))
  3523. zpos_max = SDE_STAGE_MAX - 1;
  3524. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3525. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3526. }
  3527. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3528. /* reserve zpos == 0 for primary planes */
  3529. zpos_def = drm_plane_index(plane) + 1;
  3530. }
  3531. msm_property_install_range(&psde->property_info, "zpos",
  3532. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3533. msm_property_install_range(&psde->property_info, "alpha",
  3534. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3535. /* linux default file descriptor range on each process */
  3536. msm_property_install_range(&psde->property_info, "input_fence",
  3537. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3538. if (is_master)
  3539. _sde_plane_install_master_only_properties(psde);
  3540. else
  3541. msm_property_install_enum(&psde->property_info,
  3542. "multirect_mode", 0x0, 0, e_multirect_mode,
  3543. ARRAY_SIZE(e_multirect_mode), 0,
  3544. PLANE_PROP_MULTIRECT_MODE);
  3545. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3546. msm_property_install_volatile_range(&psde->property_info,
  3547. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3548. sde_plane_rot_install_properties(plane, catalog);
  3549. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3550. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3551. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3552. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3553. PLANE_PROP_SRC_CONFIG);
  3554. if (psde->pipe_hw->ops.setup_solidfill)
  3555. msm_property_install_range(&psde->property_info, "color_fill",
  3556. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3557. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3558. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3559. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3560. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3561. msm_property_install_blob(&psde->property_info, "capabilities",
  3562. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3563. sde_kms_info_reset(info);
  3564. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3565. catalog);
  3566. _sde_plane_install_colorproc_properties(psde, info);
  3567. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3568. info->data, SDE_KMS_INFO_DATALEN(info),
  3569. PLANE_PROP_INFO);
  3570. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3571. 0x0, 0, e_fb_translation_mode,
  3572. ARRAY_SIZE(e_fb_translation_mode), 0,
  3573. PLANE_PROP_FB_TRANSLATION_MODE);
  3574. if (psde->pipe_hw->ops.set_ubwc_stats_roi)
  3575. msm_property_install_volatile_range(&psde->property_info, "ubwc_stats_roi",
  3576. 0, 0, ~0, 0, PLANE_PROP_UBWC_STATS_ROI);
  3577. vfree(info);
  3578. }
  3579. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3580. void __user *usr_ptr, struct sde_plane_state *pstate)
  3581. {
  3582. struct sde_drm_csc_v1 csc_v1;
  3583. int i;
  3584. if (!psde || !pstate) {
  3585. SDE_ERROR("invalid plane\n");
  3586. return;
  3587. }
  3588. pstate->csc_usr_ptr = NULL;
  3589. if (!usr_ptr) {
  3590. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3591. return;
  3592. }
  3593. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3594. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3595. return;
  3596. }
  3597. /* populate from user space */
  3598. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3599. pstate->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3600. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3601. pstate->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3602. pstate->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3603. }
  3604. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3605. pstate->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3606. pstate->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3607. }
  3608. pstate->csc_usr_ptr = &pstate->csc_cfg;
  3609. }
  3610. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3611. struct sde_plane_state *pstate, void __user *usr)
  3612. {
  3613. struct sde_drm_scaler_v1 scale_v1;
  3614. struct sde_hw_pixel_ext *pe;
  3615. int i;
  3616. if (!psde || !pstate) {
  3617. SDE_ERROR("invalid argument(s)\n");
  3618. return;
  3619. }
  3620. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3621. if (!usr) {
  3622. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3623. return;
  3624. }
  3625. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3626. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3627. return;
  3628. }
  3629. /* force property to be dirty, even if the pointer didn't change */
  3630. msm_property_set_dirty(&psde->property_info,
  3631. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3632. /* populate from user space */
  3633. pe = &pstate->pixel_ext;
  3634. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3635. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3636. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3637. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3638. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3639. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3640. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3641. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3642. }
  3643. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3644. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3645. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3646. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3647. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3648. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3649. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3650. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3651. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3652. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3653. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3654. }
  3655. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3656. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3657. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3658. }
  3659. static void _sde_plane_clear_predownscale_settings(
  3660. struct sde_plane_state *pstate)
  3661. {
  3662. pstate->pre_down.pre_downscale_x_0 = 0;
  3663. pstate->pre_down.pre_downscale_x_1 = 0;
  3664. pstate->pre_down.pre_downscale_y_0 = 0;
  3665. pstate->pre_down.pre_downscale_y_1 = 0;
  3666. }
  3667. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3668. struct sde_plane_state *pstate, void __user *usr)
  3669. {
  3670. struct sde_drm_scaler_v2 scale_v2;
  3671. struct sde_hw_pixel_ext *pe;
  3672. int i;
  3673. struct sde_hw_scaler3_cfg *cfg;
  3674. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3675. if (!psde || !pstate) {
  3676. SDE_ERROR("invalid argument(s)\n");
  3677. return;
  3678. }
  3679. cfg = &pstate->scaler3_cfg;
  3680. pd_cfg = &pstate->pre_down;
  3681. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3682. if (!usr) {
  3683. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3684. cfg->enable = 0;
  3685. _sde_plane_clear_predownscale_settings(pstate);
  3686. goto end;
  3687. }
  3688. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3689. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3690. return;
  3691. }
  3692. /* detach/ignore user data if 'disabled' */
  3693. if (!scale_v2.enable) {
  3694. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3695. cfg->enable = 0;
  3696. _sde_plane_clear_predownscale_settings(pstate);
  3697. goto end;
  3698. }
  3699. /* populate from user space */
  3700. sde_set_scaler_v2(cfg, &scale_v2);
  3701. if (_sde_plane_has_pre_downscale(psde)) {
  3702. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3703. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3704. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3705. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3706. }
  3707. pe = &pstate->pixel_ext;
  3708. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3709. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3710. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3711. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3712. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3713. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3714. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3715. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3716. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3717. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3718. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3719. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3720. }
  3721. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3722. end:
  3723. /* force property to be dirty, even if the pointer didn't change */
  3724. msm_property_set_dirty(&psde->property_info,
  3725. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3726. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3727. cfg->src_width[0], cfg->src_height[0],
  3728. cfg->dst_width, cfg->dst_height);
  3729. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3730. }
  3731. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3732. struct sde_plane_state *pstate, void __user *usr_ptr)
  3733. {
  3734. struct drm_clip_rect excl_rect_v1;
  3735. if (!psde || !pstate) {
  3736. SDE_ERROR("invalid argument(s)\n");
  3737. return;
  3738. }
  3739. if (!usr_ptr) {
  3740. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3741. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3742. return;
  3743. }
  3744. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3745. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3746. return;
  3747. }
  3748. /* populate from user space */
  3749. pstate->excl_rect.x = excl_rect_v1.x1;
  3750. pstate->excl_rect.y = excl_rect_v1.y1;
  3751. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3752. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3753. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3754. pstate->excl_rect.x, pstate->excl_rect.y,
  3755. pstate->excl_rect.w, pstate->excl_rect.h);
  3756. }
  3757. static void _sde_plane_set_ubwc_stats_roi(struct sde_plane *psde,
  3758. struct sde_plane_state *pstate, void __user *usr_ptr)
  3759. {
  3760. struct sde_drm_ubwc_stats_roi roi = {0};
  3761. if (!psde || !pstate) {
  3762. SDE_ERROR("invalid argument(s)\n");
  3763. return;
  3764. }
  3765. if (!usr_ptr) {
  3766. SDE_DEBUG_PLANE(psde, "ubwc roi disabled");
  3767. goto end;
  3768. }
  3769. if (copy_from_user(&roi, usr_ptr, sizeof(roi))) {
  3770. SDE_ERROR_PLANE(psde, "failed to copy ubwc stats roi");
  3771. return;
  3772. }
  3773. if (roi.y_coord0 > psde->pipe_cfg.src_rect.h || roi.y_coord1 > psde->pipe_cfg.src_rect.h) {
  3774. SDE_ERROR_PLANE(psde, "invalid ubwc roi y0 0x%x, y1 0x%x, src height 0x%x",
  3775. roi.y_coord0, roi.y_coord1, psde->pipe_cfg.src_rect.h);
  3776. memset(&roi, 0, sizeof(roi));
  3777. }
  3778. end:
  3779. SDE_EVT32(psde, roi.y_coord0, roi.y_coord1);
  3780. memcpy(&pstate->ubwc_stats_roi, &roi, sizeof(struct sde_drm_ubwc_stats_roi));
  3781. }
  3782. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3783. struct drm_plane_state *state, struct drm_property *property,
  3784. uint64_t val)
  3785. {
  3786. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3787. struct sde_plane_state *pstate;
  3788. int idx, ret = -EINVAL;
  3789. SDE_DEBUG_PLANE(psde, "\n");
  3790. if (!plane) {
  3791. SDE_ERROR("invalid plane\n");
  3792. } else if (!state) {
  3793. SDE_ERROR_PLANE(psde, "invalid state\n");
  3794. } else {
  3795. pstate = to_sde_plane_state(state);
  3796. ret = msm_property_atomic_set(&psde->property_info,
  3797. &pstate->property_state, property, val);
  3798. if (!ret) {
  3799. idx = msm_property_index(&psde->property_info,
  3800. property);
  3801. switch (idx) {
  3802. case PLANE_PROP_INPUT_FENCE:
  3803. _sde_plane_set_input_fence(psde, pstate, val);
  3804. break;
  3805. case PLANE_PROP_CSC_V1:
  3806. case PLANE_PROP_CSC_DMA_V1:
  3807. _sde_plane_set_csc_v1(psde, (void __user *)val, pstate);
  3808. break;
  3809. case PLANE_PROP_SCALER_V1:
  3810. _sde_plane_set_scaler_v1(psde, pstate,
  3811. (void *)(uintptr_t)val);
  3812. break;
  3813. case PLANE_PROP_SCALER_V2:
  3814. _sde_plane_set_scaler_v2(psde, pstate,
  3815. (void *)(uintptr_t)val);
  3816. break;
  3817. case PLANE_PROP_EXCL_RECT_V1:
  3818. _sde_plane_set_excl_rect_v1(psde, pstate,
  3819. (void *)(uintptr_t)val);
  3820. break;
  3821. case PLANE_PROP_UBWC_STATS_ROI:
  3822. _sde_plane_set_ubwc_stats_roi(psde, pstate,
  3823. (void __user *)(uintptr_t)val);
  3824. break;
  3825. default:
  3826. /* nothing to do */
  3827. break;
  3828. }
  3829. }
  3830. }
  3831. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3832. property->name, property->base.id, val, ret);
  3833. return ret;
  3834. }
  3835. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3836. const struct drm_plane_state *state,
  3837. struct drm_property *property, uint64_t *val)
  3838. {
  3839. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3840. struct sde_plane_state *pstate;
  3841. int ret = -EINVAL;
  3842. if (!plane) {
  3843. SDE_ERROR("invalid plane\n");
  3844. } else if (!state) {
  3845. SDE_ERROR("invalid state\n");
  3846. } else {
  3847. SDE_DEBUG_PLANE(psde, "\n");
  3848. pstate = to_sde_plane_state(state);
  3849. ret = msm_property_atomic_get(&psde->property_info,
  3850. &pstate->property_state, property, val);
  3851. }
  3852. return ret;
  3853. }
  3854. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3855. struct drm_plane_state *plane_state)
  3856. {
  3857. struct sde_plane *psde;
  3858. struct sde_plane_state *pstate;
  3859. struct drm_property *drm_prop;
  3860. enum msm_mdp_plane_property prop_idx;
  3861. if (!plane || !plane_state) {
  3862. SDE_ERROR("invalid params\n");
  3863. return -EINVAL;
  3864. }
  3865. psde = to_sde_plane(plane);
  3866. pstate = to_sde_plane_state(plane_state);
  3867. pstate->static_cache_state = CACHE_STATE_DISABLED;
  3868. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3869. uint64_t val = pstate->property_values[prop_idx].value;
  3870. uint64_t def;
  3871. int ret;
  3872. drm_prop = msm_property_index_to_drm_property(
  3873. &psde->property_info, prop_idx);
  3874. if (!drm_prop) {
  3875. /* not all props will be installed, based on caps */
  3876. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3877. prop_idx);
  3878. continue;
  3879. }
  3880. def = msm_property_get_default(&psde->property_info, prop_idx);
  3881. if (val == def)
  3882. continue;
  3883. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3884. drm_prop->name, prop_idx, val, def);
  3885. ret = sde_plane_atomic_set_property(plane, plane_state,
  3886. drm_prop, def);
  3887. if (ret) {
  3888. SDE_ERROR_PLANE(psde,
  3889. "set property failed, idx %d ret %d\n",
  3890. prop_idx, ret);
  3891. continue;
  3892. }
  3893. }
  3894. return 0;
  3895. }
  3896. static void sde_plane_destroy(struct drm_plane *plane)
  3897. {
  3898. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3899. SDE_DEBUG_PLANE(psde, "\n");
  3900. if (psde) {
  3901. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3902. if (psde->blob_info)
  3903. drm_property_blob_put(psde->blob_info);
  3904. msm_property_destroy(&psde->property_info);
  3905. mutex_destroy(&psde->lock);
  3906. /* this will destroy the states as well */
  3907. drm_plane_cleanup(plane);
  3908. if (psde->pipe_hw)
  3909. sde_hw_sspp_destroy(psde->pipe_hw);
  3910. kfree(psde);
  3911. }
  3912. }
  3913. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3914. {
  3915. struct sde_plane_state *pstate;
  3916. if (!state) {
  3917. SDE_ERROR("invalid arg state %d\n", !state);
  3918. return;
  3919. }
  3920. pstate = to_sde_plane_state(state);
  3921. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3922. SDE_DRM_FB_SEC) {
  3923. /* remove ref count for frame buffers */
  3924. if (state->fb) {
  3925. drm_framebuffer_put(state->fb);
  3926. state->fb = NULL;
  3927. }
  3928. }
  3929. }
  3930. static void sde_plane_destroy_state(struct drm_plane *plane,
  3931. struct drm_plane_state *state)
  3932. {
  3933. struct sde_plane *psde;
  3934. struct sde_plane_state *pstate;
  3935. if (!plane || !state) {
  3936. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3937. !plane, !state);
  3938. return;
  3939. }
  3940. psde = to_sde_plane(plane);
  3941. pstate = to_sde_plane_state(state);
  3942. SDE_DEBUG_PLANE(psde, "\n");
  3943. /* remove ref count for frame buffers */
  3944. if (state->fb)
  3945. drm_framebuffer_put(state->fb);
  3946. /* remove ref count for fence */
  3947. if (pstate->input_fence)
  3948. sde_sync_put(pstate->input_fence);
  3949. pstate->input_fence = 0;
  3950. /* destroy value helper */
  3951. msm_property_destroy_state(&psde->property_info, pstate,
  3952. &pstate->property_state);
  3953. }
  3954. static struct drm_plane_state *
  3955. sde_plane_duplicate_state(struct drm_plane *plane)
  3956. {
  3957. struct sde_plane *psde;
  3958. struct sde_plane_state *pstate;
  3959. struct sde_plane_state *old_state;
  3960. struct drm_property *drm_prop;
  3961. uint64_t input_fence_default;
  3962. if (!plane) {
  3963. SDE_ERROR("invalid plane\n");
  3964. return NULL;
  3965. } else if (!plane->state) {
  3966. SDE_ERROR("invalid plane state\n");
  3967. return NULL;
  3968. }
  3969. old_state = to_sde_plane_state(plane->state);
  3970. psde = to_sde_plane(plane);
  3971. if (old_state->cont_splash_populated) {
  3972. plane->state->crtc = NULL;
  3973. old_state->cont_splash_populated = false;
  3974. }
  3975. pstate = msm_property_alloc_state(&psde->property_info);
  3976. if (!pstate) {
  3977. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3978. return NULL;
  3979. }
  3980. SDE_DEBUG_PLANE(psde, "\n");
  3981. /* duplicate value helper */
  3982. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3983. &pstate->property_state, pstate->property_values);
  3984. /* clear out any input fence */
  3985. pstate->input_fence = 0;
  3986. input_fence_default = msm_property_get_default(
  3987. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3988. drm_prop = msm_property_index_to_drm_property(
  3989. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3990. if (msm_property_atomic_set(&psde->property_info,
  3991. &pstate->property_state, drm_prop,
  3992. input_fence_default))
  3993. SDE_DEBUG_PLANE(psde,
  3994. "error clearing duplicated input fence\n");
  3995. pstate->dirty = 0x0;
  3996. pstate->pending = false;
  3997. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3998. /* reset layout offset */
  3999. if (pstate->layout_offset) {
  4000. if (pstate->layout_offset > 0)
  4001. pstate->base.crtc_x += pstate->layout_offset;
  4002. pstate->layout = SDE_LAYOUT_NONE;
  4003. pstate->layout_offset = 0;
  4004. }
  4005. return &pstate->base;
  4006. }
  4007. static void sde_plane_reset(struct drm_plane *plane)
  4008. {
  4009. struct sde_plane *psde;
  4010. struct sde_plane_state *pstate;
  4011. if (!plane) {
  4012. SDE_ERROR("invalid plane\n");
  4013. return;
  4014. }
  4015. psde = to_sde_plane(plane);
  4016. SDE_DEBUG_PLANE(psde, "\n");
  4017. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  4018. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  4019. return;
  4020. }
  4021. /* remove previous state, if present */
  4022. if (plane->state) {
  4023. sde_plane_destroy_state(plane, plane->state);
  4024. plane->state = 0;
  4025. }
  4026. pstate = msm_property_alloc_state(&psde->property_info);
  4027. if (!pstate) {
  4028. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  4029. return;
  4030. }
  4031. /* reset value helper */
  4032. msm_property_reset_state(&psde->property_info, pstate,
  4033. &pstate->property_state,
  4034. pstate->property_values);
  4035. pstate->base.plane = plane;
  4036. plane->state = &pstate->base;
  4037. }
  4038. void sde_plane_get_frame_data(struct drm_plane *plane,
  4039. struct sde_drm_plane_frame_data *data)
  4040. {
  4041. struct sde_plane *psde;
  4042. struct sde_plane_state *pstate;
  4043. struct sde_drm_ubwc_stats_data *ubwc_stats;
  4044. if (!plane) {
  4045. SDE_ERROR("invalid plane\n");
  4046. return;
  4047. }
  4048. psde = to_sde_plane(plane);
  4049. pstate = to_sde_plane_state(plane->state);
  4050. ubwc_stats = &data->ubwc_stats;
  4051. data->plane_id = DRMID(plane);
  4052. if (psde->pipe_hw->ops.get_ubwc_stats_data) {
  4053. memcpy(&ubwc_stats->roi, &pstate->ubwc_stats_roi,
  4054. sizeof(struct sde_drm_ubwc_stats_roi));
  4055. psde->pipe_hw->ops.get_ubwc_stats_data(psde->pipe_hw,
  4056. pstate->multirect_index, ubwc_stats);
  4057. }
  4058. if (psde->pipe_hw->ops.get_ubwc_error)
  4059. ubwc_stats->error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  4060. pstate->multirect_index);
  4061. if (psde->pipe_hw->ops.clear_ubwc_error && ubwc_stats->error)
  4062. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  4063. if (psde->pipe_hw->ops.get_meta_error)
  4064. ubwc_stats->meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  4065. pstate->multirect_index);
  4066. if (psde->pipe_hw->ops.clear_meta_error && ubwc_stats->meta_error)
  4067. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  4068. if (ubwc_stats->error || ubwc_stats->meta_error) {
  4069. SDE_EVT32(DRMID(plane), ubwc_stats->error, ubwc_stats->meta_error,
  4070. SDE_EVTLOG_ERROR);
  4071. SDE_DEBUG_PLANE(psde, "ubwc_error:0x%x meta_error:0x%x\n",
  4072. ubwc_stats->error, ubwc_stats->meta_error);
  4073. }
  4074. }
  4075. #if IS_ENABLED(CONFIG_DEBUG_FS)
  4076. static ssize_t _sde_plane_danger_read(struct file *file,
  4077. char __user *buff, size_t count, loff_t *ppos)
  4078. {
  4079. struct sde_kms *kms = file->private_data;
  4080. struct sde_mdss_cfg *cfg = kms->catalog;
  4081. int len = 0;
  4082. char buf[40] = {'\0'};
  4083. if (!cfg)
  4084. return -ENODEV;
  4085. if (*ppos)
  4086. return 0; /* the end */
  4087. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  4088. if (len < 0 || len >= sizeof(buf))
  4089. return 0;
  4090. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  4091. return -EFAULT;
  4092. *ppos += len; /* increase offset */
  4093. return len;
  4094. }
  4095. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  4096. {
  4097. struct drm_plane *plane;
  4098. drm_for_each_plane(plane, kms->dev) {
  4099. if (plane->fb && plane->state) {
  4100. sde_plane_danger_signal_ctrl(plane, enable);
  4101. SDE_DEBUG("plane:%d img:%dx%d ",
  4102. plane->base.id, plane->fb->width,
  4103. plane->fb->height);
  4104. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  4105. plane->state->src_x >> 16,
  4106. plane->state->src_y >> 16,
  4107. plane->state->src_w >> 16,
  4108. plane->state->src_h >> 16,
  4109. plane->state->crtc_x, plane->state->crtc_y,
  4110. plane->state->crtc_w, plane->state->crtc_h);
  4111. } else {
  4112. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  4113. }
  4114. }
  4115. }
  4116. static ssize_t _sde_plane_danger_write(struct file *file,
  4117. const char __user *user_buf, size_t count, loff_t *ppos)
  4118. {
  4119. struct sde_kms *kms = file->private_data;
  4120. struct sde_mdss_cfg *cfg = kms->catalog;
  4121. int disable_panic;
  4122. char buf[10];
  4123. if (!cfg)
  4124. return -EFAULT;
  4125. if (count >= sizeof(buf))
  4126. return -EFAULT;
  4127. if (copy_from_user(buf, user_buf, count))
  4128. return -EFAULT;
  4129. buf[count] = 0; /* end of string */
  4130. if (kstrtoint(buf, 0, &disable_panic))
  4131. return -EFAULT;
  4132. if (disable_panic) {
  4133. /* Disable panic signal for all active pipes */
  4134. SDE_DEBUG("Disabling danger:\n");
  4135. _sde_plane_set_danger_state(kms, false);
  4136. kms->has_danger_ctrl = false;
  4137. } else {
  4138. /* Enable panic signal for all active pipes */
  4139. SDE_DEBUG("Enabling danger:\n");
  4140. kms->has_danger_ctrl = true;
  4141. _sde_plane_set_danger_state(kms, true);
  4142. }
  4143. return count;
  4144. }
  4145. static const struct file_operations sde_plane_danger_enable = {
  4146. .open = simple_open,
  4147. .read = _sde_plane_danger_read,
  4148. .write = _sde_plane_danger_write,
  4149. };
  4150. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4151. {
  4152. struct sde_plane *psde;
  4153. struct sde_kms *kms;
  4154. struct msm_drm_private *priv;
  4155. const struct sde_sspp_sub_blks *sblk = 0;
  4156. const struct sde_sspp_cfg *cfg = 0;
  4157. if (!plane || !plane->dev) {
  4158. SDE_ERROR("invalid arguments\n");
  4159. return -EINVAL;
  4160. }
  4161. priv = plane->dev->dev_private;
  4162. if (!priv || !priv->kms) {
  4163. SDE_ERROR("invalid KMS reference\n");
  4164. return -EINVAL;
  4165. }
  4166. kms = to_sde_kms(priv->kms);
  4167. psde = to_sde_plane(plane);
  4168. if (psde && psde->pipe_hw)
  4169. cfg = psde->pipe_hw->cap;
  4170. if (cfg)
  4171. sblk = cfg->sblk;
  4172. if (!sblk)
  4173. return 0;
  4174. /* create overall sub-directory for the pipe */
  4175. psde->debugfs_root =
  4176. debugfs_create_dir(psde->pipe_name,
  4177. plane->dev->primary->debugfs_root);
  4178. if (!psde->debugfs_root)
  4179. return -ENOMEM;
  4180. /* don't error check these */
  4181. debugfs_create_x64("features", 0400,
  4182. psde->debugfs_root, &psde->features);
  4183. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  4184. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  4185. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  4186. debugfs_create_bool("default_scaling",
  4187. 0600,
  4188. psde->debugfs_root,
  4189. &psde->debugfs_default_scale);
  4190. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  4191. debugfs_create_u32("in_rot_max_downscale_rt_num",
  4192. 0600,
  4193. psde->debugfs_root,
  4194. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  4195. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  4196. 0600,
  4197. psde->debugfs_root,
  4198. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  4199. debugfs_create_u32("in_rot_max_downscale_nrt",
  4200. 0600,
  4201. psde->debugfs_root,
  4202. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  4203. debugfs_create_u32("in_rot_max_height",
  4204. 0600,
  4205. psde->debugfs_root,
  4206. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  4207. }
  4208. debugfs_create_u32("xin_id",
  4209. 0400,
  4210. psde->debugfs_root,
  4211. (u32 *) &cfg->xin_id);
  4212. debugfs_create_x32("creq_vblank",
  4213. 0600,
  4214. psde->debugfs_root,
  4215. (u32 *) &sblk->creq_vblank);
  4216. debugfs_create_x32("danger_vblank",
  4217. 0600,
  4218. psde->debugfs_root,
  4219. (u32 *) &sblk->danger_vblank);
  4220. debugfs_create_file("disable_danger",
  4221. 0600,
  4222. psde->debugfs_root,
  4223. kms, &sde_plane_danger_enable);
  4224. return 0;
  4225. }
  4226. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4227. {
  4228. struct sde_plane *psde;
  4229. if (!plane)
  4230. return;
  4231. psde = to_sde_plane(plane);
  4232. debugfs_remove_recursive(psde->debugfs_root);
  4233. }
  4234. #else
  4235. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4236. {
  4237. return 0;
  4238. }
  4239. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4240. {
  4241. }
  4242. #endif /* CONFIG_DEBUG_FS */
  4243. static int sde_plane_late_register(struct drm_plane *plane)
  4244. {
  4245. return _sde_plane_init_debugfs(plane);
  4246. }
  4247. static void sde_plane_early_unregister(struct drm_plane *plane)
  4248. {
  4249. _sde_plane_destroy_debugfs(plane);
  4250. }
  4251. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
  4252. static bool sde_plane_format_mod_supported(struct drm_plane *plane,
  4253. uint32_t format, uint64_t modifier)
  4254. {
  4255. return (sde_get_sde_format_ext(format, modifier) != NULL);
  4256. }
  4257. #endif
  4258. static const struct drm_plane_funcs sde_plane_funcs = {
  4259. .update_plane = drm_atomic_helper_update_plane,
  4260. .disable_plane = drm_atomic_helper_disable_plane,
  4261. .destroy = sde_plane_destroy,
  4262. .atomic_set_property = sde_plane_atomic_set_property,
  4263. .atomic_get_property = sde_plane_atomic_get_property,
  4264. .reset = sde_plane_reset,
  4265. .atomic_duplicate_state = sde_plane_duplicate_state,
  4266. .atomic_destroy_state = sde_plane_destroy_state,
  4267. .late_register = sde_plane_late_register,
  4268. .early_unregister = sde_plane_early_unregister,
  4269. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
  4270. .format_mod_supported = sde_plane_format_mod_supported,
  4271. #endif
  4272. };
  4273. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  4274. .prepare_fb = sde_plane_prepare_fb,
  4275. .cleanup_fb = sde_plane_cleanup_fb,
  4276. .atomic_check = sde_plane_atomic_check,
  4277. .atomic_update = sde_plane_atomic_update,
  4278. };
  4279. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  4280. {
  4281. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  4282. }
  4283. bool is_sde_plane_virtual(struct drm_plane *plane)
  4284. {
  4285. return plane ? to_sde_plane(plane)->is_virtual : false;
  4286. }
  4287. /* initialize plane */
  4288. struct drm_plane *sde_plane_init(struct drm_device *dev,
  4289. uint32_t pipe, bool primary_plane,
  4290. unsigned long possible_crtcs, u32 master_plane_id)
  4291. {
  4292. struct drm_plane *plane = NULL, *master_plane = NULL;
  4293. const struct sde_format_extended *format_list;
  4294. struct sde_plane *psde;
  4295. struct msm_drm_private *priv;
  4296. struct sde_kms *kms;
  4297. enum drm_plane_type type;
  4298. struct sde_vbif_clk_client clk_client;
  4299. int ret = -EINVAL;
  4300. if (!dev) {
  4301. SDE_ERROR("[%u]device is NULL\n", pipe);
  4302. goto exit;
  4303. }
  4304. priv = dev->dev_private;
  4305. if (!priv) {
  4306. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4307. goto exit;
  4308. }
  4309. if (!priv->kms) {
  4310. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4311. goto exit;
  4312. }
  4313. kms = to_sde_kms(priv->kms);
  4314. if (!kms->catalog) {
  4315. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4316. goto exit;
  4317. }
  4318. /* create and zero local structure */
  4319. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4320. if (!psde) {
  4321. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4322. ret = -ENOMEM;
  4323. goto exit;
  4324. }
  4325. /* cache local stuff for later */
  4326. plane = &psde->base;
  4327. psde->pipe = pipe;
  4328. psde->is_virtual = (master_plane_id != 0);
  4329. INIT_LIST_HEAD(&psde->mplane_list);
  4330. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4331. if (master_plane) {
  4332. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4333. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4334. }
  4335. /* initialize underlying h/w driver */
  4336. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog, psde->is_virtual,
  4337. &clk_client);
  4338. if (IS_ERR(psde->pipe_hw)) {
  4339. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4340. ret = PTR_ERR(psde->pipe_hw);
  4341. goto clean_plane;
  4342. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4343. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4344. goto clean_sspp;
  4345. }
  4346. if (test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, kms->catalog->features)) {
  4347. ret = sde_vbif_clk_register(kms, &clk_client);
  4348. if (ret) {
  4349. SDE_ERROR("failed to register vbif client %d\n",
  4350. clk_client.clk_ctrl);
  4351. goto clean_sspp;
  4352. }
  4353. }
  4354. /* cache features mask for later */
  4355. psde->features = psde->pipe_hw->cap->features_ext;
  4356. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4357. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4358. if (!psde->pipe_sblk) {
  4359. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4360. goto clean_sspp;
  4361. }
  4362. if (psde->is_virtual)
  4363. format_list = psde->pipe_sblk->virt_format_list;
  4364. else
  4365. format_list = psde->pipe_sblk->format_list;
  4366. psde->nformats = sde_populate_formats(format_list,
  4367. psde->formats,
  4368. 0,
  4369. ARRAY_SIZE(psde->formats));
  4370. if (!psde->nformats) {
  4371. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4372. goto clean_sspp;
  4373. }
  4374. if (primary_plane)
  4375. type = DRM_PLANE_TYPE_PRIMARY;
  4376. else
  4377. type = DRM_PLANE_TYPE_OVERLAY;
  4378. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4379. psde->formats, psde->nformats,
  4380. NULL, type, NULL);
  4381. if (ret)
  4382. goto clean_sspp;
  4383. /* Populate static array of plane property flags */
  4384. _sde_plane_map_prop_to_dirty_bits();
  4385. /* success! finalize initialization */
  4386. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4387. msm_property_init(&psde->property_info, &plane->base, dev,
  4388. priv->plane_property, psde->property_data,
  4389. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4390. sizeof(struct sde_plane_state));
  4391. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4392. /* save user friendly pipe name for later */
  4393. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4394. mutex_init(&psde->lock);
  4395. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4396. pipe, plane->base.id, master_plane_id);
  4397. return plane;
  4398. clean_sspp:
  4399. if (psde && psde->pipe_hw)
  4400. sde_hw_sspp_destroy(psde->pipe_hw);
  4401. clean_plane:
  4402. kfree(psde);
  4403. exit:
  4404. return ERR_PTR(ret);
  4405. }
  4406. void sde_plane_add_data_to_minidump_va(struct drm_plane *plane)
  4407. {
  4408. struct sde_plane *sde_plane;
  4409. struct sde_plane_state *pstate;
  4410. sde_plane = to_sde_plane(plane);
  4411. pstate = to_sde_plane_state(plane->state);
  4412. sde_mini_dump_add_va_region("sde_plane", sizeof(*sde_plane), sde_plane);
  4413. sde_mini_dump_add_va_region("plane_state", sizeof(*pstate), pstate);
  4414. }