sde_encoder_phys.h 33 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #ifndef __SDE_ENCODER_PHYS_H__
  7. #define __SDE_ENCODER_PHYS_H__
  8. #include <linux/jiffies.h>
  9. #include <linux/sde_rsc.h>
  10. #include "sde_kms.h"
  11. #include "sde_hw_intf.h"
  12. #include "sde_hw_pingpong.h"
  13. #include "sde_hw_ctl.h"
  14. #include "sde_hw_top.h"
  15. #include "sde_hw_wb.h"
  16. #include "sde_hw_cdm.h"
  17. #include "sde_hw_dnsc_blur.h"
  18. #include "sde_encoder.h"
  19. #include "sde_connector.h"
  20. #define SDE_ENCODER_NAME_MAX 16
  21. /* wait for at most 2 vsync for lowest refresh rate (24hz) */
  22. #define DEFAULT_KICKOFF_TIMEOUT_MS 84
  23. /* if default timeout fails wait additional time in 1s increments */
  24. #define EXTENDED_KICKOFF_TIMEOUT_MS 1000
  25. #define EXTENDED_KICKOFF_TIMEOUT_ITERS 10
  26. /* wait 1 sec for the emulated targets */
  27. #define MAX_KICKOFF_TIMEOUT_MS 100000
  28. #define MAX_TE_PROFILE_COUNT 5
  29. /**
  30. * enum sde_enc_split_role - Role this physical encoder will play in a
  31. * split-panel configuration, where one panel is master, and others slaves.
  32. * Masters have extra responsibilities, like managing the VBLANK IRQ.
  33. * @ENC_ROLE_SOLO: This is the one and only panel. This encoder is master.
  34. * @ENC_ROLE_MASTER: This encoder is the master of a split panel config.
  35. * @ENC_ROLE_SLAVE: This encoder is not the master of a split panel config.
  36. * @ENC_ROLE_SKIP: This encoder is not participating in kickoffs
  37. */
  38. enum sde_enc_split_role {
  39. ENC_ROLE_SOLO,
  40. ENC_ROLE_MASTER,
  41. ENC_ROLE_SLAVE,
  42. ENC_ROLE_SKIP
  43. };
  44. /**
  45. * enum sde_enc_enable_state - current enabled state of the physical encoder
  46. * @SDE_ENC_DISABLING: Encoder transitioning to disable state
  47. * Events bounding transition are encoder type specific
  48. * @SDE_ENC_DISABLED: Encoder is disabled
  49. * @SDE_ENC_ENABLING: Encoder transitioning to enabled
  50. * Events bounding transition are encoder type specific
  51. * @SDE_ENC_ENABLED: Encoder is enabled
  52. * @SDE_ENC_ERR_NEEDS_HW_RESET: Encoder is enabled, but requires a hw_reset
  53. * to recover from a previous error
  54. */
  55. enum sde_enc_enable_state {
  56. SDE_ENC_DISABLING,
  57. SDE_ENC_DISABLED,
  58. SDE_ENC_ENABLING,
  59. SDE_ENC_ENABLED,
  60. SDE_ENC_ERR_NEEDS_HW_RESET
  61. };
  62. enum sde_enc_irqs {
  63. SDE_ENC_CMD_TE_ASSERT,
  64. SDE_ENC_CMD_TE_DEASSERT,
  65. SDE_ENC_CMD_TEAR_DETECT,
  66. SDE_ENC_IRQ_MAX
  67. };
  68. struct sde_encoder_phys;
  69. /**
  70. * struct sde_encoder_virt_ops - Interface the containing virtual encoder
  71. * provides for the physical encoders to use to callback.
  72. * @handle_vblank_virt: Notify virtual encoder of vblank IRQ reception
  73. * Note: This is called from IRQ handler context.
  74. * @handle_underrun_virt: Notify virtual encoder of underrun IRQ reception
  75. * Note: This is called from IRQ handler context.
  76. * @handle_frame_done: Notify virtual encoder that this phys encoder
  77. * completes last request frame.
  78. * @get_qsync_fps: Returns the min fps for the qsync feature.
  79. */
  80. struct sde_encoder_virt_ops {
  81. void (*handle_vblank_virt)(struct drm_encoder *parent,
  82. struct sde_encoder_phys *phys);
  83. void (*handle_underrun_virt)(struct drm_encoder *parent,
  84. struct sde_encoder_phys *phys);
  85. void (*handle_frame_done)(struct drm_encoder *parent,
  86. struct sde_encoder_phys *phys, u32 event);
  87. void (*get_qsync_fps)(struct drm_encoder *parent,
  88. u32 *qsync_fps, struct drm_connector_state *conn_state);
  89. };
  90. /**
  91. * struct sde_encoder_phys_ops - Interface the physical encoders provide to
  92. * the containing virtual encoder.
  93. * @late_register: DRM Call. Add Userspace interfaces, debugfs.
  94. * @prepare_commit: MSM Atomic Call, start of atomic commit sequence
  95. * @is_master: Whether this phys_enc is the current master
  96. * encoder. Can be switched at enable time. Based
  97. * on split_role and current mode (CMD/VID).
  98. * @mode_fixup: DRM Call. Fixup a DRM mode.
  99. * @cont_splash_mode_set: mode set with specific HW resources during
  100. * cont splash enabled state.
  101. * @mode_set: DRM Call. Set a DRM mode.
  102. * This likely caches the mode, for use at enable.
  103. * @enable: DRM Call. Enable a DRM mode.
  104. * @disable: DRM Call. Disable mode.
  105. * @atomic_check: DRM Call. Atomic check new DRM state.
  106. * @destroy: DRM Call. Destroy and release resources.
  107. * @get_hw_resources: Populate the structure with the hardware
  108. * resources that this phys_enc is using.
  109. * Expect no overlap between phys_encs.
  110. * @control_vblank_irq Register/Deregister for VBLANK IRQ
  111. * @wait_for_commit_done: Wait for hardware to have flushed the
  112. * current pending frames to hardware
  113. * @wait_for_tx_complete: Wait for hardware to transfer the pixels
  114. * to the panel
  115. * @wait_for_vblank: Wait for VBLANK, for sub-driver internal use
  116. * @prepare_for_kickoff: Do any work necessary prior to a kickoff
  117. * For CMD encoder, may wait for previous tx done
  118. * @handle_post_kickoff: Do any work necessary post-kickoff work
  119. * @trigger_flush: Process flush event on physical encoder
  120. * @trigger_start: Process start event on physical encoder
  121. * @needs_single_flush: Whether encoder slaves need to be flushed
  122. * @setup_misr: Sets up MISR, enable and disables based on sysfs
  123. * @collect_misr: Collects MISR data on frame update
  124. * @hw_reset: Issue HW recovery such as CTL reset and clear
  125. * SDE_ENC_ERR_NEEDS_HW_RESET state
  126. * @irq_control: Handler to enable/disable all the encoder IRQs
  127. * @update_split_role: Update the split role of the phys enc
  128. * @control_te: Interface to control the vsync_enable status
  129. * @restore: Restore all the encoder configs.
  130. * @is_autorefresh_enabled: provides the autorefresh current
  131. * enable/disable state.
  132. * @get_line_count: Obtain current internal vertical line count
  133. * @wait_dma_trigger: Returns true if lut dma has to trigger and wait
  134. * unitl transaction is complete.
  135. * @wait_for_active: Wait for display scan line to be in active area
  136. * @setup_vsync_source: Configure vsync source selection for cmd mode.
  137. * @get_underrun_line_count: Obtain and log current internal vertical line
  138. * count and underrun line count
  139. * @add_to_minidump: Add this phys_enc data to minidumps
  140. * @disable_autorefresh: Disable autorefresh
  141. * @idle_pc_cache_display_status: caches display status at idle power collapse
  142. */
  143. struct sde_encoder_phys_ops {
  144. int (*late_register)(struct sde_encoder_phys *encoder,
  145. struct dentry *debugfs_root);
  146. void (*prepare_commit)(struct sde_encoder_phys *encoder);
  147. bool (*is_master)(struct sde_encoder_phys *encoder);
  148. bool (*mode_fixup)(struct sde_encoder_phys *encoder,
  149. const struct drm_display_mode *mode,
  150. struct drm_display_mode *adjusted_mode);
  151. void (*mode_set)(struct sde_encoder_phys *encoder,
  152. struct drm_display_mode *mode,
  153. struct drm_display_mode *adjusted_mode, bool *reinit_mixers);
  154. void (*cont_splash_mode_set)(struct sde_encoder_phys *encoder,
  155. struct drm_display_mode *adjusted_mode);
  156. void (*enable)(struct sde_encoder_phys *encoder);
  157. void (*disable)(struct sde_encoder_phys *encoder);
  158. int (*atomic_check)(struct sde_encoder_phys *encoder,
  159. struct drm_crtc_state *crtc_state,
  160. struct drm_connector_state *conn_state);
  161. void (*destroy)(struct sde_encoder_phys *encoder);
  162. void (*get_hw_resources)(struct sde_encoder_phys *encoder,
  163. struct sde_encoder_hw_resources *hw_res,
  164. struct drm_connector_state *conn_state);
  165. int (*control_vblank_irq)(struct sde_encoder_phys *enc, bool enable);
  166. int (*wait_for_commit_done)(struct sde_encoder_phys *phys_enc);
  167. int (*wait_for_tx_complete)(struct sde_encoder_phys *phys_enc);
  168. int (*wait_for_vblank)(struct sde_encoder_phys *phys_enc);
  169. int (*prepare_for_kickoff)(struct sde_encoder_phys *phys_enc,
  170. struct sde_encoder_kickoff_params *params);
  171. void (*handle_post_kickoff)(struct sde_encoder_phys *phys_enc);
  172. void (*trigger_flush)(struct sde_encoder_phys *phys_enc);
  173. void (*trigger_start)(struct sde_encoder_phys *phys_enc);
  174. bool (*needs_single_flush)(struct sde_encoder_phys *phys_enc);
  175. void (*setup_misr)(struct sde_encoder_phys *phys_encs,
  176. bool enable, u32 frame_count);
  177. int (*collect_misr)(struct sde_encoder_phys *phys_enc, bool nonblock,
  178. u32 *misr_value);
  179. void (*hw_reset)(struct sde_encoder_phys *phys_enc);
  180. void (*irq_control)(struct sde_encoder_phys *phys, bool enable);
  181. void (*dynamic_irq_control)(struct sde_encoder_phys *phys, bool enable);
  182. void (*update_split_role)(struct sde_encoder_phys *phys_enc,
  183. enum sde_enc_split_role role);
  184. void (*control_te)(struct sde_encoder_phys *phys_enc, bool enable);
  185. void (*restore)(struct sde_encoder_phys *phys);
  186. bool (*is_autorefresh_enabled)(struct sde_encoder_phys *phys);
  187. int (*get_line_count)(struct sde_encoder_phys *phys);
  188. bool (*wait_dma_trigger)(struct sde_encoder_phys *phys);
  189. int (*wait_for_active)(struct sde_encoder_phys *phys);
  190. void (*setup_vsync_source)(struct sde_encoder_phys *phys, u32 vsync_source,
  191. struct msm_display_info *disp_info);
  192. u32 (*get_underrun_line_count)(struct sde_encoder_phys *phys);
  193. void (*add_to_minidump)(struct sde_encoder_phys *phys);
  194. void (*disable_autorefresh)(struct sde_encoder_phys *phys);
  195. void (*idle_pc_cache_display_status)(struct sde_encoder_phys *phys);
  196. };
  197. /**
  198. * enum sde_intr_idx - sde encoder interrupt index
  199. * @INTR_IDX_VSYNC: Vsync interrupt for video mode panel
  200. * @INTR_IDX_PINGPONG: Pingpong done interrupt for cmd mode panel
  201. * @INTR_IDX_UNDERRUN: Underrun interrupt for video and cmd mode panel
  202. * @INTR_IDX_CTL_START:Control start interrupt to indicate the frame start
  203. * @INTR_IDX_CTL_DONE: Control done interrupt indicating the control path being idle
  204. * @INTR_IDX_RDPTR: Readpointer done interrupt for cmd mode panel
  205. * @INTR_IDX_WB_DONE: Writeback done interrupt for WB
  206. * @INTR_IDX_PP1_OVFL: Pingpong overflow interrupt on PP1 for Concurrent WB
  207. * @INTR_IDX_PP2_OVFL: Pingpong overflow interrupt on PP2 for Concurrent WB
  208. * @INTR_IDX_PP3_OVFL: Pingpong overflow interrupt on PP3 for Concurrent WB
  209. * @INTR_IDX_PP4_OVFL: Pingpong overflow interrupt on PP4 for Concurrent WB
  210. * @INTR_IDX_PP5_OVFL: Pingpong overflow interrupt on PP5 for Concurrent WB
  211. * @INTR_IDX_PP_CWB_OVFL: Pingpong overflow interrupt on PP_CWB0/1 for Concurrent WB
  212. * @INTR_IDX_PP_CWB2_OVFL: Pingpong overflow interrupt on PP_CWB2/3 for Concurrent WB
  213. * @INTR_IDX_AUTOREFRESH_DONE: Autorefresh done for cmd mode panel meaning
  214. * autorefresh has triggered a double buffer flip
  215. * @INTR_IDX_WRPTR: Writepointer start interrupt for cmd mode panel
  216. * @INTR_IDX_WB_LINEPTR: Programmable lineptr interrupt for WB
  217. * @INTF_IDX_TEAR_DETECT: Tear detect interrupt
  218. * @INTR_IDX_TE_ASSERT: TE Assert interrupt
  219. * @INTR_IDX_TE_DEASSERT: TE Deassert interrupt
  220. */
  221. enum sde_intr_idx {
  222. INTR_IDX_VSYNC,
  223. INTR_IDX_PINGPONG,
  224. INTR_IDX_UNDERRUN,
  225. INTR_IDX_CTL_START,
  226. INTR_IDX_CTL_DONE,
  227. INTR_IDX_RDPTR,
  228. INTR_IDX_AUTOREFRESH_DONE,
  229. INTR_IDX_WB_DONE,
  230. INTR_IDX_PP1_OVFL,
  231. INTR_IDX_PP2_OVFL,
  232. INTR_IDX_PP3_OVFL,
  233. INTR_IDX_PP4_OVFL,
  234. INTR_IDX_PP5_OVFL,
  235. INTR_IDX_PP_CWB_OVFL,
  236. INTR_IDX_PP_CWB2_OVFL,
  237. INTR_IDX_WRPTR,
  238. INTR_IDX_WB_LINEPTR,
  239. INTF_IDX_TEAR_DETECT,
  240. INTR_IDX_TE_ASSERT,
  241. INTR_IDX_TE_DEASSERT,
  242. INTR_IDX_MAX,
  243. };
  244. /**
  245. * sde_encoder_irq - tracking structure for interrupts
  246. * @name: string name of interrupt
  247. * @intr_type: Encoder interrupt type
  248. * @intr_idx: Encoder interrupt enumeration
  249. * @hw_idx: HW Block ID
  250. * @irq_idx: IRQ interface lookup index from SDE IRQ framework
  251. * will be -EINVAL if IRQ is not registered
  252. * @irq_cb: interrupt callback
  253. */
  254. struct sde_encoder_irq {
  255. const char *name;
  256. enum sde_intr_type intr_type;
  257. enum sde_intr_idx intr_idx;
  258. int hw_idx;
  259. int irq_idx;
  260. struct sde_irq_callback cb;
  261. };
  262. /**
  263. * struct sde_encoder_phys - physical encoder that drives a single INTF block
  264. * tied to a specific panel / sub-panel. Abstract type, sub-classed by
  265. * phys_vid or phys_cmd for video mode or command mode encs respectively.
  266. * @parent: Pointer to the containing virtual encoder
  267. * @connector: If a mode is set, cached pointer to the active connector
  268. * @ops: Operations exposed to the virtual encoder
  269. * @parent_ops: Callbacks exposed by the parent to the phys_enc
  270. * @hw_mdptop: Hardware interface to the top registers
  271. * @hw_ctl: Hardware interface to the ctl registers
  272. * @hw_intf: Hardware interface to INTF registers
  273. * @hw_cdm: Hardware interface to the cdm registers
  274. * @hw_qdss: Hardware interface to the qdss registers
  275. * @cdm_cfg: Chroma-down hardware configuration
  276. * @hw_pp: Hardware interface to the ping pong registers
  277. * @hw_dnsc_blur: Hardware interface to the downscale blur registers
  278. * @sde_kms: Pointer to the sde_kms top level
  279. * @cached_mode: DRM mode cached at mode_set time, acted on in enable
  280. * @wd_jitter : Pointer to watchdog jitter prams
  281. * @enabled: Whether the encoder has enabled and running a mode
  282. * @split_role: Role to play in a split-panel configuration
  283. * @intf_mode: Interface mode
  284. * @intf_idx: Interface index on sde hardware
  285. * @intf_cfg: Interface hardware configuration
  286. * @intf_cfg_v1: Interface hardware configuration to be used if control
  287. * path supports SDE_CTL_ACTIVE_CFG
  288. * @comp_type: Type of compression supported
  289. * @comp_ratio: Compression ratio
  290. * @dsc_extra_pclk_cycle_cnt: Extra pclk cycle count for DSC over DP
  291. * @dsc_extra_disp_width: Additional display width for DSC over DP
  292. * @poms_align_vsync: poms with vsync aligned
  293. * @dce_bytes_per_line: Compressed bytes per line
  294. * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
  295. * @enable_state: Enable state tracking
  296. * @vblank_refcount: Reference count of vblank request
  297. * @wbirq_refcount: Reference count of wb irq request
  298. * @vsync_cnt: Vsync count for the physical encoder
  299. * @last_vsync_timestamp: store last vsync timestamp
  300. * @underrun_cnt: Underrun count for the physical encoder
  301. * @pending_kickoff_cnt: Atomic counter tracking the number of kickoffs
  302. * vs. the number of done/vblank irqs. Should hover
  303. * between 0-2 Incremented when a new kickoff is
  304. * scheduled. Decremented in irq handler
  305. * @pending_retire_fence_cnt: Atomic counter tracking the pending retire
  306. * fences that have to be signalled.
  307. * @pending_ctl_start_cnt: Atomic counter tracking the pending ctl-start-irq,
  308. * used to release commit thread. Currently managed
  309. * only for writeback encoder and the counter keeps
  310. * increasing for other type of encoders.
  311. * @pending_kickoff_wq: Wait queue for blocking until kickoff completes
  312. * @kickoff_timeout_ms: kickoff timeout in mill seconds
  313. * @irq: IRQ tracking structures
  314. * @has_intf_te: Interface TE configuration support
  315. * @cont_splash_enabled: Variable to store continuous splash settings.
  316. * @in_clone_mode Indicates if encoder is in clone mode ref@CWB
  317. * @vfp_cached: cached vertical front porch to be used for
  318. * programming ROT and MDP fetch start
  319. * @frame_trigger_mode: frame trigger mode indication for command
  320. * mode display
  321. * @recovered: flag set to true when recovered from pp timeout
  322. * @autorefresh_disable_trans: flag set to true during autorefresh disable transition
  323. */
  324. struct sde_encoder_phys {
  325. struct drm_encoder *parent;
  326. struct drm_connector *connector;
  327. struct sde_encoder_phys_ops ops;
  328. struct sde_encoder_virt_ops parent_ops;
  329. struct sde_hw_mdp *hw_mdptop;
  330. struct sde_hw_ctl *hw_ctl;
  331. struct sde_hw_intf *hw_intf;
  332. struct sde_hw_cdm *hw_cdm;
  333. struct sde_hw_qdss *hw_qdss;
  334. struct sde_hw_cdm_cfg cdm_cfg;
  335. struct sde_hw_pingpong *hw_pp;
  336. struct sde_hw_dnsc_blur *hw_dnsc_blur;
  337. struct sde_kms *sde_kms;
  338. struct drm_display_mode cached_mode;
  339. struct intf_wd_jitter_params wd_jitter;
  340. enum sde_enc_split_role split_role;
  341. enum sde_intf_mode intf_mode;
  342. enum sde_intf intf_idx;
  343. struct sde_hw_intf_cfg intf_cfg;
  344. struct sde_hw_intf_cfg_v1 intf_cfg_v1;
  345. enum msm_display_compression_type comp_type;
  346. u32 comp_ratio;
  347. u32 dsc_extra_pclk_cycle_cnt;
  348. u32 dsc_extra_disp_width;
  349. bool poms_align_vsync;
  350. u32 dce_bytes_per_line;
  351. spinlock_t *enc_spinlock;
  352. enum sde_enc_enable_state enable_state;
  353. struct mutex *vblank_ctl_lock;
  354. atomic_t vblank_refcount;
  355. atomic_t wbirq_refcount;
  356. atomic_t vsync_cnt;
  357. ktime_t last_vsync_timestamp;
  358. atomic_t underrun_cnt;
  359. atomic_t pending_kickoff_cnt;
  360. atomic_t pending_retire_fence_cnt;
  361. atomic_t pending_ctl_start_cnt;
  362. wait_queue_head_t pending_kickoff_wq;
  363. u32 kickoff_timeout_ms;
  364. struct sde_encoder_irq irq[INTR_IDX_MAX];
  365. bool has_intf_te;
  366. bool cont_splash_enabled;
  367. bool in_clone_mode;
  368. int vfp_cached;
  369. enum frame_trigger_mode_type frame_trigger_mode;
  370. bool recovered;
  371. bool autorefresh_disable_trans;
  372. };
  373. static inline int sde_encoder_phys_inc_pending(struct sde_encoder_phys *phys)
  374. {
  375. return atomic_inc_return(&phys->pending_kickoff_cnt);
  376. }
  377. /**
  378. * struct sde_encoder_phys_vid - sub-class of sde_encoder_phys to handle video
  379. * mode specific operations
  380. * @base: Baseclass physical encoder structure
  381. * @timing_params: Current timing parameter
  382. * @error_count: Number of consecutive kickoffs that experienced an error
  383. */
  384. struct sde_encoder_phys_vid {
  385. struct sde_encoder_phys base;
  386. struct intf_timing_params timing_params;
  387. int error_count;
  388. };
  389. /**
  390. * struct sde_encoder_phys_cmd_autorefresh - autorefresh state tracking
  391. * @cfg: current active autorefresh configuration
  392. * @kickoff_cnt: atomic count tracking autorefresh done irq kickoffs pending
  393. * @kickoff_wq: wait queue for waiting on autorefresh done irq
  394. */
  395. struct sde_encoder_phys_cmd_autorefresh {
  396. struct sde_hw_autorefresh cfg;
  397. atomic_t kickoff_cnt;
  398. wait_queue_head_t kickoff_wq;
  399. };
  400. /**
  401. * struct sde_encoder_phys_cmd_te_timestamp - list node to keep track of
  402. * rd_ptr/TE timestamp
  403. * @list: list node
  404. * @timestamp: TE timestamp
  405. */
  406. struct sde_encoder_phys_cmd_te_timestamp {
  407. struct list_head list;
  408. ktime_t timestamp;
  409. };
  410. /**
  411. * struct sde_encoder_phys_cmd - sub-class of sde_encoder_phys to handle command
  412. * mode specific operations
  413. * @base: Baseclass physical encoder structure
  414. * @stream_sel: Stream selection for multi-stream interfaces
  415. * @frame_tx_timeout_report_cnt: number of pp_done/ctl_done irq timeout errors
  416. * @autorefresh: autorefresh feature state
  417. * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
  418. * @pending_vblank_wq: Wait queue for blocking until VBLANK received
  419. * @wr_ptr_wait_success: log wr_ptr_wait success for release fence trigger
  420. * @te_timestamp_list: List head for the TE timestamp list
  421. * @te_timestamp: Array of size MAX_TE_PROFILE_COUNT te_timestamp_list elements
  422. * @qsync_threshold_lines: tearcheck threshold lines calculated based on qsync_min_fps
  423. */
  424. struct sde_encoder_phys_cmd {
  425. struct sde_encoder_phys base;
  426. int stream_sel;
  427. int frame_tx_timeout_report_cnt;
  428. struct sde_encoder_phys_cmd_autorefresh autorefresh;
  429. atomic_t pending_vblank_cnt;
  430. wait_queue_head_t pending_vblank_wq;
  431. bool wr_ptr_wait_success;
  432. struct list_head te_timestamp_list;
  433. struct sde_encoder_phys_cmd_te_timestamp
  434. te_timestamp[MAX_TE_PROFILE_COUNT];
  435. u32 qsync_threshold_lines;
  436. };
  437. /**
  438. * struct sde_encoder_phys_wb - sub-class of sde_encoder_phys to handle
  439. * writeback specific operations
  440. * @base: Baseclass physical encoder structure
  441. * @hw_wb: Hardware interface to the wb registers
  442. * @wbdone_timeout: Timeout value for writeback done in msec
  443. * @wb_cfg: Writeback hardware configuration
  444. * @cdp_cfg: Writeback CDP configuration
  445. * @wb_roi: Writeback region-of-interest
  446. * @wb_fmt: Writeback pixel format
  447. * @wb_fb: Pointer to current writeback framebuffer
  448. * @wb_aspace: Pointer to current writeback address space
  449. * @old_fb: Pointer to old writeback framebuffer
  450. * @old_aspace: Pointer to old writeback address space
  451. * @aspace: address space identifier for non-secure/secure domain
  452. * @wb_dev: Pointer to writeback device
  453. * @bo_disable: Buffer object(s) to use during the disabling state
  454. * @fb_disable: Frame buffer to use during the disabling state
  455. * @sc_cfg: Stores wb system cache config
  456. * @crtc: Pointer to drm_crtc
  457. * @prog_line: Cached programmable line value used to trigger early wb-fence
  458. */
  459. struct sde_encoder_phys_wb {
  460. struct sde_encoder_phys base;
  461. struct sde_hw_wb *hw_wb;
  462. u32 wbdone_timeout;
  463. struct sde_hw_wb_cfg wb_cfg;
  464. struct sde_hw_wb_cdp_cfg cdp_cfg;
  465. struct sde_rect wb_roi;
  466. const struct sde_format *wb_fmt;
  467. struct drm_framebuffer *wb_fb;
  468. struct msm_gem_address_space *wb_aspace;
  469. struct drm_framebuffer *old_fb;
  470. struct msm_gem_address_space *old_aspace;
  471. struct msm_gem_address_space *aspace[SDE_IOMMU_DOMAIN_MAX];
  472. struct sde_wb_device *wb_dev;
  473. struct drm_gem_object *bo_disable[SDE_MAX_PLANES];
  474. struct drm_framebuffer *fb_disable;
  475. struct sde_hw_wb_sc_cfg sc_cfg;
  476. struct drm_crtc *crtc;
  477. u32 prog_line;
  478. };
  479. /**
  480. * struct sde_enc_phys_init_params - initialization parameters for phys encs
  481. * @sde_kms: Pointer to the sde_kms top level
  482. * @parent: Pointer to the containing virtual encoder
  483. * @parent_ops: Callbacks exposed by the parent to the phys_enc
  484. * @split_role: Role to play in a split-panel configuration
  485. * @intf_idx: Interface index this phys_enc will control
  486. * @wb_idx: Writeback index this phys_enc will control
  487. * @comp_type: Type of compression supported
  488. * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
  489. */
  490. struct sde_enc_phys_init_params {
  491. struct sde_kms *sde_kms;
  492. struct drm_encoder *parent;
  493. struct sde_encoder_virt_ops parent_ops;
  494. enum sde_enc_split_role split_role;
  495. enum sde_intf intf_idx;
  496. enum sde_wb wb_idx;
  497. enum msm_display_compression_type comp_type;
  498. spinlock_t *enc_spinlock;
  499. struct mutex *vblank_ctl_lock;
  500. };
  501. /**
  502. * sde_encoder_wait_info - container for passing arguments to irq wait functions
  503. * @wq: wait queue structure
  504. * @atomic_cnt: wait until atomic_cnt equals zero
  505. * @count_check: wait for specific atomic_cnt instead of zero.
  506. * @timeout_ms: timeout value in milliseconds
  507. */
  508. struct sde_encoder_wait_info {
  509. wait_queue_head_t *wq;
  510. atomic_t *atomic_cnt;
  511. u32 count_check;
  512. s64 timeout_ms;
  513. };
  514. /**
  515. * sde_encoder_phys_vid_init - Construct a new video mode physical encoder
  516. * @p: Pointer to init params structure
  517. * Return: Error code or newly allocated encoder
  518. */
  519. struct sde_encoder_phys *sde_encoder_phys_vid_init(
  520. struct sde_enc_phys_init_params *p);
  521. /**
  522. * sde_encoder_phys_cmd_init - Construct a new command mode physical encoder
  523. * @p: Pointer to init params structure
  524. * Return: Error code or newly allocated encoder
  525. */
  526. struct sde_encoder_phys *sde_encoder_phys_cmd_init(
  527. struct sde_enc_phys_init_params *p);
  528. /**
  529. * sde_encoder_phys_wb_init - Construct a new writeback physical encoder
  530. * @p: Pointer to init params structure
  531. * Return: Error code or newly allocated encoder
  532. */
  533. #if IS_ENABLED(CONFIG_DRM_SDE_WB)
  534. struct sde_encoder_phys *sde_encoder_phys_wb_init(
  535. struct sde_enc_phys_init_params *p);
  536. #else
  537. static inline
  538. struct sde_encoder_phys *sde_encoder_phys_wb_init(
  539. struct sde_enc_phys_init_params *p)
  540. {
  541. return NULL;
  542. }
  543. #endif /* CONFIG_DRM_SDE_WB */
  544. void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc,
  545. struct drm_framebuffer *fb, const struct sde_format *format,
  546. struct sde_rect *wb_roi);
  547. /**
  548. * sde_encoder_helper_get_pp_line_count - pingpong linecount helper function
  549. * @drm_enc: Pointer to drm encoder structure
  550. * @info: structure used to populate the pp line count information
  551. */
  552. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  553. struct sde_hw_pp_vsync_info *info);
  554. /**
  555. * sde_encoder_helper_get_kickoff_timeout_ms- get the kickoff timeout value based on fps
  556. * @drm_enc: Pointer to drm encoder structure
  557. * Returns: Kickoff timeout in milli seconds
  558. */
  559. u32 sde_encoder_helper_get_kickoff_timeout_ms(struct drm_encoder *drm_enc);
  560. /**
  561. * sde_encoder_helper_trigger_flush - control flush helper function
  562. * This helper function may be optionally specified by physical
  563. * encoders if they require ctl_flush triggering.
  564. * @phys_enc: Pointer to physical encoder structure
  565. */
  566. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc);
  567. /**
  568. * sde_encoder_helper_trigger_start - control start helper function
  569. * This helper function may be optionally specified by physical
  570. * encoders if they require ctl_start triggering.
  571. * @phys_enc: Pointer to physical encoder structure
  572. */
  573. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc);
  574. /**
  575. * sde_encoder_helper_vsync_config - configure vsync source for cmd mode
  576. * @phys_enc: Pointer to physical encoder structure
  577. * @vsync_source: vsync source selection
  578. */
  579. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc, u32 vsync_source);
  580. /**
  581. * sde_encoder_helper_wait_event_timeout - wait for event with timeout
  582. * taking into account that jiffies may jump between reads leading to
  583. * incorrectly detected timeouts. Prevent failure in this scenario by
  584. * making sure that elapsed time during wait is valid.
  585. * @drm_id: drm object id for logging
  586. * @hw_id: hw instance id for logging
  587. * @info: wait info structure
  588. */
  589. int sde_encoder_helper_wait_event_timeout(
  590. int32_t drm_id,
  591. int32_t hw_id,
  592. struct sde_encoder_wait_info *info);
  593. /*
  594. * sde_encoder_get_fps - get the allowed panel jitter in nanoseconds
  595. * @frame_rate: custom input frame rate
  596. * @jitter_num: jitter numerator value
  597. * @jitter_denom: jitter denomerator value,
  598. * @l_bound: lower frame period boundary
  599. * @u_bound: upper frame period boundary
  600. */
  601. void sde_encoder_helper_get_jitter_bounds_ns(uint32_t frame_rate,
  602. u32 jitter_num, u32 jitter_denom,
  603. ktime_t *l_bound, ktime_t *u_bound);
  604. /**
  605. * sde_encoder_helper_switch_vsync - switch vsync source to WD or default
  606. * @drm_enc: Pointer to drm encoder structure
  607. * @watchdog_te: switch vsync source to watchdog TE
  608. */
  609. int sde_encoder_helper_switch_vsync(struct drm_encoder *drm_enc,
  610. bool watchdog_te);
  611. /**
  612. * sde_encoder_helper_hw_reset - issue ctl hw reset
  613. * This helper function may be optionally specified by physical
  614. * encoders if they require ctl hw reset. If state is currently
  615. * SDE_ENC_ERR_NEEDS_HW_RESET, it is set back to SDE_ENC_ENABLED.
  616. * @phys_enc: Pointer to physical encoder structure
  617. */
  618. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc);
  619. static inline enum sde_3d_blend_mode sde_encoder_helper_get_3d_blend_mode(
  620. struct sde_encoder_phys *phys_enc)
  621. {
  622. struct msm_display_topology def;
  623. enum sde_enc_split_role split_role;
  624. int ret, num_lm;
  625. bool mode_3d;
  626. if (!phys_enc || phys_enc->enable_state == SDE_ENC_DISABLING ||
  627. !phys_enc->connector || !phys_enc->connector->state)
  628. return BLEND_3D_NONE;
  629. ret = sde_connector_state_get_topology
  630. (phys_enc->connector->state, &def);
  631. if (ret)
  632. return BLEND_3D_NONE;
  633. if (phys_enc->hw_intf && phys_enc->hw_intf->cfg.split_link_en)
  634. return BLEND_3D_NONE;
  635. num_lm = def.num_lm;
  636. mode_3d = (num_lm > def.num_enc) ? true : false;
  637. split_role = phys_enc->split_role;
  638. if (split_role == ENC_ROLE_SOLO && num_lm == 2 && mode_3d)
  639. return BLEND_3D_H_ROW_INT;
  640. if ((split_role == ENC_ROLE_MASTER || split_role == ENC_ROLE_SLAVE)
  641. && num_lm == 4 && mode_3d)
  642. return BLEND_3D_H_ROW_INT;
  643. return BLEND_3D_NONE;
  644. }
  645. /**
  646. * sde_encoder_phys_is_cwb_disabling - Check if CWB encoder attached to this
  647. * CRTC and it is in SDE_ENC_DISABLING state.
  648. * @phys_enc: Pointer to physical encoder structure
  649. * @crtc: drm crtc
  650. * @Return: true if cwb encoder is in disabling state
  651. */
  652. static inline bool sde_encoder_phys_is_cwb_disabling(
  653. struct sde_encoder_phys *phys, struct drm_crtc *crtc)
  654. {
  655. struct sde_encoder_phys_wb *wb_enc;
  656. if (!phys || !phys->in_clone_mode ||
  657. phys->enable_state != SDE_ENC_DISABLING)
  658. return false;
  659. wb_enc = container_of(phys, struct sde_encoder_phys_wb, base);
  660. return (wb_enc->crtc == crtc) ? true : false;
  661. }
  662. /**
  663. * sde_encoder_helper_split_config - split display configuration helper function
  664. * This helper function may be used by physical encoders to configure
  665. * the split display related registers.
  666. * @phys_enc: Pointer to physical encoder structure
  667. * @interface: enum sde_intf setting
  668. */
  669. void sde_encoder_helper_split_config(
  670. struct sde_encoder_phys *phys_enc,
  671. enum sde_intf interface);
  672. /**
  673. * sde_encoder_helper_reset_mixers - reset mixers associated with phys enc
  674. * @phys_enc: Pointer to physical encoder structure
  675. * @fb: Optional fb for specifying new mixer output resolution, may be NULL
  676. * Return: Zero on success
  677. */
  678. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  679. struct drm_framebuffer *fb);
  680. /**
  681. * sde_encoder_helper_hw_fence_sw_override - reset mixers and do hw-fence sw override
  682. * @phys_enc: Pointer to physical encoder structure
  683. * @ctl: Pointer to hw_ctl structure
  684. */
  685. void sde_encoder_helper_hw_fence_sw_override(struct sde_encoder_phys *phys_enc,
  686. struct sde_hw_ctl *ctl);
  687. /**
  688. * sde_encoder_helper_report_irq_timeout - utility to report error that irq has
  689. * timed out, including reporting frame error event to crtc and debug dump
  690. * @phys_enc: Pointer to physical encoder structure
  691. * @intr_idx: Failing interrupt index
  692. */
  693. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  694. enum sde_intr_idx intr_idx);
  695. /**
  696. * sde_encoder_helper_wait_for_irq - utility to wait on an irq.
  697. * note: will call sde_encoder_helper_wait_for_irq on timeout
  698. * @phys_enc: Pointer to physical encoder structure
  699. * @intr_idx: encoder interrupt index
  700. * @wait_info: wait info struct
  701. * @Return: 0 or -ERROR
  702. */
  703. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  704. enum sde_intr_idx intr_idx,
  705. struct sde_encoder_wait_info *wait_info);
  706. /**
  707. * sde_encoder_helper_register_irq - register and enable an irq
  708. * @phys_enc: Pointer to physical encoder structure
  709. * @intr_idx: encoder interrupt index
  710. * @Return: 0 or -ERROR
  711. */
  712. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  713. enum sde_intr_idx intr_idx);
  714. /**
  715. * sde_encoder_helper_unregister_irq - unregister and disable an irq
  716. * @phys_enc: Pointer to physical encoder structure
  717. * @intr_idx: encoder interrupt index
  718. * @Return: 0 or -ERROR
  719. */
  720. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  721. enum sde_intr_idx intr_idx);
  722. /**
  723. * sde_encoder_helper_update_intf_cfg - update interface configuration for
  724. * single control path.
  725. * @phys_enc: Pointer to physical encoder structure
  726. */
  727. void sde_encoder_helper_update_intf_cfg(
  728. struct sde_encoder_phys *phys_enc);
  729. /**
  730. * _sde_encoder_phys_is_dual_ctl - check if encoder needs dual ctl path.
  731. * @phys_enc: Pointer to physical encoder structure
  732. * @Return: true if dual ctl paths else false
  733. */
  734. static inline bool _sde_encoder_phys_is_dual_ctl(
  735. struct sde_encoder_phys *phys_enc)
  736. {
  737. struct sde_kms *sde_kms;
  738. enum sde_rm_topology_name topology;
  739. const struct sde_rm_topology_def* def;
  740. if (!phys_enc) {
  741. pr_err("invalid phys_enc\n");
  742. return false;
  743. }
  744. sde_kms = phys_enc->sde_kms;
  745. if (!sde_kms) {
  746. pr_err("invalid kms\n");
  747. return false;
  748. }
  749. topology = sde_connector_get_topology_name(phys_enc->connector);
  750. def = sde_rm_topology_get_topology_def(&sde_kms->rm, topology);
  751. if (IS_ERR_OR_NULL(def)) {
  752. pr_err("invalid topology\n");
  753. return false;
  754. }
  755. return (def->num_ctl == 2) ? true : false;
  756. }
  757. /**
  758. * _sde_encoder_phys_is_ppsplit - check if pp_split is enabled
  759. * @phys_enc: Pointer to physical encoder structure
  760. * @Return: true or false
  761. */
  762. static inline bool _sde_encoder_phys_is_ppsplit(
  763. struct sde_encoder_phys *phys_enc)
  764. {
  765. enum sde_rm_topology_name topology;
  766. if (!phys_enc) {
  767. pr_err("invalid phys_enc\n");
  768. return false;
  769. }
  770. topology = sde_connector_get_topology_name(phys_enc->connector);
  771. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  772. return true;
  773. return false;
  774. }
  775. static inline bool sde_encoder_phys_needs_single_flush(
  776. struct sde_encoder_phys *phys_enc)
  777. {
  778. if (!phys_enc)
  779. return false;
  780. return (_sde_encoder_phys_is_ppsplit(phys_enc) ||
  781. !_sde_encoder_phys_is_dual_ctl(phys_enc));
  782. }
  783. /**
  784. * sde_encoder_helper_hw_fence_extended_wait - extended kickoff wait for hw-fence enabled case
  785. * @phys_enc: Pointer to physical encoder structure
  786. * @ctl: Pointer to hw ctl structure
  787. * @wait_info: Pointer to wait_info structure
  788. * @wait_type: Enum indicating the irq to wait for
  789. * Returns: -ETIMEDOUT in the case that the extended wait times out, 0 otherwise
  790. */
  791. int sde_encoder_helper_hw_fence_extended_wait(struct sde_encoder_phys *phys_enc,
  792. struct sde_hw_ctl *ctl, struct sde_encoder_wait_info *wait_info, int wait_type);
  793. /**
  794. * sde_encoder_helper_phys_disable - helper function to disable virt encoder
  795. * @phys_enc: Pointer to physical encoder structure
  796. * @wb_enc: Pointer to writeback encoder structure
  797. */
  798. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  799. struct sde_encoder_phys_wb *wb_enc);
  800. /**
  801. * sde_encoder_helper_phys_reset - helper function to reset virt encoder
  802. * if vsync is missing on phys encoder
  803. * @phys_enc: Pointer to physical encoder structure
  804. */
  805. void sde_encoder_helper_phys_reset(struct sde_encoder_phys *phys_enc);
  806. /**
  807. * sde_encoder_helper_setup_misr - helper function to setup misr
  808. * @phys_enc: Pointer to physical encoder structure
  809. * @enable: enable/disable flag
  810. * @frame_count: frame count for misr
  811. */
  812. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  813. bool enable, u32 frame_count);
  814. /**
  815. * sde_encoder_helper_collect_misr - helper function to collect misr
  816. * @phys_enc: Pointer to physical encoder structure
  817. * @nonblock: blocking/non-blocking flag
  818. * @misr_value: pointer to misr value
  819. * @Return: zero on success
  820. */
  821. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  822. bool nonblock, u32 *misr_value);
  823. #endif /* __sde_encoder_phys_H__ */