hal_7850_rx.h 4.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155
  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_7850_RX_H_
  19. #define _HAL_7850_RX_H_
  20. #include "qdf_util.h"
  21. #include "qdf_types.h"
  22. #include "qdf_lock.h"
  23. #include "qdf_mem.h"
  24. #include "qdf_nbuf.h"
  25. #include "tcl_data_cmd.h"
  26. //#include "mac_tcl_reg_seq_hwioreg.h"
  27. #include "phyrx_rssi_legacy.h"
  28. #include "rx_msdu_start.h"
  29. #include "tlv_tag_def.h"
  30. #include "hal_hw_headers.h"
  31. #include "hal_internal.h"
  32. #include "cdp_txrx_mon_struct.h"
  33. #include "qdf_trace.h"
  34. #include "hal_rx.h"
  35. #include "hal_tx.h"
  36. #include "dp_types.h"
  37. #include "hal_api_mon.h"
  38. #include "phyrx_other_receive_info_ru_details.h"
  39. #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
  40. (uint8_t *)(link_desc_va) + \
  41. RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  42. #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
  43. (uint8_t *)(msdu0) + \
  44. RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  45. #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
  46. (uint8_t *)(ent_ring_desc) + \
  47. RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  48. #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
  49. (uint8_t *)(dst_ring_desc) + \
  50. REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  51. #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
  52. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID)
  53. #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
  54. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID)
  55. #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \
  56. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_PEER_ID)
  57. #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
  58. do { \
  59. reg_val &= \
  60. ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\
  61. HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
  62. reg_val |= \
  63. HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
  64. AGING_LIST_ENABLE, 1) |\
  65. HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
  66. AGING_FLUSH_ENABLE, 1);\
  67. HAL_REG_WRITE((soc), \
  68. HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
  69. REO_REG_REG_BASE), \
  70. (reg_val)); \
  71. reg_val = \
  72. HAL_REG_READ((soc), \
  73. HWIO_REO_R0_MISC_CTL_ADDR( \
  74. REO_REG_REG_BASE)); \
  75. reg_val &= \
  76. ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
  77. reg_val |= \
  78. HAL_SM(HWIO_REO_R0_MISC_CTL, \
  79. FRAGMENT_DEST_RING, \
  80. (reo_params)->frag_dst_ring); \
  81. reg_val &= \
  82. (~HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK |\
  83. (REO_REMAP_TCL << HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT)); \
  84. HAL_REG_WRITE((soc), \
  85. HWIO_REO_R0_MISC_CTL_ADDR( \
  86. REO_REG_REG_BASE), \
  87. (reg_val)); \
  88. } while (0)
  89. #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
  90. ((struct rx_msdu_desc_info *) \
  91. _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
  92. RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
  93. #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
  94. ((struct rx_msdu_details *) \
  95. _OFFSET_TO_BYTE_PTR((link_desc),\
  96. RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET))
  97. #if defined(QCA_WIFI_WCN7850) && defined(WLAN_CFR_ENABLE) && \
  98. defined(WLAN_ENH_CFR_ENABLE)
  99. static inline
  100. void hal_rx_get_bb_info_7850(void *rx_tlv,
  101. void *ppdu_info_hdl)
  102. {
  103. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  104. ppdu_info->cfr_info.bb_captured_channel =
  105. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
  106. ppdu_info->cfr_info.bb_captured_timeout =
  107. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
  108. ppdu_info->cfr_info.bb_captured_reason =
  109. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
  110. }
  111. static inline
  112. void hal_rx_get_rtt_info_7850(void *rx_tlv,
  113. void *ppdu_info_hdl)
  114. {
  115. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  116. ppdu_info->cfr_info.rx_location_info_valid =
  117. HAL_RX_GET(rx_tlv, PHYRX_LOCATION,
  118. RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID);
  119. ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
  120. HAL_RX_GET(rx_tlv,
  121. RX_LOCATION_INFO,
  122. RTT_CHE_BUFFER_POINTER_LOW32);
  123. ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
  124. HAL_RX_GET(rx_tlv,
  125. RX_LOCATION_INFO,
  126. RTT_CHE_BUFFER_POINTER_HIGH8);
  127. // TODO Beryllium - Changed reserved8 to reserved3 to avoid
  128. // compilation failure for wcn7850
  129. ppdu_info->cfr_info.chan_capture_status =
  130. HAL_RX_GET(rx_tlv,
  131. RX_LOCATION_INFO,
  132. RESERVED_3);
  133. }
  134. #endif
  135. #endif