hal_srng.c 61 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "hal_hw_headers.h"
  19. #include "hal_api.h"
  20. #include "hal_reo.h"
  21. #include "target_type.h"
  22. #include "qdf_module.h"
  23. #include "wcss_version.h"
  24. #ifdef QCA_WIFI_QCA8074
  25. void hal_qca6290_attach(struct hal_soc *hal);
  26. #endif
  27. #ifdef QCA_WIFI_QCA8074
  28. void hal_qca8074_attach(struct hal_soc *hal);
  29. #endif
  30. #if defined(QCA_WIFI_QCA8074V2) || defined(QCA_WIFI_QCA6018) || \
  31. defined(QCA_WIFI_QCA9574)
  32. void hal_qca8074v2_attach(struct hal_soc *hal);
  33. #endif
  34. #ifdef QCA_WIFI_QCA6390
  35. void hal_qca6390_attach(struct hal_soc *hal);
  36. #endif
  37. #ifdef QCA_WIFI_QCA6490
  38. void hal_qca6490_attach(struct hal_soc *hal);
  39. #endif
  40. #ifdef QCA_WIFI_QCN9000
  41. void hal_qcn9000_attach(struct hal_soc *hal);
  42. #endif
  43. #ifdef QCA_WIFI_QCN9224
  44. void hal_qcn9224_attach(struct hal_soc *hal);
  45. #endif
  46. #ifdef QCA_WIFI_QCN6122
  47. void hal_qcn6122_attach(struct hal_soc *hal);
  48. #endif
  49. #ifdef QCA_WIFI_QCA6750
  50. void hal_qca6750_attach(struct hal_soc *hal);
  51. #endif
  52. #ifdef QCA_WIFI_QCA5018
  53. void hal_qca5018_attach(struct hal_soc *hal);
  54. #endif
  55. #ifdef QCA_WIFI_WCN7850
  56. void hal_wcn7850_attach(struct hal_soc *hal);
  57. #endif
  58. #ifdef ENABLE_VERBOSE_DEBUG
  59. bool is_hal_verbose_debug_enabled;
  60. #endif
  61. #define HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x4)
  62. #define HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x8)
  63. #define HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc)
  64. #define HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10)
  65. #ifdef ENABLE_HAL_REG_WR_HISTORY
  66. struct hal_reg_write_fail_history hal_reg_wr_hist;
  67. void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc,
  68. uint32_t offset,
  69. uint32_t wr_val, uint32_t rd_val)
  70. {
  71. struct hal_reg_write_fail_entry *record;
  72. int idx;
  73. idx = hal_history_get_next_index(&hal_soc->reg_wr_fail_hist->index,
  74. HAL_REG_WRITE_HIST_SIZE);
  75. record = &hal_soc->reg_wr_fail_hist->record[idx];
  76. record->timestamp = qdf_get_log_timestamp();
  77. record->reg_offset = offset;
  78. record->write_val = wr_val;
  79. record->read_val = rd_val;
  80. }
  81. static void hal_reg_write_fail_history_init(struct hal_soc *hal)
  82. {
  83. hal->reg_wr_fail_hist = &hal_reg_wr_hist;
  84. qdf_atomic_set(&hal->reg_wr_fail_hist->index, -1);
  85. }
  86. #else
  87. static void hal_reg_write_fail_history_init(struct hal_soc *hal)
  88. {
  89. }
  90. #endif
  91. /**
  92. * hal_get_srng_ring_id() - get the ring id of a descriped ring
  93. * @hal: hal_soc data structure
  94. * @ring_type: type enum describing the ring
  95. * @ring_num: which ring of the ring type
  96. * @mac_id: which mac does the ring belong to (or 0 for non-lmac rings)
  97. *
  98. * Return: the ring id or -EINVAL if the ring does not exist.
  99. */
  100. static int hal_get_srng_ring_id(struct hal_soc *hal, int ring_type,
  101. int ring_num, int mac_id)
  102. {
  103. struct hal_hw_srng_config *ring_config =
  104. HAL_SRNG_CONFIG(hal, ring_type);
  105. int ring_id;
  106. if (ring_num >= ring_config->max_rings) {
  107. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO,
  108. "%s: ring_num exceeded maximum no. of supported rings",
  109. __func__);
  110. /* TODO: This is a programming error. Assert if this happens */
  111. return -EINVAL;
  112. }
  113. /*
  114. * For BE, dmac_cmn_src_rxbuf_ring is set. If this is set
  115. * and ring is dst and also lmac ring then provide ring id per lmac
  116. */
  117. if (ring_config->lmac_ring &&
  118. (!hal->dmac_cmn_src_rxbuf_ring ||
  119. ring_config->ring_dir == HAL_SRNG_DST_RING)) {
  120. ring_id = (ring_config->start_ring_id + ring_num +
  121. (mac_id * HAL_MAX_RINGS_PER_LMAC));
  122. } else {
  123. ring_id = ring_config->start_ring_id + ring_num;
  124. }
  125. return ring_id;
  126. }
  127. static struct hal_srng *hal_get_srng(struct hal_soc *hal, int ring_id)
  128. {
  129. /* TODO: Should we allocate srng structures dynamically? */
  130. return &(hal->srng_list[ring_id]);
  131. }
  132. #ifndef SHADOW_REG_CONFIG_DISABLED
  133. #define HP_OFFSET_IN_REG_START 1
  134. #define OFFSET_FROM_HP_TO_TP 4
  135. static void hal_update_srng_hp_tp_address(struct hal_soc *hal_soc,
  136. int shadow_config_index,
  137. int ring_type,
  138. int ring_num)
  139. {
  140. struct hal_srng *srng;
  141. int ring_id;
  142. struct hal_hw_srng_config *ring_config =
  143. HAL_SRNG_CONFIG(hal_soc, ring_type);
  144. ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, 0);
  145. if (ring_id < 0)
  146. return;
  147. srng = hal_get_srng(hal_soc, ring_id);
  148. if (ring_config->ring_dir == HAL_SRNG_DST_RING) {
  149. srng->u.dst_ring.tp_addr = SHADOW_REGISTER(shadow_config_index)
  150. + hal_soc->dev_base_addr;
  151. hal_debug("tp_addr=%pK dev base addr %pK index %u",
  152. srng->u.dst_ring.tp_addr, hal_soc->dev_base_addr,
  153. shadow_config_index);
  154. } else {
  155. srng->u.src_ring.hp_addr = SHADOW_REGISTER(shadow_config_index)
  156. + hal_soc->dev_base_addr;
  157. hal_debug("hp_addr=%pK dev base addr %pK index %u",
  158. srng->u.src_ring.hp_addr,
  159. hal_soc->dev_base_addr, shadow_config_index);
  160. }
  161. }
  162. #endif
  163. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  164. void hal_set_one_target_reg_config(struct hal_soc *hal,
  165. uint32_t target_reg_offset,
  166. int list_index)
  167. {
  168. int i = list_index;
  169. qdf_assert_always(i < MAX_GENERIC_SHADOW_REG);
  170. hal->list_shadow_reg_config[i].target_register =
  171. target_reg_offset;
  172. hal->num_generic_shadow_regs_configured++;
  173. }
  174. qdf_export_symbol(hal_set_one_target_reg_config);
  175. #define REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET 0x4
  176. #define MAX_REO_REMAP_SHADOW_REGS 4
  177. QDF_STATUS hal_set_shadow_regs(void *hal_soc)
  178. {
  179. uint32_t target_reg_offset;
  180. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  181. int i;
  182. struct hal_hw_srng_config *srng_config =
  183. &hal->hw_srng_table[WBM2SW_RELEASE];
  184. uint32_t reo_reg_base;
  185. reo_reg_base = hal_get_reo_reg_base_offset(hal_soc);
  186. target_reg_offset =
  187. HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(reo_reg_base);
  188. for (i = 0; i < MAX_REO_REMAP_SHADOW_REGS; i++) {
  189. hal_set_one_target_reg_config(hal, target_reg_offset, i);
  190. target_reg_offset += REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET;
  191. }
  192. target_reg_offset = srng_config->reg_start[HP_OFFSET_IN_REG_START];
  193. target_reg_offset += (srng_config->reg_size[HP_OFFSET_IN_REG_START]
  194. * HAL_IPA_TX_COMP_RING_IDX);
  195. hal_set_one_target_reg_config(hal, target_reg_offset, i);
  196. return QDF_STATUS_SUCCESS;
  197. }
  198. qdf_export_symbol(hal_set_shadow_regs);
  199. QDF_STATUS hal_construct_shadow_regs(void *hal_soc)
  200. {
  201. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  202. int shadow_config_index = hal->num_shadow_registers_configured;
  203. int i;
  204. int num_regs = hal->num_generic_shadow_regs_configured;
  205. for (i = 0; i < num_regs; i++) {
  206. qdf_assert_always(shadow_config_index < MAX_SHADOW_REGISTERS);
  207. hal->shadow_config[shadow_config_index].addr =
  208. hal->list_shadow_reg_config[i].target_register;
  209. hal->list_shadow_reg_config[i].shadow_config_index =
  210. shadow_config_index;
  211. hal->list_shadow_reg_config[i].va =
  212. SHADOW_REGISTER(shadow_config_index) +
  213. (uintptr_t)hal->dev_base_addr;
  214. hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x",
  215. hal->shadow_config[shadow_config_index].addr,
  216. SHADOW_REGISTER(shadow_config_index),
  217. shadow_config_index);
  218. shadow_config_index++;
  219. hal->num_shadow_registers_configured++;
  220. }
  221. return QDF_STATUS_SUCCESS;
  222. }
  223. qdf_export_symbol(hal_construct_shadow_regs);
  224. #endif
  225. #ifndef SHADOW_REG_CONFIG_DISABLED
  226. QDF_STATUS hal_set_one_shadow_config(void *hal_soc,
  227. int ring_type,
  228. int ring_num)
  229. {
  230. uint32_t target_register;
  231. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  232. struct hal_hw_srng_config *srng_config = &hal->hw_srng_table[ring_type];
  233. int shadow_config_index = hal->num_shadow_registers_configured;
  234. if (shadow_config_index >= MAX_SHADOW_REGISTERS) {
  235. QDF_ASSERT(0);
  236. return QDF_STATUS_E_RESOURCES;
  237. }
  238. hal->num_shadow_registers_configured++;
  239. target_register = srng_config->reg_start[HP_OFFSET_IN_REG_START];
  240. target_register += (srng_config->reg_size[HP_OFFSET_IN_REG_START]
  241. *ring_num);
  242. /* if the ring is a dst ring, we need to shadow the tail pointer */
  243. if (srng_config->ring_dir == HAL_SRNG_DST_RING)
  244. target_register += OFFSET_FROM_HP_TO_TP;
  245. hal->shadow_config[shadow_config_index].addr = target_register;
  246. /* update hp/tp addr in the hal_soc structure*/
  247. hal_update_srng_hp_tp_address(hal_soc, shadow_config_index, ring_type,
  248. ring_num);
  249. hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x, ring_type %d, ring num %d",
  250. target_register,
  251. SHADOW_REGISTER(shadow_config_index),
  252. shadow_config_index,
  253. ring_type, ring_num);
  254. return QDF_STATUS_SUCCESS;
  255. }
  256. qdf_export_symbol(hal_set_one_shadow_config);
  257. QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc)
  258. {
  259. int ring_type, ring_num;
  260. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  261. for (ring_type = 0; ring_type < MAX_RING_TYPES; ring_type++) {
  262. struct hal_hw_srng_config *srng_config =
  263. &hal->hw_srng_table[ring_type];
  264. if (ring_type == CE_SRC ||
  265. ring_type == CE_DST ||
  266. ring_type == CE_DST_STATUS)
  267. continue;
  268. if (srng_config->lmac_ring)
  269. continue;
  270. for (ring_num = 0; ring_num < srng_config->max_rings;
  271. ring_num++)
  272. hal_set_one_shadow_config(hal_soc, ring_type, ring_num);
  273. }
  274. return QDF_STATUS_SUCCESS;
  275. }
  276. qdf_export_symbol(hal_construct_srng_shadow_regs);
  277. #else
  278. QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc)
  279. {
  280. return QDF_STATUS_SUCCESS;
  281. }
  282. qdf_export_symbol(hal_construct_srng_shadow_regs);
  283. QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type,
  284. int ring_num)
  285. {
  286. return QDF_STATUS_SUCCESS;
  287. }
  288. qdf_export_symbol(hal_set_one_shadow_config);
  289. #endif
  290. void hal_get_shadow_config(void *hal_soc,
  291. struct pld_shadow_reg_v2_cfg **shadow_config,
  292. int *num_shadow_registers_configured)
  293. {
  294. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  295. *shadow_config = hal->shadow_config;
  296. *num_shadow_registers_configured =
  297. hal->num_shadow_registers_configured;
  298. }
  299. qdf_export_symbol(hal_get_shadow_config);
  300. static bool hal_validate_shadow_register(struct hal_soc *hal,
  301. uint32_t *destination,
  302. uint32_t *shadow_address)
  303. {
  304. unsigned int index;
  305. uint32_t *shadow_0_offset = SHADOW_REGISTER(0) + hal->dev_base_addr;
  306. int destination_ba_offset =
  307. ((char *)destination) - (char *)hal->dev_base_addr;
  308. index = shadow_address - shadow_0_offset;
  309. if (index >= MAX_SHADOW_REGISTERS) {
  310. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  311. "%s: index %x out of bounds", __func__, index);
  312. goto error;
  313. } else if (hal->shadow_config[index].addr != destination_ba_offset) {
  314. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  315. "%s: sanity check failure, expected %x, found %x",
  316. __func__, destination_ba_offset,
  317. hal->shadow_config[index].addr);
  318. goto error;
  319. }
  320. return true;
  321. error:
  322. qdf_print("baddr %pK, desination %pK, shadow_address %pK s0offset %pK index %x",
  323. hal->dev_base_addr, destination, shadow_address,
  324. shadow_0_offset, index);
  325. QDF_BUG(0);
  326. return false;
  327. }
  328. static void hal_target_based_configure(struct hal_soc *hal)
  329. {
  330. /**
  331. * Indicate Initialization of srngs to avoid force wake
  332. * as umac power collapse is not enabled yet
  333. */
  334. hal->init_phase = true;
  335. switch (hal->target_type) {
  336. #ifdef QCA_WIFI_QCA6290
  337. case TARGET_TYPE_QCA6290:
  338. hal->use_register_windowing = true;
  339. hal_qca6290_attach(hal);
  340. break;
  341. #endif
  342. #ifdef QCA_WIFI_QCA6390
  343. case TARGET_TYPE_QCA6390:
  344. hal->use_register_windowing = true;
  345. hal_qca6390_attach(hal);
  346. break;
  347. #endif
  348. #ifdef QCA_WIFI_QCA6490
  349. case TARGET_TYPE_QCA6490:
  350. hal->use_register_windowing = true;
  351. hal_qca6490_attach(hal);
  352. break;
  353. #endif
  354. #ifdef QCA_WIFI_QCA6750
  355. case TARGET_TYPE_QCA6750:
  356. hal->use_register_windowing = true;
  357. hal->static_window_map = true;
  358. hal_qca6750_attach(hal);
  359. break;
  360. #endif
  361. #ifdef QCA_WIFI_WCN7850
  362. case TARGET_TYPE_WCN7850:
  363. hal->use_register_windowing = true;
  364. hal_wcn7850_attach(hal);
  365. hal->init_phase = false;
  366. break;
  367. #endif
  368. #if defined(QCA_WIFI_QCA8074) && defined(WIFI_TARGET_TYPE_3_0)
  369. case TARGET_TYPE_QCA8074:
  370. hal_qca8074_attach(hal);
  371. break;
  372. #endif
  373. #if defined(QCA_WIFI_QCA8074V2)
  374. case TARGET_TYPE_QCA8074V2:
  375. hal_qca8074v2_attach(hal);
  376. break;
  377. #endif
  378. #if defined(QCA_WIFI_QCA6018)
  379. case TARGET_TYPE_QCA6018:
  380. hal_qca8074v2_attach(hal);
  381. break;
  382. #endif
  383. #if defined(QCA_WIFI_QCA9574)
  384. case TARGET_TYPE_QCA9574:
  385. hal_qca8074v2_attach(hal);
  386. break;
  387. #endif
  388. #if defined(QCA_WIFI_QCN6122)
  389. case TARGET_TYPE_QCN6122:
  390. hal->use_register_windowing = true;
  391. /*
  392. * Static window map is enabled for qcn9000 to use 2mb bar
  393. * size and use multiple windows to write into registers.
  394. */
  395. hal->static_window_map = true;
  396. hal_qcn6122_attach(hal);
  397. break;
  398. #endif
  399. #ifdef QCA_WIFI_QCN9000
  400. case TARGET_TYPE_QCN9000:
  401. hal->use_register_windowing = true;
  402. /*
  403. * Static window map is enabled for qcn9000 to use 2mb bar
  404. * size and use multiple windows to write into registers.
  405. */
  406. hal->static_window_map = true;
  407. hal_qcn9000_attach(hal);
  408. break;
  409. #endif
  410. #ifdef QCA_WIFI_QCA5018
  411. case TARGET_TYPE_QCA5018:
  412. hal->use_register_windowing = true;
  413. hal->static_window_map = true;
  414. hal_qca5018_attach(hal);
  415. break;
  416. #endif
  417. #ifdef QCA_WIFI_QCN9224
  418. case TARGET_TYPE_QCN9224:
  419. hal->use_register_windowing = true;
  420. hal->static_window_map = true;
  421. hal_qcn9224_attach(hal);
  422. break;
  423. #endif
  424. default:
  425. break;
  426. }
  427. }
  428. uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl)
  429. {
  430. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  431. struct hif_target_info *tgt_info =
  432. hif_get_target_info_handle(hal_soc->hif_handle);
  433. return tgt_info->target_type;
  434. }
  435. qdf_export_symbol(hal_get_target_type);
  436. #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
  437. defined(FEATURE_HAL_DELAYED_REG_WRITE_V2)
  438. /**
  439. * hal_is_reg_write_tput_level_high() - throughput level for delayed reg writes
  440. * @hal: hal_soc pointer
  441. *
  442. * Return: true if throughput is high, else false.
  443. */
  444. static inline bool hal_is_reg_write_tput_level_high(struct hal_soc *hal)
  445. {
  446. int bw_level = hif_get_bandwidth_level(hal->hif_handle);
  447. return (bw_level >= PLD_BUS_WIDTH_MEDIUM) ? true : false;
  448. }
  449. static inline
  450. char *hal_fill_reg_write_srng_stats(struct hal_srng *srng,
  451. char *buf, qdf_size_t size)
  452. {
  453. qdf_scnprintf(buf, size, "enq %u deq %u coal %u direct %u",
  454. srng->wstats.enqueues, srng->wstats.dequeues,
  455. srng->wstats.coalesces, srng->wstats.direct);
  456. return buf;
  457. }
  458. /* bytes for local buffer */
  459. #define HAL_REG_WRITE_SRNG_STATS_LEN 100
  460. void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
  461. {
  462. struct hal_srng *srng;
  463. char buf[HAL_REG_WRITE_SRNG_STATS_LEN];
  464. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  465. srng = hal_get_srng(hal, HAL_SRNG_SW2TCL1);
  466. hal_debug("SW2TCL1: %s",
  467. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  468. srng = hal_get_srng(hal, HAL_SRNG_WBM2SW0_RELEASE);
  469. hal_debug("WBM2SW0: %s",
  470. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  471. srng = hal_get_srng(hal, HAL_SRNG_REO2SW1);
  472. hal_debug("REO2SW1: %s",
  473. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  474. srng = hal_get_srng(hal, HAL_SRNG_REO2SW2);
  475. hal_debug("REO2SW2: %s",
  476. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  477. srng = hal_get_srng(hal, HAL_SRNG_REO2SW3);
  478. hal_debug("REO2SW3: %s",
  479. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  480. }
  481. #ifdef FEATURE_HAL_DELAYED_REG_WRITE_V2
  482. /**
  483. * hal_dump_tcl_stats() - dump the TCL reg write stats
  484. * @hal: hal_soc pointer
  485. *
  486. * Return: None
  487. */
  488. static inline void hal_dump_tcl_stats(struct hal_soc *hal)
  489. {
  490. struct hal_srng *srng = hal_get_srng(hal, HAL_SRNG_SW2TCL1);
  491. uint32_t *hist = hal->tcl_stats.sched_delay;
  492. char buf[HAL_REG_WRITE_SRNG_STATS_LEN];
  493. hal_debug("TCL: %s sched-delay hist %u %u %u %u",
  494. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)),
  495. hist[REG_WRITE_SCHED_DELAY_SUB_100us],
  496. hist[REG_WRITE_SCHED_DELAY_SUB_1000us],
  497. hist[REG_WRITE_SCHED_DELAY_SUB_5000us],
  498. hist[REG_WRITE_SCHED_DELAY_GT_5000us]);
  499. hal_debug("wq_dly %u wq_dir %u tim_enq %u tim_dir %u enq_tim_cnt %u dir_tim_cnt %u rst_tim_cnt %u",
  500. hal->tcl_stats.wq_delayed,
  501. hal->tcl_stats.wq_direct,
  502. hal->tcl_stats.timer_enq,
  503. hal->tcl_stats.timer_direct,
  504. hal->tcl_stats.enq_timer_set,
  505. hal->tcl_stats.direct_timer_set,
  506. hal->tcl_stats.timer_reset);
  507. }
  508. #else
  509. static inline void hal_dump_tcl_stats(struct hal_soc *hal)
  510. {
  511. }
  512. #endif
  513. void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
  514. {
  515. uint32_t *hist;
  516. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  517. hist = hal->stats.wstats.sched_delay;
  518. hal_debug("wstats: enq %u deq %u coal %u direct %u q_depth %u max_q %u sched-delay hist %u %u %u %u",
  519. qdf_atomic_read(&hal->stats.wstats.enqueues),
  520. hal->stats.wstats.dequeues,
  521. qdf_atomic_read(&hal->stats.wstats.coalesces),
  522. qdf_atomic_read(&hal->stats.wstats.direct),
  523. qdf_atomic_read(&hal->stats.wstats.q_depth),
  524. hal->stats.wstats.max_q_depth,
  525. hist[REG_WRITE_SCHED_DELAY_SUB_100us],
  526. hist[REG_WRITE_SCHED_DELAY_SUB_1000us],
  527. hist[REG_WRITE_SCHED_DELAY_SUB_5000us],
  528. hist[REG_WRITE_SCHED_DELAY_GT_5000us]);
  529. hal_dump_tcl_stats(hal);
  530. }
  531. int hal_get_reg_write_pending_work(void *hal_soc)
  532. {
  533. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  534. return qdf_atomic_read(&hal->active_work_cnt);
  535. }
  536. #endif
  537. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  538. #ifdef MEMORY_DEBUG
  539. /*
  540. * Length of the queue(array) used to hold delayed register writes.
  541. * Must be a multiple of 2.
  542. */
  543. #define HAL_REG_WRITE_QUEUE_LEN 128
  544. #else
  545. #define HAL_REG_WRITE_QUEUE_LEN 32
  546. #endif
  547. #ifdef FEATURE_HAL_DELAYED_REG_WRITE_V2
  548. /**
  549. * hal_process_reg_write_q_elem() - process a regiter write queue element
  550. * @hal: hal_soc pointer
  551. * @q_elem: pointer to hal regiter write queue element
  552. *
  553. * Return: The value which was written to the address
  554. */
  555. static uint32_t
  556. hal_process_reg_write_q_elem(struct hal_soc *hal,
  557. struct hal_reg_write_q_elem *q_elem)
  558. {
  559. struct hal_srng *srng = q_elem->srng;
  560. uint32_t write_val;
  561. SRNG_LOCK(&srng->lock);
  562. srng->reg_write_in_progress = false;
  563. srng->wstats.dequeues++;
  564. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  565. write_val = srng->u.src_ring.hp;
  566. q_elem->dequeue_val = write_val;
  567. q_elem->valid = 0;
  568. SRNG_UNLOCK(&srng->lock);
  569. hal_write_address_32_mb(hal,
  570. srng->u.src_ring.hp_addr,
  571. write_val, false);
  572. } else {
  573. write_val = srng->u.dst_ring.tp;
  574. q_elem->dequeue_val = write_val;
  575. q_elem->valid = 0;
  576. SRNG_UNLOCK(&srng->lock);
  577. hal_write_address_32_mb(hal,
  578. srng->u.dst_ring.tp_addr,
  579. write_val, false);
  580. }
  581. return write_val;
  582. }
  583. #else
  584. /**
  585. * hal_process_reg_write_q_elem() - process a regiter write queue element
  586. * @hal: hal_soc pointer
  587. * @q_elem: pointer to hal regiter write queue element
  588. *
  589. * Return: The value which was written to the address
  590. */
  591. static uint32_t
  592. hal_process_reg_write_q_elem(struct hal_soc *hal,
  593. struct hal_reg_write_q_elem *q_elem)
  594. {
  595. struct hal_srng *srng = q_elem->srng;
  596. uint32_t write_val;
  597. SRNG_LOCK(&srng->lock);
  598. srng->reg_write_in_progress = false;
  599. srng->wstats.dequeues++;
  600. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  601. q_elem->dequeue_val = srng->u.src_ring.hp;
  602. hal_write_address_32_mb(hal,
  603. srng->u.src_ring.hp_addr,
  604. srng->u.src_ring.hp, false);
  605. write_val = srng->u.src_ring.hp;
  606. } else {
  607. q_elem->dequeue_val = srng->u.dst_ring.tp;
  608. hal_write_address_32_mb(hal,
  609. srng->u.dst_ring.tp_addr,
  610. srng->u.dst_ring.tp, false);
  611. write_val = srng->u.dst_ring.tp;
  612. }
  613. q_elem->valid = 0;
  614. srng->last_dequeue_time = q_elem->dequeue_time;
  615. SRNG_UNLOCK(&srng->lock);
  616. return write_val;
  617. }
  618. #endif
  619. /**
  620. * hal_reg_write_fill_sched_delay_hist() - fill reg write delay histogram in hal
  621. * @hal: hal_soc pointer
  622. * @delay: delay in us
  623. *
  624. * Return: None
  625. */
  626. static inline void hal_reg_write_fill_sched_delay_hist(struct hal_soc *hal,
  627. uint64_t delay_us)
  628. {
  629. uint32_t *hist;
  630. hist = hal->stats.wstats.sched_delay;
  631. if (delay_us < 100)
  632. hist[REG_WRITE_SCHED_DELAY_SUB_100us]++;
  633. else if (delay_us < 1000)
  634. hist[REG_WRITE_SCHED_DELAY_SUB_1000us]++;
  635. else if (delay_us < 5000)
  636. hist[REG_WRITE_SCHED_DELAY_SUB_5000us]++;
  637. else
  638. hist[REG_WRITE_SCHED_DELAY_GT_5000us]++;
  639. }
  640. #ifdef SHADOW_WRITE_DELAY
  641. #define SHADOW_WRITE_MIN_DELTA_US 5
  642. #define SHADOW_WRITE_DELAY_US 50
  643. /*
  644. * Never add those srngs which are performance relate.
  645. * The delay itself will hit performance heavily.
  646. */
  647. #define IS_SRNG_MATCH(s) ((s)->ring_id == HAL_SRNG_CE_1_DST_STATUS || \
  648. (s)->ring_id == HAL_SRNG_CE_1_DST)
  649. static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem)
  650. {
  651. struct hal_srng *srng = elem->srng;
  652. struct hal_soc *hal;
  653. qdf_time_t now;
  654. qdf_iomem_t real_addr;
  655. if (qdf_unlikely(!srng))
  656. return false;
  657. hal = srng->hal_soc;
  658. if (qdf_unlikely(!hal))
  659. return false;
  660. /* Check if it is target srng, and valid shadow reg */
  661. if (qdf_likely(!IS_SRNG_MATCH(srng)))
  662. return false;
  663. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  664. real_addr = SRNG_SRC_ADDR(srng, HP);
  665. else
  666. real_addr = SRNG_DST_ADDR(srng, TP);
  667. if (!hal_validate_shadow_register(hal, real_addr, elem->addr))
  668. return false;
  669. /* Check the time delta from last write of same srng */
  670. now = qdf_get_log_timestamp();
  671. if (qdf_log_timestamp_to_usecs(now - srng->last_dequeue_time) >
  672. SHADOW_WRITE_MIN_DELTA_US)
  673. return false;
  674. /* Delay dequeue, and record */
  675. qdf_udelay(SHADOW_WRITE_DELAY_US);
  676. srng->wstats.dequeue_delay++;
  677. hal->stats.wstats.dequeue_delay++;
  678. return true;
  679. }
  680. #else
  681. static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem)
  682. {
  683. return false;
  684. }
  685. #endif
  686. /**
  687. * hal_reg_write_work() - Worker to process delayed writes
  688. * @arg: hal_soc pointer
  689. *
  690. * Return: None
  691. */
  692. static void hal_reg_write_work(void *arg)
  693. {
  694. int32_t q_depth, write_val;
  695. struct hal_soc *hal = arg;
  696. struct hal_reg_write_q_elem *q_elem;
  697. uint64_t delta_us;
  698. uint8_t ring_id;
  699. uint32_t *addr;
  700. uint32_t num_processed = 0;
  701. q_elem = &hal->reg_write_queue[(hal->read_idx)];
  702. q_elem->work_scheduled_time = qdf_get_log_timestamp();
  703. /* Make sure q_elem consistent in the memory for multi-cores */
  704. qdf_rmb();
  705. if (!q_elem->valid)
  706. return;
  707. q_depth = qdf_atomic_read(&hal->stats.wstats.q_depth);
  708. if (q_depth > hal->stats.wstats.max_q_depth)
  709. hal->stats.wstats.max_q_depth = q_depth;
  710. if (hif_prevent_link_low_power_states(hal->hif_handle)) {
  711. hal->stats.wstats.prevent_l1_fails++;
  712. return;
  713. }
  714. while (true) {
  715. qdf_rmb();
  716. if (!q_elem->valid)
  717. break;
  718. q_elem->dequeue_time = qdf_get_log_timestamp();
  719. ring_id = q_elem->srng->ring_id;
  720. addr = q_elem->addr;
  721. delta_us = qdf_log_timestamp_to_usecs(q_elem->dequeue_time -
  722. q_elem->enqueue_time);
  723. hal_reg_write_fill_sched_delay_hist(hal, delta_us);
  724. hal->stats.wstats.dequeues++;
  725. qdf_atomic_dec(&hal->stats.wstats.q_depth);
  726. if (hal_reg_write_need_delay(q_elem))
  727. hal_verbose_debug("Delay reg writer for srng 0x%x, addr 0x%pK",
  728. q_elem->srng->ring_id, q_elem->addr);
  729. write_val = hal_process_reg_write_q_elem(hal, q_elem);
  730. hal_verbose_debug("read_idx %u srng 0x%x, addr 0x%pK dequeue_val %u sched delay %llu us",
  731. hal->read_idx, ring_id, addr, write_val, delta_us);
  732. num_processed++;
  733. hal->read_idx = (hal->read_idx + 1) &
  734. (HAL_REG_WRITE_QUEUE_LEN - 1);
  735. q_elem = &hal->reg_write_queue[(hal->read_idx)];
  736. }
  737. hif_allow_link_low_power_states(hal->hif_handle);
  738. /*
  739. * Decrement active_work_cnt by the number of elements dequeued after
  740. * hif_allow_link_low_power_states.
  741. * This makes sure that hif_try_complete_tasks will wait till we make
  742. * the bus access in hif_allow_link_low_power_states. This will avoid
  743. * race condition between delayed register worker and bus suspend
  744. * (system suspend or runtime suspend).
  745. *
  746. * The following decrement should be done at the end!
  747. */
  748. qdf_atomic_sub(num_processed, &hal->active_work_cnt);
  749. }
  750. static void __hal_flush_reg_write_work(struct hal_soc *hal)
  751. {
  752. qdf_cancel_work(&hal->reg_write_work);
  753. }
  754. void hal_flush_reg_write_work(hal_soc_handle_t hal_handle)
  755. { __hal_flush_reg_write_work((struct hal_soc *)hal_handle);
  756. }
  757. /**
  758. * hal_reg_write_enqueue() - enqueue register writes into kworker
  759. * @hal_soc: hal_soc pointer
  760. * @srng: srng pointer
  761. * @addr: iomem address of regiter
  762. * @value: value to be written to iomem address
  763. *
  764. * This function executes from within the SRNG LOCK
  765. *
  766. * Return: None
  767. */
  768. static void hal_reg_write_enqueue(struct hal_soc *hal_soc,
  769. struct hal_srng *srng,
  770. void __iomem *addr,
  771. uint32_t value)
  772. {
  773. struct hal_reg_write_q_elem *q_elem;
  774. uint32_t write_idx;
  775. if (srng->reg_write_in_progress) {
  776. hal_verbose_debug("Already in progress srng ring id 0x%x addr 0x%pK val %u",
  777. srng->ring_id, addr, value);
  778. qdf_atomic_inc(&hal_soc->stats.wstats.coalesces);
  779. srng->wstats.coalesces++;
  780. return;
  781. }
  782. write_idx = qdf_atomic_inc_return(&hal_soc->write_idx);
  783. write_idx = write_idx & (HAL_REG_WRITE_QUEUE_LEN - 1);
  784. q_elem = &hal_soc->reg_write_queue[write_idx];
  785. if (q_elem->valid) {
  786. hal_err("queue full");
  787. QDF_BUG(0);
  788. return;
  789. }
  790. qdf_atomic_inc(&hal_soc->stats.wstats.enqueues);
  791. srng->wstats.enqueues++;
  792. qdf_atomic_inc(&hal_soc->stats.wstats.q_depth);
  793. q_elem->srng = srng;
  794. q_elem->addr = addr;
  795. q_elem->enqueue_val = value;
  796. q_elem->enqueue_time = qdf_get_log_timestamp();
  797. /*
  798. * Before the valid flag is set to true, all the other
  799. * fields in the q_elem needs to be updated in memory.
  800. * Else there is a chance that the dequeuing worker thread
  801. * might read stale entries and process incorrect srng.
  802. */
  803. qdf_wmb();
  804. q_elem->valid = true;
  805. /*
  806. * After all other fields in the q_elem has been updated
  807. * in memory successfully, the valid flag needs to be updated
  808. * in memory in time too.
  809. * Else there is a chance that the dequeuing worker thread
  810. * might read stale valid flag and the work will be bypassed
  811. * for this round. And if there is no other work scheduled
  812. * later, this hal register writing won't be updated any more.
  813. */
  814. qdf_wmb();
  815. srng->reg_write_in_progress = true;
  816. qdf_atomic_inc(&hal_soc->active_work_cnt);
  817. hal_verbose_debug("write_idx %u srng ring id 0x%x addr 0x%pK val %u",
  818. write_idx, srng->ring_id, addr, value);
  819. qdf_queue_work(hal_soc->qdf_dev, hal_soc->reg_write_wq,
  820. &hal_soc->reg_write_work);
  821. }
  822. /**
  823. * hal_delayed_reg_write_init() - Initialization function for delayed reg writes
  824. * @hal_soc: hal_soc pointer
  825. *
  826. * Initialize main data structures to process register writes in a delayed
  827. * workqueue.
  828. *
  829. * Return: QDF_STATUS_SUCCESS on success else a QDF error.
  830. */
  831. static QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal)
  832. {
  833. hal->reg_write_wq =
  834. qdf_alloc_high_prior_ordered_workqueue("hal_register_write_wq");
  835. qdf_create_work(0, &hal->reg_write_work, hal_reg_write_work, hal);
  836. hal->reg_write_queue = qdf_mem_malloc(HAL_REG_WRITE_QUEUE_LEN *
  837. sizeof(*hal->reg_write_queue));
  838. if (!hal->reg_write_queue) {
  839. hal_err("unable to allocate memory");
  840. QDF_BUG(0);
  841. return QDF_STATUS_E_NOMEM;
  842. }
  843. /* Initial value of indices */
  844. hal->read_idx = 0;
  845. qdf_atomic_set(&hal->write_idx, -1);
  846. return QDF_STATUS_SUCCESS;
  847. }
  848. /**
  849. * hal_delayed_reg_write_deinit() - De-Initialize delayed reg write processing
  850. * @hal_soc: hal_soc pointer
  851. *
  852. * De-initialize main data structures to process register writes in a delayed
  853. * workqueue.
  854. *
  855. * Return: None
  856. */
  857. static void hal_delayed_reg_write_deinit(struct hal_soc *hal)
  858. {
  859. __hal_flush_reg_write_work(hal);
  860. qdf_flush_workqueue(0, hal->reg_write_wq);
  861. qdf_destroy_workqueue(0, hal->reg_write_wq);
  862. qdf_mem_free(hal->reg_write_queue);
  863. }
  864. #else
  865. static inline QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal)
  866. {
  867. return QDF_STATUS_SUCCESS;
  868. }
  869. static inline void hal_delayed_reg_write_deinit(struct hal_soc *hal)
  870. {
  871. }
  872. #endif
  873. #ifdef FEATURE_HAL_DELAYED_REG_WRITE_V2
  874. #ifdef MEMORY_DEBUG
  875. /**
  876. * hal_reg_write_get_timestamp() - Function to get the timestamp
  877. *
  878. * Return: return present simestamp
  879. */
  880. static inline qdf_time_t hal_del_reg_write_get_ts(void)
  881. {
  882. return qdf_get_log_timestamp();
  883. }
  884. /**
  885. * hal_del_reg_write_ts_usecs() - Convert the timestamp to micro secs
  886. * @ts: timestamp value to be converted
  887. *
  888. * Return: return the timestamp in micro secs
  889. */
  890. static inline qdf_time_t hal_del_reg_write_ts_usecs(qdf_time_t ts)
  891. {
  892. return qdf_log_timestamp_to_usecs(ts);
  893. }
  894. /**
  895. * hal_tcl_write_fill_sched_delay_hist() - fill TCL reg write delay histogram
  896. * @hal: hal_soc pointer
  897. * @delay: delay in us
  898. *
  899. * Return: None
  900. */
  901. static inline void hal_tcl_write_fill_sched_delay_hist(struct hal_soc *hal)
  902. {
  903. uint32_t *hist;
  904. uint32_t delay_us;
  905. hal->tcl_stats.deq_time = hal_del_reg_write_get_ts();
  906. delay_us = hal_del_reg_write_ts_usecs(hal->tcl_stats.deq_time -
  907. hal->tcl_stats.enq_time);
  908. hist = hal->tcl_stats.sched_delay;
  909. if (delay_us < 100)
  910. hist[REG_WRITE_SCHED_DELAY_SUB_100us]++;
  911. else if (delay_us < 1000)
  912. hist[REG_WRITE_SCHED_DELAY_SUB_1000us]++;
  913. else if (delay_us < 5000)
  914. hist[REG_WRITE_SCHED_DELAY_SUB_5000us]++;
  915. else
  916. hist[REG_WRITE_SCHED_DELAY_GT_5000us]++;
  917. }
  918. #else
  919. static inline qdf_time_t hal_del_reg_write_get_ts(void)
  920. {
  921. return 0;
  922. }
  923. static inline qdf_time_t hal_del_reg_write_ts_usecs(qdf_time_t ts)
  924. {
  925. return 0;
  926. }
  927. static inline void hal_tcl_write_fill_sched_delay_hist(struct hal_soc *hal)
  928. {
  929. }
  930. #endif
  931. /**
  932. * hal_tcl_reg_write_work() - Worker to process delayed SW2TCL1 writes
  933. * @arg: hal_soc pointer
  934. *
  935. * Return: None
  936. */
  937. static void hal_tcl_reg_write_work(void *arg)
  938. {
  939. struct hal_soc *hal = arg;
  940. struct hal_srng *srng = hal_get_srng(hal, HAL_SRNG_SW2TCL1);
  941. SRNG_LOCK(&srng->lock);
  942. srng->wstats.dequeues++;
  943. hal_tcl_write_fill_sched_delay_hist(hal);
  944. /*
  945. * During the tranition of low to high tput scenario, reg write moves
  946. * from delayed to direct write context, there is a little chance that
  947. * worker thread gets scheduled later than direct context write which
  948. * already wrote the latest HP value. This check can catch that case
  949. * and avoid the repetitive writing of the same HP value.
  950. */
  951. if (srng->last_reg_wr_val != srng->u.src_ring.hp) {
  952. srng->last_reg_wr_val = srng->u.src_ring.hp;
  953. if (hal->tcl_direct) {
  954. /*
  955. * TCL reg writes have been moved to direct context and
  956. * the assumption is that PCIe bus stays in Active state
  957. * during high tput, hence its fine to write the HP
  958. * while the SRNG_LOCK is being held.
  959. */
  960. hal->tcl_stats.wq_direct++;
  961. hal_write_address_32_mb(hal, srng->u.src_ring.hp_addr,
  962. srng->last_reg_wr_val, false);
  963. srng->reg_write_in_progress = false;
  964. SRNG_UNLOCK(&srng->lock);
  965. } else {
  966. /*
  967. * TCL reg write to happen in delayed context,
  968. * write operation might take time due to possibility of
  969. * PCIe bus stays in low power state during low tput,
  970. * Hence release the SRNG_LOCK before writing.
  971. */
  972. hal->tcl_stats.wq_delayed++;
  973. srng->reg_write_in_progress = false;
  974. SRNG_UNLOCK(&srng->lock);
  975. hal_write_address_32_mb(hal, srng->u.src_ring.hp_addr,
  976. srng->last_reg_wr_val, false);
  977. }
  978. } else {
  979. srng->reg_write_in_progress = false;
  980. SRNG_UNLOCK(&srng->lock);
  981. }
  982. /*
  983. * Decrement active_work_cnt to make sure that hif_try_complete_tasks
  984. * will wait. This will avoid race condition between delayed register
  985. * worker and bus suspend (system suspend or runtime suspend).
  986. *
  987. * The following decrement should be done at the end!
  988. */
  989. qdf_atomic_dec(&hal->active_work_cnt);
  990. qdf_atomic_set(&hal->tcl_work_active, false);
  991. }
  992. static void __hal_flush_tcl_reg_write_work(struct hal_soc *hal)
  993. {
  994. qdf_cancel_work(&hal->tcl_reg_write_work);
  995. }
  996. /**
  997. * hal_tcl_reg_write_enqueue() - enqueue TCL register writes into kworker
  998. * @hal_soc: hal_soc pointer
  999. * @srng: srng pointer
  1000. * @addr: iomem address of regiter
  1001. * @value: value to be written to iomem address
  1002. *
  1003. * This function executes from within the SRNG LOCK
  1004. *
  1005. * Return: None
  1006. */
  1007. static void hal_tcl_reg_write_enqueue(struct hal_soc *hal_soc,
  1008. struct hal_srng *srng,
  1009. void __iomem *addr,
  1010. uint32_t value)
  1011. {
  1012. hal_soc->tcl_stats.enq_time = hal_del_reg_write_get_ts();
  1013. if (qdf_queue_work(hal_soc->qdf_dev, hal_soc->tcl_reg_write_wq,
  1014. &hal_soc->tcl_reg_write_work)) {
  1015. srng->reg_write_in_progress = true;
  1016. qdf_atomic_inc(&hal_soc->active_work_cnt);
  1017. qdf_atomic_set(&hal_soc->tcl_work_active, true);
  1018. srng->wstats.enqueues++;
  1019. } else {
  1020. hal_soc->tcl_stats.enq_timer_set++;
  1021. qdf_timer_mod(&hal_soc->tcl_reg_write_timer, 1);
  1022. }
  1023. }
  1024. /**
  1025. * hal_tcl_reg_write_timer() - timer handler to take care of pending TCL writes
  1026. * @arg: srng handle
  1027. *
  1028. * This function handles the pending TCL reg writes missed due to the previous
  1029. * scheduled worker running.
  1030. *
  1031. * Return: None
  1032. */
  1033. static void hal_tcl_reg_write_timer(void *arg)
  1034. {
  1035. hal_ring_handle_t srng_hdl = arg;
  1036. struct hal_srng *srng;
  1037. struct hal_soc *hal;
  1038. srng = (struct hal_srng *)srng_hdl;
  1039. hal = srng->hal_soc;
  1040. if (hif_pm_runtime_get(hal->hif_handle, RTPM_ID_DW_TX_HW_ENQUEUE,
  1041. true)) {
  1042. hal_srng_set_event(srng_hdl, HAL_SRNG_FLUSH_EVENT);
  1043. hal_srng_inc_flush_cnt(srng_hdl);
  1044. goto fail;
  1045. }
  1046. SRNG_LOCK(&srng->lock);
  1047. if (hal->tcl_direct) {
  1048. /*
  1049. * Due to the previous scheduled worker still running,
  1050. * direct reg write cannot be performed, so posted the
  1051. * pending writes to timer context.
  1052. */
  1053. if (srng->last_reg_wr_val != srng->u.src_ring.hp) {
  1054. srng->last_reg_wr_val = srng->u.src_ring.hp;
  1055. srng->wstats.direct++;
  1056. hal->tcl_stats.timer_direct++;
  1057. hal_write_address_32_mb(hal, srng->u.src_ring.hp_addr,
  1058. srng->last_reg_wr_val, false);
  1059. }
  1060. } else {
  1061. /*
  1062. * Due to the previous scheduled worker still running,
  1063. * queue_work from delayed context would fail,
  1064. * so retry from timer context.
  1065. */
  1066. if (qdf_queue_work(hal->qdf_dev, hal->tcl_reg_write_wq,
  1067. &hal->tcl_reg_write_work)) {
  1068. srng->reg_write_in_progress = true;
  1069. qdf_atomic_inc(&hal->active_work_cnt);
  1070. qdf_atomic_set(&hal->tcl_work_active, true);
  1071. srng->wstats.enqueues++;
  1072. hal->tcl_stats.timer_enq++;
  1073. } else {
  1074. if (srng->last_reg_wr_val != srng->u.src_ring.hp) {
  1075. hal->tcl_stats.timer_reset++;
  1076. qdf_timer_mod(&hal->tcl_reg_write_timer, 1);
  1077. }
  1078. }
  1079. }
  1080. SRNG_UNLOCK(&srng->lock);
  1081. hif_pm_runtime_put(hal->hif_handle, RTPM_ID_DW_TX_HW_ENQUEUE);
  1082. fail:
  1083. return;
  1084. }
  1085. /**
  1086. * hal_delayed_tcl_reg_write_init() - Initialization for delayed TCL reg writes
  1087. * @hal_soc: hal_soc pointer
  1088. *
  1089. * Initialize main data structures to process TCL register writes in a delayed
  1090. * workqueue.
  1091. *
  1092. * Return: QDF_STATUS_SUCCESS on success else a QDF error.
  1093. */
  1094. static QDF_STATUS hal_delayed_tcl_reg_write_init(struct hal_soc *hal)
  1095. {
  1096. struct hal_srng *srng = hal_get_srng(hal, HAL_SRNG_SW2TCL1);
  1097. QDF_STATUS status;
  1098. hal->tcl_reg_write_wq =
  1099. qdf_alloc_high_prior_ordered_workqueue("hal_tcl_reg_write_wq");
  1100. if (!hal->tcl_reg_write_wq) {
  1101. hal_err("hal_tcl_reg_write_wq alloc failed");
  1102. return QDF_STATUS_E_NOMEM;
  1103. }
  1104. status = qdf_create_work(0, &hal->tcl_reg_write_work,
  1105. hal_tcl_reg_write_work, hal);
  1106. if (status != QDF_STATUS_SUCCESS) {
  1107. hal_err("tcl_reg_write_work create failed");
  1108. goto fail;
  1109. }
  1110. status = qdf_timer_init(hal->qdf_dev, &hal->tcl_reg_write_timer,
  1111. hal_tcl_reg_write_timer, (void *)srng,
  1112. QDF_TIMER_TYPE_WAKE_APPS);
  1113. if (status != QDF_STATUS_SUCCESS) {
  1114. hal_err("tcl_reg_write_timer init failed");
  1115. goto fail;
  1116. }
  1117. qdf_atomic_init(&hal->tcl_work_active);
  1118. return QDF_STATUS_SUCCESS;
  1119. fail:
  1120. qdf_destroy_workqueue(0, hal->tcl_reg_write_wq);
  1121. return status;
  1122. }
  1123. /**
  1124. * hal_delayed_tcl_reg_write_deinit() - De-Initialize delayed TCL reg writes
  1125. * @hal_soc: hal_soc pointer
  1126. *
  1127. * De-initialize main data structures to process TCL register writes in a
  1128. * delayed workqueue.
  1129. *
  1130. * Return: None
  1131. */
  1132. static void hal_delayed_tcl_reg_write_deinit(struct hal_soc *hal)
  1133. {
  1134. qdf_timer_stop(&hal->tcl_reg_write_timer);
  1135. qdf_timer_free(&hal->tcl_reg_write_timer);
  1136. __hal_flush_tcl_reg_write_work(hal);
  1137. qdf_flush_workqueue(0, hal->tcl_reg_write_wq);
  1138. qdf_destroy_workqueue(0, hal->tcl_reg_write_wq);
  1139. }
  1140. #else
  1141. static inline QDF_STATUS hal_delayed_tcl_reg_write_init(struct hal_soc *hal)
  1142. {
  1143. return QDF_STATUS_SUCCESS;
  1144. }
  1145. static inline void hal_delayed_tcl_reg_write_deinit(struct hal_soc *hal)
  1146. {
  1147. }
  1148. #endif
  1149. #ifdef FEATURE_HAL_DELAYED_REG_WRITE_V2
  1150. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  1151. static inline void hal_reg_write_enqueue_v2(struct hal_soc *hal_soc,
  1152. struct hal_srng *srng,
  1153. void __iomem *addr,
  1154. uint32_t value)
  1155. {
  1156. hal_reg_write_enqueue(hal_soc, srng, addr, value);
  1157. }
  1158. #else
  1159. static inline void hal_reg_write_enqueue_v2(struct hal_soc *hal_soc,
  1160. struct hal_srng *srng,
  1161. void __iomem *addr,
  1162. uint32_t value)
  1163. {
  1164. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  1165. srng->wstats.direct++;
  1166. hal_write_address_32_mb(hal_soc, addr, value, false);
  1167. }
  1168. #endif
  1169. void hal_delayed_reg_write(struct hal_soc *hal_soc,
  1170. struct hal_srng *srng,
  1171. void __iomem *addr,
  1172. uint32_t value)
  1173. {
  1174. switch (srng->ring_type) {
  1175. case TCL_DATA:
  1176. if (hal_is_reg_write_tput_level_high(hal_soc)) {
  1177. hal_soc->tcl_direct = true;
  1178. if (srng->reg_write_in_progress ||
  1179. !qdf_atomic_read(&hal_soc->tcl_work_active)) {
  1180. /*
  1181. * Now the delayed work have either completed
  1182. * the writing or not even scheduled and would
  1183. * be blocked by SRNG_LOCK, hence it is fine to
  1184. * do direct write here.
  1185. */
  1186. srng->last_reg_wr_val = srng->u.src_ring.hp;
  1187. srng->wstats.direct++;
  1188. hal_write_address_32_mb(hal_soc, addr,
  1189. srng->last_reg_wr_val,
  1190. false);
  1191. } else {
  1192. hal_soc->tcl_stats.direct_timer_set++;
  1193. qdf_timer_mod(&hal_soc->tcl_reg_write_timer, 1);
  1194. }
  1195. } else {
  1196. hal_soc->tcl_direct = false;
  1197. if (srng->reg_write_in_progress) {
  1198. srng->wstats.coalesces++;
  1199. } else {
  1200. hal_tcl_reg_write_enqueue(hal_soc, srng,
  1201. addr, value);
  1202. }
  1203. }
  1204. break;
  1205. case CE_SRC:
  1206. case CE_DST:
  1207. case CE_DST_STATUS:
  1208. hal_reg_write_enqueue_v2(hal_soc, srng, addr, value);
  1209. break;
  1210. default:
  1211. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  1212. srng->wstats.direct++;
  1213. hal_write_address_32_mb(hal_soc, addr, value, false);
  1214. break;
  1215. }
  1216. }
  1217. #else
  1218. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  1219. #ifdef QCA_WIFI_QCA6750
  1220. void hal_delayed_reg_write(struct hal_soc *hal_soc,
  1221. struct hal_srng *srng,
  1222. void __iomem *addr,
  1223. uint32_t value)
  1224. {
  1225. uint8_t vote_access;
  1226. switch (srng->ring_type) {
  1227. case CE_SRC:
  1228. case CE_DST:
  1229. case CE_DST_STATUS:
  1230. vote_access = hif_get_ep_vote_access(hal_soc->hif_handle,
  1231. HIF_EP_VOTE_NONDP_ACCESS);
  1232. if ((vote_access == HIF_EP_VOTE_ACCESS_DISABLE) ||
  1233. (vote_access == HIF_EP_VOTE_INTERMEDIATE_ACCESS &&
  1234. PLD_MHI_STATE_L0 ==
  1235. pld_get_mhi_state(hal_soc->qdf_dev->dev))) {
  1236. hal_write_address_32_mb(hal_soc, addr, value, false);
  1237. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  1238. srng->wstats.direct++;
  1239. } else {
  1240. hal_reg_write_enqueue(hal_soc, srng, addr, value);
  1241. }
  1242. break;
  1243. default:
  1244. if (hif_get_ep_vote_access(hal_soc->hif_handle,
  1245. HIF_EP_VOTE_DP_ACCESS) ==
  1246. HIF_EP_VOTE_ACCESS_DISABLE ||
  1247. hal_is_reg_write_tput_level_high(hal_soc) ||
  1248. PLD_MHI_STATE_L0 ==
  1249. pld_get_mhi_state(hal_soc->qdf_dev->dev)) {
  1250. hal_write_address_32_mb(hal_soc, addr, value, false);
  1251. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  1252. srng->wstats.direct++;
  1253. } else {
  1254. hal_reg_write_enqueue(hal_soc, srng, addr, value);
  1255. }
  1256. break;
  1257. }
  1258. }
  1259. #else
  1260. void hal_delayed_reg_write(struct hal_soc *hal_soc,
  1261. struct hal_srng *srng,
  1262. void __iomem *addr,
  1263. uint32_t value)
  1264. {
  1265. if (pld_is_device_awake(hal_soc->qdf_dev->dev) ||
  1266. hal_is_reg_write_tput_level_high(hal_soc)) {
  1267. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  1268. srng->wstats.direct++;
  1269. hal_write_address_32_mb(hal_soc, addr, value, false);
  1270. } else {
  1271. hal_reg_write_enqueue(hal_soc, srng, addr, value);
  1272. }
  1273. }
  1274. #endif
  1275. #endif
  1276. #endif
  1277. /**
  1278. * hal_attach - Initialize HAL layer
  1279. * @hif_handle: Opaque HIF handle
  1280. * @qdf_dev: QDF device
  1281. *
  1282. * Return: Opaque HAL SOC handle
  1283. * NULL on failure (if given ring is not available)
  1284. *
  1285. * This function should be called as part of HIF initialization (for accessing
  1286. * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle()
  1287. *
  1288. */
  1289. void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev)
  1290. {
  1291. struct hal_soc *hal;
  1292. int i;
  1293. hal = qdf_mem_malloc(sizeof(*hal));
  1294. if (!hal) {
  1295. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1296. "%s: hal_soc allocation failed", __func__);
  1297. goto fail0;
  1298. }
  1299. hal->hif_handle = hif_handle;
  1300. hal->dev_base_addr = hif_get_dev_ba(hif_handle); /* UMAC */
  1301. hal->dev_base_addr_ce = hif_get_dev_ba_ce(hif_handle); /* CE */
  1302. hal->qdf_dev = qdf_dev;
  1303. hal->shadow_rdptr_mem_vaddr = (uint32_t *)qdf_mem_alloc_consistent(
  1304. qdf_dev, qdf_dev->dev, sizeof(*(hal->shadow_rdptr_mem_vaddr)) *
  1305. HAL_SRNG_ID_MAX, &(hal->shadow_rdptr_mem_paddr));
  1306. if (!hal->shadow_rdptr_mem_paddr) {
  1307. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1308. "%s: hal->shadow_rdptr_mem_paddr allocation failed",
  1309. __func__);
  1310. goto fail1;
  1311. }
  1312. qdf_mem_zero(hal->shadow_rdptr_mem_vaddr,
  1313. sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX);
  1314. hal->shadow_wrptr_mem_vaddr =
  1315. (uint32_t *)qdf_mem_alloc_consistent(qdf_dev, qdf_dev->dev,
  1316. sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS,
  1317. &(hal->shadow_wrptr_mem_paddr));
  1318. if (!hal->shadow_wrptr_mem_vaddr) {
  1319. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1320. "%s: hal->shadow_wrptr_mem_vaddr allocation failed",
  1321. __func__);
  1322. goto fail2;
  1323. }
  1324. qdf_mem_zero(hal->shadow_wrptr_mem_vaddr,
  1325. sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS);
  1326. for (i = 0; i < HAL_SRNG_ID_MAX; i++) {
  1327. hal->srng_list[i].initialized = 0;
  1328. hal->srng_list[i].ring_id = i;
  1329. }
  1330. qdf_spinlock_create(&hal->register_access_lock);
  1331. hal->register_window = 0;
  1332. hal->target_type = hal_get_target_type(hal_soc_to_hal_soc_handle(hal));
  1333. hal->ops = qdf_mem_malloc(sizeof(*hal->ops));
  1334. if (!hal->ops) {
  1335. hal_err("unable to allocable memory for HAL ops");
  1336. goto fail3;
  1337. }
  1338. hal_target_based_configure(hal);
  1339. hal_reg_write_fail_history_init(hal);
  1340. qdf_minidump_log(hal, sizeof(*hal), "hal_soc");
  1341. qdf_atomic_init(&hal->active_work_cnt);
  1342. hal_delayed_reg_write_init(hal);
  1343. hal_delayed_tcl_reg_write_init(hal);
  1344. return (void *)hal;
  1345. fail3:
  1346. qdf_mem_free_consistent(qdf_dev, qdf_dev->dev,
  1347. sizeof(*hal->shadow_wrptr_mem_vaddr) *
  1348. HAL_MAX_LMAC_RINGS,
  1349. hal->shadow_wrptr_mem_vaddr,
  1350. hal->shadow_wrptr_mem_paddr, 0);
  1351. fail2:
  1352. qdf_mem_free_consistent(qdf_dev, qdf_dev->dev,
  1353. sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX,
  1354. hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0);
  1355. fail1:
  1356. qdf_mem_free(hal);
  1357. fail0:
  1358. return NULL;
  1359. }
  1360. qdf_export_symbol(hal_attach);
  1361. /**
  1362. * hal_mem_info - Retrieve hal memory base address
  1363. *
  1364. * @hal_soc: Opaque HAL SOC handle
  1365. * @mem: pointer to structure to be updated with hal mem info
  1366. */
  1367. void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem)
  1368. {
  1369. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  1370. mem->dev_base_addr = (void *)hal->dev_base_addr;
  1371. mem->shadow_rdptr_mem_vaddr = (void *)hal->shadow_rdptr_mem_vaddr;
  1372. mem->shadow_wrptr_mem_vaddr = (void *)hal->shadow_wrptr_mem_vaddr;
  1373. mem->shadow_rdptr_mem_paddr = (void *)hal->shadow_rdptr_mem_paddr;
  1374. mem->shadow_wrptr_mem_paddr = (void *)hal->shadow_wrptr_mem_paddr;
  1375. hif_read_phy_mem_base((void *)hal->hif_handle,
  1376. (qdf_dma_addr_t *)&mem->dev_base_paddr);
  1377. mem->lmac_srng_start_id = HAL_SRNG_LMAC1_ID_START;
  1378. return;
  1379. }
  1380. qdf_export_symbol(hal_get_meminfo);
  1381. /**
  1382. * hal_detach - Detach HAL layer
  1383. * @hal_soc: HAL SOC handle
  1384. *
  1385. * Return: Opaque HAL SOC handle
  1386. * NULL on failure (if given ring is not available)
  1387. *
  1388. * This function should be called as part of HIF initialization (for accessing
  1389. * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle()
  1390. *
  1391. */
  1392. extern void hal_detach(void *hal_soc)
  1393. {
  1394. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1395. hal_delayed_reg_write_deinit(hal);
  1396. hal_delayed_tcl_reg_write_deinit(hal);
  1397. qdf_mem_free(hal->ops);
  1398. qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
  1399. sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX,
  1400. hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0);
  1401. qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
  1402. sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS,
  1403. hal->shadow_wrptr_mem_vaddr, hal->shadow_wrptr_mem_paddr, 0);
  1404. qdf_minidump_remove(hal, sizeof(*hal), "hal_soc");
  1405. qdf_mem_free(hal);
  1406. return;
  1407. }
  1408. qdf_export_symbol(hal_detach);
  1409. #define HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
  1410. #define HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0x0000ffff
  1411. #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
  1412. #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
  1413. /**
  1414. * hal_ce_dst_setup - Initialize CE destination ring registers
  1415. * @hal_soc: HAL SOC handle
  1416. * @srng: SRNG ring pointer
  1417. */
  1418. static inline void hal_ce_dst_setup(struct hal_soc *hal, struct hal_srng *srng,
  1419. int ring_num)
  1420. {
  1421. uint32_t reg_val = 0;
  1422. uint32_t reg_addr;
  1423. struct hal_hw_srng_config *ring_config =
  1424. HAL_SRNG_CONFIG(hal, CE_DST);
  1425. /* set DEST_MAX_LENGTH according to ce assignment */
  1426. reg_addr = HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR(
  1427. ring_config->reg_start[R0_INDEX] +
  1428. (ring_num * ring_config->reg_size[R0_INDEX]));
  1429. reg_val = HAL_REG_READ(hal, reg_addr);
  1430. reg_val &= ~HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK;
  1431. reg_val |= srng->u.dst_ring.max_buffer_length &
  1432. HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK;
  1433. HAL_REG_WRITE(hal, reg_addr, reg_val);
  1434. if (srng->prefetch_timer) {
  1435. reg_addr = HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(
  1436. ring_config->reg_start[R0_INDEX] +
  1437. (ring_num * ring_config->reg_size[R0_INDEX]));
  1438. reg_val = HAL_REG_READ(hal, reg_addr);
  1439. reg_val &= ~HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK;
  1440. reg_val |= srng->prefetch_timer;
  1441. HAL_REG_WRITE(hal, reg_addr, reg_val);
  1442. reg_val = HAL_REG_READ(hal, reg_addr);
  1443. }
  1444. }
  1445. /**
  1446. * hal_reo_read_write_ctrl_ix - Read or write REO_DESTINATION_RING_CTRL_IX
  1447. * @hal: HAL SOC handle
  1448. * @read: boolean value to indicate if read or write
  1449. * @ix0: pointer to store IX0 reg value
  1450. * @ix1: pointer to store IX1 reg value
  1451. * @ix2: pointer to store IX2 reg value
  1452. * @ix3: pointer to store IX3 reg value
  1453. */
  1454. void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read,
  1455. uint32_t *ix0, uint32_t *ix1,
  1456. uint32_t *ix2, uint32_t *ix3)
  1457. {
  1458. uint32_t reg_offset;
  1459. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  1460. uint32_t reo_reg_base;
  1461. reo_reg_base = hal_get_reo_reg_base_offset(hal_soc_hdl);
  1462. if (read) {
  1463. if (ix0) {
  1464. reg_offset =
  1465. HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(
  1466. reo_reg_base);
  1467. *ix0 = HAL_REG_READ(hal, reg_offset);
  1468. }
  1469. if (ix1) {
  1470. reg_offset =
  1471. HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(
  1472. reo_reg_base);
  1473. *ix1 = HAL_REG_READ(hal, reg_offset);
  1474. }
  1475. if (ix2) {
  1476. reg_offset =
  1477. HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(
  1478. reo_reg_base);
  1479. *ix2 = HAL_REG_READ(hal, reg_offset);
  1480. }
  1481. if (ix3) {
  1482. reg_offset =
  1483. HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(
  1484. reo_reg_base);
  1485. *ix3 = HAL_REG_READ(hal, reg_offset);
  1486. }
  1487. } else {
  1488. if (ix0) {
  1489. reg_offset =
  1490. HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(
  1491. reo_reg_base);
  1492. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1493. *ix0, true);
  1494. }
  1495. if (ix1) {
  1496. reg_offset =
  1497. HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(
  1498. reo_reg_base);
  1499. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1500. *ix1, true);
  1501. }
  1502. if (ix2) {
  1503. reg_offset =
  1504. HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(
  1505. reo_reg_base);
  1506. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1507. *ix2, true);
  1508. }
  1509. if (ix3) {
  1510. reg_offset =
  1511. HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(
  1512. reo_reg_base);
  1513. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1514. *ix3, true);
  1515. }
  1516. }
  1517. }
  1518. /**
  1519. * hal_srng_dst_set_hp_paddr_confirm() - Set physical address to dest ring head
  1520. * pointer and confirm that write went through by reading back the value
  1521. * @srng: sring pointer
  1522. * @paddr: physical address
  1523. *
  1524. * Return: None
  1525. */
  1526. void hal_srng_dst_set_hp_paddr_confirm(struct hal_srng *srng, uint64_t paddr)
  1527. {
  1528. SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_LSB, paddr & 0xffffffff);
  1529. SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_MSB, paddr >> 32);
  1530. }
  1531. /**
  1532. * hal_srng_dst_init_hp() - Initialize destination ring head
  1533. * pointer
  1534. * @hal_soc: hal_soc handle
  1535. * @srng: sring pointer
  1536. * @vaddr: virtual address
  1537. */
  1538. void hal_srng_dst_init_hp(struct hal_soc_handle *hal_soc,
  1539. struct hal_srng *srng,
  1540. uint32_t *vaddr)
  1541. {
  1542. uint32_t reg_offset;
  1543. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1544. if (!srng)
  1545. return;
  1546. srng->u.dst_ring.hp_addr = vaddr;
  1547. reg_offset = SRNG_DST_ADDR(srng, HP) - hal->dev_base_addr;
  1548. HAL_REG_WRITE_CONFIRM_RETRY(
  1549. hal, reg_offset, srng->u.dst_ring.cached_hp, true);
  1550. if (vaddr) {
  1551. *srng->u.dst_ring.hp_addr = srng->u.dst_ring.cached_hp;
  1552. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1553. "hp_addr=%pK, cached_hp=%d, hp=%d",
  1554. (void *)srng->u.dst_ring.hp_addr,
  1555. srng->u.dst_ring.cached_hp,
  1556. *srng->u.dst_ring.hp_addr);
  1557. }
  1558. }
  1559. /**
  1560. * hal_srng_hw_init - Private function to initialize SRNG HW
  1561. * @hal_soc: HAL SOC handle
  1562. * @srng: SRNG ring pointer
  1563. */
  1564. static inline void hal_srng_hw_init(struct hal_soc *hal,
  1565. struct hal_srng *srng)
  1566. {
  1567. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1568. hal_srng_src_hw_init(hal, srng);
  1569. else
  1570. hal_srng_dst_hw_init(hal, srng);
  1571. }
  1572. #ifdef CONFIG_SHADOW_V2
  1573. #define ignore_shadow false
  1574. #define CHECK_SHADOW_REGISTERS true
  1575. #else
  1576. #define ignore_shadow true
  1577. #define CHECK_SHADOW_REGISTERS false
  1578. #endif
  1579. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1580. /**
  1581. * hal_srng_is_near_full_irq_supported() - Check if near full irq is
  1582. * supported on this SRNG
  1583. * @hal_soc: HAL SoC handle
  1584. * @ring_type: SRNG type
  1585. * @ring_num: ring number
  1586. *
  1587. * Return: true, if near full irq is supported for this SRNG
  1588. * false, if near full irq is not supported for this SRNG
  1589. */
  1590. bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc,
  1591. int ring_type, int ring_num)
  1592. {
  1593. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1594. struct hal_hw_srng_config *ring_config =
  1595. HAL_SRNG_CONFIG(hal, ring_type);
  1596. return ring_config->nf_irq_support;
  1597. }
  1598. /**
  1599. * hal_srng_set_msi2_params() - Set MSI2 params to SRNG data structure from
  1600. * ring params
  1601. * @srng: SRNG handle
  1602. * @ring_params: ring params for this SRNG
  1603. *
  1604. * Return: None
  1605. */
  1606. static inline void
  1607. hal_srng_set_msi2_params(struct hal_srng *srng,
  1608. struct hal_srng_params *ring_params)
  1609. {
  1610. srng->msi2_addr = ring_params->msi2_addr;
  1611. srng->msi2_data = ring_params->msi2_data;
  1612. }
  1613. /**
  1614. * hal_srng_get_nf_params() - Get the near full MSI2 params from srng
  1615. * @srng: SRNG handle
  1616. * @ring_params: ring params for this SRNG
  1617. *
  1618. * Return: None
  1619. */
  1620. static inline void
  1621. hal_srng_get_nf_params(struct hal_srng *srng,
  1622. struct hal_srng_params *ring_params)
  1623. {
  1624. ring_params->msi2_addr = srng->msi2_addr;
  1625. ring_params->msi2_data = srng->msi2_data;
  1626. }
  1627. /**
  1628. * hal_srng_set_nf_thresholds() - Set the near full thresholds in SRNG
  1629. * @srng: SRNG handle where the params are to be set
  1630. * @ring_params: ring params, from where threshold is to be fetched
  1631. *
  1632. * Return: None
  1633. */
  1634. static inline void
  1635. hal_srng_set_nf_thresholds(struct hal_srng *srng,
  1636. struct hal_srng_params *ring_params)
  1637. {
  1638. srng->u.dst_ring.nf_irq_support = ring_params->nf_irq_support;
  1639. srng->u.dst_ring.high_thresh = ring_params->high_thresh;
  1640. }
  1641. #else
  1642. static inline void
  1643. hal_srng_set_msi2_params(struct hal_srng *srng,
  1644. struct hal_srng_params *ring_params)
  1645. {
  1646. }
  1647. static inline void
  1648. hal_srng_get_nf_params(struct hal_srng *srng,
  1649. struct hal_srng_params *ring_params)
  1650. {
  1651. }
  1652. static inline void
  1653. hal_srng_set_nf_thresholds(struct hal_srng *srng,
  1654. struct hal_srng_params *ring_params)
  1655. {
  1656. }
  1657. #endif
  1658. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  1659. /**
  1660. * hal_srng_last_desc_cleared_init - Initialize SRNG last_desc_cleared ptr
  1661. *
  1662. * @srng: Source ring pointer
  1663. *
  1664. * Return: None
  1665. */
  1666. static inline
  1667. void hal_srng_last_desc_cleared_init(struct hal_srng *srng)
  1668. {
  1669. srng->last_desc_cleared = srng->ring_size - srng->entry_size;
  1670. }
  1671. #else
  1672. static inline
  1673. void hal_srng_last_desc_cleared_init(struct hal_srng *srng)
  1674. {
  1675. }
  1676. #endif /* CLEAR_SW2TCL_CONSUMED_DESC */
  1677. /**
  1678. * hal_srng_setup - Initialize HW SRNG ring.
  1679. * @hal_soc: Opaque HAL SOC handle
  1680. * @ring_type: one of the types from hal_ring_type
  1681. * @ring_num: Ring number if there are multiple rings of same type (staring
  1682. * from 0)
  1683. * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
  1684. * @ring_params: SRNG ring params in hal_srng_params structure.
  1685. * Callers are expected to allocate contiguous ring memory of size
  1686. * 'num_entries * entry_size' bytes and pass the physical and virtual base
  1687. * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in
  1688. * hal_srng_params structure. Ring base address should be 8 byte aligned
  1689. * and size of each ring entry should be queried using the API
  1690. * hal_srng_get_entrysize
  1691. *
  1692. * Return: Opaque pointer to ring on success
  1693. * NULL on failure (if given ring is not available)
  1694. */
  1695. void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
  1696. int mac_id, struct hal_srng_params *ring_params)
  1697. {
  1698. int ring_id;
  1699. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1700. struct hal_srng *srng;
  1701. struct hal_hw_srng_config *ring_config =
  1702. HAL_SRNG_CONFIG(hal, ring_type);
  1703. void *dev_base_addr;
  1704. int i;
  1705. ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, mac_id);
  1706. if (ring_id < 0)
  1707. return NULL;
  1708. hal_verbose_debug("mac_id %d ring_id %d", mac_id, ring_id);
  1709. srng = hal_get_srng(hal_soc, ring_id);
  1710. if (srng->initialized) {
  1711. hal_verbose_debug("Ring (ring_type, ring_num) already initialized");
  1712. return NULL;
  1713. }
  1714. dev_base_addr = hal->dev_base_addr;
  1715. srng->ring_id = ring_id;
  1716. srng->ring_type = ring_type;
  1717. srng->ring_dir = ring_config->ring_dir;
  1718. srng->ring_base_paddr = ring_params->ring_base_paddr;
  1719. srng->ring_base_vaddr = ring_params->ring_base_vaddr;
  1720. srng->entry_size = ring_config->entry_size;
  1721. srng->num_entries = ring_params->num_entries;
  1722. srng->ring_size = srng->num_entries * srng->entry_size;
  1723. srng->ring_size_mask = srng->ring_size - 1;
  1724. srng->msi_addr = ring_params->msi_addr;
  1725. srng->msi_data = ring_params->msi_data;
  1726. srng->intr_timer_thres_us = ring_params->intr_timer_thres_us;
  1727. srng->intr_batch_cntr_thres_entries =
  1728. ring_params->intr_batch_cntr_thres_entries;
  1729. srng->prefetch_timer = ring_params->prefetch_timer;
  1730. srng->hal_soc = hal_soc;
  1731. hal_srng_set_msi2_params(srng, ring_params);
  1732. for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) {
  1733. srng->hwreg_base[i] = dev_base_addr + ring_config->reg_start[i]
  1734. + (ring_num * ring_config->reg_size[i]);
  1735. }
  1736. /* Zero out the entire ring memory */
  1737. qdf_mem_zero(srng->ring_base_vaddr, (srng->entry_size *
  1738. srng->num_entries) << 2);
  1739. srng->flags = ring_params->flags;
  1740. #ifdef BIG_ENDIAN_HOST
  1741. /* TODO: See if we should we get these flags from caller */
  1742. srng->flags |= HAL_SRNG_DATA_TLV_SWAP;
  1743. srng->flags |= HAL_SRNG_MSI_SWAP;
  1744. srng->flags |= HAL_SRNG_RING_PTR_SWAP;
  1745. #endif
  1746. hal_srng_last_desc_cleared_init(srng);
  1747. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1748. srng->u.src_ring.hp = 0;
  1749. srng->u.src_ring.reap_hp = srng->ring_size -
  1750. srng->entry_size;
  1751. srng->u.src_ring.tp_addr =
  1752. &(hal->shadow_rdptr_mem_vaddr[ring_id]);
  1753. srng->u.src_ring.low_threshold =
  1754. ring_params->low_threshold * srng->entry_size;
  1755. if (ring_config->lmac_ring) {
  1756. /* For LMAC rings, head pointer updates will be done
  1757. * through FW by writing to a shared memory location
  1758. */
  1759. srng->u.src_ring.hp_addr =
  1760. &(hal->shadow_wrptr_mem_vaddr[ring_id -
  1761. HAL_SRNG_LMAC1_ID_START]);
  1762. srng->flags |= HAL_SRNG_LMAC_RING;
  1763. } else if (ignore_shadow || (srng->u.src_ring.hp_addr == 0)) {
  1764. srng->u.src_ring.hp_addr =
  1765. hal_get_window_address(hal,
  1766. SRNG_SRC_ADDR(srng, HP));
  1767. if (CHECK_SHADOW_REGISTERS) {
  1768. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1769. QDF_TRACE_LEVEL_ERROR,
  1770. "%s: Ring (%d, %d) missing shadow config",
  1771. __func__, ring_type, ring_num);
  1772. }
  1773. } else {
  1774. hal_validate_shadow_register(hal,
  1775. SRNG_SRC_ADDR(srng, HP),
  1776. srng->u.src_ring.hp_addr);
  1777. }
  1778. } else {
  1779. /* During initialization loop count in all the descriptors
  1780. * will be set to zero, and HW will set it to 1 on completing
  1781. * descriptor update in first loop, and increments it by 1 on
  1782. * subsequent loops (loop count wraps around after reaching
  1783. * 0xffff). The 'loop_cnt' in SW ring state is the expected
  1784. * loop count in descriptors updated by HW (to be processed
  1785. * by SW).
  1786. */
  1787. hal_srng_set_nf_thresholds(srng, ring_params);
  1788. srng->u.dst_ring.loop_cnt = 1;
  1789. srng->u.dst_ring.tp = 0;
  1790. srng->u.dst_ring.hp_addr =
  1791. &(hal->shadow_rdptr_mem_vaddr[ring_id]);
  1792. if (ring_config->lmac_ring) {
  1793. /* For LMAC rings, tail pointer updates will be done
  1794. * through FW by writing to a shared memory location
  1795. */
  1796. srng->u.dst_ring.tp_addr =
  1797. &(hal->shadow_wrptr_mem_vaddr[ring_id -
  1798. HAL_SRNG_LMAC1_ID_START]);
  1799. srng->flags |= HAL_SRNG_LMAC_RING;
  1800. } else if (ignore_shadow || srng->u.dst_ring.tp_addr == 0) {
  1801. srng->u.dst_ring.tp_addr =
  1802. hal_get_window_address(hal,
  1803. SRNG_DST_ADDR(srng, TP));
  1804. if (CHECK_SHADOW_REGISTERS) {
  1805. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1806. QDF_TRACE_LEVEL_ERROR,
  1807. "%s: Ring (%d, %d) missing shadow config",
  1808. __func__, ring_type, ring_num);
  1809. }
  1810. } else {
  1811. hal_validate_shadow_register(hal,
  1812. SRNG_DST_ADDR(srng, TP),
  1813. srng->u.dst_ring.tp_addr);
  1814. }
  1815. }
  1816. if (!(ring_config->lmac_ring)) {
  1817. hal_srng_hw_init(hal, srng);
  1818. if (ring_type == CE_DST) {
  1819. srng->u.dst_ring.max_buffer_length = ring_params->max_buffer_length;
  1820. hal_ce_dst_setup(hal, srng, ring_num);
  1821. }
  1822. }
  1823. SRNG_LOCK_INIT(&srng->lock);
  1824. srng->srng_event = 0;
  1825. srng->initialized = true;
  1826. return (void *)srng;
  1827. }
  1828. qdf_export_symbol(hal_srng_setup);
  1829. /**
  1830. * hal_srng_cleanup - Deinitialize HW SRNG ring.
  1831. * @hal_soc: Opaque HAL SOC handle
  1832. * @hal_srng: Opaque HAL SRNG pointer
  1833. */
  1834. void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1835. {
  1836. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1837. SRNG_LOCK_DESTROY(&srng->lock);
  1838. srng->initialized = 0;
  1839. }
  1840. qdf_export_symbol(hal_srng_cleanup);
  1841. /**
  1842. * hal_srng_get_entrysize - Returns size of ring entry in bytes
  1843. * @hal_soc: Opaque HAL SOC handle
  1844. * @ring_type: one of the types from hal_ring_type
  1845. *
  1846. */
  1847. uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type)
  1848. {
  1849. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1850. struct hal_hw_srng_config *ring_config =
  1851. HAL_SRNG_CONFIG(hal, ring_type);
  1852. return ring_config->entry_size << 2;
  1853. }
  1854. qdf_export_symbol(hal_srng_get_entrysize);
  1855. /**
  1856. * hal_srng_max_entries - Returns maximum possible number of ring entries
  1857. * @hal_soc: Opaque HAL SOC handle
  1858. * @ring_type: one of the types from hal_ring_type
  1859. *
  1860. * Return: Maximum number of entries for the given ring_type
  1861. */
  1862. uint32_t hal_srng_max_entries(void *hal_soc, int ring_type)
  1863. {
  1864. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1865. struct hal_hw_srng_config *ring_config =
  1866. HAL_SRNG_CONFIG(hal, ring_type);
  1867. return ring_config->max_size / ring_config->entry_size;
  1868. }
  1869. qdf_export_symbol(hal_srng_max_entries);
  1870. enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type)
  1871. {
  1872. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1873. struct hal_hw_srng_config *ring_config =
  1874. HAL_SRNG_CONFIG(hal, ring_type);
  1875. return ring_config->ring_dir;
  1876. }
  1877. /**
  1878. * hal_srng_dump - Dump ring status
  1879. * @srng: hal srng pointer
  1880. */
  1881. void hal_srng_dump(struct hal_srng *srng)
  1882. {
  1883. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1884. hal_debug("=== SRC RING %d ===", srng->ring_id);
  1885. hal_debug("hp %u, reap_hp %u, tp %u, cached tp %u",
  1886. srng->u.src_ring.hp,
  1887. srng->u.src_ring.reap_hp,
  1888. *srng->u.src_ring.tp_addr,
  1889. srng->u.src_ring.cached_tp);
  1890. } else {
  1891. hal_debug("=== DST RING %d ===", srng->ring_id);
  1892. hal_debug("tp %u, hp %u, cached tp %u, loop_cnt %u",
  1893. srng->u.dst_ring.tp,
  1894. *srng->u.dst_ring.hp_addr,
  1895. srng->u.dst_ring.cached_hp,
  1896. srng->u.dst_ring.loop_cnt);
  1897. }
  1898. }
  1899. /**
  1900. * hal_get_srng_params - Retrieve SRNG parameters for a given ring from HAL
  1901. *
  1902. * @hal_soc: Opaque HAL SOC handle
  1903. * @hal_ring: Ring pointer (Source or Destination ring)
  1904. * @ring_params: SRNG parameters will be returned through this structure
  1905. */
  1906. extern void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl,
  1907. hal_ring_handle_t hal_ring_hdl,
  1908. struct hal_srng_params *ring_params)
  1909. {
  1910. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1911. int i =0;
  1912. ring_params->ring_id = srng->ring_id;
  1913. ring_params->ring_dir = srng->ring_dir;
  1914. ring_params->entry_size = srng->entry_size;
  1915. ring_params->ring_base_paddr = srng->ring_base_paddr;
  1916. ring_params->ring_base_vaddr = srng->ring_base_vaddr;
  1917. ring_params->num_entries = srng->num_entries;
  1918. ring_params->msi_addr = srng->msi_addr;
  1919. ring_params->msi_data = srng->msi_data;
  1920. ring_params->intr_timer_thres_us = srng->intr_timer_thres_us;
  1921. ring_params->intr_batch_cntr_thres_entries =
  1922. srng->intr_batch_cntr_thres_entries;
  1923. ring_params->low_threshold = srng->u.src_ring.low_threshold;
  1924. ring_params->flags = srng->flags;
  1925. ring_params->ring_id = srng->ring_id;
  1926. for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++)
  1927. ring_params->hwreg_base[i] = srng->hwreg_base[i];
  1928. hal_srng_get_nf_params(srng, ring_params);
  1929. }
  1930. qdf_export_symbol(hal_get_srng_params);
  1931. void hal_set_low_threshold(hal_ring_handle_t hal_ring_hdl,
  1932. uint32_t low_threshold)
  1933. {
  1934. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1935. srng->u.src_ring.low_threshold = low_threshold * srng->entry_size;
  1936. }
  1937. qdf_export_symbol(hal_set_low_threshold);
  1938. #ifdef FORCE_WAKE
  1939. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase)
  1940. {
  1941. struct hal_soc *hal_soc = (struct hal_soc *)soc;
  1942. hal_soc->init_phase = init_phase;
  1943. }
  1944. #endif /* FORCE_WAKE */