hal_be_generic_api.h 48 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_BE_GENERIC_API_H_
  19. #define _HAL_BE_GENERIC_API_H_
  20. #include <hal_be_hw_headers.h>
  21. #include "hal_be_tx.h"
  22. #include "hal_be_reo.h"
  23. #include <hal_api_mon.h>
  24. #include <hal_generic_api.h>
  25. /**
  26. * hal_tx_comp_get_status() - TQM Release reason
  27. * @hal_desc: completion ring Tx status
  28. *
  29. * This function will parse the WBM completion descriptor and populate in
  30. * HAL structure
  31. *
  32. * Return: none
  33. */
  34. static inline void
  35. hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
  36. struct hal_soc *hal)
  37. {
  38. uint8_t rate_stats_valid = 0;
  39. uint32_t rate_stats = 0;
  40. struct hal_tx_completion_status *ts =
  41. (struct hal_tx_completion_status *)ts1;
  42. ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  43. TQM_STATUS_NUMBER);
  44. ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  45. ACK_FRAME_RSSI);
  46. ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  47. FIRST_MSDU);
  48. ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  49. LAST_MSDU);
  50. #if 0
  51. // TODO - This has to be calculated form first and last msdu
  52. ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc,
  53. WBM2SW_COMPLETION_RING_TX,
  54. MSDU_PART_OF_AMSDU);
  55. #endif
  56. ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  57. SW_PEER_ID);
  58. ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID);
  59. ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  60. TRANSMIT_COUNT);
  61. rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
  62. rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO,
  63. TX_RATE_STATS_INFO_VALID, rate_stats);
  64. ts->valid = rate_stats_valid;
  65. if (rate_stats_valid) {
  66. ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW,
  67. rate_stats);
  68. ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO,
  69. TRANSMIT_PKT_TYPE, rate_stats);
  70. ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO,
  71. TRANSMIT_STBC, rate_stats);
  72. ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC,
  73. rate_stats);
  74. ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI,
  75. rate_stats);
  76. ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS,
  77. rate_stats);
  78. ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION,
  79. rate_stats);
  80. ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU,
  81. rate_stats);
  82. }
  83. ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc);
  84. ts->status = hal_tx_comp_get_release_reason(
  85. desc,
  86. hal_soc_to_hal_soc_handle(hal));
  87. ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
  88. TX_RATE_STATS_INFO_TX_RATE_STATS);
  89. }
  90. #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
  91. /**
  92. * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL
  93. * tlv_tag: Taf of the TLVs
  94. * rx_tlv: the pointer to the TLVs
  95. * @ppdu_info: pointer to ppdu_info
  96. *
  97. * Return: true if the tlv is handled, false if not
  98. */
  99. static inline bool
  100. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  101. struct hal_rx_ppdu_info *ppdu_info)
  102. {
  103. uint32_t value;
  104. switch (tlv_tag) {
  105. case WIFIPHYRX_HE_SIG_A_MU_UL_E:
  106. {
  107. uint8_t *he_sig_a_mu_ul_info =
  108. (uint8_t *)rx_tlv +
  109. HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL,
  110. HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS);
  111. ppdu_info->rx_status.he_flags = 1;
  112. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  113. FORMAT_INDICATION);
  114. if (value == 0) {
  115. ppdu_info->rx_status.he_data1 =
  116. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  117. } else {
  118. ppdu_info->rx_status.he_data1 =
  119. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  120. }
  121. /* data1 */
  122. ppdu_info->rx_status.he_data1 |=
  123. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  124. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  125. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  126. /* data2 */
  127. ppdu_info->rx_status.he_data2 |=
  128. QDF_MON_STATUS_TXOP_KNOWN;
  129. /*data3*/
  130. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  131. HE_SIG_A_MU_UL_INFO, BSS_COLOR_ID);
  132. ppdu_info->rx_status.he_data3 = value;
  133. /* 1 for UL and 0 for DL */
  134. value = 1;
  135. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  136. ppdu_info->rx_status.he_data3 |= value;
  137. /*data4*/
  138. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  139. SPATIAL_REUSE);
  140. ppdu_info->rx_status.he_data4 = value;
  141. /*data5*/
  142. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  143. HE_SIG_A_MU_UL_INFO, TRANSMIT_BW);
  144. ppdu_info->rx_status.he_data5 = value;
  145. ppdu_info->rx_status.bw = value;
  146. /*data6*/
  147. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO,
  148. TXOP_DURATION);
  149. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  150. ppdu_info->rx_status.he_data6 |= value;
  151. return true;
  152. }
  153. default:
  154. return false;
  155. }
  156. }
  157. #else
  158. static inline bool
  159. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  160. struct hal_rx_ppdu_info *ppdu_info)
  161. {
  162. return false;
  163. }
  164. #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */
  165. #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \
  166. defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET)
  167. static inline void
  168. hal_rx_handle_mu_ul_info(void *rx_tlv,
  169. struct mon_rx_user_status *mon_rx_user_status)
  170. {
  171. mon_rx_user_status->mu_ul_user_v0_word0 =
  172. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  173. SW_RESPONSE_REFERENCE_PTR);
  174. mon_rx_user_status->mu_ul_user_v0_word1 =
  175. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  176. SW_RESPONSE_REFERENCE_PTR_EXT);
  177. }
  178. static inline void
  179. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  180. struct mon_rx_user_status *mon_rx_user_status)
  181. {
  182. uint32_t mpdu_ok_byte_count;
  183. uint32_t mpdu_err_byte_count;
  184. mpdu_ok_byte_count = HAL_RX_GET(rx_tlv,
  185. RX_PPDU_END_USER_STATS,
  186. MPDU_OK_BYTE_COUNT);
  187. mpdu_err_byte_count = HAL_RX_GET(rx_tlv,
  188. RX_PPDU_END_USER_STATS,
  189. MPDU_ERR_BYTE_COUNT);
  190. mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count;
  191. mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count;
  192. }
  193. #else
  194. static inline void
  195. hal_rx_handle_mu_ul_info(void *rx_tlv,
  196. struct mon_rx_user_status *mon_rx_user_status)
  197. {
  198. }
  199. static inline void
  200. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  201. struct mon_rx_user_status *mon_rx_user_status)
  202. {
  203. struct hal_rx_ppdu_info *ppdu_info =
  204. (struct hal_rx_ppdu_info *)ppduinfo;
  205. /* HKV1: doesn't support mpdu byte count */
  206. mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len;
  207. mon_rx_user_status->mpdu_err_byte_count = 0;
  208. }
  209. #endif
  210. static inline void
  211. hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id,
  212. struct mon_rx_user_status *mon_rx_user_status)
  213. {
  214. struct mon_rx_info *mon_rx_info;
  215. struct mon_rx_user_info *mon_rx_user_info;
  216. struct hal_rx_ppdu_info *ppdu_info =
  217. (struct hal_rx_ppdu_info *)ppduinfo;
  218. mon_rx_info = &ppdu_info->rx_info;
  219. mon_rx_user_info = &ppdu_info->rx_user_info[user_id];
  220. mon_rx_user_info->qos_control_info_valid =
  221. mon_rx_info->qos_control_info_valid;
  222. mon_rx_user_info->qos_control = mon_rx_info->qos_control;
  223. mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index;
  224. mon_rx_user_status->tid = ppdu_info->rx_status.tid;
  225. mon_rx_user_status->tcp_msdu_count =
  226. ppdu_info->rx_status.tcp_msdu_count;
  227. mon_rx_user_status->udp_msdu_count =
  228. ppdu_info->rx_status.udp_msdu_count;
  229. mon_rx_user_status->other_msdu_count =
  230. ppdu_info->rx_status.other_msdu_count;
  231. mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control;
  232. mon_rx_user_status->frame_control_info_valid =
  233. ppdu_info->rx_status.frame_control_info_valid;
  234. mon_rx_user_status->data_sequence_control_info_valid =
  235. ppdu_info->rx_status.data_sequence_control_info_valid;
  236. mon_rx_user_status->first_data_seq_ctrl =
  237. ppdu_info->rx_status.first_data_seq_ctrl;
  238. mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type;
  239. mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags;
  240. mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags;
  241. mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags;
  242. mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags;
  243. mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags;
  244. mon_rx_user_status->mpdu_cnt_fcs_ok =
  245. ppdu_info->com_info.mpdu_cnt_fcs_ok;
  246. mon_rx_user_status->mpdu_cnt_fcs_err =
  247. ppdu_info->com_info.mpdu_cnt_fcs_err;
  248. qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap,
  249. &ppdu_info->com_info.mpdu_fcs_ok_bitmap,
  250. HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
  251. sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0]));
  252. hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status);
  253. }
  254. #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \
  255. ppdu_info, rssi_info_tlv) \
  256. { \
  257. ppdu_info->rx_status.rssi_chain[chain][0] = \
  258. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  259. RSSI_PRI20_CHAIN##chain); \
  260. ppdu_info->rx_status.rssi_chain[chain][1] = \
  261. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  262. RSSI_EXT20_CHAIN##chain); \
  263. ppdu_info->rx_status.rssi_chain[chain][2] = \
  264. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  265. RSSI_EXT40_LOW20_CHAIN##chain); \
  266. ppdu_info->rx_status.rssi_chain[chain][3] = \
  267. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  268. RSSI_EXT40_HIGH20_CHAIN##chain); \
  269. ppdu_info->rx_status.rssi_chain[chain][4] = \
  270. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  271. RSSI_EXT80_LOW20_CHAIN##chain); \
  272. ppdu_info->rx_status.rssi_chain[chain][5] = \
  273. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  274. RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \
  275. ppdu_info->rx_status.rssi_chain[chain][6] = \
  276. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  277. RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \
  278. ppdu_info->rx_status.rssi_chain[chain][7] = \
  279. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  280. RSSI_EXT80_HIGH20_CHAIN##chain); \
  281. } \
  282. #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \
  283. {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \
  284. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \
  285. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \
  286. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \
  287. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, ppdu_info, rssi_info_tlv) \
  288. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, ppdu_info, rssi_info_tlv) \
  289. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, ppdu_info, rssi_info_tlv) \
  290. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, ppdu_info, rssi_info_tlv)} \
  291. static inline uint32_t
  292. hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info,
  293. uint8_t *rssi_info_tlv)
  294. {
  295. // TODO - Find all these registers for wcn7850
  296. #if 0
  297. HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv)
  298. #endif
  299. return 0;
  300. }
  301. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  302. static inline void
  303. hal_get_qos_control(void *rx_tlv,
  304. struct hal_rx_ppdu_info *ppdu_info)
  305. {
  306. ppdu_info->rx_info.qos_control_info_valid =
  307. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  308. QOS_CONTROL_INFO_VALID);
  309. if (ppdu_info->rx_info.qos_control_info_valid)
  310. ppdu_info->rx_info.qos_control =
  311. HAL_RX_GET(rx_tlv,
  312. RX_PPDU_END_USER_STATS,
  313. QOS_CONTROL_FIELD);
  314. }
  315. static inline void
  316. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  317. struct hal_rx_ppdu_info *ppdu_info)
  318. {
  319. if ((ppdu_info->sw_frame_group_id
  320. == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) ||
  321. (ppdu_info->sw_frame_group_id ==
  322. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) {
  323. ppdu_info->rx_info.mac_addr1_valid =
  324. HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start);
  325. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] =
  326. HAL_RX_GET(rx_mpdu_start,
  327. RX_MPDU_INFO,
  328. MAC_ADDR_AD1_31_0);
  329. if (ppdu_info->sw_frame_group_id ==
  330. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) {
  331. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] =
  332. HAL_RX_GET(rx_mpdu_start,
  333. RX_MPDU_INFO,
  334. MAC_ADDR_AD1_47_32);
  335. }
  336. }
  337. }
  338. #else
  339. static inline void
  340. hal_get_qos_control(void *rx_tlv,
  341. struct hal_rx_ppdu_info *ppdu_info)
  342. {
  343. }
  344. static inline void
  345. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  346. struct hal_rx_ppdu_info *ppdu_info)
  347. {
  348. }
  349. #endif
  350. /**
  351. * hal_rx_status_get_tlv_info() - process receive info TLV
  352. * @rx_tlv_hdr: pointer to TLV header
  353. * @ppdu_info: pointer to ppdu_info
  354. *
  355. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  356. */
  357. static inline uint32_t
  358. hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo,
  359. hal_soc_handle_t hal_soc_hdl,
  360. qdf_nbuf_t nbuf)
  361. {
  362. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  363. uint32_t tlv_tag, user_id, tlv_len, value;
  364. uint8_t group_id = 0;
  365. uint8_t he_dcm = 0;
  366. uint8_t he_stbc = 0;
  367. uint16_t he_gi = 0;
  368. uint16_t he_ltf = 0;
  369. void *rx_tlv;
  370. bool unhandled = false;
  371. struct mon_rx_user_status *mon_rx_user_status;
  372. struct hal_rx_ppdu_info *ppdu_info =
  373. (struct hal_rx_ppdu_info *)ppduinfo;
  374. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  375. user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
  376. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  377. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  378. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  379. rx_tlv, tlv_len);
  380. switch (tlv_tag) {
  381. case WIFIRX_PPDU_START_E:
  382. {
  383. if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id ==
  384. HAL_RX_GET(rx_tlv, RX_PPDU_START, PHY_PPDU_ID)))
  385. hal_err("Matching ppdu_id(%u) detected",
  386. ppdu_info->com_info.last_ppdu_id);
  387. /* Reset ppdu_info before processing the ppdu */
  388. qdf_mem_zero(ppdu_info,
  389. sizeof(struct hal_rx_ppdu_info));
  390. ppdu_info->com_info.last_ppdu_id =
  391. ppdu_info->com_info.ppdu_id =
  392. HAL_RX_GET(rx_tlv, RX_PPDU_START,
  393. PHY_PPDU_ID);
  394. /* channel number is set in PHY meta data */
  395. ppdu_info->rx_status.chan_num =
  396. (HAL_RX_GET(rx_tlv, RX_PPDU_START,
  397. SW_PHY_META_DATA) & 0x0000FFFF);
  398. ppdu_info->rx_status.chan_freq =
  399. (HAL_RX_GET(rx_tlv, RX_PPDU_START,
  400. SW_PHY_META_DATA) & 0xFFFF0000) >> 16;
  401. if (ppdu_info->rx_status.chan_num &&
  402. ppdu_info->rx_status.chan_freq) {
  403. ppdu_info->rx_status.chan_freq =
  404. hal_rx_radiotap_num_to_freq(
  405. ppdu_info->rx_status.chan_num,
  406. ppdu_info->rx_status.chan_freq);
  407. }
  408. #ifdef DP_BE_NOTYET_WAR
  409. // TODO - timestamp is changed to 64-bit for wcn7850
  410. ppdu_info->com_info.ppdu_timestamp =
  411. HAL_RX_GET(rx_tlv, RX_PPDU_START,
  412. PPDU_START_TIMESTAMP);
  413. #endif
  414. ppdu_info->rx_status.ppdu_timestamp =
  415. ppdu_info->com_info.ppdu_timestamp;
  416. ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
  417. break;
  418. }
  419. case WIFIRX_PPDU_START_USER_INFO_E:
  420. break;
  421. case WIFIRX_PPDU_END_E:
  422. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  423. "[%s][%d] ppdu_end_e len=%d",
  424. __func__, __LINE__, tlv_len);
  425. /* This is followed by sub-TLVs of PPDU_END */
  426. ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
  427. break;
  428. case WIFIPHYRX_PKT_END_E:
  429. hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info);
  430. break;
  431. case WIFIRXPCU_PPDU_END_INFO_E:
  432. ppdu_info->rx_status.rx_antenna =
  433. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA);
  434. ppdu_info->rx_status.tsft =
  435. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO,
  436. WB_TIMESTAMP_UPPER_32);
  437. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  438. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO,
  439. WB_TIMESTAMP_LOWER_32);
  440. ppdu_info->rx_status.duration =
  441. HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8,
  442. RX_PPDU_DURATION);
  443. hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info);
  444. break;
  445. /*
  446. * WIFIRX_PPDU_END_USER_STATS_E comes for each user received.
  447. * for MU, based on num users we see this tlv that many times.
  448. */
  449. case WIFIRX_PPDU_END_USER_STATS_E:
  450. {
  451. unsigned long tid = 0;
  452. uint16_t seq = 0;
  453. ppdu_info->rx_status.ast_index =
  454. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  455. AST_INDEX);
  456. tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  457. RECEIVED_QOS_DATA_TID_BITMAP);
  458. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid,
  459. sizeof(tid) * 8);
  460. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  461. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  462. ppdu_info->rx_status.tcp_msdu_count =
  463. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  464. TCP_MSDU_COUNT) +
  465. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  466. TCP_ACK_MSDU_COUNT);
  467. ppdu_info->rx_status.udp_msdu_count =
  468. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  469. UDP_MSDU_COUNT);
  470. ppdu_info->rx_status.other_msdu_count =
  471. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  472. OTHER_MSDU_COUNT);
  473. if (ppdu_info->sw_frame_group_id
  474. != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  475. ppdu_info->rx_status.frame_control_info_valid =
  476. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  477. FRAME_CONTROL_INFO_VALID);
  478. if (ppdu_info->rx_status.frame_control_info_valid)
  479. ppdu_info->rx_status.frame_control =
  480. HAL_RX_GET(rx_tlv,
  481. RX_PPDU_END_USER_STATS,
  482. FRAME_CONTROL_FIELD);
  483. hal_get_qos_control(rx_tlv, ppdu_info);
  484. }
  485. ppdu_info->rx_status.data_sequence_control_info_valid =
  486. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  487. DATA_SEQUENCE_CONTROL_INFO_VALID);
  488. seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  489. FIRST_DATA_SEQ_CTRL);
  490. if (ppdu_info->rx_status.data_sequence_control_info_valid)
  491. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  492. ppdu_info->rx_status.preamble_type =
  493. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  494. HT_CONTROL_FIELD_PKT_TYPE);
  495. switch (ppdu_info->rx_status.preamble_type) {
  496. case HAL_RX_PKT_TYPE_11N:
  497. ppdu_info->rx_status.ht_flags = 1;
  498. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  499. break;
  500. case HAL_RX_PKT_TYPE_11AC:
  501. ppdu_info->rx_status.vht_flags = 1;
  502. break;
  503. case HAL_RX_PKT_TYPE_11AX:
  504. ppdu_info->rx_status.he_flags = 1;
  505. break;
  506. default:
  507. break;
  508. }
  509. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  510. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  511. MPDU_CNT_FCS_OK);
  512. ppdu_info->com_info.mpdu_cnt_fcs_err =
  513. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  514. MPDU_CNT_FCS_ERR);
  515. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  516. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  517. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  518. else
  519. ppdu_info->rx_status.rs_flags &=
  520. (~IEEE80211_AMPDU_FLAG);
  521. ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] =
  522. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  523. FCS_OK_BITMAP_31_0);
  524. ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] =
  525. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS,
  526. FCS_OK_BITMAP_63_32);
  527. if (user_id < HAL_MAX_UL_MU_USERS) {
  528. mon_rx_user_status =
  529. &ppdu_info->rx_user_status[user_id];
  530. hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status);
  531. ppdu_info->com_info.num_users++;
  532. hal_rx_populate_mu_user_info(rx_tlv, ppdu_info,
  533. user_id,
  534. mon_rx_user_status);
  535. }
  536. break;
  537. }
  538. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  539. ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] =
  540. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  541. FCS_OK_BITMAP_95_64);
  542. ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] =
  543. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  544. FCS_OK_BITMAP_127_96);
  545. ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] =
  546. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  547. FCS_OK_BITMAP_159_128);
  548. ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] =
  549. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  550. FCS_OK_BITMAP_191_160);
  551. ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] =
  552. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  553. FCS_OK_BITMAP_223_192);
  554. ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] =
  555. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  556. FCS_OK_BITMAP_255_224);
  557. break;
  558. case WIFIRX_PPDU_END_STATUS_DONE_E:
  559. return HAL_TLV_STATUS_PPDU_DONE;
  560. case WIFIDUMMY_E:
  561. return HAL_TLV_STATUS_BUF_DONE;
  562. case WIFIPHYRX_HT_SIG_E:
  563. {
  564. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  565. HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0,
  566. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  567. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO,
  568. FEC_CODING);
  569. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  570. 1 : 0;
  571. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  572. HT_SIG_INFO, MCS);
  573. ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs;
  574. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  575. HT_SIG_INFO, CBW);
  576. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  577. HT_SIG_INFO, SHORT_GI);
  578. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  579. ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >>
  580. HT_SIG_SU_NSS_SHIFT) + 1;
  581. ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1);
  582. break;
  583. }
  584. case WIFIPHYRX_L_SIG_B_E:
  585. {
  586. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  587. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0,
  588. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  589. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE);
  590. ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info);
  591. switch (value) {
  592. case 1:
  593. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  594. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  595. break;
  596. case 2:
  597. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  598. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  599. break;
  600. case 3:
  601. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  602. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  603. break;
  604. case 4:
  605. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  606. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  607. break;
  608. case 5:
  609. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  610. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  611. break;
  612. case 6:
  613. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  614. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  615. break;
  616. case 7:
  617. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  618. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  619. break;
  620. default:
  621. break;
  622. }
  623. ppdu_info->rx_status.cck_flag = 1;
  624. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  625. break;
  626. }
  627. case WIFIPHYRX_L_SIG_A_E:
  628. {
  629. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  630. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0,
  631. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  632. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE);
  633. ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info);
  634. switch (value) {
  635. case 8:
  636. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  637. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  638. break;
  639. case 9:
  640. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  641. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  642. break;
  643. case 10:
  644. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  645. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  646. break;
  647. case 11:
  648. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  649. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  650. break;
  651. case 12:
  652. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  653. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  654. break;
  655. case 13:
  656. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  657. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  658. break;
  659. case 14:
  660. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  661. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  662. break;
  663. case 15:
  664. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  665. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7;
  666. break;
  667. default:
  668. break;
  669. }
  670. ppdu_info->rx_status.ofdm_flag = 1;
  671. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  672. break;
  673. }
  674. case WIFIPHYRX_VHT_SIG_A_E:
  675. {
  676. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  677. HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0,
  678. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  679. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO,
  680. SU_MU_CODING);
  681. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  682. 1 : 0;
  683. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID);
  684. ppdu_info->rx_status.vht_flag_values5 = group_id;
  685. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  686. VHT_SIG_A_INFO, MCS);
  687. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  688. VHT_SIG_A_INFO, GI_SETTING);
  689. switch (hal->target_type) {
  690. case TARGET_TYPE_QCA8074:
  691. case TARGET_TYPE_QCA8074V2:
  692. case TARGET_TYPE_QCA6018:
  693. case TARGET_TYPE_QCA5018:
  694. case TARGET_TYPE_QCN9000:
  695. case TARGET_TYPE_QCN6122:
  696. #ifdef QCA_WIFI_QCA6390
  697. case TARGET_TYPE_QCA6390:
  698. #endif
  699. ppdu_info->rx_status.is_stbc =
  700. HAL_RX_GET(vht_sig_a_info,
  701. VHT_SIG_A_INFO, STBC);
  702. value = HAL_RX_GET(vht_sig_a_info,
  703. VHT_SIG_A_INFO, N_STS);
  704. value = value & VHT_SIG_SU_NSS_MASK;
  705. if (ppdu_info->rx_status.is_stbc && (value > 0))
  706. value = ((value + 1) >> 1) - 1;
  707. ppdu_info->rx_status.nss =
  708. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  709. break;
  710. case TARGET_TYPE_QCA6290:
  711. #if !defined(QCA_WIFI_QCA6290_11AX)
  712. ppdu_info->rx_status.is_stbc =
  713. HAL_RX_GET(vht_sig_a_info,
  714. VHT_SIG_A_INFO, STBC);
  715. value = HAL_RX_GET(vht_sig_a_info,
  716. VHT_SIG_A_INFO, N_STS);
  717. value = value & VHT_SIG_SU_NSS_MASK;
  718. if (ppdu_info->rx_status.is_stbc && (value > 0))
  719. value = ((value + 1) >> 1) - 1;
  720. ppdu_info->rx_status.nss =
  721. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  722. #else
  723. ppdu_info->rx_status.nss = 0;
  724. #endif
  725. break;
  726. case TARGET_TYPE_QCA6490:
  727. case TARGET_TYPE_QCA6750:
  728. case TARGET_TYPE_WCN7850:
  729. ppdu_info->rx_status.nss = 0;
  730. break;
  731. default:
  732. break;
  733. }
  734. ppdu_info->rx_status.vht_flag_values3[0] =
  735. (((ppdu_info->rx_status.mcs) << 4)
  736. | ppdu_info->rx_status.nss);
  737. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  738. VHT_SIG_A_INFO, BANDWIDTH);
  739. ppdu_info->rx_status.vht_flag_values2 =
  740. ppdu_info->rx_status.bw;
  741. ppdu_info->rx_status.vht_flag_values4 =
  742. HAL_RX_GET(vht_sig_a_info,
  743. VHT_SIG_A_INFO, SU_MU_CODING);
  744. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  745. VHT_SIG_A_INFO, BEAMFORMED);
  746. if (group_id == 0 || group_id == 63)
  747. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  748. else
  749. ppdu_info->rx_status.reception_type =
  750. HAL_RX_TYPE_MU_MIMO;
  751. break;
  752. }
  753. case WIFIPHYRX_HE_SIG_A_SU_E:
  754. {
  755. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  756. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0,
  757. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  758. ppdu_info->rx_status.he_flags = 1;
  759. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  760. FORMAT_INDICATION);
  761. if (value == 0) {
  762. ppdu_info->rx_status.he_data1 =
  763. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  764. } else {
  765. ppdu_info->rx_status.he_data1 =
  766. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  767. }
  768. /* data1 */
  769. ppdu_info->rx_status.he_data1 |=
  770. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  771. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  772. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  773. QDF_MON_STATUS_HE_MCS_KNOWN |
  774. QDF_MON_STATUS_HE_DCM_KNOWN |
  775. QDF_MON_STATUS_HE_CODING_KNOWN |
  776. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  777. QDF_MON_STATUS_HE_STBC_KNOWN |
  778. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  779. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  780. /* data2 */
  781. ppdu_info->rx_status.he_data2 =
  782. QDF_MON_STATUS_HE_GI_KNOWN;
  783. ppdu_info->rx_status.he_data2 |=
  784. QDF_MON_STATUS_TXBF_KNOWN |
  785. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  786. QDF_MON_STATUS_TXOP_KNOWN |
  787. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  788. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  789. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  790. /* data3 */
  791. value = HAL_RX_GET(he_sig_a_su_info,
  792. HE_SIG_A_SU_INFO, BSS_COLOR_ID);
  793. ppdu_info->rx_status.he_data3 = value;
  794. value = HAL_RX_GET(he_sig_a_su_info,
  795. HE_SIG_A_SU_INFO, BEAM_CHANGE);
  796. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  797. ppdu_info->rx_status.he_data3 |= value;
  798. value = HAL_RX_GET(he_sig_a_su_info,
  799. HE_SIG_A_SU_INFO, DL_UL_FLAG);
  800. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  801. ppdu_info->rx_status.he_data3 |= value;
  802. value = HAL_RX_GET(he_sig_a_su_info,
  803. HE_SIG_A_SU_INFO, TRANSMIT_MCS);
  804. ppdu_info->rx_status.mcs = value;
  805. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  806. ppdu_info->rx_status.he_data3 |= value;
  807. value = HAL_RX_GET(he_sig_a_su_info,
  808. HE_SIG_A_SU_INFO, DCM);
  809. he_dcm = value;
  810. value = value << QDF_MON_STATUS_DCM_SHIFT;
  811. ppdu_info->rx_status.he_data3 |= value;
  812. value = HAL_RX_GET(he_sig_a_su_info,
  813. HE_SIG_A_SU_INFO, CODING);
  814. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  815. 1 : 0;
  816. value = value << QDF_MON_STATUS_CODING_SHIFT;
  817. ppdu_info->rx_status.he_data3 |= value;
  818. value = HAL_RX_GET(he_sig_a_su_info,
  819. HE_SIG_A_SU_INFO,
  820. LDPC_EXTRA_SYMBOL);
  821. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  822. ppdu_info->rx_status.he_data3 |= value;
  823. value = HAL_RX_GET(he_sig_a_su_info,
  824. HE_SIG_A_SU_INFO, STBC);
  825. he_stbc = value;
  826. value = value << QDF_MON_STATUS_STBC_SHIFT;
  827. ppdu_info->rx_status.he_data3 |= value;
  828. /* data4 */
  829. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  830. SPATIAL_REUSE);
  831. ppdu_info->rx_status.he_data4 = value;
  832. /* data5 */
  833. value = HAL_RX_GET(he_sig_a_su_info,
  834. HE_SIG_A_SU_INFO, TRANSMIT_BW);
  835. ppdu_info->rx_status.he_data5 = value;
  836. ppdu_info->rx_status.bw = value;
  837. value = HAL_RX_GET(he_sig_a_su_info,
  838. HE_SIG_A_SU_INFO, CP_LTF_SIZE);
  839. switch (value) {
  840. case 0:
  841. he_gi = HE_GI_0_8;
  842. he_ltf = HE_LTF_1_X;
  843. break;
  844. case 1:
  845. he_gi = HE_GI_0_8;
  846. he_ltf = HE_LTF_2_X;
  847. break;
  848. case 2:
  849. he_gi = HE_GI_1_6;
  850. he_ltf = HE_LTF_2_X;
  851. break;
  852. case 3:
  853. if (he_dcm && he_stbc) {
  854. he_gi = HE_GI_0_8;
  855. he_ltf = HE_LTF_4_X;
  856. } else {
  857. he_gi = HE_GI_3_2;
  858. he_ltf = HE_LTF_4_X;
  859. }
  860. break;
  861. }
  862. ppdu_info->rx_status.sgi = he_gi;
  863. ppdu_info->rx_status.ltf_size = he_ltf;
  864. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  865. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  866. ppdu_info->rx_status.he_data5 |= value;
  867. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  868. ppdu_info->rx_status.he_data5 |= value;
  869. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS);
  870. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  871. ppdu_info->rx_status.he_data5 |= value;
  872. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  873. PACKET_EXTENSION_A_FACTOR);
  874. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  875. ppdu_info->rx_status.he_data5 |= value;
  876. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF);
  877. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  878. ppdu_info->rx_status.he_data5 |= value;
  879. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  880. PACKET_EXTENSION_PE_DISAMBIGUITY);
  881. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  882. ppdu_info->rx_status.he_data5 |= value;
  883. /* data6 */
  884. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS);
  885. value++;
  886. ppdu_info->rx_status.nss = value;
  887. ppdu_info->rx_status.he_data6 = value;
  888. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  889. DOPPLER_INDICATION);
  890. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  891. ppdu_info->rx_status.he_data6 |= value;
  892. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  893. TXOP_DURATION);
  894. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  895. ppdu_info->rx_status.he_data6 |= value;
  896. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  897. HE_SIG_A_SU_INFO, TXBF);
  898. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  899. break;
  900. }
  901. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  902. {
  903. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  904. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0,
  905. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  906. ppdu_info->rx_status.he_mu_flags = 1;
  907. /* HE Flags */
  908. /*data1*/
  909. ppdu_info->rx_status.he_data1 =
  910. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  911. ppdu_info->rx_status.he_data1 |=
  912. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  913. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  914. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  915. QDF_MON_STATUS_HE_STBC_KNOWN |
  916. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  917. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  918. /* data2 */
  919. ppdu_info->rx_status.he_data2 =
  920. QDF_MON_STATUS_HE_GI_KNOWN;
  921. ppdu_info->rx_status.he_data2 |=
  922. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  923. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  924. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  925. QDF_MON_STATUS_TXOP_KNOWN |
  926. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  927. /*data3*/
  928. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  929. HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID);
  930. ppdu_info->rx_status.he_data3 = value;
  931. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  932. HE_SIG_A_MU_DL_INFO, DL_UL_FLAG);
  933. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  934. ppdu_info->rx_status.he_data3 |= value;
  935. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  936. HE_SIG_A_MU_DL_INFO,
  937. LDPC_EXTRA_SYMBOL);
  938. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  939. ppdu_info->rx_status.he_data3 |= value;
  940. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  941. HE_SIG_A_MU_DL_INFO, STBC);
  942. he_stbc = value;
  943. value = value << QDF_MON_STATUS_STBC_SHIFT;
  944. ppdu_info->rx_status.he_data3 |= value;
  945. /*data4*/
  946. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  947. SPATIAL_REUSE);
  948. ppdu_info->rx_status.he_data4 = value;
  949. /*data5*/
  950. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  951. HE_SIG_A_MU_DL_INFO, TRANSMIT_BW);
  952. ppdu_info->rx_status.he_data5 = value;
  953. ppdu_info->rx_status.bw = value;
  954. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  955. HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE);
  956. switch (value) {
  957. case 0:
  958. he_gi = HE_GI_0_8;
  959. he_ltf = HE_LTF_4_X;
  960. break;
  961. case 1:
  962. he_gi = HE_GI_0_8;
  963. he_ltf = HE_LTF_2_X;
  964. break;
  965. case 2:
  966. he_gi = HE_GI_1_6;
  967. he_ltf = HE_LTF_2_X;
  968. break;
  969. case 3:
  970. he_gi = HE_GI_3_2;
  971. he_ltf = HE_LTF_4_X;
  972. break;
  973. }
  974. ppdu_info->rx_status.sgi = he_gi;
  975. ppdu_info->rx_status.ltf_size = he_ltf;
  976. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  977. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  978. ppdu_info->rx_status.he_data5 |= value;
  979. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  980. ppdu_info->rx_status.he_data5 |= value;
  981. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  982. HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS);
  983. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  984. ppdu_info->rx_status.he_data5 |= value;
  985. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  986. PACKET_EXTENSION_A_FACTOR);
  987. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  988. ppdu_info->rx_status.he_data5 |= value;
  989. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  990. PACKET_EXTENSION_PE_DISAMBIGUITY);
  991. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  992. ppdu_info->rx_status.he_data5 |= value;
  993. /*data6*/
  994. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  995. DOPPLER_INDICATION);
  996. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  997. ppdu_info->rx_status.he_data6 |= value;
  998. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  999. TXOP_DURATION);
  1000. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  1001. ppdu_info->rx_status.he_data6 |= value;
  1002. /* HE-MU Flags */
  1003. /* HE-MU-flags1 */
  1004. ppdu_info->rx_status.he_flags1 =
  1005. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  1006. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  1007. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  1008. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  1009. QDF_MON_STATUS_RU_0_KNOWN;
  1010. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1011. HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B);
  1012. ppdu_info->rx_status.he_flags1 |= value;
  1013. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1014. HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B);
  1015. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  1016. ppdu_info->rx_status.he_flags1 |= value;
  1017. /* HE-MU-flags2 */
  1018. ppdu_info->rx_status.he_flags2 =
  1019. QDF_MON_STATUS_BW_KNOWN;
  1020. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1021. HE_SIG_A_MU_DL_INFO, TRANSMIT_BW);
  1022. ppdu_info->rx_status.he_flags2 |= value;
  1023. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1024. HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B);
  1025. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  1026. ppdu_info->rx_status.he_flags2 |= value;
  1027. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1028. HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS);
  1029. value = value - 1;
  1030. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  1031. ppdu_info->rx_status.he_flags2 |= value;
  1032. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1033. break;
  1034. }
  1035. case WIFIPHYRX_HE_SIG_B1_MU_E:
  1036. {
  1037. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  1038. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0,
  1039. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  1040. ppdu_info->rx_status.he_sig_b_common_known |=
  1041. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  1042. /* TODO: Check on the availability of other fields in
  1043. * sig_b_common
  1044. */
  1045. value = HAL_RX_GET(he_sig_b1_mu_info,
  1046. HE_SIG_B1_MU_INFO, RU_ALLOCATION);
  1047. ppdu_info->rx_status.he_RU[0] = value;
  1048. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1049. break;
  1050. }
  1051. case WIFIPHYRX_HE_SIG_B2_MU_E:
  1052. {
  1053. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  1054. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0,
  1055. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  1056. /*
  1057. * Not all "HE" fields can be updated from
  1058. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1059. * to populate rest of the "HE" fields for MU scenarios.
  1060. */
  1061. /* HE-data1 */
  1062. ppdu_info->rx_status.he_data1 |=
  1063. QDF_MON_STATUS_HE_MCS_KNOWN |
  1064. QDF_MON_STATUS_HE_CODING_KNOWN;
  1065. /* HE-data2 */
  1066. /* HE-data3 */
  1067. value = HAL_RX_GET(he_sig_b2_mu_info,
  1068. HE_SIG_B2_MU_INFO, STA_MCS);
  1069. ppdu_info->rx_status.mcs = value;
  1070. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1071. ppdu_info->rx_status.he_data3 |= value;
  1072. value = HAL_RX_GET(he_sig_b2_mu_info,
  1073. HE_SIG_B2_MU_INFO, STA_CODING);
  1074. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1075. ppdu_info->rx_status.he_data3 |= value;
  1076. /* HE-data4 */
  1077. value = HAL_RX_GET(he_sig_b2_mu_info,
  1078. HE_SIG_B2_MU_INFO, STA_ID);
  1079. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1080. ppdu_info->rx_status.he_data4 |= value;
  1081. /* HE-data5 */
  1082. /* HE-data6 */
  1083. value = HAL_RX_GET(he_sig_b2_mu_info,
  1084. HE_SIG_B2_MU_INFO, NSTS);
  1085. /* value n indicates n+1 spatial streams */
  1086. value++;
  1087. ppdu_info->rx_status.nss = value;
  1088. ppdu_info->rx_status.he_data6 |= value;
  1089. break;
  1090. }
  1091. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  1092. {
  1093. uint8_t *he_sig_b2_ofdma_info =
  1094. (uint8_t *)rx_tlv +
  1095. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0,
  1096. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  1097. /*
  1098. * Not all "HE" fields can be updated from
  1099. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1100. * to populate rest of "HE" fields for MU OFDMA scenarios.
  1101. */
  1102. /* HE-data1 */
  1103. ppdu_info->rx_status.he_data1 |=
  1104. QDF_MON_STATUS_HE_MCS_KNOWN |
  1105. QDF_MON_STATUS_HE_DCM_KNOWN |
  1106. QDF_MON_STATUS_HE_CODING_KNOWN;
  1107. /* HE-data2 */
  1108. ppdu_info->rx_status.he_data2 |=
  1109. QDF_MON_STATUS_TXBF_KNOWN;
  1110. /* HE-data3 */
  1111. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1112. HE_SIG_B2_OFDMA_INFO, STA_MCS);
  1113. ppdu_info->rx_status.mcs = value;
  1114. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1115. ppdu_info->rx_status.he_data3 |= value;
  1116. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1117. HE_SIG_B2_OFDMA_INFO, STA_DCM);
  1118. he_dcm = value;
  1119. value = value << QDF_MON_STATUS_DCM_SHIFT;
  1120. ppdu_info->rx_status.he_data3 |= value;
  1121. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1122. HE_SIG_B2_OFDMA_INFO, STA_CODING);
  1123. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1124. ppdu_info->rx_status.he_data3 |= value;
  1125. /* HE-data4 */
  1126. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1127. HE_SIG_B2_OFDMA_INFO, STA_ID);
  1128. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1129. ppdu_info->rx_status.he_data4 |= value;
  1130. /* HE-data5 */
  1131. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1132. HE_SIG_B2_OFDMA_INFO, TXBF);
  1133. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  1134. ppdu_info->rx_status.he_data5 |= value;
  1135. /* HE-data6 */
  1136. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1137. HE_SIG_B2_OFDMA_INFO, NSTS);
  1138. /* value n indicates n+1 spatial streams */
  1139. value++;
  1140. ppdu_info->rx_status.nss = value;
  1141. ppdu_info->rx_status.he_data6 |= value;
  1142. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
  1143. break;
  1144. }
  1145. case WIFIPHYRX_RSSI_LEGACY_E:
  1146. {
  1147. uint8_t reception_type;
  1148. int8_t rssi_value;
  1149. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  1150. HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19,
  1151. RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS);
  1152. ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
  1153. PHYRX_RSSI_LEGACY, RSSI_COMB);
  1154. ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
  1155. ppdu_info->rx_status.he_re = 0;
  1156. reception_type = HAL_RX_GET(rx_tlv,
  1157. PHYRX_RSSI_LEGACY,
  1158. RECEPTION_TYPE);
  1159. switch (reception_type) {
  1160. case QDF_RECEPTION_TYPE_ULOFMDA:
  1161. ppdu_info->rx_status.reception_type =
  1162. HAL_RX_TYPE_MU_OFDMA;
  1163. ppdu_info->rx_status.ulofdma_flag = 1;
  1164. ppdu_info->rx_status.he_data1 =
  1165. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  1166. break;
  1167. case QDF_RECEPTION_TYPE_ULMIMO:
  1168. ppdu_info->rx_status.reception_type =
  1169. HAL_RX_TYPE_MU_MIMO;
  1170. ppdu_info->rx_status.he_data1 =
  1171. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  1172. break;
  1173. default:
  1174. ppdu_info->rx_status.reception_type =
  1175. HAL_RX_TYPE_SU;
  1176. break;
  1177. }
  1178. hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv);
  1179. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1180. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN0);
  1181. ppdu_info->rx_status.rssi[0] = rssi_value;
  1182. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1183. "RSSI_PRI20_CHAIN0: %d\n", rssi_value);
  1184. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1185. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN1);
  1186. ppdu_info->rx_status.rssi[1] = rssi_value;
  1187. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1188. "RSSI_PRI20_CHAIN1: %d\n", rssi_value);
  1189. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1190. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN2);
  1191. ppdu_info->rx_status.rssi[2] = rssi_value;
  1192. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1193. "RSSI_PRI20_CHAIN2: %d\n", rssi_value);
  1194. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1195. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN3);
  1196. ppdu_info->rx_status.rssi[3] = rssi_value;
  1197. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1198. "RSSI_PRI20_CHAIN3: %d\n", rssi_value);
  1199. #ifdef DP_BE_NOTYET_WAR
  1200. // TODO - this is not preset for wcn7850
  1201. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1202. RECEIVE_RSSI_INFO, RSSI_PRI20_CHAIN4);
  1203. ppdu_info->rx_status.rssi[4] = rssi_value;
  1204. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1205. "RSSI_PRI20_CHAIN4: %d\n", rssi_value);
  1206. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1207. RECEIVE_RSSI_INFO,
  1208. RSSI_PRI20_CHAIN5);
  1209. ppdu_info->rx_status.rssi[5] = rssi_value;
  1210. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1211. "RSSI_PRI20_CHAIN5: %d\n", rssi_value);
  1212. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1213. RECEIVE_RSSI_INFO,
  1214. RSSI_PRI20_CHAIN6);
  1215. ppdu_info->rx_status.rssi[6] = rssi_value;
  1216. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1217. "RSSI_PRI20_CHAIN6: %d\n", rssi_value);
  1218. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1219. RECEIVE_RSSI_INFO,
  1220. RSSI_PRI20_CHAIN7);
  1221. ppdu_info->rx_status.rssi[7] = rssi_value;
  1222. #endif
  1223. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1224. "RSSI_PRI20_CHAIN7: %d\n", rssi_value);
  1225. break;
  1226. }
  1227. case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
  1228. hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
  1229. ppdu_info);
  1230. break;
  1231. case WIFIRX_HEADER_E:
  1232. {
  1233. struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info;
  1234. if (ppdu_info->fcs_ok_cnt >=
  1235. HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) {
  1236. hal_err("Number of MPDUs(%d) per status buff exceeded",
  1237. ppdu_info->fcs_ok_cnt);
  1238. break;
  1239. }
  1240. /* Update first_msdu_payload for every mpdu and increment
  1241. * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV
  1242. */
  1243. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload =
  1244. rx_tlv;
  1245. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len;
  1246. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  1247. ppdu_info->msdu_info.payload_len = tlv_len;
  1248. ppdu_info->user_id = user_id;
  1249. ppdu_info->hdr_len = tlv_len;
  1250. ppdu_info->data = rx_tlv;
  1251. ppdu_info->data += 4;
  1252. /* for every RX_HEADER TLV increment mpdu_cnt */
  1253. com_info->mpdu_cnt++;
  1254. return HAL_TLV_STATUS_HEADER;
  1255. }
  1256. case WIFIRX_MPDU_START_E:
  1257. {
  1258. uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv;
  1259. uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_tlv);
  1260. uint8_t filter_category = 0;
  1261. ppdu_info->nac_info.fc_valid =
  1262. HAL_RX_GET_FC_VALID(rx_tlv);
  1263. ppdu_info->nac_info.to_ds_flag =
  1264. HAL_RX_GET_TO_DS_FLAG(rx_tlv);
  1265. ppdu_info->nac_info.frame_control =
  1266. HAL_RX_GET(rx_mpdu_start,
  1267. RX_MPDU_INFO,
  1268. MPDU_FRAME_CONTROL_FIELD);
  1269. ppdu_info->sw_frame_group_id =
  1270. HAL_RX_GET_SW_FRAME_GROUP_ID(rx_tlv);
  1271. if (ppdu_info->sw_frame_group_id ==
  1272. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  1273. ppdu_info->rx_status.frame_control_info_valid =
  1274. ppdu_info->nac_info.fc_valid;
  1275. ppdu_info->rx_status.frame_control =
  1276. ppdu_info->nac_info.frame_control;
  1277. }
  1278. hal_get_mac_addr1(rx_mpdu_start,
  1279. ppdu_info);
  1280. ppdu_info->nac_info.mac_addr2_valid =
  1281. HAL_RX_TLV_MPDU_MAC_ADDR_AD2_VALID_GET(rx_tlv);
  1282. *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
  1283. HAL_RX_GET(rx_mpdu_start,
  1284. RX_MPDU_INFO,
  1285. MAC_ADDR_AD2_15_0);
  1286. *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
  1287. HAL_RX_GET(rx_mpdu_start,
  1288. RX_MPDU_INFO,
  1289. MAC_ADDR_AD2_47_16);
  1290. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  1291. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  1292. ppdu_info->rx_status.ppdu_len =
  1293. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO,
  1294. MPDU_LENGTH);
  1295. } else {
  1296. ppdu_info->rx_status.ppdu_len +=
  1297. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO,
  1298. MPDU_LENGTH);
  1299. }
  1300. filter_category =
  1301. HAL_RX_GET_FILTER_CATEGORY(rx_tlv);
  1302. if (filter_category == 0)
  1303. ppdu_info->rx_status.rxpcu_filter_pass = 1;
  1304. else if (filter_category == 1)
  1305. ppdu_info->rx_status.monitor_direct_used = 1;
  1306. ppdu_info->nac_info.mcast_bcast =
  1307. HAL_RX_GET(rx_mpdu_start,
  1308. RX_MPDU_INFO,
  1309. MCAST_BCAST);
  1310. break;
  1311. }
  1312. case WIFIRX_MPDU_END_E:
  1313. ppdu_info->user_id = user_id;
  1314. ppdu_info->fcs_err =
  1315. HAL_RX_GET(rx_tlv, RX_MPDU_END,
  1316. FCS_ERR);
  1317. return HAL_TLV_STATUS_MPDU_END;
  1318. case WIFIRX_MSDU_END_E:
  1319. if (user_id < HAL_MAX_UL_MU_USERS) {
  1320. ppdu_info->rx_msdu_info[user_id].cce_metadata =
  1321. HAL_RX_TLV_CCE_METADATA_GET(rx_tlv);
  1322. ppdu_info->rx_msdu_info[user_id].fse_metadata =
  1323. HAL_RX_TLV_FSE_METADATA_GET(rx_tlv);
  1324. ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout =
  1325. HAL_RX_TLV_FLOW_IDX_TIMEOUT_GET(rx_tlv);
  1326. ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid =
  1327. HAL_RX_TLV_FLOW_IDX_INVALID_GET(rx_tlv);
  1328. ppdu_info->rx_msdu_info[user_id].flow_idx =
  1329. HAL_RX_TLV_FLOW_IDX_GET(rx_tlv);
  1330. }
  1331. return HAL_TLV_STATUS_MSDU_END;
  1332. case 0:
  1333. return HAL_TLV_STATUS_PPDU_DONE;
  1334. default:
  1335. if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info))
  1336. unhandled = false;
  1337. else
  1338. unhandled = true;
  1339. break;
  1340. }
  1341. if (!unhandled)
  1342. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1343. "%s TLV type: %d, TLV len:%d %s",
  1344. __func__, tlv_tag, tlv_len,
  1345. unhandled == true ? "unhandled" : "");
  1346. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1347. rx_tlv, tlv_len);
  1348. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1349. }
  1350. /**
  1351. * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table
  1352. * @soc: HAL SoC context
  1353. * @map: PCP-TID mapping table
  1354. *
  1355. * PCP are mapped to 8 TID values using TID values programmed
  1356. * in one set of mapping registers PCP_TID_MAP_<0 to 6>
  1357. * The mapping register has TID mapping for 8 PCP values
  1358. *
  1359. * Return: none
  1360. */
  1361. static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map)
  1362. {
  1363. uint32_t addr, value;
  1364. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  1365. MAC_TCL_REG_REG_BASE);
  1366. value = (map[0] |
  1367. (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
  1368. (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
  1369. (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
  1370. (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
  1371. (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
  1372. (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
  1373. (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
  1374. HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  1375. }
  1376. /**
  1377. * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with
  1378. * value received from user-space
  1379. * @soc: HAL SoC context
  1380. * @pcp: pcp value
  1381. * @tid : tid value
  1382. *
  1383. * Return: void
  1384. */
  1385. static void
  1386. hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc,
  1387. uint8_t pcp, uint8_t tid)
  1388. {
  1389. uint32_t addr, value, regval;
  1390. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  1391. MAC_TCL_REG_REG_BASE);
  1392. value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
  1393. /* Read back previous PCP TID config and update
  1394. * with new config.
  1395. */
  1396. regval = HAL_REG_READ(soc, addr);
  1397. regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
  1398. regval |= value;
  1399. HAL_REG_WRITE(soc, addr,
  1400. (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  1401. }
  1402. /**
  1403. * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority
  1404. * @soc: HAL SoC context
  1405. * @val: priority value
  1406. *
  1407. * Return: void
  1408. */
  1409. static
  1410. void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value)
  1411. {
  1412. uint32_t addr;
  1413. addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
  1414. MAC_TCL_REG_REG_BASE);
  1415. HAL_REG_WRITE(soc, addr,
  1416. (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
  1417. }
  1418. /**
  1419. * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size
  1420. * @rx_pkt_tlv_size: TLV size for regular RX packets
  1421. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  1422. *
  1423. * Return: size of rx pkt tlv before the actual data
  1424. */
  1425. static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size,
  1426. uint16_t *rx_mon_pkt_tlv_size)
  1427. {
  1428. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  1429. /* For now mon pkt tlv is same as rx pkt tlv */
  1430. *rx_mon_pkt_tlv_size = RX_PKT_TLVS_LEN;
  1431. }
  1432. #endif /* _HAL_BE_GENERIC_API_H_ */