dp_li_rx.c 25 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "cdp_txrx_cmn_struct.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_types.h"
  21. #include "dp_rx.h"
  22. #include "dp_li_rx.h"
  23. #include "dp_peer.h"
  24. #include "hal_rx.h"
  25. #include "hal_li_rx.h"
  26. #include "hal_api.h"
  27. #include "hal_li_api.h"
  28. #include "qdf_nbuf.h"
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "dp_internal.h"
  33. #include "dp_ipa.h"
  34. #ifdef WIFI_MONITOR_SUPPORT
  35. #include <dp_mon.h>
  36. #endif
  37. #ifdef FEATURE_WDS
  38. #include "dp_txrx_wds.h"
  39. #endif
  40. #include "dp_hist.h"
  41. #include "dp_rx_buffer_pool.h"
  42. static inline
  43. bool is_sa_da_idx_valid(struct dp_soc *soc, uint8_t *rx_tlv_hdr,
  44. qdf_nbuf_t nbuf, struct hal_rx_msdu_metadata msdu_info)
  45. {
  46. if ((qdf_nbuf_is_sa_valid(nbuf) &&
  47. (msdu_info.sa_idx > wlan_cfg_get_max_ast_idx(soc->wlan_cfg_ctx))) ||
  48. (!qdf_nbuf_is_da_mcbc(nbuf) && qdf_nbuf_is_da_valid(nbuf) &&
  49. (msdu_info.da_idx > wlan_cfg_get_max_ast_idx(soc->wlan_cfg_ctx))))
  50. return false;
  51. return true;
  52. }
  53. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  54. #if defined(FEATURE_MCL_REPEATER) && defined(FEATURE_MEC)
  55. /**
  56. * dp_rx_mec_check_wrapper() - wrapper to dp_rx_mcast_echo_check
  57. * @soc: core DP main context
  58. * @peer: dp peer handler
  59. * @rx_tlv_hdr: start of the rx TLV header
  60. * @nbuf: pkt buffer
  61. *
  62. * Return: bool (true if it is a looped back pkt else false)
  63. */
  64. static inline bool dp_rx_mec_check_wrapper(struct dp_soc *soc,
  65. struct dp_peer *peer,
  66. uint8_t *rx_tlv_hdr,
  67. qdf_nbuf_t nbuf)
  68. {
  69. return dp_rx_mcast_echo_check(soc, peer, rx_tlv_hdr, nbuf);
  70. }
  71. #else
  72. static inline bool dp_rx_mec_check_wrapper(struct dp_soc *soc,
  73. struct dp_peer *peer,
  74. uint8_t *rx_tlv_hdr,
  75. qdf_nbuf_t nbuf)
  76. {
  77. return false;
  78. }
  79. #endif
  80. #endif
  81. /**
  82. * dp_rx_process_li() - Brain of the Rx processing functionality
  83. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  84. * @int_ctx: per interrupt context
  85. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  86. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  87. * @quota: No. of units (packets) that can be serviced in one shot.
  88. *
  89. * This function implements the core of Rx functionality. This is
  90. * expected to handle only non-error frames.
  91. *
  92. * Return: uint32_t: No. of elements processed
  93. */
  94. uint32_t dp_rx_process_li(struct dp_intr *int_ctx,
  95. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  96. uint32_t quota)
  97. {
  98. hal_ring_desc_t ring_desc;
  99. hal_soc_handle_t hal_soc;
  100. struct dp_rx_desc *rx_desc = NULL;
  101. qdf_nbuf_t nbuf, next;
  102. bool near_full;
  103. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT];
  104. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT];
  105. uint32_t num_pending;
  106. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  107. uint16_t msdu_len = 0;
  108. uint16_t peer_id;
  109. uint8_t vdev_id;
  110. struct dp_peer *peer;
  111. struct dp_vdev *vdev;
  112. uint32_t pkt_len = 0;
  113. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  114. struct hal_rx_msdu_desc_info msdu_desc_info;
  115. enum hal_reo_error_status error;
  116. uint32_t peer_mdata;
  117. uint8_t *rx_tlv_hdr;
  118. uint32_t rx_bufs_reaped[MAX_PDEV_CNT];
  119. uint8_t mac_id = 0;
  120. struct dp_pdev *rx_pdev;
  121. struct dp_srng *dp_rxdma_srng;
  122. struct rx_desc_pool *rx_desc_pool;
  123. struct dp_soc *soc = int_ctx->soc;
  124. uint8_t core_id = 0;
  125. struct cdp_tid_rx_stats *tid_stats;
  126. qdf_nbuf_t nbuf_head;
  127. qdf_nbuf_t nbuf_tail;
  128. qdf_nbuf_t deliver_list_head;
  129. qdf_nbuf_t deliver_list_tail;
  130. uint32_t num_rx_bufs_reaped = 0;
  131. uint32_t intr_id;
  132. struct hif_opaque_softc *scn;
  133. int32_t tid = 0;
  134. bool is_prev_msdu_last = true;
  135. uint32_t num_entries_avail = 0;
  136. uint32_t rx_ol_pkt_cnt = 0;
  137. uint32_t num_entries = 0;
  138. struct hal_rx_msdu_metadata msdu_metadata;
  139. QDF_STATUS status;
  140. qdf_nbuf_t ebuf_head;
  141. qdf_nbuf_t ebuf_tail;
  142. uint8_t pkt_capture_offload = 0;
  143. int max_reap_limit;
  144. DP_HIST_INIT();
  145. qdf_assert_always(soc && hal_ring_hdl);
  146. hal_soc = soc->hal_soc;
  147. qdf_assert_always(hal_soc);
  148. scn = soc->hif_handle;
  149. hif_pm_runtime_mark_dp_rx_busy(scn);
  150. intr_id = int_ctx->dp_intr_id;
  151. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  152. more_data:
  153. /* reset local variables here to be re-used in the function */
  154. nbuf_head = NULL;
  155. nbuf_tail = NULL;
  156. deliver_list_head = NULL;
  157. deliver_list_tail = NULL;
  158. peer = NULL;
  159. vdev = NULL;
  160. num_rx_bufs_reaped = 0;
  161. ebuf_head = NULL;
  162. ebuf_tail = NULL;
  163. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  164. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  165. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  166. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  167. qdf_mem_zero(head, sizeof(head));
  168. qdf_mem_zero(tail, sizeof(tail));
  169. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  170. /*
  171. * Need API to convert from hal_ring pointer to
  172. * Ring Type / Ring Id combo
  173. */
  174. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  175. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  176. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  177. goto done;
  178. }
  179. /*
  180. * start reaping the buffers from reo ring and queue
  181. * them in per vdev queue.
  182. * Process the received pkts in a different per vdev loop.
  183. */
  184. while (qdf_likely(quota &&
  185. (ring_desc = hal_srng_dst_peek(hal_soc,
  186. hal_ring_hdl)))) {
  187. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  188. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  189. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  190. soc, hal_ring_hdl, error);
  191. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  192. 1);
  193. /* Don't know how to deal with this -- assert */
  194. qdf_assert(0);
  195. }
  196. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  197. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  198. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  199. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  200. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  201. break;
  202. }
  203. rx_desc = dp_rx_cookie_2_va_rxdma_buf(soc, rx_buf_cookie);
  204. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  205. ring_desc, rx_desc);
  206. if (QDF_IS_STATUS_ERROR(status)) {
  207. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  208. qdf_assert_always(!rx_desc->unmapped);
  209. dp_ipa_reo_ctx_buf_mapping_lock(soc,
  210. reo_ring_num);
  211. dp_ipa_handle_rx_buf_smmu_mapping(
  212. soc,
  213. rx_desc->nbuf,
  214. RX_DATA_BUFFER_SIZE,
  215. false);
  216. qdf_nbuf_unmap_nbytes_single(
  217. soc->osdev,
  218. rx_desc->nbuf,
  219. QDF_DMA_FROM_DEVICE,
  220. RX_DATA_BUFFER_SIZE);
  221. rx_desc->unmapped = 1;
  222. dp_ipa_reo_ctx_buf_mapping_unlock(soc,
  223. reo_ring_num);
  224. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  225. rx_desc->pool_id);
  226. dp_rx_add_to_free_desc_list(
  227. &head[rx_desc->pool_id],
  228. &tail[rx_desc->pool_id],
  229. rx_desc);
  230. }
  231. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  232. continue;
  233. }
  234. /*
  235. * this is a unlikely scenario where the host is reaping
  236. * a descriptor which it already reaped just a while ago
  237. * but is yet to replenish it back to HW.
  238. * In this case host will dump the last 128 descriptors
  239. * including the software descriptor rx_desc and assert.
  240. */
  241. if (qdf_unlikely(!rx_desc->in_use)) {
  242. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  243. dp_info_rl("Reaping rx_desc not in use!");
  244. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  245. ring_desc, rx_desc);
  246. /* ignore duplicate RX desc and continue to process */
  247. /* Pop out the descriptor */
  248. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  249. continue;
  250. }
  251. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  252. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  253. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  254. dp_info_rl("Nbuf sanity check failure!");
  255. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  256. ring_desc, rx_desc);
  257. rx_desc->in_err_state = 1;
  258. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  259. continue;
  260. }
  261. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  262. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  263. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  264. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  265. ring_desc, rx_desc);
  266. }
  267. /* Get MPDU DESC info */
  268. hal_rx_mpdu_desc_info_get_li(ring_desc, &mpdu_desc_info);
  269. /* Get MSDU DESC info */
  270. hal_rx_msdu_desc_info_get_li(ring_desc, &msdu_desc_info);
  271. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  272. HAL_MSDU_F_MSDU_CONTINUATION)) {
  273. /* previous msdu has end bit set, so current one is
  274. * the new MPDU
  275. */
  276. if (is_prev_msdu_last) {
  277. /* Get number of entries available in HW ring */
  278. num_entries_avail =
  279. hal_srng_dst_num_valid(hal_soc,
  280. hal_ring_hdl, 1);
  281. /* For new MPDU check if we can read complete
  282. * MPDU by comparing the number of buffers
  283. * available and number of buffers needed to
  284. * reap this MPDU
  285. */
  286. if ((msdu_desc_info.msdu_len /
  287. (RX_DATA_BUFFER_SIZE -
  288. soc->rx_pkt_tlv_size) + 1) >
  289. num_entries_avail) {
  290. DP_STATS_INC(soc,
  291. rx.msdu_scatter_wait_break,
  292. 1);
  293. dp_rx_cookie_reset_invalid_bit(
  294. ring_desc);
  295. break;
  296. }
  297. is_prev_msdu_last = false;
  298. }
  299. }
  300. core_id = smp_processor_id();
  301. DP_STATS_INC(soc, rx.ring_packets[core_id][reo_ring_num], 1);
  302. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  303. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  304. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  305. HAL_MPDU_F_RAW_AMPDU))
  306. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  307. if (!is_prev_msdu_last &&
  308. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  309. is_prev_msdu_last = true;
  310. /* Pop out the descriptor*/
  311. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  312. rx_bufs_reaped[rx_desc->pool_id]++;
  313. peer_mdata = mpdu_desc_info.peer_meta_data;
  314. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  315. DP_PEER_METADATA_PEER_ID_GET(peer_mdata);
  316. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  317. DP_PEER_METADATA_VDEV_ID_GET(peer_mdata);
  318. /* to indicate whether this msdu is rx offload */
  319. pkt_capture_offload =
  320. DP_PEER_METADATA_OFFLOAD_GET(peer_mdata);
  321. /*
  322. * save msdu flags first, last and continuation msdu in
  323. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  324. * length to nbuf->cb. This ensures the info required for
  325. * per pkt processing is always in the same cache line.
  326. * This helps in improving throughput for smaller pkt
  327. * sizes.
  328. */
  329. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  330. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  331. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  332. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  333. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  334. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  335. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  336. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  337. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  338. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  339. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  340. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  341. qdf_nbuf_set_tid_val(rx_desc->nbuf,
  342. HAL_RX_REO_QUEUE_NUMBER_GET(ring_desc));
  343. qdf_nbuf_set_rx_reo_dest_ind(
  344. rx_desc->nbuf,
  345. HAL_RX_REO_MSDU_REO_DST_IND_GET(ring_desc));
  346. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  347. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  348. /*
  349. * move unmap after scattered msdu waiting break logic
  350. * in case double skb unmap happened.
  351. */
  352. rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
  353. dp_ipa_reo_ctx_buf_mapping_lock(soc, reo_ring_num);
  354. dp_ipa_handle_rx_buf_smmu_mapping(soc, rx_desc->nbuf,
  355. rx_desc_pool->buf_size,
  356. false);
  357. qdf_nbuf_unmap_nbytes_single(soc->osdev, rx_desc->nbuf,
  358. QDF_DMA_FROM_DEVICE,
  359. rx_desc_pool->buf_size);
  360. rx_desc->unmapped = 1;
  361. dp_ipa_reo_ctx_buf_mapping_unlock(soc, reo_ring_num);
  362. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  363. ebuf_tail, rx_desc);
  364. /*
  365. * if continuation bit is set then we have MSDU spread
  366. * across multiple buffers, let us not decrement quota
  367. * till we reap all buffers of that MSDU.
  368. */
  369. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(rx_desc->nbuf)))
  370. quota -= 1;
  371. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  372. &tail[rx_desc->pool_id], rx_desc);
  373. num_rx_bufs_reaped++;
  374. /*
  375. * only if complete msdu is received for scatter case,
  376. * then allow break.
  377. */
  378. if (is_prev_msdu_last &&
  379. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  380. max_reap_limit))
  381. break;
  382. }
  383. done:
  384. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  385. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  386. /*
  387. * continue with next mac_id if no pkts were reaped
  388. * from that pool
  389. */
  390. if (!rx_bufs_reaped[mac_id])
  391. continue;
  392. dp_rxdma_srng = &soc->rx_refill_buf_ring[mac_id];
  393. rx_desc_pool = &soc->rx_desc_buf[mac_id];
  394. dp_rx_buffers_replenish(soc, mac_id, dp_rxdma_srng,
  395. rx_desc_pool, rx_bufs_reaped[mac_id],
  396. &head[mac_id], &tail[mac_id]);
  397. }
  398. dp_verbose_debug("replenished %u\n", rx_bufs_reaped[0]);
  399. /* Peer can be NULL is case of LFR */
  400. if (qdf_likely(peer))
  401. vdev = NULL;
  402. /*
  403. * BIG loop where each nbuf is dequeued from global queue,
  404. * processed and queued back on a per vdev basis. These nbufs
  405. * are sent to stack as and when we run out of nbufs
  406. * or a new nbuf dequeued from global queue has a different
  407. * vdev when compared to previous nbuf.
  408. */
  409. nbuf = nbuf_head;
  410. while (nbuf) {
  411. next = nbuf->next;
  412. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  413. nbuf = next;
  414. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  415. continue;
  416. }
  417. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  418. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  419. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  420. if (dp_rx_is_list_ready(deliver_list_head, vdev, peer,
  421. peer_id, vdev_id)) {
  422. dp_rx_deliver_to_stack(soc, vdev, peer,
  423. deliver_list_head,
  424. deliver_list_tail);
  425. deliver_list_head = NULL;
  426. deliver_list_tail = NULL;
  427. }
  428. /* Get TID from struct cb->tid_val, save to tid */
  429. if (qdf_nbuf_is_rx_chfrag_start(nbuf))
  430. tid = qdf_nbuf_get_tid_val(nbuf);
  431. if (qdf_unlikely(!peer)) {
  432. peer = dp_peer_get_ref_by_id(soc, peer_id,
  433. DP_MOD_ID_RX);
  434. } else if (peer && peer->peer_id != peer_id) {
  435. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  436. peer = dp_peer_get_ref_by_id(soc, peer_id,
  437. DP_MOD_ID_RX);
  438. }
  439. if (peer) {
  440. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  441. qdf_dp_trace_set_track(nbuf, QDF_RX);
  442. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  443. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  444. QDF_NBUF_RX_PKT_DATA_TRACK;
  445. }
  446. rx_bufs_used++;
  447. if (qdf_likely(peer)) {
  448. vdev = peer->vdev;
  449. } else {
  450. nbuf->next = NULL;
  451. dp_rx_deliver_to_pkt_capture_no_peer(
  452. soc, nbuf, pkt_capture_offload);
  453. if (!pkt_capture_offload)
  454. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  455. nbuf = next;
  456. continue;
  457. }
  458. if (qdf_unlikely(!vdev)) {
  459. qdf_nbuf_free(nbuf);
  460. nbuf = next;
  461. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  462. continue;
  463. }
  464. /* when hlos tid override is enabled, save tid in
  465. * skb->priority
  466. */
  467. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  468. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  469. qdf_nbuf_set_priority(nbuf, tid);
  470. rx_pdev = vdev->pdev;
  471. DP_RX_TID_SAVE(nbuf, tid);
  472. if (qdf_unlikely(rx_pdev->delay_stats_flag) ||
  473. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  474. soc->wlan_cfg_ctx)))
  475. qdf_nbuf_set_timestamp(nbuf);
  476. tid_stats =
  477. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  478. /*
  479. * Check if DMA completed -- msdu_done is the last bit
  480. * to be written
  481. */
  482. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(nbuf))) {
  483. if (qdf_unlikely(!hal_rx_attn_msdu_done_get_li(
  484. rx_tlv_hdr))) {
  485. dp_err_rl("MSDU DONE failure");
  486. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  487. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  488. QDF_TRACE_LEVEL_INFO);
  489. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  490. qdf_assert(0);
  491. qdf_nbuf_free(nbuf);
  492. nbuf = next;
  493. continue;
  494. } else if (qdf_unlikely(hal_rx_attn_msdu_len_err_get_li(
  495. rx_tlv_hdr))) {
  496. DP_STATS_INC(soc, rx.err.msdu_len_err, 1);
  497. qdf_nbuf_free(nbuf);
  498. nbuf = next;
  499. continue;
  500. }
  501. }
  502. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  503. /*
  504. * First IF condition:
  505. * 802.11 Fragmented pkts are reinjected to REO
  506. * HW block as SG pkts and for these pkts we only
  507. * need to pull the RX TLVS header length.
  508. * Second IF condition:
  509. * The below condition happens when an MSDU is spread
  510. * across multiple buffers. This can happen in two cases
  511. * 1. The nbuf size is smaller then the received msdu.
  512. * ex: we have set the nbuf size to 2048 during
  513. * nbuf_alloc. but we received an msdu which is
  514. * 2304 bytes in size then this msdu is spread
  515. * across 2 nbufs.
  516. *
  517. * 2. AMSDUs when RAW mode is enabled.
  518. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  519. * across 1st nbuf and 2nd nbuf and last MSDU is
  520. * spread across 2nd nbuf and 3rd nbuf.
  521. *
  522. * for these scenarios let us create a skb frag_list and
  523. * append these buffers till the last MSDU of the AMSDU
  524. * Third condition:
  525. * This is the most likely case, we receive 802.3 pkts
  526. * decapsulated by HW, here we need to set the pkt length.
  527. */
  528. hal_rx_msdu_metadata_get(hal_soc, rx_tlv_hdr, &msdu_metadata);
  529. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  530. bool is_mcbc, is_sa_vld, is_da_vld;
  531. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  532. rx_tlv_hdr);
  533. is_sa_vld =
  534. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  535. rx_tlv_hdr);
  536. is_da_vld =
  537. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  538. rx_tlv_hdr);
  539. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  540. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  541. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  542. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  543. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  544. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  545. nbuf = dp_rx_sg_create(soc, nbuf);
  546. next = nbuf->next;
  547. if (qdf_nbuf_is_raw_frame(nbuf)) {
  548. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  549. DP_STATS_INC_PKT(peer, rx.raw, 1, msdu_len);
  550. } else {
  551. qdf_nbuf_free(nbuf);
  552. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  553. dp_info_rl("scatter msdu len %d, dropped",
  554. msdu_len);
  555. nbuf = next;
  556. continue;
  557. }
  558. } else {
  559. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  560. pkt_len = msdu_len +
  561. msdu_metadata.l3_hdr_pad +
  562. soc->rx_pkt_tlv_size;
  563. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  564. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  565. }
  566. /*
  567. * process frame for mulitpass phrase processing
  568. */
  569. if (qdf_unlikely(vdev->multipass_en)) {
  570. if (dp_rx_multipass_process(peer, nbuf, tid) == false) {
  571. DP_STATS_INC(peer, rx.multipass_rx_pkt_drop, 1);
  572. qdf_nbuf_free(nbuf);
  573. nbuf = next;
  574. continue;
  575. }
  576. }
  577. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, peer)) {
  578. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  579. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  580. /* Drop & free packet */
  581. qdf_nbuf_free(nbuf);
  582. /* Statistics */
  583. nbuf = next;
  584. continue;
  585. }
  586. if (qdf_unlikely(peer && (peer->nawds_enabled) &&
  587. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  588. (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc,
  589. rx_tlv_hdr) ==
  590. false))) {
  591. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  592. DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
  593. qdf_nbuf_free(nbuf);
  594. nbuf = next;
  595. continue;
  596. }
  597. /*
  598. * Drop non-EAPOL frames from unauthorized peer.
  599. */
  600. if (qdf_likely(peer) && qdf_unlikely(!peer->authorize) &&
  601. !qdf_nbuf_is_raw_frame(nbuf)) {
  602. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  603. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  604. if (!is_eapol) {
  605. DP_STATS_INC(soc,
  606. rx.err.peer_unauth_rx_pkt_drop,
  607. 1);
  608. qdf_nbuf_free(nbuf);
  609. nbuf = next;
  610. continue;
  611. }
  612. }
  613. if (soc->process_rx_status)
  614. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  615. /* Update the protocol tag in SKB based on CCE metadata */
  616. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  617. reo_ring_num, false, true);
  618. /* Update the flow tag in SKB based on FSE metadata */
  619. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  620. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, peer,
  621. reo_ring_num, tid_stats);
  622. if (qdf_unlikely(vdev->mesh_vdev)) {
  623. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  624. == QDF_STATUS_SUCCESS) {
  625. dp_rx_info("%pK: mesh pkt filtered", soc);
  626. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  627. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  628. 1);
  629. qdf_nbuf_free(nbuf);
  630. nbuf = next;
  631. continue;
  632. }
  633. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
  634. }
  635. if (qdf_likely(vdev->rx_decap_type ==
  636. htt_cmn_pkt_type_ethernet) &&
  637. qdf_likely(!vdev->mesh_vdev)) {
  638. /* WDS Destination Address Learning */
  639. dp_rx_da_learn(soc, rx_tlv_hdr, peer, nbuf);
  640. /* Due to HW issue, sometimes we see that the sa_idx
  641. * and da_idx are invalid with sa_valid and da_valid
  642. * bits set
  643. *
  644. * in this case we also see that value of
  645. * sa_sw_peer_id is set as 0
  646. *
  647. * Drop the packet if sa_idx and da_idx OOB or
  648. * sa_sw_peerid is 0
  649. */
  650. if (!is_sa_da_idx_valid(soc, rx_tlv_hdr, nbuf,
  651. msdu_metadata)) {
  652. qdf_nbuf_free(nbuf);
  653. nbuf = next;
  654. DP_STATS_INC(soc, rx.err.invalid_sa_da_idx, 1);
  655. continue;
  656. }
  657. if (qdf_unlikely(dp_rx_mec_check_wrapper(soc,
  658. peer,
  659. rx_tlv_hdr,
  660. nbuf))) {
  661. /* this is a looped back MCBC pkt,drop it */
  662. DP_STATS_INC_PKT(peer, rx.mec_drop, 1,
  663. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  664. qdf_nbuf_free(nbuf);
  665. nbuf = next;
  666. continue;
  667. }
  668. /* WDS Source Port Learning */
  669. if (qdf_likely(vdev->wds_enabled))
  670. dp_rx_wds_srcport_learn(soc,
  671. rx_tlv_hdr,
  672. peer,
  673. nbuf,
  674. msdu_metadata);
  675. /* Intrabss-fwd */
  676. if (dp_rx_check_ap_bridge(vdev))
  677. if (DP_RX_INTRABSS_FWD(soc, peer, rx_tlv_hdr,
  678. nbuf, msdu_metadata)) {
  679. nbuf = next;
  680. tid_stats->intrabss_cnt++;
  681. continue; /* Get next desc */
  682. }
  683. }
  684. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  685. dp_rx_update_stats(soc, nbuf);
  686. DP_RX_LIST_APPEND(deliver_list_head,
  687. deliver_list_tail,
  688. nbuf);
  689. DP_STATS_INC_PKT(peer, rx.to_stack, 1,
  690. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  691. if (qdf_unlikely(peer->in_twt))
  692. DP_STATS_INC_PKT(peer, rx.to_stack_twt, 1,
  693. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  694. tid_stats->delivered_to_stack++;
  695. nbuf = next;
  696. }
  697. if (qdf_likely(deliver_list_head)) {
  698. if (qdf_likely(peer)) {
  699. dp_rx_deliver_to_pkt_capture(soc, vdev->pdev, peer_id,
  700. pkt_capture_offload,
  701. deliver_list_head);
  702. if (!pkt_capture_offload)
  703. dp_rx_deliver_to_stack(soc, vdev, peer,
  704. deliver_list_head,
  705. deliver_list_tail);
  706. } else {
  707. nbuf = deliver_list_head;
  708. while (nbuf) {
  709. next = nbuf->next;
  710. nbuf->next = NULL;
  711. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  712. nbuf = next;
  713. }
  714. }
  715. }
  716. if (qdf_likely(peer))
  717. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  718. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  719. if (quota) {
  720. num_pending =
  721. dp_rx_srng_get_num_pending(hal_soc,
  722. hal_ring_hdl,
  723. num_entries,
  724. &near_full);
  725. if (num_pending) {
  726. DP_STATS_INC(soc, rx.hp_oos2, 1);
  727. if (!hif_exec_should_yield(scn, intr_id))
  728. goto more_data;
  729. if (qdf_unlikely(near_full)) {
  730. DP_STATS_INC(soc, rx.near_full, 1);
  731. goto more_data;
  732. }
  733. }
  734. }
  735. if (vdev && vdev->osif_fisa_flush)
  736. vdev->osif_fisa_flush(soc, reo_ring_num);
  737. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  738. vdev->osif_gro_flush(vdev->osif_vdev,
  739. reo_ring_num);
  740. }
  741. }
  742. /* Update histogram statistics by looping through pdev's */
  743. DP_RX_HIST_STATS_PER_PDEV();
  744. return rx_bufs_used; /* Assume no scale factor for now */
  745. }
  746. QDF_STATUS dp_rx_desc_pool_init_li(struct dp_soc *soc,
  747. struct rx_desc_pool *rx_desc_pool,
  748. uint32_t pool_id)
  749. {
  750. return dp_rx_desc_pool_init_generic(soc, rx_desc_pool, pool_id);
  751. }
  752. void dp_rx_desc_pool_deinit_li(struct dp_soc *soc,
  753. struct rx_desc_pool *rx_desc_pool,
  754. uint32_t pool_id)
  755. {
  756. }
  757. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_li(
  758. struct dp_soc *soc,
  759. void *ring_desc,
  760. struct dp_rx_desc **r_rx_desc)
  761. {
  762. struct hal_buf_info buf_info = {0};
  763. hal_soc_handle_t hal_soc = soc->hal_soc;
  764. /* only cookie and rbm will be valid in buf_info */
  765. hal_rx_buf_cookie_rbm_get(hal_soc, (uint32_t *)ring_desc,
  766. &buf_info);
  767. if (qdf_unlikely(buf_info.rbm !=
  768. HAL_RX_BUF_RBM_SW3_BM(soc->wbm_sw0_bm_id))) {
  769. /* TODO */
  770. /* Call appropriate handler */
  771. DP_STATS_INC(soc, rx.err.invalid_rbm, 1);
  772. dp_rx_err("%pK: Invalid RBM %d", soc, buf_info.rbm);
  773. return QDF_STATUS_E_INVAL;
  774. }
  775. *r_rx_desc = dp_rx_cookie_2_va_rxdma_buf(soc, buf_info.sw_cookie);
  776. return QDF_STATUS_SUCCESS;
  777. }