hal_api_mon.h 36 KB

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  1. /*
  2. * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_API_MON_H_
  19. #define _HAL_API_MON_H_
  20. #include "qdf_types.h"
  21. #include "hal_internal.h"
  22. #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET
  23. #define HAL_RX_LSB(block, field) block##_##field##_LSB
  24. #define HAL_RX_MASk(block, field) block##_##field##_MASK
  25. #define HAL_RX_GET(_ptr, block, field) \
  26. (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \
  27. HAL_RX_MASk(block, field)) >> \
  28. HAL_RX_LSB(block, field))
  29. #define HAL_RX_PHY_DATA_RADAR 0x01
  30. #define HAL_SU_MU_CODING_LDPC 0x01
  31. #define HAL_RX_FCS_LEN (4)
  32. #define KEY_EXTIV 0x20
  33. #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000
  34. #define HAL_RX_USER_TLV32_TYPE_LSB 1
  35. #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE
  36. #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000
  37. #define HAL_RX_USER_TLV32_LEN_LSB 10
  38. #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00
  39. #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000
  40. #define HAL_RX_USER_TLV32_USERID_LSB 26
  41. #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000
  42. #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1)
  43. #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask))
  44. #define HAL_RX_TLV32_HDR_SIZE 4
  45. #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \
  46. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  47. HAL_RX_USER_TLV32_TYPE_MASK) >> \
  48. HAL_RX_USER_TLV32_TYPE_LSB)
  49. #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \
  50. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  51. HAL_RX_USER_TLV32_LEN_MASK) >> \
  52. HAL_RX_USER_TLV32_LEN_LSB)
  53. #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \
  54. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  55. HAL_RX_USER_TLV32_USERID_MASK) >> \
  56. HAL_RX_USER_TLV32_USERID_LSB)
  57. #define HAL_TLV_STATUS_PPDU_NOT_DONE 0
  58. #define HAL_TLV_STATUS_PPDU_DONE 1
  59. #define HAL_TLV_STATUS_BUF_DONE 2
  60. #define HAL_MAX_UL_MU_USERS 8
  61. #define HAL_RX_PKT_TYPE_11A 0
  62. #define HAL_RX_PKT_TYPE_11B 1
  63. #define HAL_RX_PKT_TYPE_11N 2
  64. #define HAL_RX_PKT_TYPE_11AC 3
  65. #define HAL_RX_PKT_TYPE_11AX 4
  66. #define HAL_RX_RECEPTION_TYPE_SU 0
  67. #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1
  68. #define HAL_RX_RECEPTION_TYPE_OFDMA 2
  69. #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3
  70. /* Multiply rate by 2 to avoid float point
  71. * and get rate in units of 500kbps
  72. */
  73. #define HAL_11B_RATE_0MCS 11*2
  74. #define HAL_11B_RATE_1MCS 5.5*2
  75. #define HAL_11B_RATE_2MCS 2*2
  76. #define HAL_11B_RATE_3MCS 1*2
  77. #define HAL_11B_RATE_4MCS 11*2
  78. #define HAL_11B_RATE_5MCS 5.5*2
  79. #define HAL_11B_RATE_6MCS 2*2
  80. #define HAL_11A_RATE_0MCS 48*2
  81. #define HAL_11A_RATE_1MCS 24*2
  82. #define HAL_11A_RATE_2MCS 12*2
  83. #define HAL_11A_RATE_3MCS 6*2
  84. #define HAL_11A_RATE_4MCS 54*2
  85. #define HAL_11A_RATE_5MCS 36*2
  86. #define HAL_11A_RATE_6MCS 18*2
  87. #define HAL_11A_RATE_7MCS 9*2
  88. #define HE_GI_0_8 0
  89. #define HE_GI_1_6 1
  90. #define HE_GI_3_2 2
  91. #define HT_SGI_PRESENT 0x80
  92. #define HE_LTF_1_X 0
  93. #define HE_LTF_2_X 1
  94. #define HE_LTF_4_X 2
  95. #define VHT_SIG_SU_NSS_MASK 0x7
  96. #define HAL_TID_INVALID 31
  97. #define HAL_AST_IDX_INVALID 0xFFFF
  98. #ifdef GET_MSDU_AGGREGATION
  99. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\
  100. {\
  101. struct rx_msdu_end *rx_msdu_end;\
  102. bool first_msdu, last_msdu; \
  103. rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\
  104. first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\
  105. last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\
  106. if (first_msdu && last_msdu)\
  107. rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\
  108. else\
  109. rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \
  110. } \
  111. #else
  112. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)
  113. #endif
  114. enum {
  115. HAL_HW_RX_DECAP_FORMAT_RAW = 0,
  116. HAL_HW_RX_DECAP_FORMAT_NWIFI,
  117. HAL_HW_RX_DECAP_FORMAT_ETH2,
  118. HAL_HW_RX_DECAP_FORMAT_8023,
  119. };
  120. enum {
  121. DP_PPDU_STATUS_START,
  122. DP_PPDU_STATUS_DONE,
  123. };
  124. static inline
  125. uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void)
  126. {
  127. /* return the HW_RX_DESC size */
  128. return sizeof(struct rx_pkt_tlvs);
  129. }
  130. static inline
  131. uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data)
  132. {
  133. return data;
  134. }
  135. static inline
  136. uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr)
  137. {
  138. struct rx_attention *rx_attn;
  139. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  140. rx_attn = &rx_desc->attn_tlv.rx_attn;
  141. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
  142. }
  143. static inline
  144. uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr)
  145. {
  146. struct rx_attention *rx_attn;
  147. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  148. rx_attn = &rx_desc->attn_tlv.rx_attn;
  149. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
  150. }
  151. static inline
  152. uint32_t
  153. HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) {
  154. struct rx_msdu_start *rx_msdu_start;
  155. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  156. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  157. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  158. }
  159. static inline
  160. uint8_t *
  161. HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) {
  162. uint8_t *rx_pkt_hdr;
  163. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  164. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  165. return rx_pkt_hdr;
  166. }
  167. static inline
  168. uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr)
  169. {
  170. struct rx_mpdu_info *rx_mpdu_info;
  171. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  172. rx_mpdu_info =
  173. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  174. return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
  175. }
  176. /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */
  177. static inline
  178. uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr)
  179. {
  180. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  181. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  182. return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
  183. }
  184. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  185. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  186. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \
  187. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \
  188. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB))
  189. #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \
  190. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  191. (((struct reo_entrance_ring *)reo_ent_desc) \
  192. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  193. #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \
  194. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  195. (((struct reo_entrance_ring *)reo_ent_desc) \
  196. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  197. #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \
  198. (HAL_RX_BUF_COOKIE_GET(& \
  199. (((struct reo_entrance_ring *)reo_ent_desc) \
  200. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  201. /**
  202. * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and
  203. * cookie from the REO entrance ring element
  204. *
  205. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  206. * the current descriptor
  207. * @ buf_info: structure to return the buffer information
  208. * @ msdu_cnt: pointer to msdu count in MPDU
  209. * Return: void
  210. */
  211. static inline
  212. void hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
  213. struct hal_buf_info *buf_info,
  214. void **pp_buf_addr_info,
  215. uint32_t *msdu_cnt
  216. )
  217. {
  218. struct reo_entrance_ring *reo_ent_ring =
  219. (struct reo_entrance_ring *)rx_desc;
  220. struct buffer_addr_info *buf_addr_info;
  221. struct rx_mpdu_desc_info *rx_mpdu_desc_info_details;
  222. uint32_t loop_cnt;
  223. rx_mpdu_desc_info_details =
  224. &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
  225. *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details,
  226. RX_MPDU_DESC_INFO_0, MSDU_COUNT);
  227. loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT);
  228. buf_addr_info =
  229. &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
  230. buf_info->paddr =
  231. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  232. ((uint64_t)
  233. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  234. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  235. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  236. "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d\n",
  237. __func__, __LINE__, reo_ent_ring, buf_addr_info,
  238. (unsigned long long)buf_info->paddr, loop_cnt);
  239. *pp_buf_addr_info = (void *)buf_addr_info;
  240. }
  241. static inline
  242. void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
  243. struct hal_buf_info *buf_info, void **pp_buf_addr_info)
  244. {
  245. struct rx_msdu_link *msdu_link =
  246. (struct rx_msdu_link *)rx_msdu_link_desc;
  247. struct buffer_addr_info *buf_addr_info;
  248. buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info;
  249. buf_info->paddr =
  250. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  251. ((uint64_t)
  252. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  253. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  254. *pp_buf_addr_info = (void *)buf_addr_info;
  255. }
  256. /**
  257. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  258. *
  259. * @ soc : HAL version of the SOC pointer
  260. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  261. * @ buf_addr_info : void pointer to the buffer_addr_info
  262. *
  263. * Return: void
  264. */
  265. static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc,
  266. void *src_srng_desc, void *buf_addr_info)
  267. {
  268. struct buffer_addr_info *wbm_srng_buffer_addr_info =
  269. (struct buffer_addr_info *)src_srng_desc;
  270. uint64_t paddr;
  271. struct buffer_addr_info *p_buffer_addr_info =
  272. (struct buffer_addr_info *)buf_addr_info;
  273. paddr =
  274. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  275. ((uint64_t)
  276. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  277. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  278. "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx\n",
  279. __func__, __LINE__, src_srng_desc, (unsigned long long)paddr,
  280. (unsigned long long)p_buffer_addr_info->sw_buffer_cookie);
  281. /* Structure copy !!! */
  282. *wbm_srng_buffer_addr_info =
  283. *((struct buffer_addr_info *)buf_addr_info);
  284. }
  285. static inline
  286. uint32 hal_get_rx_msdu_link_desc_size(void)
  287. {
  288. return sizeof(struct rx_msdu_link);
  289. }
  290. enum {
  291. HAL_PKT_TYPE_OFDM = 0,
  292. HAL_PKT_TYPE_CCK,
  293. HAL_PKT_TYPE_HT,
  294. HAL_PKT_TYPE_VHT,
  295. HAL_PKT_TYPE_HE,
  296. };
  297. enum {
  298. HAL_SGI_0_8_US,
  299. HAL_SGI_0_4_US,
  300. HAL_SGI_1_6_US,
  301. HAL_SGI_3_2_US,
  302. };
  303. enum {
  304. HAL_FULL_RX_BW_20,
  305. HAL_FULL_RX_BW_40,
  306. HAL_FULL_RX_BW_80,
  307. HAL_FULL_RX_BW_160,
  308. };
  309. enum {
  310. HAL_RX_TYPE_SU,
  311. HAL_RX_TYPE_MU_MIMO,
  312. HAL_RX_TYPE_MU_OFDMA,
  313. HAL_RX_TYPE_MU_OFDMA_MIMO,
  314. };
  315. /**
  316. * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status
  317. *
  318. * @ hw_desc_addr: Start address of Rx HW TLVs
  319. * @ rs: Status for monitor mode
  320. *
  321. * Return: void
  322. */
  323. static inline
  324. void hal_rx_mon_hw_desc_get_mpdu_status(void *hw_desc_addr,
  325. struct mon_rx_status *rs)
  326. {
  327. struct rx_msdu_start *rx_msdu_start;
  328. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  329. uint32_t reg_value;
  330. static uint32_t sgi_hw_to_cdp[] = {
  331. CDP_SGI_0_8_US,
  332. CDP_SGI_0_4_US,
  333. CDP_SGI_1_6_US,
  334. CDP_SGI_3_2_US,
  335. };
  336. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  337. HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
  338. rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
  339. RX_MSDU_START_5, USER_RSSI);
  340. rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
  341. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
  342. rs->sgi = sgi_hw_to_cdp[reg_value];
  343. #if !defined(QCA_WIFI_QCA6290_11AX)
  344. rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS);
  345. #endif
  346. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
  347. rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
  348. /* TODO: rs->beamformed should be set for SU beamforming also */
  349. }
  350. struct hal_rx_ppdu_user_info {
  351. };
  352. struct hal_rx_ppdu_common_info {
  353. uint32_t ppdu_id;
  354. uint32_t last_ppdu_id;
  355. uint32_t ppdu_timestamp;
  356. uint32_t mpdu_cnt_fcs_ok;
  357. uint32_t mpdu_cnt_fcs_err;
  358. };
  359. struct hal_rx_msdu_payload_info {
  360. uint8_t *first_msdu_payload;
  361. uint32_t payload_len;
  362. };
  363. struct hal_rx_ppdu_info {
  364. struct hal_rx_ppdu_common_info com_info;
  365. struct hal_rx_ppdu_user_info user_info[HAL_MAX_UL_MU_USERS];
  366. struct mon_rx_status rx_status;
  367. struct hal_rx_msdu_payload_info msdu_info;
  368. };
  369. static inline uint32_t
  370. hal_get_rx_status_buf_size(void) {
  371. /* RX status buffer size is hard coded for now */
  372. return 2048;
  373. }
  374. static inline uint8_t*
  375. hal_rx_status_get_next_tlv(uint8_t *rx_tlv) {
  376. uint32_t tlv_len, tlv_tag;
  377. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
  378. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  379. /* The actual length of PPDU_END is the combined lenght of many PHY
  380. * TLVs that follow. Skip the TLV header and
  381. * rx_rxpcu_classification_overview that follows the header to get to
  382. * next TLV.
  383. */
  384. if (tlv_tag == WIFIRX_PPDU_END_E)
  385. tlv_len = sizeof(struct rx_rxpcu_classification_overview);
  386. return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len +
  387. HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3)));
  388. }
  389. static inline uint32_t
  390. hal_rx_status_get_tlv_info(void *rx_tlv, struct hal_rx_ppdu_info *ppdu_info)
  391. {
  392. uint32_t tlv_tag, user_id, tlv_len, value;
  393. uint8_t group_id = 0;
  394. uint8_t he_dcm = 0;
  395. uint8_t he_stbc = 0;
  396. uint16_t he_gi = 0;
  397. uint16_t he_ltf = 0;
  398. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  399. user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv);
  400. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
  401. rx_tlv = (uint8_t *) rx_tlv + HAL_RX_TLV32_HDR_SIZE;
  402. switch (tlv_tag) {
  403. case WIFIRX_PPDU_START_E:
  404. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  405. "[%s][%d] ppdu_start_e len=%d",
  406. __func__, __LINE__, tlv_len);
  407. ppdu_info->com_info.ppdu_id =
  408. HAL_RX_GET(rx_tlv, RX_PPDU_START_0,
  409. PHY_PPDU_ID);
  410. /* channel number is set in PHY meta data */
  411. ppdu_info->rx_status.chan_num =
  412. HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
  413. SW_PHY_META_DATA);
  414. ppdu_info->com_info.ppdu_timestamp =
  415. HAL_RX_GET(rx_tlv, RX_PPDU_START_2,
  416. PPDU_START_TIMESTAMP);
  417. break;
  418. case WIFIRX_PPDU_START_USER_INFO_E:
  419. break;
  420. case WIFIRX_PPDU_END_E:
  421. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  422. "[%s][%d] ppdu_end_e len=%d",
  423. __func__, __LINE__, tlv_len);
  424. /* This is followed by sub-TLVs of PPDU_END */
  425. break;
  426. case WIFIRXPCU_PPDU_END_INFO_E:
  427. ppdu_info->rx_status.tsft =
  428. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1,
  429. WB_TIMESTAMP_UPPER_32);
  430. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  431. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0,
  432. WB_TIMESTAMP_LOWER_32);
  433. ppdu_info->rx_status.duration =
  434. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_8,
  435. RX_PPDU_DURATION);
  436. break;
  437. case WIFIRX_PPDU_END_USER_STATS_E:
  438. {
  439. unsigned long tid = 0;
  440. uint16_t seq = 0;
  441. ppdu_info->rx_status.ast_index =
  442. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4,
  443. AST_INDEX);
  444. tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12,
  445. RECEIVED_QOS_DATA_TID_BITMAP);
  446. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8);
  447. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  448. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  449. ppdu_info->rx_status.tcp_msdu_count =
  450. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  451. TCP_MSDU_COUNT) +
  452. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  453. TCP_ACK_MSDU_COUNT);
  454. ppdu_info->rx_status.udp_msdu_count =
  455. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  456. UDP_MSDU_COUNT);
  457. ppdu_info->rx_status.other_msdu_count =
  458. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  459. OTHER_MSDU_COUNT);
  460. ppdu_info->rx_status.frame_control_info_valid =
  461. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  462. DATA_SEQUENCE_CONTROL_INFO_VALID);
  463. seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5,
  464. FIRST_DATA_SEQ_CTRL);
  465. if (ppdu_info->rx_status.frame_control_info_valid)
  466. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  467. ppdu_info->rx_status.preamble_type =
  468. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  469. HT_CONTROL_FIELD_PKT_TYPE);
  470. switch (ppdu_info->rx_status.preamble_type) {
  471. case HAL_RX_PKT_TYPE_11N:
  472. ppdu_info->rx_status.ht_flags = 1;
  473. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  474. break;
  475. case HAL_RX_PKT_TYPE_11AC:
  476. ppdu_info->rx_status.vht_flags = 1;
  477. break;
  478. case HAL_RX_PKT_TYPE_11AX:
  479. ppdu_info->rx_status.he_flags = 1;
  480. break;
  481. default:
  482. break;
  483. }
  484. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  485. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  486. MPDU_CNT_FCS_OK);
  487. ppdu_info->com_info.mpdu_cnt_fcs_err =
  488. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2,
  489. MPDU_CNT_FCS_ERR);
  490. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  491. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  492. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  493. else
  494. ppdu_info->rx_status.rs_flags &=
  495. (~IEEE80211_AMPDU_FLAG);
  496. break;
  497. }
  498. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  499. break;
  500. case WIFIRX_PPDU_END_STATUS_DONE_E:
  501. return HAL_TLV_STATUS_PPDU_DONE;
  502. case WIFIDUMMY_E:
  503. return HAL_TLV_STATUS_BUF_DONE;
  504. case WIFIPHYRX_HT_SIG_E:
  505. {
  506. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  507. HAL_RX_OFFSET(PHYRX_HT_SIG_0,
  508. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  509. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1,
  510. FEC_CODING);
  511. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  512. 1 : 0;
  513. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  514. HT_SIG_INFO_0, MCS);
  515. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  516. HT_SIG_INFO_0, CBW);
  517. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  518. HT_SIG_INFO_1, SHORT_GI);
  519. break;
  520. }
  521. case WIFIPHYRX_L_SIG_B_E:
  522. {
  523. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  524. HAL_RX_OFFSET(PHYRX_L_SIG_B_0,
  525. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  526. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE);
  527. switch (value) {
  528. case 1:
  529. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  530. break;
  531. case 2:
  532. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  533. break;
  534. case 3:
  535. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  536. break;
  537. case 4:
  538. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  539. break;
  540. case 5:
  541. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  542. break;
  543. case 6:
  544. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  545. break;
  546. case 7:
  547. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  548. break;
  549. default:
  550. break;
  551. }
  552. ppdu_info->rx_status.cck_flag = 1;
  553. break;
  554. }
  555. case WIFIPHYRX_L_SIG_A_E:
  556. {
  557. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  558. HAL_RX_OFFSET(PHYRX_L_SIG_A_0,
  559. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  560. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE);
  561. switch (value) {
  562. case 8:
  563. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  564. break;
  565. case 9:
  566. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  567. break;
  568. case 10:
  569. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  570. break;
  571. case 11:
  572. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  573. break;
  574. case 12:
  575. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  576. break;
  577. case 13:
  578. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  579. break;
  580. case 14:
  581. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  582. break;
  583. case 15:
  584. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  585. break;
  586. default:
  587. break;
  588. }
  589. ppdu_info->rx_status.ofdm_flag = 1;
  590. break;
  591. }
  592. case WIFIPHYRX_VHT_SIG_A_E:
  593. {
  594. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  595. HAL_RX_OFFSET(PHYRX_VHT_SIG_A_0,
  596. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  597. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1,
  598. SU_MU_CODING);
  599. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  600. 1 : 0;
  601. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID);
  602. ppdu_info->rx_status.vht_flag_values5 = group_id;
  603. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  604. VHT_SIG_A_INFO_1, MCS);
  605. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  606. VHT_SIG_A_INFO_1, GI_SETTING);
  607. #if !defined(QCA_WIFI_QCA6290_11AX)
  608. value = HAL_RX_GET(vht_sig_a_info,
  609. VHT_SIG_A_INFO_0, N_STS);
  610. ppdu_info->rx_status.nss = ((value & VHT_SIG_SU_NSS_MASK) + 1);
  611. #else
  612. ppdu_info->rx_status.nss = 0;
  613. #endif
  614. ppdu_info->rx_status.vht_flag_values3[0] =
  615. (((ppdu_info->rx_status.mcs) << 4)
  616. | ppdu_info->rx_status.nss);
  617. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  618. VHT_SIG_A_INFO_0, BANDWIDTH);
  619. ppdu_info->rx_status.vht_flag_values2 =
  620. ppdu_info->rx_status.bw;
  621. ppdu_info->rx_status.vht_flag_values4 =
  622. HAL_RX_GET(vht_sig_a_info,
  623. VHT_SIG_A_INFO_1, SU_MU_CODING);
  624. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  625. VHT_SIG_A_INFO_1, BEAMFORMED);
  626. break;
  627. }
  628. case WIFIPHYRX_HE_SIG_A_SU_E:
  629. {
  630. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  631. HAL_RX_OFFSET(PHYRX_HE_SIG_A_SU_0,
  632. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  633. ppdu_info->rx_status.he_flags = 1;
  634. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  635. FORMAT_INDICATION);
  636. if (value == 0) {
  637. ppdu_info->rx_status.he_data1 =
  638. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  639. } else {
  640. ppdu_info->rx_status.he_data1 =
  641. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  642. }
  643. /* data1 */
  644. ppdu_info->rx_status.he_data1 |=
  645. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  646. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  647. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  648. QDF_MON_STATUS_HE_MCS_KNOWN |
  649. QDF_MON_STATUS_HE_DCM_KNOWN |
  650. QDF_MON_STATUS_HE_CODING_KNOWN |
  651. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  652. QDF_MON_STATUS_HE_STBC_KNOWN |
  653. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  654. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  655. /* data2 */
  656. ppdu_info->rx_status.he_data2 =
  657. QDF_MON_STATUS_HE_GI_KNOWN;
  658. ppdu_info->rx_status.he_data2 |=
  659. QDF_MON_STATUS_TXBF_KNOWN |
  660. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  661. QDF_MON_STATUS_TXOP_KNOWN |
  662. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  663. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  664. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  665. /* data3 */
  666. value = HAL_RX_GET(he_sig_a_su_info,
  667. HE_SIG_A_SU_INFO_0, BSS_COLOR_ID);
  668. ppdu_info->rx_status.he_data3 = value;
  669. value = HAL_RX_GET(he_sig_a_su_info,
  670. HE_SIG_A_SU_INFO_0, BEAM_CHANGE);
  671. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  672. ppdu_info->rx_status.he_data3 |= value;
  673. value = HAL_RX_GET(he_sig_a_su_info,
  674. HE_SIG_A_SU_INFO_0, DL_UL_FLAG);
  675. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  676. ppdu_info->rx_status.he_data3 |= value;
  677. value = HAL_RX_GET(he_sig_a_su_info,
  678. HE_SIG_A_SU_INFO_0, TRANSMIT_MCS);
  679. ppdu_info->rx_status.mcs = value;
  680. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  681. ppdu_info->rx_status.he_data3 |= value;
  682. value = HAL_RX_GET(he_sig_a_su_info,
  683. HE_SIG_A_SU_INFO_0, DCM);
  684. he_dcm = value;
  685. value = value << QDF_MON_STATUS_DCM_SHIFT;
  686. ppdu_info->rx_status.he_data3 |= value;
  687. value = HAL_RX_GET(he_sig_a_su_info,
  688. HE_SIG_A_SU_INFO_1, CODING);
  689. value = value << QDF_MON_STATUS_CODING_SHIFT;
  690. ppdu_info->rx_status.he_data3 |= value;
  691. value = HAL_RX_GET(he_sig_a_su_info,
  692. HE_SIG_A_SU_INFO_1,
  693. LDPC_EXTRA_SYMBOL);
  694. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  695. ppdu_info->rx_status.he_data3 |= value;
  696. value = HAL_RX_GET(he_sig_a_su_info,
  697. HE_SIG_A_SU_INFO_1, STBC);
  698. he_stbc = value;
  699. value = value << QDF_MON_STATUS_STBC_SHIFT;
  700. ppdu_info->rx_status.he_data3 |= value;
  701. /* data4 */
  702. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  703. SPATIAL_REUSE);
  704. ppdu_info->rx_status.he_data4 = value;
  705. /* data5 */
  706. value = HAL_RX_GET(he_sig_a_su_info,
  707. HE_SIG_A_SU_INFO_0, TRANSMIT_BW);
  708. ppdu_info->rx_status.he_data5 = value;
  709. ppdu_info->rx_status.bw = value;
  710. value = HAL_RX_GET(he_sig_a_su_info,
  711. HE_SIG_A_SU_INFO_0, CP_LTF_SIZE);
  712. switch (value) {
  713. case 0:
  714. he_gi = HE_GI_0_8;
  715. he_ltf = HE_LTF_1_X;
  716. break;
  717. case 1:
  718. he_gi = HE_GI_0_8;
  719. he_ltf = HE_LTF_2_X;
  720. break;
  721. case 2:
  722. he_gi = HE_GI_1_6;
  723. he_ltf = HE_LTF_2_X;
  724. break;
  725. case 3:
  726. if (he_dcm && he_stbc) {
  727. he_gi = HE_GI_0_8;
  728. he_ltf = HE_LTF_4_X;
  729. } else {
  730. he_gi = HE_GI_3_2;
  731. he_ltf = HE_LTF_4_X;
  732. }
  733. break;
  734. }
  735. ppdu_info->rx_status.sgi = he_gi;
  736. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  737. ppdu_info->rx_status.he_data5 |= value;
  738. value = he_ltf << QDF_MON_STATUS_HE_LTF_SHIFT;
  739. ppdu_info->rx_status.he_data5 |= value;
  740. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  741. PACKET_EXTENSION_A_FACTOR);
  742. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  743. ppdu_info->rx_status.he_data5 |= value;
  744. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF);
  745. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  746. ppdu_info->rx_status.he_data5 |= value;
  747. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  748. PACKET_EXTENSION_PE_DISAMBIGUITY);
  749. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  750. ppdu_info->rx_status.he_data5 |= value;
  751. /* data6 */
  752. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
  753. value++;
  754. ppdu_info->rx_status.nss = value;
  755. ppdu_info->rx_status.he_data6 = value;
  756. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  757. DOPPLER_INDICATION);
  758. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  759. ppdu_info->rx_status.he_data6 |= value;
  760. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  761. TXOP_DURATION);
  762. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  763. ppdu_info->rx_status.he_data6 |= value;
  764. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  765. HE_SIG_A_SU_INFO_1, TXBF);
  766. break;
  767. }
  768. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  769. {
  770. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  771. HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_DL_0,
  772. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  773. ppdu_info->rx_status.he_mu_flags = 1;
  774. /* HE Flags */
  775. /*data1*/
  776. ppdu_info->rx_status.he_data1 =
  777. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  778. ppdu_info->rx_status.he_data1 |=
  779. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  780. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  781. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  782. QDF_MON_STATUS_HE_STBC_KNOWN |
  783. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  784. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  785. /* data2 */
  786. ppdu_info->rx_status.he_data2 =
  787. QDF_MON_STATUS_HE_GI_KNOWN;
  788. ppdu_info->rx_status.he_data2 |=
  789. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  790. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  791. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  792. QDF_MON_STATUS_TXOP_KNOWN |
  793. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  794. /*data3*/
  795. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  796. HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID);
  797. ppdu_info->rx_status.he_data3 = value;
  798. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  799. HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG);
  800. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  801. ppdu_info->rx_status.he_data3 |= value;
  802. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  803. HE_SIG_A_MU_DL_INFO_1,
  804. LDPC_EXTRA_SYMBOL);
  805. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  806. ppdu_info->rx_status.he_data3 |= value;
  807. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  808. HE_SIG_A_MU_DL_INFO_1, STBC);
  809. he_stbc = value;
  810. value = value << QDF_MON_STATUS_STBC_SHIFT;
  811. ppdu_info->rx_status.he_data3 |= value;
  812. /*data4*/
  813. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  814. SPATIAL_REUSE);
  815. ppdu_info->rx_status.he_data4 = value;
  816. /*data5*/
  817. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  818. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  819. ppdu_info->rx_status.he_data5 = value;
  820. ppdu_info->rx_status.bw = value;
  821. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  822. HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE);
  823. switch (value) {
  824. case 0:
  825. he_gi = HE_GI_0_8;
  826. he_ltf = HE_LTF_4_X;
  827. break;
  828. case 1:
  829. he_gi = HE_GI_0_8;
  830. he_ltf = HE_LTF_2_X;
  831. break;
  832. case 2:
  833. he_gi = HE_GI_1_6;
  834. he_ltf = HE_LTF_2_X;
  835. break;
  836. case 3:
  837. he_gi = HE_GI_3_2;
  838. he_ltf = HE_LTF_4_X;
  839. break;
  840. }
  841. ppdu_info->rx_status.sgi = he_gi;
  842. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  843. ppdu_info->rx_status.he_data5 |= value;
  844. value = he_ltf << QDF_MON_STATUS_HE_LTF_SHIFT;
  845. ppdu_info->rx_status.he_data5 |= value;
  846. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  847. PACKET_EXTENSION_A_FACTOR);
  848. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  849. ppdu_info->rx_status.he_data5 |= value;
  850. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  851. PACKET_EXTENSION_PE_DISAMBIGUITY);
  852. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  853. ppdu_info->rx_status.he_data5 |= value;
  854. /*data6*/
  855. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  856. DOPPLER_INDICATION);
  857. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  858. ppdu_info->rx_status.he_data6 |= value;
  859. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  860. TXOP_DURATION);
  861. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  862. ppdu_info->rx_status.he_data6 |= value;
  863. /* HE-MU Flags */
  864. /* HE-MU-flags1 */
  865. ppdu_info->rx_status.he_flags1 =
  866. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  867. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  868. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  869. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  870. QDF_MON_STATUS_RU_0_KNOWN;
  871. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  872. HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B);
  873. ppdu_info->rx_status.he_flags1 |= value;
  874. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  875. HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B);
  876. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  877. ppdu_info->rx_status.he_flags1 |= value;
  878. /* HE-MU-flags2 */
  879. ppdu_info->rx_status.he_flags2 =
  880. QDF_MON_STATUS_BW_KNOWN;
  881. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  882. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  883. ppdu_info->rx_status.he_flags2 |= value;
  884. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  885. HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B);
  886. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  887. ppdu_info->rx_status.he_flags2 |= value;
  888. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  889. HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS);
  890. value = value - 1;
  891. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  892. ppdu_info->rx_status.he_flags2 |= value;
  893. break;
  894. }
  895. case WIFIPHYRX_HE_SIG_B1_MU_E:
  896. {
  897. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  898. HAL_RX_OFFSET(PHYRX_HE_SIG_B1_MU_0,
  899. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  900. ppdu_info->rx_status.he_sig_b_common_known |=
  901. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  902. /* TODO: Check on the availability of other fields in
  903. * sig_b_common
  904. */
  905. value = HAL_RX_GET(he_sig_b1_mu_info,
  906. HE_SIG_B1_MU_INFO_0, RU_ALLOCATION);
  907. ppdu_info->rx_status.he_RU[0] = value;
  908. break;
  909. }
  910. case WIFIPHYRX_HE_SIG_B2_MU_E:
  911. {
  912. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  913. HAL_RX_OFFSET(PHYRX_HE_SIG_B2_MU_0,
  914. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  915. /*
  916. * Not all "HE" fields can be updated from
  917. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  918. * to populate rest of the "HE" fields for MU scenarios.
  919. */
  920. /* HE-data1 */
  921. ppdu_info->rx_status.he_data1 |=
  922. QDF_MON_STATUS_HE_MCS_KNOWN |
  923. QDF_MON_STATUS_HE_CODING_KNOWN;
  924. /* HE-data2 */
  925. /* HE-data3 */
  926. value = HAL_RX_GET(he_sig_b2_mu_info,
  927. HE_SIG_B2_MU_INFO_0, STA_MCS);
  928. ppdu_info->rx_status.mcs = value;
  929. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  930. ppdu_info->rx_status.he_data3 |= value;
  931. value = HAL_RX_GET(he_sig_b2_mu_info,
  932. HE_SIG_B2_MU_INFO_0, STA_CODING);
  933. value = value << QDF_MON_STATUS_CODING_SHIFT;
  934. ppdu_info->rx_status.he_data3 |= value;
  935. /* HE-data4 */
  936. value = HAL_RX_GET(he_sig_b2_mu_info,
  937. HE_SIG_B2_MU_INFO_0, STA_ID);
  938. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  939. ppdu_info->rx_status.he_data4 |= value;
  940. /* HE-data5 */
  941. /* HE-data6 */
  942. value = HAL_RX_GET(he_sig_b2_mu_info,
  943. HE_SIG_B2_MU_INFO_0, NSTS);
  944. /* value n indicates n+1 spatial streams */
  945. value++;
  946. ppdu_info->rx_status.nss = value;
  947. ppdu_info->rx_status.he_data6 |= value;
  948. break;
  949. }
  950. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  951. {
  952. uint8_t *he_sig_b2_ofdma_info =
  953. (uint8_t *)rx_tlv +
  954. HAL_RX_OFFSET(PHYRX_HE_SIG_B2_OFDMA_0,
  955. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  956. /*
  957. * Not all "HE" fields can be updated from
  958. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  959. * to populate rest of "HE" fields for MU OFDMA scenarios.
  960. */
  961. /* HE-data1 */
  962. ppdu_info->rx_status.he_data1 |=
  963. QDF_MON_STATUS_HE_MCS_KNOWN |
  964. QDF_MON_STATUS_HE_DCM_KNOWN |
  965. QDF_MON_STATUS_HE_CODING_KNOWN;
  966. /* HE-data2 */
  967. ppdu_info->rx_status.he_data2 |=
  968. QDF_MON_STATUS_TXBF_KNOWN;
  969. /* HE-data3 */
  970. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  971. HE_SIG_B2_OFDMA_INFO_0, STA_MCS);
  972. ppdu_info->rx_status.mcs = value;
  973. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  974. ppdu_info->rx_status.he_data3 |= value;
  975. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  976. HE_SIG_B2_OFDMA_INFO_0, STA_DCM);
  977. he_dcm = value;
  978. value = value << QDF_MON_STATUS_DCM_SHIFT;
  979. ppdu_info->rx_status.he_data3 |= value;
  980. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  981. HE_SIG_B2_OFDMA_INFO_0, STA_CODING);
  982. value = value << QDF_MON_STATUS_CODING_SHIFT;
  983. ppdu_info->rx_status.he_data3 |= value;
  984. /* HE-data4 */
  985. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  986. HE_SIG_B2_OFDMA_INFO_0, STA_ID);
  987. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  988. ppdu_info->rx_status.he_data4 |= value;
  989. /* HE-data5 */
  990. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  991. HE_SIG_B2_OFDMA_INFO_0, TXBF);
  992. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  993. ppdu_info->rx_status.he_data5 |= value;
  994. /* HE-data6 */
  995. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  996. HE_SIG_B2_OFDMA_INFO_0, NSTS);
  997. /* value n indicates n+1 spatial streams */
  998. value++;
  999. ppdu_info->rx_status.nss = value;
  1000. ppdu_info->rx_status.he_data6 |= value;
  1001. break;
  1002. }
  1003. case WIFIPHYRX_RSSI_LEGACY_E:
  1004. {
  1005. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  1006. HAL_RX_OFFSET(PHYRX_RSSI_LEGACY_3,
  1007. RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS);
  1008. ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
  1009. PHYRX_RSSI_LEGACY_35, RSSI_COMB);
  1010. ppdu_info->rx_status.bw = HAL_RX_GET(rx_tlv,
  1011. #if !defined(QCA_WIFI_QCA6290_11AX)
  1012. PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH);
  1013. #else
  1014. PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
  1015. #endif
  1016. ppdu_info->rx_status.he_re = 0;
  1017. ppdu_info->rx_status.reception_type = HAL_RX_GET(rx_tlv,
  1018. PHYRX_RSSI_LEGACY_0, RECEPTION_TYPE);
  1019. value = HAL_RX_GET(rssi_info_tlv,
  1020. RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0);
  1021. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1022. "RSSI_PRI20_CHAIN0: %d\n", value);
  1023. value = HAL_RX_GET(rssi_info_tlv,
  1024. RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0);
  1025. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1026. "RSSI_EXT20_CHAIN0: %d\n", value);
  1027. value = HAL_RX_GET(rssi_info_tlv,
  1028. RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0);
  1029. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1030. "RSSI_EXT40_LOW20_CHAIN0: %d\n", value);
  1031. value = HAL_RX_GET(rssi_info_tlv,
  1032. RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0);
  1033. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1034. "RSSI_EXT40_HIGH20_CHAIN0: %d\n", value);
  1035. value = HAL_RX_GET(rssi_info_tlv,
  1036. RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0);
  1037. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1038. "RSSI_EXT80_LOW20_CHAIN0: %d\n", value);
  1039. value = HAL_RX_GET(rssi_info_tlv,
  1040. RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0);
  1041. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1042. "RSSI_EXT80_LOW_HIGH20_CHAIN0: %d\n", value);
  1043. value = HAL_RX_GET(rssi_info_tlv,
  1044. RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0);
  1045. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1046. "RSSI_EXT80_HIGH_LOW20_CHAIN0: %d\n", value);
  1047. value = HAL_RX_GET(rssi_info_tlv,
  1048. RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH20_CHAIN0);
  1049. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1050. "RSSI_EXT80_HIGH20_CHAIN0: %d\n", value);
  1051. break;
  1052. }
  1053. case WIFIRX_HEADER_E:
  1054. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  1055. ppdu_info->msdu_info.payload_len = tlv_len;
  1056. break;
  1057. case WIFIRX_MPDU_START_E:
  1058. {
  1059. uint8_t *rx_mpdu_start =
  1060. (uint8_t *)rx_tlv + HAL_RX_OFFSET(RX_MPDU_START_0,
  1061. RX_MPDU_INFO_RX_MPDU_INFO_DETAILS);
  1062. uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0,
  1063. PHY_PPDU_ID);
  1064. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  1065. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  1066. ppdu_info->rx_status.ppdu_len =
  1067. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1068. MPDU_LENGTH);
  1069. } else {
  1070. ppdu_info->rx_status.ppdu_len +=
  1071. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1072. MPDU_LENGTH);
  1073. }
  1074. break;
  1075. }
  1076. case 0:
  1077. return HAL_TLV_STATUS_PPDU_DONE;
  1078. default:
  1079. break;
  1080. }
  1081. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1082. "%s TLV type: %d, TLV len:%d",
  1083. __func__, tlv_tag, tlv_len);
  1084. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1085. }
  1086. static inline
  1087. uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc)
  1088. {
  1089. return HAL_RX_TLV32_HDR_SIZE;
  1090. }
  1091. static inline QDF_STATUS
  1092. hal_get_rx_status_done(uint8_t *rx_tlv)
  1093. {
  1094. uint32_t tlv_tag;
  1095. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  1096. if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E)
  1097. return QDF_STATUS_SUCCESS;
  1098. else
  1099. return QDF_STATUS_E_EMPTY;
  1100. }
  1101. static inline QDF_STATUS
  1102. hal_clear_rx_status_done(uint8_t *rx_tlv)
  1103. {
  1104. *(uint32_t *)rx_tlv = 0;
  1105. return QDF_STATUS_SUCCESS;
  1106. }
  1107. #endif