core.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Copyright (c) 2011-2019, The Linux Foundation. All rights reserved.
  3. */
  4. #ifndef __MFD_TABLA_CORE_H__
  5. #define __MFD_TABLA_CORE_H__
  6. #include <linux/types.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/of_irq.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/pm_qos.h>
  11. #include "pdata.h"
  12. #define WCD9XXX_MAX_IRQ_REGS 4
  13. #define WCD9XXX_MAX_NUM_IRQS (WCD9XXX_MAX_IRQ_REGS * 8)
  14. #define WCD9XXX_SLIM_NUM_PORT_REG 3
  15. #define TABLA_VERSION_1_0 0
  16. #define TABLA_VERSION_1_1 1
  17. #define TABLA_VERSION_2_0 2
  18. #define TABLA_IS_1_X(ver) \
  19. (((ver == TABLA_VERSION_1_0) || (ver == TABLA_VERSION_1_1)) ? 1 : 0)
  20. #define TABLA_IS_2_0(ver) ((ver == TABLA_VERSION_2_0) ? 1 : 0)
  21. #define WCD9XXX_SUPPLY_BUCK_NAME "cdc-vdd-buck"
  22. #define SITAR_VERSION_1P0 0
  23. #define SITAR_VERSION_1P1 1
  24. #define SITAR_IS_1P0(ver) \
  25. ((ver == SITAR_VERSION_1P0) ? 1 : 0)
  26. #define SITAR_IS_1P1(ver) \
  27. ((ver == SITAR_VERSION_1P1) ? 1 : 0)
  28. #define TAIKO_VERSION_1_0 1
  29. #define TAIKO_IS_1_0(ver) \
  30. ((ver == TAIKO_VERSION_1_0) ? 1 : 0)
  31. #define TAPAN_VERSION_1_0 0
  32. #define TAPAN_IS_1_0(ver) \
  33. ((ver == TAPAN_VERSION_1_0) ? 1 : 0)
  34. #define TOMTOM_VERSION_1_0 1
  35. #define TOMTOM_IS_1_0(ver) \
  36. ((ver == TOMTOM_VERSION_1_0) ? 1 : 0)
  37. #define TASHA_VERSION_1_0 0
  38. #define TASHA_VERSION_1_1 1
  39. #define TASHA_VERSION_2_0 2
  40. #define TASHA_IS_1_0(wcd) \
  41. ((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
  42. ((wcd->version == TASHA_VERSION_1_0) ? 1 : 0) : 0)
  43. #define TASHA_IS_1_1(wcd) \
  44. ((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
  45. ((wcd->version == TASHA_VERSION_1_1) ? 1 : 0) : 0)
  46. #define TASHA_IS_2_0(wcd) \
  47. ((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
  48. ((wcd->version == TASHA_VERSION_2_0) ? 1 : 0) : 0)
  49. /*
  50. * As fine version info cannot be retrieved before tavil probe.
  51. * Define three coarse versions for possible future use before tavil probe.
  52. */
  53. #define TAVIL_VERSION_1_0 0
  54. #define TAVIL_VERSION_1_1 1
  55. #define TAVIL_VERSION_WCD9340_1_0 2
  56. #define TAVIL_VERSION_WCD9341_1_0 3
  57. #define TAVIL_VERSION_WCD9340_1_1 4
  58. #define TAVIL_VERSION_WCD9341_1_1 5
  59. #define TAVIL_IS_1_0(wcd) \
  60. ((wcd->type == WCD934X) ? \
  61. ((wcd->version == TAVIL_VERSION_1_0 || \
  62. wcd->version == TAVIL_VERSION_WCD9340_1_0 || \
  63. wcd->version == TAVIL_VERSION_WCD9341_1_0) ? 1 : 0) : 0)
  64. #define TAVIL_IS_1_1(wcd) \
  65. ((wcd->type == WCD934X) ? \
  66. ((wcd->version == TAVIL_VERSION_1_1 || \
  67. wcd->version == TAVIL_VERSION_WCD9340_1_1 || \
  68. wcd->version == TAVIL_VERSION_WCD9341_1_1) ? 1 : 0) : 0)
  69. #define TAVIL_IS_WCD9340_1_0(wcd) \
  70. ((wcd->type == WCD934X) ? \
  71. ((wcd->version == TAVIL_VERSION_WCD9340_1_0) ? 1 : 0) : 0)
  72. #define TAVIL_IS_WCD9341_1_0(wcd) \
  73. ((wcd->type == WCD934X) ? \
  74. ((wcd->version == TAVIL_VERSION_WCD9341_1_0) ? 1 : 0) : 0)
  75. #define TAVIL_IS_WCD9340_1_1(wcd) \
  76. ((wcd->type == WCD934X) ? \
  77. ((wcd->version == TAVIL_VERSION_WCD9340_1_1) ? 1 : 0) : 0)
  78. #define TAVIL_IS_WCD9341_1_1(wcd) \
  79. ((wcd->type == WCD934X) ? \
  80. ((wcd->version == TAVIL_VERSION_WCD9341_1_1) ? 1 : 0) : 0)
  81. #define IS_CODEC_TYPE(wcd, wcdtype) \
  82. ((wcd->type == wcdtype) ? true : false)
  83. #define IS_CODEC_VERSION(wcd, wcdversion) \
  84. ((wcd->version == wcdversion) ? true : false)
  85. enum {
  86. CDC_V_1_0,
  87. CDC_V_1_1,
  88. CDC_V_2_0,
  89. };
  90. enum codec_variant {
  91. WCD9XXX,
  92. WCD9330,
  93. WCD9335,
  94. WCD9326,
  95. WCD934X,
  96. };
  97. enum wcd9xxx_slim_slave_addr_type {
  98. WCD9XXX_SLIM_SLAVE_ADDR_TYPE_0,
  99. WCD9XXX_SLIM_SLAVE_ADDR_TYPE_1,
  100. };
  101. enum wcd9xxx_pm_state {
  102. WCD9XXX_PM_SLEEPABLE,
  103. WCD9XXX_PM_AWAKE,
  104. WCD9XXX_PM_ASLEEP,
  105. };
  106. enum {
  107. WCD9XXX_INTR_STATUS_BASE = 0,
  108. WCD9XXX_INTR_CLEAR_BASE,
  109. WCD9XXX_INTR_MASK_BASE,
  110. WCD9XXX_INTR_LEVEL_BASE,
  111. WCD9XXX_INTR_CLR_COMMIT,
  112. WCD9XXX_INTR_REG_MAX,
  113. };
  114. enum wcd9xxx_intf_status {
  115. WCD9XXX_INTERFACE_TYPE_PROBING,
  116. WCD9XXX_INTERFACE_TYPE_SLIMBUS,
  117. WCD9XXX_INTERFACE_TYPE_I2C,
  118. };
  119. enum {
  120. /* INTR_REG 0 */
  121. WCD9XXX_IRQ_SLIMBUS = 0,
  122. WCD9XXX_IRQ_MBHC_REMOVAL,
  123. WCD9XXX_IRQ_MBHC_SHORT_TERM,
  124. WCD9XXX_IRQ_MBHC_PRESS,
  125. WCD9XXX_IRQ_MBHC_RELEASE,
  126. WCD9XXX_IRQ_MBHC_POTENTIAL,
  127. WCD9XXX_IRQ_MBHC_INSERTION,
  128. WCD9XXX_IRQ_BG_PRECHARGE,
  129. /* INTR_REG 1 */
  130. WCD9XXX_IRQ_PA1_STARTUP,
  131. WCD9XXX_IRQ_PA2_STARTUP,
  132. WCD9XXX_IRQ_PA3_STARTUP,
  133. WCD9XXX_IRQ_PA4_STARTUP,
  134. WCD9306_IRQ_HPH_PA_OCPR_FAULT = WCD9XXX_IRQ_PA4_STARTUP,
  135. WCD9XXX_IRQ_PA5_STARTUP,
  136. WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
  137. WCD9306_IRQ_HPH_PA_OCPL_FAULT = WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
  138. WCD9XXX_IRQ_MICBIAS2_PRECHARGE,
  139. WCD9XXX_IRQ_MICBIAS3_PRECHARGE,
  140. /* INTR_REG 2 */
  141. WCD9XXX_IRQ_HPH_PA_OCPL_FAULT,
  142. WCD9XXX_IRQ_HPH_PA_OCPR_FAULT,
  143. WCD9XXX_IRQ_EAR_PA_OCPL_FAULT,
  144. WCD9XXX_IRQ_HPH_L_PA_STARTUP,
  145. WCD9XXX_IRQ_HPH_R_PA_STARTUP,
  146. WCD9320_IRQ_EAR_PA_STARTUP,
  147. WCD9306_IRQ_MBHC_JACK_SWITCH = WCD9320_IRQ_EAR_PA_STARTUP,
  148. WCD9310_NUM_IRQS,
  149. WCD9XXX_IRQ_RESERVED_0 = WCD9310_NUM_IRQS,
  150. WCD9XXX_IRQ_RESERVED_1,
  151. WCD9330_IRQ_SVASS_ERR_EXCEPTION = WCD9310_NUM_IRQS,
  152. WCD9330_IRQ_MBHC_JACK_SWITCH,
  153. /* INTR_REG 3 */
  154. WCD9XXX_IRQ_MAD_AUDIO,
  155. WCD9XXX_IRQ_MAD_ULTRASOUND,
  156. WCD9XXX_IRQ_MAD_BEACON,
  157. WCD9XXX_IRQ_SPEAKER_CLIPPING,
  158. WCD9320_IRQ_MBHC_JACK_SWITCH,
  159. WCD9306_NUM_IRQS,
  160. WCD9XXX_IRQ_VBAT_MONITOR_ATTACK = WCD9306_NUM_IRQS,
  161. WCD9XXX_IRQ_VBAT_MONITOR_RELEASE,
  162. WCD9XXX_NUM_IRQS,
  163. /* WCD9330 INTR1_REG 3*/
  164. WCD9330_IRQ_SVASS_ENGINE = WCD9XXX_IRQ_MAD_AUDIO,
  165. WCD9330_IRQ_MAD_AUDIO,
  166. WCD9330_IRQ_MAD_ULTRASOUND,
  167. WCD9330_IRQ_MAD_BEACON,
  168. WCD9330_IRQ_SPEAKER1_CLIPPING,
  169. WCD9330_IRQ_SPEAKER2_CLIPPING,
  170. WCD9330_IRQ_VBAT_MONITOR_ATTACK,
  171. WCD9330_IRQ_VBAT_MONITOR_RELEASE,
  172. WCD9330_NUM_IRQS,
  173. WCD9XXX_IRQ_RESERVED_2 = WCD9330_NUM_IRQS,
  174. };
  175. enum {
  176. TABLA_NUM_IRQS = WCD9310_NUM_IRQS,
  177. SITAR_NUM_IRQS = WCD9310_NUM_IRQS,
  178. TAIKO_NUM_IRQS = WCD9XXX_NUM_IRQS,
  179. TAPAN_NUM_IRQS = WCD9306_NUM_IRQS,
  180. TOMTOM_NUM_IRQS = WCD9330_NUM_IRQS,
  181. };
  182. struct intr_data {
  183. int intr_num;
  184. bool clear_first;
  185. };
  186. struct wcd9xxx_core_resource {
  187. struct mutex irq_lock;
  188. struct mutex nested_irq_lock;
  189. enum wcd9xxx_pm_state pm_state;
  190. struct mutex pm_lock;
  191. /* pm_wq notifies change of pm_state */
  192. wait_queue_head_t pm_wq;
  193. struct pm_qos_request pm_qos_req;
  194. int wlock_holders;
  195. /* holds the table of interrupts per codec */
  196. const struct intr_data *intr_table;
  197. int intr_table_size;
  198. unsigned int irq_base;
  199. unsigned int irq;
  200. u8 irq_masks_cur[WCD9XXX_MAX_IRQ_REGS];
  201. u8 irq_masks_cache[WCD9XXX_MAX_IRQ_REGS];
  202. bool irq_level_high[WCD9XXX_MAX_NUM_IRQS];
  203. int num_irqs;
  204. int num_irq_regs;
  205. u16 intr_reg[WCD9XXX_INTR_REG_MAX];
  206. struct regmap *wcd_core_regmap;
  207. /* Pointer to parent container data structure */
  208. void *parent;
  209. struct device *dev;
  210. struct irq_domain *domain;
  211. };
  212. /*
  213. * data structure for Slimbus and I2S channel.
  214. * Some of fields are only used in smilbus mode
  215. */
  216. struct wcd9xxx_ch {
  217. u32 sph; /* share channel handle - slimbus only */
  218. u32 ch_num; /*
  219. * vitrual channel number, such as 128 -144.
  220. * apply for slimbus only
  221. */
  222. u16 ch_h; /* chanel handle - slimbus only */
  223. u16 port; /*
  224. * tabla port for RX and TX
  225. * such as 0-9 for TX and 10 -16 for RX
  226. * apply for both i2s and slimbus
  227. */
  228. u16 shift; /*
  229. * shift bit for RX and TX
  230. * apply for both i2s and slimbus
  231. */
  232. struct list_head list; /*
  233. * channel link list
  234. * apply for both i2s and slimbus
  235. */
  236. };
  237. struct wcd9xxx_codec_dai_data {
  238. u32 rate; /* sample rate */
  239. u32 bit_width; /* sit width 16,24,32 */
  240. struct list_head wcd9xxx_ch_list; /* channel list */
  241. u16 grph; /* slimbus group handle */
  242. unsigned long ch_mask;
  243. wait_queue_head_t dai_wait;
  244. bool bus_down_in_recovery;
  245. };
  246. #define WCD9XXX_CH(xport, xshift) \
  247. {.port = xport, .shift = xshift}
  248. enum wcd9xxx_chipid_major {
  249. TABLA_MAJOR = cpu_to_le16(0x100),
  250. SITAR_MAJOR = cpu_to_le16(0x101),
  251. TAIKO_MAJOR = cpu_to_le16(0x102),
  252. TAPAN_MAJOR = cpu_to_le16(0x103),
  253. TOMTOM_MAJOR = cpu_to_le16(0x105),
  254. TASHA_MAJOR = cpu_to_le16(0x0),
  255. TASHA2P0_MAJOR = cpu_to_le16(0x107),
  256. TAVIL_MAJOR = cpu_to_le16(0x108),
  257. };
  258. enum codec_power_states {
  259. WCD_REGION_POWER_COLLAPSE_REMOVE,
  260. WCD_REGION_POWER_COLLAPSE_BEGIN,
  261. WCD_REGION_POWER_DOWN,
  262. };
  263. enum wcd_power_regions {
  264. WCD9XXX_DIG_CORE_REGION_1,
  265. WCD9XXX_MAX_PWR_REGIONS,
  266. };
  267. struct wcd9xxx_codec_type {
  268. u16 id_major;
  269. u16 id_minor;
  270. struct mfd_cell *dev;
  271. int size;
  272. int num_irqs;
  273. int version; /* -1 to retrieve version from chip version register */
  274. enum wcd9xxx_slim_slave_addr_type slim_slave_type;
  275. u16 i2c_chip_status;
  276. const struct intr_data *intr_tbl;
  277. int intr_tbl_size;
  278. u16 intr_reg[WCD9XXX_INTR_REG_MAX];
  279. };
  280. struct wcd9xxx_power_region {
  281. enum codec_power_states power_state;
  282. u16 pwr_collapse_reg_min;
  283. u16 pwr_collapse_reg_max;
  284. };
  285. struct wcd9xxx {
  286. struct device *dev;
  287. struct slim_device *slim;
  288. struct slim_device *slim_slave;
  289. struct mutex io_lock;
  290. struct mutex xfer_lock;
  291. struct mutex reset_lock;
  292. u8 version;
  293. int reset_gpio;
  294. struct device_node *wcd_rst_np;
  295. int (*read_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg,
  296. int bytes, void *dest, bool interface_reg);
  297. int (*write_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg,
  298. int bytes, void *src, bool interface_reg);
  299. int (*multi_reg_write)(struct wcd9xxx *wcd9xxx, const void *data,
  300. size_t count);
  301. int (*dev_down)(struct wcd9xxx *wcd9xxx);
  302. int (*post_reset)(struct wcd9xxx *wcd9xxx);
  303. void *ssr_priv;
  304. bool dev_up;
  305. u32 num_of_supplies;
  306. struct regulator_bulk_data *supplies;
  307. struct wcd9xxx_core_resource core_res;
  308. u16 id_minor;
  309. u16 id_major;
  310. /* Slimbus or I2S port */
  311. u32 num_rx_port;
  312. u32 num_tx_port;
  313. struct wcd9xxx_ch *rx_chs;
  314. struct wcd9xxx_ch *tx_chs;
  315. u32 mclk_rate;
  316. enum codec_variant type;
  317. struct regmap *regmap;
  318. struct wcd9xxx_codec_type *codec_type;
  319. bool prev_pg_valid;
  320. u8 prev_pg;
  321. u8 avoid_cdc_rstlow;
  322. struct wcd9xxx_power_region *wcd9xxx_pwr[WCD9XXX_MAX_PWR_REGIONS];
  323. };
  324. struct wcd9xxx_reg_val {
  325. unsigned short reg; /* register address */
  326. u8 *buf; /* buffer to be written to reg. addr */
  327. int bytes; /* number of bytes to be written */
  328. };
  329. #ifdef CONFIG_WCD9XXX_CODEC_CORE
  330. int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg);
  331. int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
  332. u8 val);
  333. int wcd9xxx_get_logical_addresses(u8 *pgd_la, u8 *inf_la);
  334. int wcd9xxx_slim_write_repeat(struct wcd9xxx *wcd9xxx, unsigned short reg,
  335. int bytes, void *src);
  336. int wcd9xxx_slim_reserve_bw(struct wcd9xxx *wcd9xxx,
  337. u32 bw_ops, bool commit);
  338. int wcd9xxx_set_power_state(struct wcd9xxx *wcd9xxx, enum codec_power_states,
  339. enum wcd_power_regions);
  340. int wcd9xxx_get_current_power_state(struct wcd9xxx *wcd9xxx,
  341. enum wcd_power_regions);
  342. int wcd9xxx_page_write(struct wcd9xxx *wcd9xxx, unsigned short *reg);
  343. int wcd9xxx_slim_bulk_write(struct wcd9xxx *wcd9xxx,
  344. struct wcd9xxx_reg_val *bulk_reg,
  345. unsigned int size, bool interface);
  346. int wcd9xxx_vote_ondemand_regulator(struct wcd9xxx *wcd9xxx,
  347. struct wcd9xxx_pdata *pdata,
  348. const char *supply_name,
  349. bool enable);
  350. extern int wcd9xxx_core_res_init(
  351. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  352. int num_irqs, int num_irq_regs, struct regmap *wcd_regmap);
  353. extern void wcd9xxx_core_res_deinit(
  354. struct wcd9xxx_core_resource *wcd9xxx_core_res);
  355. extern int wcd9xxx_core_res_suspend(
  356. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  357. pm_message_t pmesg);
  358. extern int wcd9xxx_core_res_resume(
  359. struct wcd9xxx_core_resource *wcd9xxx_core_res);
  360. extern int wcd9xxx_core_irq_init(
  361. struct wcd9xxx_core_resource *wcd9xxx_core_res);
  362. extern int wcd9xxx_assign_irq(struct wcd9xxx_core_resource *wcd9xxx_core_res,
  363. unsigned int irq,
  364. unsigned int irq_base);
  365. extern enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void);
  366. extern void wcd9xxx_set_intf_type(enum wcd9xxx_intf_status);
  367. extern enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(
  368. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  369. enum wcd9xxx_pm_state o,
  370. enum wcd9xxx_pm_state n);
  371. static inline int __init wcd9xxx_irq_of_init(struct device_node *node,
  372. struct device_node *parent)
  373. {
  374. return 0;
  375. }
  376. int wcd9xxx_init(void);
  377. void wcd9xxx_exit(void);
  378. #else
  379. static inline int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg)
  380. {
  381. return 0;
  382. }
  383. static inline int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
  384. u8 val)
  385. {
  386. return 0;
  387. }
  388. static inline int wcd9xxx_get_logical_addresses(u8 *pgd_la, u8 *inf_la)
  389. {
  390. return 0;
  391. }
  392. static inline int wcd9xxx_slim_write_repeat(struct wcd9xxx *wcd9xxx, unsigned short reg,
  393. int bytes, void *src)
  394. {
  395. return 0;
  396. }
  397. static inline int wcd9xxx_slim_reserve_bw(struct wcd9xxx *wcd9xxx,
  398. u32 bw_ops, bool commit)
  399. {
  400. return 0;
  401. }
  402. static inline int wcd9xxx_set_power_state(struct wcd9xxx *wcd9xxx, enum codec_power_states
  403. cdc_power_state, enum wcd_power_regions pwr_region)
  404. {
  405. return 0;
  406. }
  407. static inline int wcd9xxx_get_current_power_state(struct wcd9xxx *wcd9xxx,
  408. enum wcd_power_regions pwr_region)
  409. {
  410. return 0;
  411. }
  412. static inline int wcd9xxx_page_write(struct wcd9xxx *wcd9xxx, unsigned short *reg)
  413. {
  414. return 0;
  415. }
  416. static inline int wcd9xxx_slim_bulk_write(struct wcd9xxx *wcd9xxx,
  417. struct wcd9xxx_reg_val *bulk_reg,
  418. unsigned int size, bool interface)
  419. {
  420. return 0;
  421. }
  422. static inline int wcd9xxx_core_res_init(
  423. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  424. int num_irqs, int num_irq_regs, struct regmap *wcd_regmap)
  425. {
  426. return 0;
  427. }
  428. static inline void wcd9xxx_core_res_deinit(
  429. struct wcd9xxx_core_resource *wcd9xxx_core_res)
  430. {
  431. }
  432. static inline int wcd9xxx_core_res_suspend(
  433. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  434. pm_message_t pmesg)
  435. {
  436. return 0;
  437. }
  438. static inline int wcd9xxx_core_res_resume(
  439. struct wcd9xxx_core_resource *wcd9xxx_core_res)
  440. {
  441. return 0;
  442. }
  443. static inline int wcd9xxx_core_irq_init(
  444. struct wcd9xxx_core_resource *wcd9xxx_core_res)
  445. {
  446. return 0;
  447. }
  448. static inline int wcd9xxx_assign_irq(struct wcd9xxx_core_resource *wcd9xxx_core_res,
  449. unsigned int irq,
  450. unsigned int irq_base)
  451. {
  452. return 0;
  453. }
  454. static inline enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void)
  455. {
  456. return 0;
  457. }
  458. static inline void wcd9xxx_set_intf_type(enum wcd9xxx_intf_status int_state)
  459. {
  460. }
  461. static inline enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(
  462. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  463. enum wcd9xxx_pm_state o,
  464. enum wcd9xxx_pm_state n)
  465. {
  466. return 0;
  467. }
  468. static inline int __init wcd9xxx_irq_of_init(struct device_node *node,
  469. struct device_node *parent)
  470. {
  471. return 0;
  472. }
  473. static inline int wcd9xxx_init(void)
  474. {
  475. return 0;
  476. }
  477. static inline void wcd9xxx_exit(void)
  478. {
  479. }
  480. #endif
  481. #endif