msm_cvp_resources.h 4.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef __MSM_CVP_RESOURCES_H__
  6. #define __MSM_CVP_RESOURCES_H__
  7. #include <linux/devfreq.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/pm_qos.h>
  10. #include "msm_cvp_core.h"
  11. #include <linux/soc/qcom/llcc-qcom.h>
  12. struct reg_value_pair {
  13. u32 reg;
  14. u32 value;
  15. };
  16. struct reg_set {
  17. struct reg_value_pair *reg_tbl;
  18. int count;
  19. };
  20. struct addr_range {
  21. u32 start;
  22. u32 size;
  23. };
  24. struct addr_set {
  25. struct addr_range *addr_tbl;
  26. int count;
  27. };
  28. struct context_bank_info {
  29. struct list_head list;
  30. const char *name;
  31. u32 buffer_type;
  32. bool is_secure;
  33. struct addr_range addr_range;
  34. struct device *dev;
  35. struct iommu_domain *domain;
  36. };
  37. struct regulator_info {
  38. struct regulator *regulator;
  39. bool has_hw_power_collapse;
  40. char *name;
  41. };
  42. struct regulator_set {
  43. struct regulator_info *regulator_tbl;
  44. u32 count;
  45. };
  46. struct clock_info {
  47. const char *name;
  48. u32 clk_id;
  49. struct clk *clk;
  50. u32 count;
  51. bool has_scaling;
  52. bool has_mem_retention;
  53. };
  54. struct clock_set {
  55. struct clock_info *clock_tbl;
  56. u32 count;
  57. };
  58. struct bus_info {
  59. char *name;
  60. int master;
  61. int slave;
  62. unsigned int range[2];
  63. const char *governor;
  64. struct device *dev;
  65. struct devfreq_dev_profile devfreq_prof;
  66. struct devfreq *devfreq;
  67. struct icc_path *client;
  68. bool is_prfm_gov_used;
  69. };
  70. struct bus_set {
  71. struct bus_info *bus_tbl;
  72. u32 count;
  73. };
  74. enum action_stage {
  75. CVP_ON_INIT,
  76. CVP_ON_USE,
  77. CVP_ON_INVALID,
  78. };
  79. enum reset_clk_state {
  80. RESET_INIT,
  81. RESET_ACQUIRED,
  82. RESET_RELEASED,
  83. };
  84. struct reset_info {
  85. struct reset_control *rst;
  86. enum action_stage required_stage;
  87. enum reset_clk_state state;
  88. const char *name;
  89. };
  90. struct reset_set {
  91. struct reset_info *reset_tbl;
  92. u32 count;
  93. };
  94. struct allowed_clock_rates_table {
  95. u32 clock_rate;
  96. };
  97. struct clock_profile_entry {
  98. u32 codec_mask;
  99. u32 vpp_cycles;
  100. u32 vsp_cycles;
  101. u32 low_power_cycles;
  102. };
  103. struct clock_freq_table {
  104. struct clock_profile_entry *clk_prof_entries;
  105. u32 count;
  106. };
  107. struct subcache_info {
  108. const char *name;
  109. bool isactive;
  110. bool isset;
  111. struct llcc_slice_desc *subcache;
  112. };
  113. struct subcache_set {
  114. struct subcache_info *subcache_tbl;
  115. u32 count;
  116. };
  117. struct msm_cvp_mem_cdsp {
  118. struct device *dev;
  119. };
  120. #define MAX_SILVER_CORE_NUM 8
  121. #define HFI_SESSION_FD 4
  122. #define HFI_SESSION_DMM 2
  123. struct cvp_pm_qos {
  124. u32 silver_count;
  125. u32 latency_us;
  126. u32 off_vote_cnt;
  127. spinlock_t lock;
  128. int silver_cores[MAX_SILVER_CORE_NUM];
  129. struct dev_pm_qos_request *pm_qos_hdls;
  130. };
  131. struct cvp_fw_reg_mappings {
  132. phys_addr_t ipclite_iova;
  133. phys_addr_t ipclite_phyaddr;
  134. uint32_t ipclite_size;
  135. phys_addr_t hwmutex_iova;
  136. phys_addr_t hwmutex_phyaddr;
  137. uint32_t hwmutex_size;
  138. phys_addr_t aon_iova;
  139. phys_addr_t aon_phyaddr;
  140. uint32_t aon_size;
  141. phys_addr_t timer_iova;
  142. phys_addr_t timer_phyaddr;
  143. uint32_t timer_size;
  144. };
  145. struct msm_cvp_platform_resources {
  146. phys_addr_t firmware_base;
  147. phys_addr_t register_base;
  148. phys_addr_t ipcc_reg_base;
  149. phys_addr_t gcc_reg_base;
  150. uint32_t register_size;
  151. uint32_t ipcc_reg_size;
  152. uint32_t gcc_reg_size;
  153. struct cvp_fw_reg_mappings reg_mappings;
  154. uint32_t irq;
  155. uint32_t irq_wd;
  156. uint32_t sku_version;
  157. struct allowed_clock_rates_table *allowed_clks_tbl;
  158. u32 allowed_clks_tbl_size;
  159. struct clock_freq_table clock_freq_tbl;
  160. bool sys_cache_present;
  161. bool sys_cache_res_set;
  162. struct subcache_set subcache_set;
  163. struct reg_set reg_set;
  164. struct addr_set qdss_addr_set;
  165. uint32_t max_ssr_allowed;
  166. struct platform_device *pdev;
  167. struct regulator_set regulator_set;
  168. struct clock_set clock_set;
  169. struct bus_set bus_set;
  170. struct reset_set reset_set;
  171. bool use_non_secure_pil;
  172. bool sw_power_collapsible;
  173. bool dsp_enabled;
  174. struct list_head context_banks;
  175. bool thermal_mitigable;
  176. const char *fw_name;
  177. const char *hfi_version;
  178. bool debug_timeout;
  179. struct cvp_pm_qos pm_qos;
  180. uint32_t max_inst_count;
  181. uint32_t max_secure_inst_count;
  182. int msm_cvp_hw_rsp_timeout;
  183. int msm_cvp_dsp_rsp_timeout;
  184. uint32_t msm_cvp_pwr_collapse_delay;
  185. bool non_fatal_pagefaults;
  186. bool fatal_ssr;
  187. struct msm_cvp_mem_cdsp mem_cdsp;
  188. uint32_t vpu_ver;
  189. uint32_t fw_cycles;
  190. struct msm_cvp_ubwc_config_data *ubwc_config;
  191. };
  192. static inline bool is_iommu_present(struct msm_cvp_platform_resources *res)
  193. {
  194. return !list_empty(&res->context_banks);
  195. }
  196. int cvp_of_fdt_get_ddrtype(void);
  197. #endif