msm_cvp_platform.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/debugfs.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/init.h>
  9. #include <linux/ioctl.h>
  10. #include <linux/list.h>
  11. #include <linux/module.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/slab.h>
  15. #include <linux/types.h>
  16. #include <linux/version.h>
  17. #include <linux/io.h>
  18. #include <soc/qcom/of_common.h>
  19. #include "msm_cvp_internal.h"
  20. #include "msm_cvp_debug.h"
  21. #include "cvp_hfi_api.h"
  22. #include "cvp_hfi.h"
  23. #define UBWC_CONFIG(mco, mlo, hbo, bslo, bso, rs, mc, ml, hbb, bsl, bsp) \
  24. { \
  25. .override_bit_info.max_channel_override = mco, \
  26. .override_bit_info.mal_length_override = mlo, \
  27. .override_bit_info.hb_override = hbo, \
  28. .override_bit_info.bank_swzl_level_override = bslo, \
  29. .override_bit_info.bank_spreading_override = bso, \
  30. .override_bit_info.reserved = rs, \
  31. .max_channels = mc, \
  32. .mal_length = ml, \
  33. .highest_bank_bit = hbb, \
  34. .bank_swzl_level = bsl, \
  35. .bank_spreading = bsp, \
  36. }
  37. static struct msm_cvp_common_data default_common_data[] = {
  38. {
  39. .key = "qcom,auto-pil",
  40. .value = 1,
  41. },
  42. };
  43. static struct msm_cvp_common_data sm8450_common_data[] = {
  44. {
  45. .key = "qcom,pm-qos-latency-us",
  46. .value = 50,
  47. },
  48. {
  49. .key = "qcom,sw-power-collapse",
  50. .value = 1,
  51. },
  52. {
  53. .key = "qcom,domain-attr-non-fatal-faults",
  54. .value = 1,
  55. },
  56. {
  57. .key = "qcom,max-secure-instances",
  58. .value = 2, /*
  59. * As per design driver allows 3rd
  60. * instance as well since the secure
  61. * flags were updated later for the
  62. * current instance. Hence total
  63. * secure sessions would be
  64. * max-secure-instances + 1.
  65. */
  66. },
  67. {
  68. .key = "qcom,max-ssr-allowed",
  69. .value = 1, /*
  70. * Maxinum number of SSR before BUG_ON
  71. */
  72. },
  73. {
  74. .key = "qcom,power-collapse-delay",
  75. .value = 3000,
  76. },
  77. {
  78. .key = "qcom,hw-resp-timeout",
  79. .value = 2000,
  80. },
  81. {
  82. .key = "qcom,dsp-resp-timeout",
  83. .value = 1000,
  84. },
  85. {
  86. .key = "qcom,debug-timeout",
  87. .value = 0,
  88. },
  89. {
  90. .key = "qcom,dsp-enabled",
  91. .value = 1,
  92. }
  93. };
  94. static struct msm_cvp_common_data sm8550_common_data[] = {
  95. {
  96. .key = "qcom,pm-qos-latency-us",
  97. .value = 50,
  98. },
  99. {
  100. .key = "qcom,sw-power-collapse",
  101. .value = 1,
  102. },
  103. {
  104. .key = "qcom,domain-attr-non-fatal-faults",
  105. .value = 0,
  106. },
  107. {
  108. .key = "qcom,max-secure-instances",
  109. .value = 2, /*
  110. * As per design driver allows 3rd
  111. * instance as well since the secure
  112. * flags were updated later for the
  113. * current instance. Hence total
  114. * secure sessions would be
  115. * max-secure-instances + 1.
  116. */
  117. },
  118. {
  119. .key = "qcom,max-ssr-allowed",
  120. .value = 1, /*
  121. * Maxinum number of SSR before BUG_ON
  122. */
  123. },
  124. {
  125. .key = "qcom,power-collapse-delay",
  126. .value = 3000,
  127. },
  128. {
  129. .key = "qcom,hw-resp-timeout",
  130. .value = 2000,
  131. },
  132. {
  133. .key = "qcom,dsp-resp-timeout",
  134. .value = 1000,
  135. },
  136. {
  137. .key = "qcom,debug-timeout",
  138. .value = 0,
  139. },
  140. {
  141. .key = "qcom,dsp-enabled",
  142. .value = 1,
  143. }
  144. };
  145. static struct msm_cvp_common_data sm8550_tvm_common_data[] = {
  146. {
  147. .key = "qcom,pm-qos-latency-us",
  148. .value = 50,
  149. },
  150. {
  151. .key = "qcom,sw-power-collapse",
  152. .value = 0,
  153. },
  154. {
  155. .key = "qcom,domain-attr-non-fatal-faults",
  156. .value = 0,
  157. },
  158. {
  159. .key = "qcom,max-secure-instances",
  160. .value = 2, /*
  161. * As per design driver allows 3rd
  162. * instance as well since the secure
  163. * flags were updated later for the
  164. * current instance. Hence total
  165. * secure sessions would be
  166. * max-secure-instances + 1.
  167. */
  168. },
  169. {
  170. .key = "qcom,max-ssr-allowed",
  171. .value = 1, /*
  172. * Maxinum number of SSR before BUG_ON
  173. */
  174. },
  175. {
  176. .key = "qcom,power-collapse-delay",
  177. .value = 3000,
  178. },
  179. {
  180. .key = "qcom,hw-resp-timeout",
  181. .value = 2000,
  182. },
  183. {
  184. .key = "qcom,dsp-resp-timeout",
  185. .value = 1000,
  186. },
  187. {
  188. .key = "qcom,debug-timeout",
  189. .value = 0,
  190. },
  191. {
  192. .key = "qcom,dsp-enabled",
  193. .value = 0,
  194. }
  195. };
  196. static struct msm_cvp_common_data sm8650_common_data[] = {
  197. {
  198. .key = "qcom,pm-qos-latency-us",
  199. .value = 50,
  200. },
  201. {
  202. .key = "qcom,sw-power-collapse",
  203. .value = 1,
  204. },
  205. {
  206. .key = "qcom,domain-attr-non-fatal-faults",
  207. .value = 0,
  208. },
  209. {
  210. .key = "qcom,max-secure-instances",
  211. .value = 2, /*
  212. * As per design driver allows 3rd
  213. * instance as well since the secure
  214. * flags were updated later for the
  215. * current instance. Hence total
  216. * secure sessions would be
  217. * max-secure-instances + 1.
  218. */
  219. },
  220. {
  221. .key = "qcom,max-ssr-allowed",
  222. .value = 1, /*
  223. * Maxinum number of SSR before BUG_ON
  224. */
  225. },
  226. {
  227. .key = "qcom,power-collapse-delay",
  228. .value = 3000,
  229. },
  230. {
  231. .key = "qcom,hw-resp-timeout",
  232. .value = 2000,
  233. },
  234. {
  235. .key = "qcom,dsp-resp-timeout",
  236. .value = 1000,
  237. },
  238. {
  239. .key = "qcom,debug-timeout",
  240. .value = 0,
  241. },
  242. {
  243. .key = "qcom,dsp-enabled",
  244. .value = 1,
  245. }
  246. };
  247. static struct msm_cvp_common_data sm7650_common_data[] = {
  248. {
  249. .key = "qcom,pm-qos-latency-us",
  250. .value = 50,
  251. },
  252. {
  253. .key = "qcom,sw-power-collapse",
  254. .value = 1,
  255. },
  256. {
  257. .key = "qcom,domain-attr-non-fatal-faults",
  258. .value = 0,
  259. },
  260. {
  261. .key = "qcom,max-secure-instances",
  262. .value = 2,
  263. },
  264. {
  265. .key = "qcom,max-ssr-allowed",
  266. .value = 1,
  267. },
  268. {
  269. .key = "qcom,power-collapse-delay",
  270. .value = 3000,
  271. },
  272. {
  273. .key = "qcom,hw-resp-timeout",
  274. .value = 2000,
  275. },
  276. {
  277. .key = "qcom,dsp-resp-timeout",
  278. .value = 1000,
  279. },
  280. {
  281. .key = "qcom,debug-timeout",
  282. .value = 0,
  283. },
  284. {
  285. .key = "qcom,dsp-enabled",
  286. .value = 1,
  287. }
  288. };
  289. /* Default UBWC config for LPDDR5 */
  290. static struct msm_cvp_ubwc_config_data kona_ubwc_data[] = {
  291. UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 16, 0, 0),
  292. };
  293. static struct msm_cvp_qos_setting waipio_noc_qos = {
  294. .axi_qos = 0x99,
  295. .prioritylut_low = 0x22222222,
  296. .prioritylut_high = 0x33333333,
  297. .urgency_low = 0x1022,
  298. .dangerlut_low = 0x0,
  299. .safelut_low = 0xffff,
  300. };
  301. static struct msm_cvp_qos_setting lanai_noc_qos = {
  302. .axi_qos = 0x99,
  303. .prioritylut_low = 0x33333333,
  304. .prioritylut_high = 0x33333333,
  305. .urgency_low = 0x1033,
  306. .urgency_low_ro = 0x1003,
  307. .dangerlut_low = 0x0,
  308. .safelut_low = 0xffff,
  309. };
  310. static struct msm_cvp_platform_data default_data = {
  311. .common_data = default_common_data,
  312. .common_data_length = ARRAY_SIZE(default_common_data),
  313. .sku_version = 0,
  314. .vpu_ver = VPU_VERSION_5,
  315. .ubwc_config = 0x0,
  316. .noc_qos = 0x0,
  317. .vm_id = 1,
  318. };
  319. static struct msm_cvp_platform_data sm8450_data = {
  320. .common_data = sm8450_common_data,
  321. .common_data_length = ARRAY_SIZE(sm8450_common_data),
  322. .sku_version = 0,
  323. .vpu_ver = VPU_VERSION_5,
  324. .ubwc_config = kona_ubwc_data,
  325. .noc_qos = &waipio_noc_qos,
  326. .vm_id = 1,
  327. };
  328. static struct msm_cvp_platform_data sm8550_data = {
  329. .common_data = sm8550_common_data,
  330. .common_data_length = ARRAY_SIZE(sm8550_common_data),
  331. .sku_version = 0,
  332. .vpu_ver = VPU_VERSION_5,
  333. .ubwc_config = kona_ubwc_data, /*Reuse Kona setting*/
  334. .noc_qos = &waipio_noc_qos, /*Reuse Waipio setting*/
  335. .vm_id = 1,
  336. };
  337. static struct msm_cvp_platform_data sm8550_tvm_data = {
  338. .common_data = sm8550_tvm_common_data,
  339. .common_data_length = ARRAY_SIZE(sm8550_tvm_common_data),
  340. .sku_version = 0,
  341. .vpu_ver = VPU_VERSION_5,
  342. .ubwc_config = kona_ubwc_data, /*Reuse Kona setting*/
  343. .noc_qos = &waipio_noc_qos, /*Reuse Waipio setting*/
  344. .vm_id = 2,
  345. };
  346. static struct msm_cvp_platform_data sm8650_data = {
  347. .common_data = sm8650_common_data,
  348. .common_data_length = ARRAY_SIZE(sm8650_common_data),
  349. .sku_version = 0,
  350. .vpu_ver = VPU_VERSION_5,
  351. .ubwc_config = kona_ubwc_data, /*Reuse Kona setting*/
  352. .noc_qos = &lanai_noc_qos,
  353. .vm_id = 1,
  354. };
  355. static struct msm_cvp_platform_data sm7650_data = {
  356. .common_data = sm7650_common_data,
  357. .common_data_length = ARRAY_SIZE(sm7650_common_data),
  358. .sku_version = 0,
  359. .vpu_ver = VPU_VERSION_5,
  360. .ubwc_config = kona_ubwc_data, /*Reuse Kona setting*/
  361. .noc_qos = &waipio_noc_qos, /*Reuse Waipio setting*/
  362. .vm_id = 1,
  363. };
  364. static const struct of_device_id msm_cvp_dt_match[] = {
  365. {
  366. .compatible = "qcom,waipio-cvp",
  367. .data = &sm8450_data,
  368. },
  369. {
  370. .compatible = "qcom,kalama-cvp",
  371. .data = &sm8550_data,
  372. },
  373. {
  374. .compatible = "qcom,kalama-cvp-tvm",
  375. .data = &sm8550_tvm_data,
  376. },
  377. {
  378. .compatible = "qcom,pineapple-cvp",
  379. .data = &sm8650_data,
  380. },
  381. {
  382. .compatible = "qcom,cliffs-cvp",
  383. .data = &sm7650_data,
  384. },
  385. {},
  386. };
  387. /*
  388. * WARN: name field CAN NOT hold more than 23 chars
  389. * excluding the ending '\0'
  390. *
  391. * NOTE: the def entry index for the command packet is
  392. * "the packet type - HFI_CMD_SESSION_CVP_START"
  393. */
  394. const struct msm_cvp_hfi_defs cvp_hfi_defs[MAX_PKT_IDX] = {
  395. [HFI_CMD_SESSION_CVP_DFS_CONFIG - HFI_CMD_SESSION_CVP_START] =
  396. {
  397. .size = HFI_DFS_CONFIG_CMD_SIZE,
  398. .type = HFI_CMD_SESSION_CVP_DFS_CONFIG,
  399. .is_config_pkt = true,
  400. .resp = HAL_NO_RESP,
  401. .name = "DFS",
  402. },
  403. [HFI_CMD_SESSION_CVP_DFS_FRAME - HFI_CMD_SESSION_CVP_START] =
  404. {
  405. .size = HFI_DFS_FRAME_CMD_SIZE,
  406. .type = HFI_CMD_SESSION_CVP_DFS_FRAME,
  407. .is_config_pkt = false,
  408. .resp = HAL_NO_RESP,
  409. .name = "DFS_FRAME",
  410. .force_kernel_fence = false,
  411. },
  412. [HFI_CMD_SESSION_CVP_SGM_OF_CONFIG - HFI_CMD_SESSION_CVP_START] =
  413. {
  414. .size = 0xFFFFFFFF,
  415. .type = HFI_CMD_SESSION_CVP_SGM_OF_CONFIG,
  416. .is_config_pkt = true,
  417. .resp = HAL_NO_RESP,
  418. .name = "SGM_OF",
  419. },
  420. [HFI_CMD_SESSION_CVP_SGM_OF_FRAME - HFI_CMD_SESSION_CVP_START] =
  421. {
  422. .size = 0xFFFFFFFF,
  423. .type = HFI_CMD_SESSION_CVP_SGM_OF_FRAME,
  424. .is_config_pkt = false,
  425. .resp = HAL_NO_RESP,
  426. .name = "SGM_OF_FRAME",
  427. .force_kernel_fence = false,
  428. },
  429. [HFI_CMD_SESSION_CVP_WARP_NCC_CONFIG - HFI_CMD_SESSION_CVP_START] =
  430. {
  431. .size = 0xFFFFFFFF,
  432. .type = HFI_CMD_SESSION_CVP_WARP_NCC_CONFIG,
  433. .is_config_pkt = true,
  434. .resp = HAL_NO_RESP,
  435. .name = "WARP_NCC",
  436. },
  437. [HFI_CMD_SESSION_CVP_WARP_NCC_FRAME - HFI_CMD_SESSION_CVP_START] =
  438. {
  439. .size = 0xFFFFFFFF,
  440. .type = HFI_CMD_SESSION_CVP_WARP_NCC_FRAME,
  441. .is_config_pkt = false,
  442. .resp = HAL_NO_RESP,
  443. .name = "WARP_NCC_FRAME",
  444. .force_kernel_fence = false,
  445. },
  446. [HFI_CMD_SESSION_CVP_WARP_CONFIG - HFI_CMD_SESSION_CVP_START] =
  447. {
  448. .size = 0xFFFFFFFF,
  449. .type = HFI_CMD_SESSION_CVP_WARP_CONFIG,
  450. .is_config_pkt = true,
  451. .resp = HAL_NO_RESP,
  452. .name = "WARP",
  453. },
  454. [HFI_CMD_SESSION_CVP_WARP_DS_PARAMS - HFI_CMD_SESSION_CVP_START] =
  455. {
  456. .size = 0xFFFFFFFF,
  457. .type = HFI_CMD_SESSION_CVP_WARP_DS_PARAMS,
  458. .is_config_pkt = true,
  459. .resp = HAL_NO_RESP,
  460. .name = "WARP_DS_PARAMS",
  461. },
  462. [HFI_CMD_SESSION_CVP_WARP_FRAME - HFI_CMD_SESSION_CVP_START] =
  463. {
  464. .size = 0xFFFFFFFF,
  465. .type = HFI_CMD_SESSION_CVP_WARP_FRAME,
  466. .is_config_pkt = false,
  467. .resp = HAL_NO_RESP,
  468. .name = "WARP_FRAME",
  469. .force_kernel_fence = true,
  470. },
  471. [HFI_CMD_SESSION_CVP_DMM_CONFIG - HFI_CMD_SESSION_CVP_START] =
  472. {
  473. .size = HFI_DMM_CONFIG_CMD_SIZE,
  474. .type = HFI_CMD_SESSION_CVP_DMM_CONFIG,
  475. .is_config_pkt = true,
  476. .resp = HAL_NO_RESP,
  477. .name = "DMM",
  478. },
  479. [HFI_CMD_SESSION_CVP_DMM_PARAMS - HFI_CMD_SESSION_CVP_START] =
  480. {
  481. .size = 0xFFFFFFFF,
  482. .type = HFI_CMD_SESSION_CVP_DMM_PARAMS,
  483. .is_config_pkt = true,
  484. .resp = HAL_NO_RESP,
  485. .name = "DMM_PARAMS",
  486. },
  487. [HFI_CMD_SESSION_CVP_DMM_FRAME - HFI_CMD_SESSION_CVP_START] =
  488. {
  489. .size = HFI_DMM_FRAME_CMD_SIZE,
  490. .type = HFI_CMD_SESSION_CVP_DMM_FRAME,
  491. .is_config_pkt = false,
  492. .resp = HAL_NO_RESP,
  493. .name = "DMM_FRAME",
  494. .force_kernel_fence = true,
  495. },
  496. [HFI_CMD_SESSION_CVP_SET_PERSIST_BUFFERS - HFI_CMD_SESSION_CVP_START] =
  497. {
  498. .size = HFI_PERSIST_CMD_SIZE,
  499. .type =HFI_CMD_SESSION_CVP_SET_PERSIST_BUFFERS,
  500. .is_config_pkt = true,
  501. .resp = HAL_NO_RESP,
  502. .name = "SET_PERSIST",
  503. },
  504. [HFI_CMD_SESSION_CVP_RELEASE_PERSIST_BUFFERS - HFI_CMD_SESSION_CVP_START] =
  505. {
  506. .size = 0xffffffff,
  507. .type =HFI_CMD_SESSION_CVP_RELEASE_PERSIST_BUFFERS,
  508. .is_config_pkt = false,
  509. .resp = HAL_NO_RESP,
  510. .name = "REL_PERSIST",
  511. },
  512. [HFI_CMD_SESSION_CVP_DS_CONFIG - HFI_CMD_SESSION_CVP_START] =
  513. {
  514. .size = HFI_DS_CONFIG_CMD_SIZE,
  515. .type = HFI_CMD_SESSION_CVP_DS_CONFIG,
  516. .is_config_pkt = true,
  517. .resp = HAL_NO_RESP,
  518. .name = "DS_CONFIG",
  519. },
  520. [HFI_CMD_SESSION_CVP_DS - HFI_CMD_SESSION_CVP_START] =
  521. {
  522. .size = HFI_DS_CMD_SIZE,
  523. .type =HFI_CMD_SESSION_CVP_DS,
  524. .is_config_pkt = false,
  525. .resp = HAL_NO_RESP,
  526. .name = "DS",
  527. },
  528. [HFI_CMD_SESSION_CVP_CV_TME_CONFIG - HFI_CMD_SESSION_CVP_START] =
  529. {
  530. .size = HFI_OF_CONFIG_CMD_SIZE,
  531. .type =HFI_CMD_SESSION_CVP_CV_TME_CONFIG,
  532. .is_config_pkt = true,
  533. .resp = HAL_NO_RESP,
  534. .name = "TME",
  535. },
  536. [HFI_CMD_SESSION_CVP_CV_TME_FRAME - HFI_CMD_SESSION_CVP_START] =
  537. {
  538. .size = HFI_OF_FRAME_CMD_SIZE,
  539. .type =HFI_CMD_SESSION_CVP_CV_TME_FRAME,
  540. .is_config_pkt = false,
  541. .resp = HAL_NO_RESP,
  542. .name = "TME_FRAME",
  543. .force_kernel_fence = false,
  544. },
  545. [HFI_CMD_SESSION_CVP_CV_ODT_CONFIG - HFI_CMD_SESSION_CVP_START] =
  546. {
  547. .size = HFI_ODT_CONFIG_CMD_SIZE,
  548. .type = HFI_CMD_SESSION_CVP_CV_ODT_CONFIG,
  549. .is_config_pkt = true,
  550. .resp = HAL_NO_RESP,
  551. .name = "ODT",
  552. },
  553. [HFI_CMD_SESSION_CVP_CV_ODT_FRAME - HFI_CMD_SESSION_CVP_START] =
  554. {
  555. .size = HFI_ODT_FRAME_CMD_SIZE,
  556. .type =HFI_CMD_SESSION_CVP_CV_ODT_FRAME,
  557. .is_config_pkt = false,
  558. .resp = HAL_NO_RESP,
  559. .name = "ODT_FRAME",
  560. },
  561. [HFI_CMD_SESSION_CVP_CV_OD_CONFIG - HFI_CMD_SESSION_CVP_START] =
  562. {
  563. .size = HFI_OD_CONFIG_CMD_SIZE,
  564. .type = HFI_CMD_SESSION_CVP_CV_OD_CONFIG,
  565. .is_config_pkt = true,
  566. .resp = HAL_NO_RESP,
  567. .name = "OD",
  568. },
  569. [HFI_CMD_SESSION_CVP_CV_OD_FRAME - HFI_CMD_SESSION_CVP_START] =
  570. {
  571. .size = HFI_OD_FRAME_CMD_SIZE,
  572. .type = HFI_CMD_SESSION_CVP_CV_OD_FRAME,
  573. .is_config_pkt = false,
  574. .resp = HAL_NO_RESP,
  575. .name = "OD_FRAME",
  576. },
  577. [HFI_CMD_SESSION_CVP_NCC_CONFIG - HFI_CMD_SESSION_CVP_START] =
  578. {
  579. .size = HFI_NCC_CONFIG_CMD_SIZE,
  580. .type =HFI_CMD_SESSION_CVP_NCC_CONFIG,
  581. .is_config_pkt = true,
  582. .resp = HAL_NO_RESP,
  583. .name = "NCC",
  584. },
  585. [HFI_CMD_SESSION_CVP_NCC_FRAME - HFI_CMD_SESSION_CVP_START] =
  586. {
  587. .size = HFI_NCC_FRAME_CMD_SIZE,
  588. .type = HFI_CMD_SESSION_CVP_NCC_FRAME,
  589. .is_config_pkt = false,
  590. .resp = HAL_NO_RESP,
  591. .name = "NCC_FRAME",
  592. .force_kernel_fence = false,
  593. },
  594. [HFI_CMD_SESSION_CVP_ICA_CONFIG - HFI_CMD_SESSION_CVP_START] =
  595. {
  596. .size = HFI_ICA_CONFIG_CMD_SIZE,
  597. .type = HFI_CMD_SESSION_CVP_ICA_CONFIG,
  598. .is_config_pkt = true,
  599. .resp = HAL_NO_RESP,
  600. .name = "ICA",
  601. },
  602. [HFI_CMD_SESSION_CVP_ICA_FRAME - HFI_CMD_SESSION_CVP_START] =
  603. {
  604. .size = HFI_ICA_FRAME_CMD_SIZE,
  605. .type =HFI_CMD_SESSION_CVP_ICA_FRAME,
  606. .is_config_pkt = false,
  607. .resp = HAL_NO_RESP,
  608. .name = "ICA_FRAME",
  609. .force_kernel_fence = false,
  610. },
  611. [HFI_CMD_SESSION_CVP_HCD_CONFIG - HFI_CMD_SESSION_CVP_START] =
  612. {
  613. .size = HFI_HCD_CONFIG_CMD_SIZE,
  614. .type = HFI_CMD_SESSION_CVP_HCD_CONFIG,
  615. .is_config_pkt = true,
  616. .resp = HAL_NO_RESP,
  617. .name = "HCD",
  618. },
  619. [HFI_CMD_SESSION_CVP_HCD_FRAME - HFI_CMD_SESSION_CVP_START] =
  620. {
  621. .size = HFI_HCD_FRAME_CMD_SIZE,
  622. .type = HFI_CMD_SESSION_CVP_HCD_FRAME,
  623. .is_config_pkt = false,
  624. .resp = HAL_NO_RESP,
  625. .name = "HCD_FRAME",
  626. .force_kernel_fence = false,
  627. },
  628. [HFI_CMD_SESSION_CVP_DC_CONFIG - HFI_CMD_SESSION_CVP_START] =
  629. {
  630. .size = HFI_DCM_CONFIG_CMD_SIZE,
  631. .type = HFI_CMD_SESSION_CVP_DC_CONFIG,
  632. .is_config_pkt = true,
  633. .resp = HAL_NO_RESP,
  634. .name = "DC",
  635. },
  636. [HFI_CMD_SESSION_CVP_DC_FRAME - HFI_CMD_SESSION_CVP_START] =
  637. {
  638. .size = HFI_DCM_FRAME_CMD_SIZE,
  639. .type = HFI_CMD_SESSION_CVP_DC_FRAME,
  640. .is_config_pkt = false,
  641. .resp = HAL_NO_RESP,
  642. .name = "DC_FRAME",
  643. .force_kernel_fence = false,
  644. },
  645. [HFI_CMD_SESSION_CVP_DCM_CONFIG - HFI_CMD_SESSION_CVP_START] =
  646. {
  647. .size = HFI_DCM_CONFIG_CMD_SIZE,
  648. .type = HFI_CMD_SESSION_CVP_DCM_CONFIG,
  649. .is_config_pkt = true,
  650. .resp = HAL_NO_RESP,
  651. .name = "DCM",
  652. },
  653. [HFI_CMD_SESSION_CVP_DCM_FRAME - HFI_CMD_SESSION_CVP_START] =
  654. {
  655. .size = HFI_DCM_FRAME_CMD_SIZE,
  656. .type = HFI_CMD_SESSION_CVP_DCM_FRAME,
  657. .is_config_pkt = false,
  658. .resp = HAL_NO_RESP,
  659. .name = "DCM_FRAME",
  660. .force_kernel_fence = false,
  661. },
  662. [HFI_CMD_SESSION_CVP_PYS_HCD_CONFIG - HFI_CMD_SESSION_CVP_START] =
  663. {
  664. .size = HFI_PYS_HCD_CONFIG_CMD_SIZE,
  665. .type = HFI_CMD_SESSION_CVP_PYS_HCD_CONFIG,
  666. .is_config_pkt = true,
  667. .resp = HAL_NO_RESP,
  668. .name = "PYS_HCD",
  669. },
  670. [HFI_CMD_SESSION_CVP_PYS_HCD_FRAME - HFI_CMD_SESSION_CVP_START] =
  671. {
  672. .size = HFI_PYS_HCD_FRAME_CMD_SIZE,
  673. .type = HFI_CMD_SESSION_CVP_PYS_HCD_FRAME,
  674. .is_config_pkt = false,
  675. .resp = HAL_NO_RESP,
  676. .name = "PYS_HCD_FRAME",
  677. .force_kernel_fence = true,
  678. },
  679. [HFI_CMD_SESSION_CVP_SET_MODEL_BUFFERS - HFI_CMD_SESSION_CVP_START] =
  680. {
  681. .size = 0xFFFFFFFF,
  682. .type = HFI_CMD_SESSION_CVP_SET_MODEL_BUFFERS,
  683. .is_config_pkt = true,
  684. .resp = HAL_NO_RESP,
  685. .name = "SET_MODEL",
  686. },
  687. [HFI_CMD_SESSION_CVP_SET_SNAPSHOT_BUFFERS - HFI_CMD_SESSION_CVP_START] =
  688. {
  689. .size = 0xFFFFFFFF,
  690. .type = HFI_CMD_SESSION_CVP_SET_SNAPSHOT_BUFFERS,
  691. .is_config_pkt = false,
  692. .resp = HAL_NO_RESP,
  693. .name = "SET_SNAPSHOT",
  694. },
  695. [HFI_CMD_SESSION_CVP_RELEASE_SNAPSHOT_BUFFERS - HFI_CMD_SESSION_CVP_START] =
  696. {
  697. .size = 0xFFFFFFFF,
  698. .type = HFI_CMD_SESSION_CVP_RELEASE_SNAPSHOT_BUFFERS,
  699. .is_config_pkt = false,
  700. .resp = HAL_NO_RESP,
  701. .name = "REL_SNAPSHOT",
  702. },
  703. [HFI_CMD_SESSION_CVP_SET_SNAPSHOT_MODE - HFI_CMD_SESSION_CVP_START] =
  704. {
  705. .size = 0xFFFFFFFF,
  706. .type = HFI_CMD_SESSION_CVP_SET_SNAPSHOT_MODE,
  707. .is_config_pkt = true,
  708. .resp = HAL_NO_RESP,
  709. .name = "SNAPSHOT_MODE",
  710. },
  711. [HFI_CMD_SESSION_CVP_SNAPSHOT_WRITE_DONE - HFI_CMD_SESSION_CVP_START] =
  712. {
  713. .size = 0xFFFFFFFF,
  714. .type = HFI_CMD_SESSION_CVP_SNAPSHOT_WRITE_DONE,
  715. .is_config_pkt = true,
  716. .resp = HAL_NO_RESP,
  717. .name = "SNAPSHOT_DONE",
  718. },
  719. [HFI_CMD_SESSION_CVP_FD_CONFIG - HFI_CMD_SESSION_CVP_START] =
  720. {
  721. .size = 0xFFFFFFFF,
  722. .type = HFI_CMD_SESSION_CVP_FD_CONFIG,
  723. .is_config_pkt = true,
  724. .resp = HAL_NO_RESP,
  725. .name = "FD",
  726. },
  727. [HFI_CMD_SESSION_CVP_FD_FRAME - HFI_CMD_SESSION_CVP_START] =
  728. {
  729. .size = 0xFFFFFFFF,
  730. .type = HFI_CMD_SESSION_CVP_FD_FRAME,
  731. .is_config_pkt = false,
  732. .resp = HAL_NO_RESP,
  733. .name = "FD_FRAME",
  734. },
  735. [HFI_CMD_SESSION_CVP_XRA_FRAME - HFI_CMD_SESSION_CVP_START] =
  736. {
  737. .size = 0xFFFFFFFF,
  738. .type = HFI_CMD_SESSION_CVP_XRA_FRAME,
  739. .is_config_pkt = false,
  740. .resp = HAL_NO_RESP,
  741. .name = "XRA_FRAME",
  742. },
  743. [HFI_CMD_SESSION_CVP_XRA_CONFIG - HFI_CMD_SESSION_CVP_START] =
  744. {
  745. .size = 0xFFFFFFFF,
  746. .type = HFI_CMD_SESSION_CVP_XRA_CONFIG,
  747. .is_config_pkt = true,
  748. .resp = HAL_NO_RESP,
  749. .name = "XRA_CONFIG",
  750. },
  751. [HFI_CMD_SESSION_CVP_XRA_BLOB_FRAME - HFI_CMD_SESSION_CVP_START] =
  752. {
  753. .size = 0xFFFFFFFF,
  754. .type = HFI_CMD_SESSION_CVP_XRA_BLOB_FRAME,
  755. .is_config_pkt = false,
  756. .resp = HAL_NO_RESP,
  757. .name = "XRA_BLOB_FRAME",
  758. },
  759. [HFI_CMD_SESSION_CVP_XRA_BLOB_CONFIG - HFI_CMD_SESSION_CVP_START] =
  760. {
  761. .size = 0xFFFFFFFF,
  762. .type = HFI_CMD_SESSION_CVP_XRA_BLOB_CONFIG,
  763. .is_config_pkt = true,
  764. .resp = HAL_NO_RESP,
  765. .name = "XRA_BLOB_CONFIG",
  766. },
  767. [HFI_CMD_SESSION_CVP_XRA_PATCH_FRAME - HFI_CMD_SESSION_CVP_START] =
  768. {
  769. .size = 0xFFFFFFFF,
  770. .type = HFI_CMD_SESSION_CVP_XRA_PATCH_FRAME,
  771. .is_config_pkt = false,
  772. .resp = HAL_NO_RESP,
  773. .name = "XRA_PATCH_FRAME",
  774. .force_kernel_fence = false,
  775. },
  776. [HFI_CMD_SESSION_CVP_XRA_PATCH_CONFIG - HFI_CMD_SESSION_CVP_START] =
  777. {
  778. .size = 0xFFFFFFFF,
  779. .type = HFI_CMD_SESSION_CVP_XRA_PATCH_CONFIG,
  780. .is_config_pkt = true,
  781. .resp = HAL_NO_RESP,
  782. .name = "XRA_PATCH_CONFIG",
  783. },
  784. [HFI_CMD_SESSION_CVP_XRA_MATCH_FRAME - HFI_CMD_SESSION_CVP_START] =
  785. {
  786. .size = 0xFFFFFFFF,
  787. .type = HFI_CMD_SESSION_CVP_XRA_MATCH_FRAME,
  788. .is_config_pkt = false,
  789. .resp = HAL_NO_RESP,
  790. .name = "XRA_MATCH_FRAME",
  791. .force_kernel_fence = false,
  792. },
  793. [HFI_CMD_SESSION_CVP_XRA_MATCH_CONFIG - HFI_CMD_SESSION_CVP_START] =
  794. {
  795. .size = 0xFFFFFFFF,
  796. .type = HFI_CMD_SESSION_CVP_XRA_MATCH_CONFIG,
  797. .is_config_pkt = true,
  798. .resp = HAL_NO_RESP,
  799. .name = "XRA_MATCH_CONFIG",
  800. },
  801. [HFI_CMD_SESSION_CVP_RGE_FRAME - HFI_CMD_SESSION_CVP_START] =
  802. {
  803. .size = 0xFFFFFFFF,
  804. .type = HFI_CMD_SESSION_CVP_RGE_FRAME,
  805. .is_config_pkt = false,
  806. .resp = HAL_NO_RESP,
  807. .name = "RGE_FRAME",
  808. .force_kernel_fence = true,
  809. },
  810. [HFI_CMD_SESSION_CVP_RGE_CONFIG - HFI_CMD_SESSION_CVP_START] =
  811. {
  812. .size = 0xFFFFFFFF,
  813. .type = HFI_CMD_SESSION_CVP_RGE_CONFIG,
  814. .is_config_pkt = true,
  815. .resp = HAL_NO_RESP,
  816. .name = "RGE_CONFIG",
  817. },
  818. [HFI_CMD_SESSION_EVA_ITOF_FRAME - HFI_CMD_SESSION_CVP_START] =
  819. {
  820. .size = 0xFFFFFFFF,
  821. .type = HFI_CMD_SESSION_EVA_ITOF_FRAME,
  822. .is_config_pkt = false,
  823. .resp = HAL_NO_RESP,
  824. .name = "ITOF_FRAME",
  825. .force_kernel_fence = true,
  826. },
  827. [HFI_CMD_SESSION_EVA_ITOF_CONFIG - HFI_CMD_SESSION_CVP_START] =
  828. {
  829. .size = 0xFFFFFFFF,
  830. .type = HFI_CMD_SESSION_EVA_ITOF_CONFIG,
  831. .is_config_pkt = true,
  832. .resp = HAL_NO_RESP,
  833. .name = "ITOF_CONFIG",
  834. },
  835. [HFI_CMD_SESSION_EVA_DLFD_FRAME - HFI_CMD_SESSION_CVP_START] =
  836. {
  837. .size = 0xFFFFFFFF,
  838. .type = HFI_CMD_SESSION_EVA_DLFD_FRAME,
  839. .is_config_pkt = false,
  840. .resp = HAL_NO_RESP,
  841. .name = "DLFD_FRAME",
  842. },
  843. [HFI_CMD_SESSION_EVA_DLFD_CONFIG - HFI_CMD_SESSION_CVP_START] =
  844. {
  845. .size = 0xFFFFFFFF,
  846. .type = HFI_CMD_SESSION_EVA_DLFD_CONFIG,
  847. .is_config_pkt = true,
  848. .resp = HAL_NO_RESP,
  849. .name = "DLFD_CONFIG",
  850. },
  851. [HFI_CMD_SESSION_EVA_DLFL_FRAME - HFI_CMD_SESSION_CVP_START] =
  852. {
  853. .size = 0xFFFFFFFF,
  854. .type = HFI_CMD_SESSION_EVA_DLFL_FRAME,
  855. .is_config_pkt = false,
  856. .resp = HAL_NO_RESP,
  857. .name = "DLFL_FRAME",
  858. .force_kernel_fence = false,
  859. },
  860. [HFI_CMD_SESSION_EVA_DLFL_CONFIG - HFI_CMD_SESSION_CVP_START] =
  861. {
  862. .size = 0xFFFFFFFF,
  863. .type = HFI_CMD_SESSION_EVA_DLFL_CONFIG,
  864. .is_config_pkt = true,
  865. .resp = HAL_NO_RESP,
  866. .name = "DLFL_CONFIG",
  867. },
  868. [HFI_CMD_SESSION_CVP_SYNX - HFI_CMD_SESSION_CVP_START] =
  869. {
  870. .size = 0xFFFFFFFF,
  871. .type = HFI_CMD_SESSION_CVP_SYNX,
  872. .is_config_pkt = true,
  873. .resp = HAL_NO_RESP,
  874. .name = "SYNX_TEST",
  875. },
  876. [HFI_CMD_SESSION_EVA_DME_ONLY_CONFIG - HFI_CMD_SESSION_CVP_START] =
  877. {
  878. .size = 0xFFFFFFFF,
  879. .type = HFI_CMD_SESSION_EVA_DME_ONLY_CONFIG,
  880. .is_config_pkt = true,
  881. .resp = HAL_NO_RESP,
  882. .name = "DME_CONFIG",
  883. },
  884. [HFI_CMD_SESSION_EVA_DME_ONLY_FRAME - HFI_CMD_SESSION_CVP_START] =
  885. {
  886. .size = 0xFFFFFFFF,
  887. .type = HFI_CMD_SESSION_EVA_DME_ONLY_FRAME,
  888. .is_config_pkt = false,
  889. .resp = HAL_NO_RESP,
  890. .name = "DME_FRAME",
  891. .force_kernel_fence = true,
  892. },
  893. };
  894. int get_pkt_index(struct cvp_hal_session_cmd_pkt *hdr)
  895. {
  896. if (!hdr || (hdr->packet_type < HFI_CMD_SESSION_CVP_START)
  897. || hdr->packet_type >= (HFI_CMD_SESSION_CVP_START + MAX_PKT_IDX))
  898. return -EINVAL;
  899. if (cvp_hfi_defs[hdr->packet_type - HFI_CMD_SESSION_CVP_START].size)
  900. return (hdr->packet_type - HFI_CMD_SESSION_CVP_START);
  901. return -EINVAL;
  902. }
  903. int get_pkt_fenceoverride(struct cvp_hal_session_cmd_pkt* hdr)
  904. {
  905. return cvp_hfi_defs[hdr->packet_type - HFI_CMD_SESSION_CVP_START].force_kernel_fence;
  906. }
  907. int get_pkt_index_from_type(u32 pkt_type)
  908. {
  909. if ((pkt_type < HFI_CMD_SESSION_CVP_START) ||
  910. pkt_type >= (HFI_CMD_SESSION_CVP_START + MAX_PKT_IDX))
  911. return -EINVAL;
  912. if (cvp_hfi_defs[pkt_type - HFI_CMD_SESSION_CVP_START].size)
  913. return (pkt_type - HFI_CMD_SESSION_CVP_START);
  914. return -EINVAL;
  915. }
  916. MODULE_DEVICE_TABLE(of, msm_cvp_dt_match);
  917. int cvp_of_fdt_get_ddrtype(void)
  918. {
  919. #ifdef FIXED_DDR_TYPE
  920. /* of_fdt_get_ddrtype() is usually unavailable during pre-sil */
  921. return DDR_TYPE_LPDDR5;
  922. #else
  923. return of_fdt_get_ddrtype();
  924. #endif
  925. }
  926. void *cvp_get_drv_data(struct device *dev)
  927. {
  928. struct msm_cvp_platform_data *driver_data;
  929. const struct of_device_id *match;
  930. uint32_t ddr_type = DDR_TYPE_LPDDR5;
  931. driver_data = &default_data;
  932. if (!IS_ENABLED(CONFIG_OF) || !dev->of_node)
  933. goto exit;
  934. match = of_match_node(msm_cvp_dt_match, dev->of_node);
  935. if (!match)
  936. return NULL;
  937. driver_data = (struct msm_cvp_platform_data *)match->data;
  938. if (!strcmp(match->compatible, "qcom,waipio-cvp")) {
  939. ddr_type = cvp_of_fdt_get_ddrtype();
  940. if (ddr_type == -ENOENT) {
  941. dprintk(CVP_ERR,
  942. "Failed to get ddr type, use LPDDR5\n");
  943. }
  944. if (driver_data->ubwc_config &&
  945. (ddr_type == DDR_TYPE_LPDDR4 ||
  946. ddr_type == DDR_TYPE_LPDDR4X))
  947. driver_data->ubwc_config->highest_bank_bit = 15;
  948. dprintk(CVP_CORE, "DDR Type 0x%x hbb 0x%x\n",
  949. ddr_type, driver_data->ubwc_config ?
  950. driver_data->ubwc_config->highest_bank_bit : -1);
  951. }
  952. exit:
  953. return driver_data;
  954. }