cvp_hfi.c 140 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <asm/memory.h>
  7. #include <linux/coresight-stm.h>
  8. #include <linux/delay.h>
  9. #include <linux/devfreq.h>
  10. #include <linux/hash.h>
  11. #include <linux/io.h>
  12. #include <linux/iommu.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/of.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/slab.h>
  18. #include <linux/workqueue.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/soc/qcom/llcc-qcom.h>
  21. #include <linux/qcom_scm.h>
  22. #include <linux/soc/qcom/smem.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/reset.h>
  25. #include <linux/pm_wakeup.h>
  26. #include "hfi_packetization.h"
  27. #include "msm_cvp_debug.h"
  28. #include "cvp_core_hfi.h"
  29. #include "cvp_hfi_helper.h"
  30. #include "cvp_hfi_io.h"
  31. #include "msm_cvp_dsp.h"
  32. #include "msm_cvp_clocks.h"
  33. #include "vm/cvp_vm.h"
  34. #include "cvp_dump.h"
  35. // ysi - added for debug
  36. #include <linux/clk/qcom.h>
  37. #include "msm_cvp_common.h"
  38. #define REG_ADDR_OFFSET_BITMASK 0x000FFFFF
  39. #define QDSS_IOVA_START 0x80001000
  40. #define MIN_PAYLOAD_SIZE 3
  41. struct cvp_tzbsp_memprot {
  42. u32 cp_start;
  43. u32 cp_size;
  44. u32 cp_nonpixel_start;
  45. u32 cp_nonpixel_size;
  46. };
  47. #define TZBSP_CVP_PAS_ID 26
  48. /* Poll interval in uS */
  49. #define POLL_INTERVAL_US 50
  50. enum tzbsp_subsys_state {
  51. TZ_SUBSYS_STATE_SUSPEND = 0,
  52. TZ_SUBSYS_STATE_RESUME = 1,
  53. TZ_SUBSYS_STATE_RESTORE_THRESHOLD = 2,
  54. };
  55. const struct msm_cvp_gov_data CVP_DEFAULT_BUS_VOTE = {
  56. .data = NULL,
  57. .data_count = 0,
  58. };
  59. const int cvp_max_packets = 32;
  60. static void iris_hfi_pm_handler(struct work_struct *work);
  61. static DECLARE_DELAYED_WORK(iris_hfi_pm_work, iris_hfi_pm_handler);
  62. static inline int __resume(struct iris_hfi_device *device);
  63. static inline int __suspend(struct iris_hfi_device *device);
  64. static int __disable_regulator(struct iris_hfi_device *device,
  65. const char *name);
  66. static int __enable_regulator(struct iris_hfi_device *device,
  67. const char *name);
  68. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet);
  69. static int __initialize_packetization(struct iris_hfi_device *device);
  70. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  71. u32 session_id);
  72. static bool __is_session_valid(struct iris_hfi_device *device,
  73. struct cvp_hal_session *session, const char *func);
  74. static int __iface_cmdq_write(struct iris_hfi_device *device,
  75. void *pkt);
  76. static int __load_fw(struct iris_hfi_device *device);
  77. static int __power_on_init(struct iris_hfi_device *device);
  78. static void __unload_fw(struct iris_hfi_device *device);
  79. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state);
  80. static int __enable_subcaches(struct iris_hfi_device *device);
  81. static int __set_subcaches(struct iris_hfi_device *device);
  82. static int __release_subcaches(struct iris_hfi_device *device);
  83. static int __disable_subcaches(struct iris_hfi_device *device);
  84. static int __power_collapse(struct iris_hfi_device *device, bool force);
  85. static int iris_hfi_noc_error_info(void *dev);
  86. static void interrupt_init_iris2(struct iris_hfi_device *device);
  87. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device);
  88. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device);
  89. static void power_off_iris2(struct iris_hfi_device *device);
  90. static int __set_ubwc_config(struct iris_hfi_device *device);
  91. static void __noc_error_info_iris2(struct iris_hfi_device *device);
  92. static int __enable_hw_power_collapse(struct iris_hfi_device *device);
  93. static int __disable_hw_power_collapse(struct iris_hfi_device *device);
  94. static int __power_off_controller(struct iris_hfi_device *device);
  95. static int __hwfence_regs_map(struct iris_hfi_device *device);
  96. static int __hwfence_regs_unmap(struct iris_hfi_device *device);
  97. static int __reset_control_assert_name(struct iris_hfi_device *device, const char *name);
  98. static int __reset_control_deassert_name(struct iris_hfi_device *device, const char *name);
  99. static int __reset_control_acquire(struct iris_hfi_device *device, const char *name);
  100. static int __reset_control_release(struct iris_hfi_device *device, const char *name);
  101. static bool __is_ctl_power_on(struct iris_hfi_device *device);
  102. static struct cvp_hal_ops hal_ops = {
  103. .interrupt_init = interrupt_init_iris2,
  104. .setup_dsp_uc_memmap = setup_dsp_uc_memmap_vpu5,
  105. .clock_config_on_enable = clock_config_on_enable_vpu5,
  106. .power_off = power_off_iris2,
  107. .noc_error_info = __noc_error_info_iris2,
  108. .reset_control_assert_name = __reset_control_assert_name,
  109. .reset_control_deassert_name = __reset_control_deassert_name,
  110. .reset_control_acquire_name = __reset_control_acquire,
  111. .reset_control_release_name = __reset_control_release,
  112. };
  113. /**
  114. * Utility function to enforce some of our assumptions. Spam calls to this
  115. * in hotspots in code to double check some of the assumptions that we hold.
  116. */
  117. static inline void __strict_check(struct iris_hfi_device *device)
  118. {
  119. msm_cvp_res_handle_fatal_hw_error(device->res,
  120. !mutex_is_locked(&device->lock));
  121. }
  122. static inline void __set_state(struct iris_hfi_device *device,
  123. enum iris_hfi_state state)
  124. {
  125. device->state = state;
  126. }
  127. static inline bool __core_in_valid_state(struct iris_hfi_device *device)
  128. {
  129. return device->state != IRIS_STATE_DEINIT;
  130. }
  131. static inline bool is_sys_cache_present(struct iris_hfi_device *device)
  132. {
  133. return device->res->sys_cache_present;
  134. }
  135. static int cvp_synx_recover(void)
  136. {
  137. #ifdef CVP_SYNX_ENABLED
  138. return synx_recover(SYNX_CLIENT_EVA_CTX0);
  139. #else
  140. return 0;
  141. #endif /* End of CVP_SYNX_ENABLED */
  142. }
  143. #define ROW_SIZE 32
  144. unsigned long long get_aon_time(void)
  145. {
  146. unsigned long long val;
  147. asm volatile("mrs %0, cntvct_el0" : "=r" (val));
  148. return val;
  149. }
  150. int get_hfi_version(void)
  151. {
  152. struct msm_cvp_core *core;
  153. struct iris_hfi_device *hfi;
  154. core = cvp_driver->cvp_core;
  155. hfi = (struct iris_hfi_device *)core->dev_ops->hfi_device_data;
  156. return hfi->version;
  157. }
  158. unsigned int get_msg_size(struct cvp_hfi_msg_session_hdr *hdr)
  159. {
  160. struct msm_cvp_core *core;
  161. struct iris_hfi_device *device;
  162. u32 minor_ver;
  163. core = cvp_driver->cvp_core;
  164. if (core)
  165. device = core->dev_ops->hfi_device_data;
  166. else
  167. return 0;
  168. if (!device) {
  169. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  170. return 0;
  171. }
  172. minor_ver = (device->version & HFI_VERSION_MINOR_MASK) >>
  173. HFI_VERSION_MINOR_SHIFT;
  174. if (minor_ver < 2)
  175. return sizeof(struct cvp_hfi_msg_session_hdr);
  176. if (hdr->packet_type == HFI_MSG_SESSION_CVP_FD)
  177. return sizeof(struct cvp_hfi_msg_session_hdr_ext);
  178. else
  179. return sizeof(struct cvp_hfi_msg_session_hdr);
  180. }
  181. unsigned int get_msg_session_id(void *msg)
  182. {
  183. struct cvp_hfi_msg_session_hdr *hdr =
  184. (struct cvp_hfi_msg_session_hdr *)msg;
  185. return hdr->session_id;
  186. }
  187. unsigned int get_msg_errorcode(void *msg)
  188. {
  189. struct cvp_hfi_msg_session_hdr *hdr =
  190. (struct cvp_hfi_msg_session_hdr *)msg;
  191. return hdr->error_type;
  192. }
  193. int get_msg_opconfigs(void *msg, unsigned int *session_id,
  194. unsigned int *error_type, unsigned int *config_id)
  195. {
  196. struct cvp_hfi_msg_session_op_cfg_packet *cfg =
  197. (struct cvp_hfi_msg_session_op_cfg_packet *)msg;
  198. *session_id = cfg->session_id;
  199. *error_type = cfg->error_type;
  200. *config_id = cfg->op_conf_id;
  201. return 0;
  202. }
  203. static void __dump_packet(u8 *packet, enum cvp_msg_prio log_level)
  204. {
  205. u32 c = 0, packet_size = *(u32 *)packet;
  206. /*
  207. * row must contain enough for 0xdeadbaad * 8 to be converted into
  208. * "de ad ba ab " * 8 + '\0'
  209. */
  210. char row[3 * ROW_SIZE];
  211. for (c = 0; c * ROW_SIZE < packet_size; ++c) {
  212. int bytes_to_read = ((c + 1) * ROW_SIZE > packet_size) ?
  213. packet_size % ROW_SIZE : ROW_SIZE;
  214. hex_dump_to_buffer(packet + c * ROW_SIZE, bytes_to_read,
  215. ROW_SIZE, 4, row, sizeof(row), false);
  216. dprintk(log_level, "%s\n", row);
  217. }
  218. }
  219. static int __dsp_suspend(struct iris_hfi_device *device, bool force)
  220. {
  221. int rc;
  222. if (msm_cvp_dsp_disable)
  223. return 0;
  224. dprintk(CVP_DSP, "%s: suspend dsp\n", __func__);
  225. rc = cvp_dsp_suspend(force);
  226. if (rc) {
  227. if (rc != -EBUSY)
  228. dprintk(CVP_ERR,
  229. "%s: dsp suspend failed with error %d\n",
  230. __func__, rc);
  231. return rc;
  232. }
  233. dprintk(CVP_DSP, "%s: dsp suspended\n", __func__);
  234. return 0;
  235. }
  236. static int __dsp_resume(struct iris_hfi_device *device)
  237. {
  238. int rc;
  239. if (msm_cvp_dsp_disable)
  240. return 0;
  241. dprintk(CVP_DSP, "%s: resume dsp\n", __func__);
  242. rc = cvp_dsp_resume();
  243. if (rc) {
  244. dprintk(CVP_ERR,
  245. "%s: dsp resume failed with error %d\n",
  246. __func__, rc);
  247. return rc;
  248. }
  249. dprintk(CVP_DSP, "%s: dsp resumed\n", __func__);
  250. return rc;
  251. }
  252. static int __dsp_shutdown(struct iris_hfi_device *device)
  253. {
  254. int rc;
  255. if (msm_cvp_dsp_disable)
  256. return 0;
  257. dprintk(CVP_DSP, "%s: shutdown dsp\n", __func__);
  258. rc = cvp_dsp_shutdown();
  259. if (rc) {
  260. dprintk(CVP_ERR,
  261. "%s: dsp shutdown failed with error %d\n",
  262. __func__, rc);
  263. WARN_ON(1);
  264. }
  265. dprintk(CVP_DSP, "%s: dsp shutdown successful\n", __func__);
  266. return rc;
  267. }
  268. static int __acquire_regulator(struct regulator_info *rinfo,
  269. struct iris_hfi_device *device)
  270. {
  271. int rc = 0;
  272. if (rinfo->has_hw_power_collapse) {
  273. rc = regulator_set_mode(rinfo->regulator,
  274. REGULATOR_MODE_NORMAL);
  275. if (rc) {
  276. /*
  277. * This is somewhat fatal, but nothing we can do
  278. * about it. We can't disable the regulator w/o
  279. * getting it back under s/w control
  280. */
  281. dprintk(CVP_WARN,
  282. "Failed to acquire regulator control: %s\n",
  283. rinfo->name);
  284. } else {
  285. dprintk(CVP_PWR,
  286. "Acquire regulator control from HW: %s\n",
  287. rinfo->name);
  288. }
  289. }
  290. if (!regulator_is_enabled(rinfo->regulator)) {
  291. dprintk(CVP_WARN, "Regulator is not enabled %s\n",
  292. rinfo->name);
  293. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  294. }
  295. return rc;
  296. }
  297. static int __hand_off_regulator(struct regulator_info *rinfo)
  298. {
  299. int rc = 0;
  300. if (rinfo->has_hw_power_collapse) {
  301. rc = regulator_set_mode(rinfo->regulator,
  302. REGULATOR_MODE_FAST);
  303. if (rc) {
  304. dprintk(CVP_WARN,
  305. "Failed to hand off regulator control: %s\n",
  306. rinfo->name);
  307. } else {
  308. dprintk(CVP_PWR,
  309. "Hand off regulator control to HW: %s\n",
  310. rinfo->name);
  311. }
  312. }
  313. return rc;
  314. }
  315. static int __hand_off_regulators(struct iris_hfi_device *device)
  316. {
  317. struct regulator_info *rinfo;
  318. int rc = 0, c = 0;
  319. iris_hfi_for_each_regulator(device, rinfo) {
  320. rc = __hand_off_regulator(rinfo);
  321. /*
  322. * If one regulator hand off failed, driver should take
  323. * the control for other regulators back.
  324. */
  325. if (rc)
  326. goto err_reg_handoff_failed;
  327. c++;
  328. }
  329. return rc;
  330. err_reg_handoff_failed:
  331. iris_hfi_for_each_regulator_reverse_continue(device, rinfo, c)
  332. __acquire_regulator(rinfo, device);
  333. return rc;
  334. }
  335. static int __take_back_regulators(struct iris_hfi_device *device)
  336. {
  337. struct regulator_info *rinfo;
  338. int rc = 0;
  339. iris_hfi_for_each_regulator(device, rinfo) {
  340. rc = __acquire_regulator(rinfo, device);
  341. /*
  342. * if one regulator hand off failed, driver should take
  343. * the control for other regulators back.
  344. */
  345. if (rc)
  346. return rc;
  347. }
  348. return rc;
  349. }
  350. static int __write_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  351. bool *rx_req_is_set)
  352. {
  353. struct cvp_hfi_queue_header *queue;
  354. struct cvp_hfi_cmd_session_hdr *cmd_pkt;
  355. u32 packet_size_in_words, new_write_idx;
  356. u32 empty_space, read_idx, write_idx;
  357. u32 *write_ptr;
  358. if (!qinfo || !packet) {
  359. dprintk(CVP_ERR, "Invalid Params\n");
  360. return -EINVAL;
  361. } else if (!qinfo->q_array.align_virtual_addr) {
  362. dprintk(CVP_WARN, "Queues have already been freed\n");
  363. return -EINVAL;
  364. }
  365. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  366. if (!queue) {
  367. dprintk(CVP_ERR, "queue not present\n");
  368. return -ENOENT;
  369. }
  370. cmd_pkt = (struct cvp_hfi_cmd_session_hdr *)packet;
  371. if (cmd_pkt->size >= sizeof(struct cvp_hfi_cmd_session_hdr))
  372. dprintk(CVP_CMD, "%s: pkt_type %08x sess_id %08x trans_id %u ktid %llu\n",
  373. __func__, cmd_pkt->packet_type,
  374. cmd_pkt->session_id,
  375. cmd_pkt->client_data.transaction_id,
  376. cmd_pkt->client_data.kdata & (FENCE_BIT - 1));
  377. else if (cmd_pkt->size >= 12)
  378. dprintk(CVP_CMD, "%s: pkt_type %08x sess_id %08x\n", __func__,
  379. cmd_pkt->packet_type, cmd_pkt->session_id);
  380. if (msm_cvp_debug & CVP_PKT) {
  381. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  382. __dump_packet(packet, CVP_PKT);
  383. }
  384. packet_size_in_words = (*(u32 *)packet) >> 2;
  385. if (!packet_size_in_words || packet_size_in_words >
  386. qinfo->q_array.mem_size>>2) {
  387. dprintk(CVP_ERR, "Invalid packet size\n");
  388. return -ENODATA;
  389. }
  390. spin_lock(&qinfo->hfi_lock);
  391. read_idx = queue->qhdr_read_idx;
  392. write_idx = queue->qhdr_write_idx;
  393. empty_space = (write_idx >= read_idx) ?
  394. ((qinfo->q_array.mem_size>>2) - (write_idx - read_idx)) :
  395. (read_idx - write_idx);
  396. if (empty_space <= packet_size_in_words) {
  397. queue->qhdr_tx_req = 1;
  398. spin_unlock(&qinfo->hfi_lock);
  399. dprintk(CVP_ERR, "Insufficient size (%d) to write (%d)\n",
  400. empty_space, packet_size_in_words);
  401. return -ENOTEMPTY;
  402. }
  403. queue->qhdr_tx_req = 0;
  404. new_write_idx = write_idx + packet_size_in_words;
  405. write_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  406. (write_idx << 2));
  407. if (write_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  408. write_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  409. qinfo->q_array.mem_size)) {
  410. spin_unlock(&qinfo->hfi_lock);
  411. dprintk(CVP_ERR, "Invalid write index\n");
  412. return -ENODATA;
  413. }
  414. if (new_write_idx < (qinfo->q_array.mem_size >> 2)) {
  415. memcpy(write_ptr, packet, packet_size_in_words << 2);
  416. } else {
  417. new_write_idx -= qinfo->q_array.mem_size >> 2;
  418. memcpy(write_ptr, packet, (packet_size_in_words -
  419. new_write_idx) << 2);
  420. memcpy((void *)qinfo->q_array.align_virtual_addr,
  421. packet + ((packet_size_in_words - new_write_idx) << 2),
  422. new_write_idx << 2);
  423. }
  424. /*
  425. * Memory barrier to make sure packet is written before updating the
  426. * write index
  427. */
  428. mb();
  429. queue->qhdr_write_idx = new_write_idx;
  430. if (rx_req_is_set)
  431. *rx_req_is_set = queue->qhdr_rx_req == 1;
  432. /*
  433. * Memory barrier to make sure write index is updated before an
  434. * interrupt is raised.
  435. */
  436. mb();
  437. spin_unlock(&qinfo->hfi_lock);
  438. return 0;
  439. }
  440. static int __read_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  441. u32 *pb_tx_req_is_set)
  442. {
  443. struct cvp_hfi_queue_header *queue;
  444. struct cvp_hfi_msg_session_hdr *msg_pkt;
  445. u32 packet_size_in_words, new_read_idx;
  446. u32 *read_ptr;
  447. u32 receive_request = 0;
  448. u32 read_idx, write_idx;
  449. int rc = 0;
  450. if (!qinfo || !packet || !pb_tx_req_is_set) {
  451. dprintk(CVP_ERR, "Invalid Params\n");
  452. return -EINVAL;
  453. } else if (!qinfo->q_array.align_virtual_addr) {
  454. dprintk(CVP_WARN, "Queues have already been freed\n");
  455. return -EINVAL;
  456. }
  457. /*
  458. * Memory barrier to make sure data is valid before
  459. *reading it
  460. */
  461. mb();
  462. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  463. if (!queue) {
  464. dprintk(CVP_ERR, "Queue memory is not allocated\n");
  465. return -ENOMEM;
  466. }
  467. /*
  468. * Do not set receive request for debug queue, if set,
  469. * Iris generates interrupt for debug messages even
  470. * when there is no response message available.
  471. * In general debug queue will not become full as it
  472. * is being emptied out for every interrupt from Iris.
  473. * Iris will anyway generates interrupt if it is full.
  474. */
  475. spin_lock(&qinfo->hfi_lock);
  476. if (queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_MSG_Q)
  477. receive_request = 1;
  478. read_idx = queue->qhdr_read_idx;
  479. write_idx = queue->qhdr_write_idx;
  480. if (read_idx == write_idx) {
  481. queue->qhdr_rx_req = receive_request;
  482. /*
  483. * mb() to ensure qhdr is updated in main memory
  484. * so that iris reads the updated header values
  485. */
  486. mb();
  487. *pb_tx_req_is_set = 0;
  488. if (write_idx != queue->qhdr_write_idx) {
  489. queue->qhdr_rx_req = 0;
  490. } else {
  491. spin_unlock(&qinfo->hfi_lock);
  492. dprintk(CVP_HFI,
  493. "%s queue is empty, rx_req = %u, tx_req = %u, read_idx = %u\n",
  494. receive_request ? "message" : "debug",
  495. queue->qhdr_rx_req, queue->qhdr_tx_req,
  496. queue->qhdr_read_idx);
  497. return -ENODATA;
  498. }
  499. }
  500. read_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  501. (read_idx << 2));
  502. if (read_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  503. read_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  504. qinfo->q_array.mem_size - sizeof(*read_ptr))) {
  505. spin_unlock(&qinfo->hfi_lock);
  506. dprintk(CVP_ERR, "Invalid read index\n");
  507. return -ENODATA;
  508. }
  509. packet_size_in_words = (*read_ptr) >> 2;
  510. if (!packet_size_in_words) {
  511. spin_unlock(&qinfo->hfi_lock);
  512. dprintk(CVP_ERR, "Zero packet size\n");
  513. return -ENODATA;
  514. }
  515. new_read_idx = read_idx + packet_size_in_words;
  516. if (((packet_size_in_words << 2) <= CVP_IFACEQ_VAR_HUGE_PKT_SIZE)
  517. && read_idx <= (qinfo->q_array.mem_size >> 2)) {
  518. if (new_read_idx < (qinfo->q_array.mem_size >> 2)) {
  519. memcpy(packet, read_ptr,
  520. packet_size_in_words << 2);
  521. } else {
  522. new_read_idx -= (qinfo->q_array.mem_size >> 2);
  523. memcpy(packet, read_ptr,
  524. (packet_size_in_words - new_read_idx) << 2);
  525. memcpy(packet + ((packet_size_in_words -
  526. new_read_idx) << 2),
  527. (u8 *)qinfo->q_array.align_virtual_addr,
  528. new_read_idx << 2);
  529. }
  530. } else {
  531. dprintk(CVP_WARN,
  532. "BAD packet received, read_idx: %#x, pkt_size: %d\n",
  533. read_idx, packet_size_in_words << 2);
  534. dprintk(CVP_WARN, "Dropping this packet\n");
  535. new_read_idx = write_idx;
  536. rc = -ENODATA;
  537. }
  538. if (new_read_idx != queue->qhdr_write_idx)
  539. queue->qhdr_rx_req = 0;
  540. else
  541. queue->qhdr_rx_req = receive_request;
  542. queue->qhdr_read_idx = new_read_idx;
  543. /*
  544. * mb() to ensure qhdr is updated in main memory
  545. * so that iris reads the updated header values
  546. */
  547. mb();
  548. *pb_tx_req_is_set = (queue->qhdr_tx_req == 1) ? 1 : 0;
  549. spin_unlock(&qinfo->hfi_lock);
  550. if (!(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  551. msg_pkt = (struct cvp_hfi_msg_session_hdr *)packet;
  552. dprintk(CVP_CMD, "%s: "
  553. "pkt_type %08x sess_id %08x trans_id %u ktid %llu\n",
  554. __func__, msg_pkt->packet_type,
  555. msg_pkt->session_id,
  556. msg_pkt->client_data.transaction_id,
  557. msg_pkt->client_data.kdata & (FENCE_BIT - 1));
  558. }
  559. if ((msm_cvp_debug & CVP_PKT) &&
  560. !(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  561. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  562. __dump_packet(packet, CVP_PKT);
  563. }
  564. return rc;
  565. }
  566. static int __smem_alloc(struct iris_hfi_device *dev, struct cvp_mem_addr *mem,
  567. u32 size, u32 align, u32 flags)
  568. {
  569. struct msm_cvp_smem *alloc = &mem->mem_data;
  570. int rc = 0;
  571. if (!dev || !mem || !size) {
  572. dprintk(CVP_ERR, "Invalid Params\n");
  573. return -EINVAL;
  574. }
  575. dprintk(CVP_INFO, "start to alloc size: %d, flags: %d\n", size, flags);
  576. alloc->flags = flags;
  577. rc = msm_cvp_smem_alloc(size, align, 1, (void *)dev->res, alloc);
  578. if (rc) {
  579. dprintk(CVP_ERR, "Alloc failed\n");
  580. rc = -ENOMEM;
  581. goto fail_smem_alloc;
  582. }
  583. dprintk(CVP_MEM, "%s: ptr = %pK, size = %d\n", __func__,
  584. alloc->kvaddr, size);
  585. mem->mem_size = alloc->size;
  586. mem->align_virtual_addr = alloc->kvaddr;
  587. mem->align_device_addr = alloc->device_addr;
  588. alloc->pkt_type = 0;
  589. alloc->buf_idx = 0;
  590. return rc;
  591. fail_smem_alloc:
  592. return rc;
  593. }
  594. static void __smem_free(struct iris_hfi_device *dev, struct msm_cvp_smem *mem)
  595. {
  596. if (!dev || !mem) {
  597. dprintk(CVP_ERR, "invalid param %pK %pK\n", dev, mem);
  598. return;
  599. }
  600. msm_cvp_smem_free(mem);
  601. }
  602. static void __write_register(struct iris_hfi_device *device,
  603. u32 reg, u32 value)
  604. {
  605. u32 hwiosymaddr = reg;
  606. u8 *base_addr;
  607. if (!device) {
  608. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  609. return;
  610. }
  611. __strict_check(device);
  612. if (!device->power_enabled) {
  613. dprintk(CVP_WARN,
  614. "HFI Write register failed : Power is OFF\n");
  615. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  616. return;
  617. }
  618. base_addr = device->cvp_hal_data->register_base;
  619. dprintk(CVP_REG, "Base addr: %pK, written to: %#x, Value: %#x...\n",
  620. base_addr, hwiosymaddr, value);
  621. base_addr += hwiosymaddr;
  622. writel_relaxed(value, base_addr);
  623. /*
  624. * Memory barrier to make sure value is written into the register.
  625. */
  626. wmb();
  627. }
  628. static int __read_gcc_register(struct iris_hfi_device *device, u32 reg)
  629. {
  630. int rc = 0;
  631. u8 *base_addr;
  632. if (!device) {
  633. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  634. return -EINVAL;
  635. }
  636. __strict_check(device);
  637. if (!device->power_enabled) {
  638. dprintk(CVP_WARN,
  639. "%s HFI Read register failed : Power is OFF\n",
  640. __func__);
  641. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  642. return -EINVAL;
  643. }
  644. base_addr = device->cvp_hal_data->gcc_reg_base;
  645. rc = readl_relaxed(base_addr + reg);
  646. /*
  647. * Memory barrier to make sure value is read correctly from the
  648. * register.
  649. */
  650. rmb();
  651. dprintk(CVP_REG,
  652. "GCC Base addr: %pK, read from: %#x, value: %#x...\n",
  653. base_addr, reg, rc);
  654. return rc;
  655. }
  656. static int __read_register(struct iris_hfi_device *device, u32 reg)
  657. {
  658. int rc = 0;
  659. u8 *base_addr;
  660. if (!device) {
  661. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  662. return -EINVAL;
  663. }
  664. __strict_check(device);
  665. if (!device->power_enabled) {
  666. dprintk(CVP_WARN,
  667. "HFI Read register failed : Power is OFF\n");
  668. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  669. return -EINVAL;
  670. }
  671. base_addr = device->cvp_hal_data->register_base;
  672. rc = readl_relaxed(base_addr + reg);
  673. /*
  674. * Memory barrier to make sure value is read correctly from the
  675. * register.
  676. */
  677. rmb();
  678. dprintk(CVP_REG, "Base addr: %pK, read from: %#x, value: %#x...\n",
  679. base_addr, reg, rc);
  680. return rc;
  681. }
  682. static bool __is_ctl_power_on(struct iris_hfi_device *device)
  683. {
  684. u32 reg;
  685. reg = __read_register(device, CVP_CC_MVS1C_GDSCR);
  686. if (!(reg & 0x80000000))
  687. return false;
  688. reg = __read_register(device, CVP_CC_MVS1C_CBCR);
  689. if (reg & 0x80000000)
  690. return false;
  691. return true;
  692. }
  693. static int __set_registers(struct iris_hfi_device *device)
  694. {
  695. struct msm_cvp_core *core;
  696. struct msm_cvp_platform_data *pdata;
  697. struct reg_set *reg_set;
  698. int i;
  699. if (!device->res) {
  700. dprintk(CVP_ERR,
  701. "device resources null, cannot set registers\n");
  702. return -EINVAL ;
  703. }
  704. core = cvp_driver->cvp_core;
  705. pdata = core->platform_data;
  706. reg_set = &device->res->reg_set;
  707. for (i = 0; i < reg_set->count; i++) {
  708. __write_register(device, reg_set->reg_tbl[i].reg,
  709. reg_set->reg_tbl[i].value);
  710. dprintk(CVP_REG, "write_reg offset=%x, val=%x\n",
  711. reg_set->reg_tbl[i].reg,
  712. reg_set->reg_tbl[i].value);
  713. }
  714. i = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  715. if (i) {
  716. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  717. return -EINVAL;
  718. }
  719. __write_register(device, CVP_CPU_CS_AXI4_QOS,
  720. pdata->noc_qos->axi_qos);
  721. __write_register(device, CVP_NOC_RGE_PRIORITYLUT_LOW,
  722. pdata->noc_qos->prioritylut_low);
  723. __write_register(device, CVP_NOC_RGE_PRIORITYLUT_HIGH,
  724. pdata->noc_qos->prioritylut_high);
  725. __write_register(device, CVP_NOC_RGE_URGENCY_LOW,
  726. pdata->noc_qos->urgency_low);
  727. __write_register(device, CVP_NOC_RGE_DANGERLUT_LOW,
  728. pdata->noc_qos->dangerlut_low);
  729. __write_register(device, CVP_NOC_RGE_SAFELUT_LOW,
  730. pdata->noc_qos->safelut_low);
  731. __write_register(device, CVP_NOC_GCE_PRIORITYLUT_LOW,
  732. pdata->noc_qos->prioritylut_low);
  733. __write_register(device, CVP_NOC_GCE_PRIORITYLUT_HIGH,
  734. pdata->noc_qos->prioritylut_high);
  735. __write_register(device, CVP_NOC_GCE_URGENCY_LOW,
  736. pdata->noc_qos->urgency_low);
  737. __write_register(device, CVP_NOC_GCE_DANGERLUT_LOW,
  738. pdata->noc_qos->dangerlut_low);
  739. __write_register(device, CVP_NOC_GCE_SAFELUT_LOW,
  740. pdata->noc_qos->safelut_low);
  741. __write_register(device, CVP_NOC_CDM_PRIORITYLUT_LOW,
  742. pdata->noc_qos->prioritylut_low);
  743. __write_register(device, CVP_NOC_CDM_PRIORITYLUT_HIGH,
  744. pdata->noc_qos->prioritylut_high);
  745. __write_register(device, CVP_NOC_CDM_URGENCY_LOW,
  746. pdata->noc_qos->urgency_low_ro);
  747. __write_register(device, CVP_NOC_CDM_DANGERLUT_LOW,
  748. pdata->noc_qos->dangerlut_low);
  749. __write_register(device, CVP_NOC_CDM_SAFELUT_LOW,
  750. pdata->noc_qos->safelut_low);
  751. /* Below registers write moved from FW to SW to enable UBWC */
  752. __write_register(device, CVP_NOC_RGE_NIU_DECCTL_LOW,
  753. 0x1);
  754. __write_register(device, CVP_NOC_RGE_NIU_ENCCTL_LOW,
  755. 0x1);
  756. __write_register(device, CVP_NOC_GCE_VADL_TOF_NIU_DECCTL_LOW,
  757. 0x1);
  758. __write_register(device, CVP_NOC_GCE_VADL_TOF_NIU_ENCCTL_LOW,
  759. 0x1);
  760. __write_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS,
  761. 0x3);
  762. __write_register(device, CVP_NOC_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW,
  763. 0x1);
  764. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  765. return 0;
  766. }
  767. /*
  768. * The existence of this function is a hack for 8996 (or certain Iris versions)
  769. * to overcome a hardware bug. Whenever the GDSCs momentarily power collapse
  770. * (after calling __hand_off_regulators()), the values of the threshold
  771. * registers (typically programmed by TZ) are incorrectly reset. As a result
  772. * reprogram these registers at certain agreed upon points.
  773. */
  774. static void __set_threshold_registers(struct iris_hfi_device *device)
  775. {
  776. u32 version = __read_register(device, CVP_WRAPPER_HW_VERSION);
  777. version &= ~GENMASK(15, 0);
  778. if (version != (0x3 << 28 | 0x43 << 16))
  779. return;
  780. if (__tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESTORE_THRESHOLD))
  781. dprintk(CVP_ERR, "Failed to restore threshold values\n");
  782. }
  783. static int __unvote_buses(struct iris_hfi_device *device)
  784. {
  785. int rc = 0;
  786. struct bus_info *bus = NULL;
  787. kfree(device->bus_vote.data);
  788. device->bus_vote.data = NULL;
  789. device->bus_vote.data_count = 0;
  790. iris_hfi_for_each_bus(device, bus) {
  791. rc = cvp_set_bw(bus, 0);
  792. if (rc) {
  793. dprintk(CVP_ERR,
  794. "%s: Failed unvoting bus\n", __func__);
  795. goto err_unknown_device;
  796. }
  797. }
  798. err_unknown_device:
  799. return rc;
  800. }
  801. static int __vote_buses(struct iris_hfi_device *device,
  802. struct cvp_bus_vote_data *data, int num_data)
  803. {
  804. int rc = 0;
  805. struct bus_info *bus = NULL;
  806. struct cvp_bus_vote_data *new_data = NULL;
  807. if (!num_data) {
  808. dprintk(CVP_PWR, "No vote data available\n");
  809. goto no_data_count;
  810. } else if (!data) {
  811. dprintk(CVP_ERR, "Invalid voting data\n");
  812. return -EINVAL;
  813. }
  814. new_data = kmemdup(data, num_data * sizeof(*new_data), GFP_KERNEL);
  815. if (!new_data) {
  816. dprintk(CVP_ERR, "Can't alloc memory to cache bus votes\n");
  817. rc = -ENOMEM;
  818. goto err_no_mem;
  819. }
  820. no_data_count:
  821. kfree(device->bus_vote.data);
  822. device->bus_vote.data = new_data;
  823. device->bus_vote.data_count = num_data;
  824. iris_hfi_for_each_bus(device, bus) {
  825. if (bus) {
  826. rc = cvp_set_bw(bus, bus->range[1]);
  827. if (rc)
  828. dprintk(CVP_ERR,
  829. "Failed voting bus %s to ab %u\n",
  830. bus->name, bus->range[1]*1000);
  831. }
  832. }
  833. err_no_mem:
  834. return rc;
  835. }
  836. static int iris_hfi_vote_buses(void *dev, struct bus_info *bus, unsigned long bw)
  837. {
  838. int rc = 0;
  839. struct iris_hfi_device *device = dev;
  840. if (!device)
  841. return -EINVAL;
  842. mutex_lock(&device->lock);
  843. rc = cvp_set_bw(bus, bw);
  844. mutex_unlock(&device->lock);
  845. return rc;
  846. }
  847. static int __core_set_resource(struct iris_hfi_device *device,
  848. struct cvp_resource_hdr *resource_hdr, void *resource_value)
  849. {
  850. struct cvp_hfi_cmd_sys_set_resource_packet *pkt;
  851. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  852. int rc = 0;
  853. if (!device || !resource_hdr || !resource_value) {
  854. dprintk(CVP_ERR, "set_res: Invalid Params\n");
  855. return -EINVAL;
  856. }
  857. pkt = (struct cvp_hfi_cmd_sys_set_resource_packet *) packet;
  858. rc = call_hfi_pkt_op(device, sys_set_resource,
  859. pkt, resource_hdr, resource_value);
  860. if (rc) {
  861. dprintk(CVP_ERR, "set_res: failed to create packet\n");
  862. goto err_create_pkt;
  863. }
  864. rc = __iface_cmdq_write(device, pkt);
  865. if (rc)
  866. rc = -ENOTEMPTY;
  867. err_create_pkt:
  868. return rc;
  869. }
  870. static int __core_release_resource(struct iris_hfi_device *device,
  871. struct cvp_resource_hdr *resource_hdr)
  872. {
  873. struct cvp_hfi_cmd_sys_release_resource_packet *pkt;
  874. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  875. int rc = 0;
  876. if (!device || !resource_hdr) {
  877. dprintk(CVP_ERR, "release_res: Invalid Params\n");
  878. return -EINVAL;
  879. }
  880. pkt = (struct cvp_hfi_cmd_sys_release_resource_packet *) packet;
  881. rc = call_hfi_pkt_op(device, sys_release_resource,
  882. pkt, resource_hdr);
  883. if (rc) {
  884. dprintk(CVP_ERR, "release_res: failed to create packet\n");
  885. goto err_create_pkt;
  886. }
  887. rc = __iface_cmdq_write(device, pkt);
  888. if (rc)
  889. rc = -ENOTEMPTY;
  890. err_create_pkt:
  891. return rc;
  892. }
  893. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state)
  894. {
  895. int rc = 0;
  896. rc = qcom_scm_set_remote_state(state, TZBSP_CVP_PAS_ID);
  897. dprintk(CVP_CORE, "Set state %d, resp %d\n", state, rc);
  898. if (rc) {
  899. dprintk(CVP_ERR, "Failed qcom_scm_set_remote_state %d\n", rc);
  900. return rc;
  901. }
  902. return 0;
  903. }
  904. /*
  905. * Based on fal10_veto, X2RPMh, core_pwr_on and PWAitMode value, infer
  906. * value of xtss_sw_reset. xtss_sw_reset is a TZ register bit. Driver
  907. * cannot access it directly.
  908. *
  909. * In __boot_firmware() function, the caller of this function. It checks
  910. * "core_pwr_on" == false, basically core powered off. So this function
  911. * doesn't check core_pwr_on. Assume core_pwr_on = false.
  912. *
  913. * fal10_veto = VPU_CPU_CS_X2RPMh[2] |
  914. * ( ~VPU_CPU_CS_X2RPMh[1] & core_pwr_on ) |
  915. * ( ~VPU_CPU_CS_X2RPMh[0] & ~( xtss_sw_reset | PWaitMode ) ) ;
  916. */
  917. static inline void check_tensilica_in_reset(struct iris_hfi_device *device)
  918. {
  919. u32 X2RPMh, fal10_veto, wait_mode;
  920. X2RPMh = __read_register(device, CVP_CPU_CS_X2RPMh);
  921. X2RPMh = X2RPMh & 0x7;
  922. /* wait_mode = 1: Tensilica is in WFI mode (PWaitMode = true) */
  923. wait_mode = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  924. wait_mode = wait_mode & 0x1;
  925. fal10_veto = __read_register(device, CVP_CPU_CS_X2RPMh_STATUS);
  926. fal10_veto = fal10_veto & 0x1;
  927. dprintk(CVP_WARN, "tensilica reset check %#x %#x %#x\n",
  928. X2RPMh, wait_mode, fal10_veto);
  929. }
  930. static const char boot_states[0x40][32] = {
  931. "NOT INIT",
  932. "RST_START",
  933. "INIT_MEMCTL",
  934. "INTENABLE_RST",
  935. "LITBASE_RST",
  936. "PREFETCH_EN",
  937. "MPU_INIT",
  938. "CTRL_INIT_READ",
  939. "MEMCTL_L1_FIX",
  940. "RESTORE_EXTRA_NW",
  941. "CORE_RESTORE",
  942. "COLD_BOOT",
  943. "DISABLE_CACHE",
  944. "BEFORE_MPU_C",
  945. "RET_MPU_C",
  946. "IN_MPU_C",
  947. "IN_MPU_DEFAULT",
  948. "IN_MPU_SYNX",
  949. "UCR_SIZE_FAIL",
  950. "UCR_ADDR_FAIL",
  951. "UCR1_SIZE_FAIL",
  952. "UCR1_ADDR_FAIL",
  953. "UCR_OVERLAPPED_UCR1",
  954. "UCR1_OVERLAPPED_UCR",
  955. "UCR_EQ_UCR1",
  956. "MPU_CHECK_DONE",
  957. "BEFORE_INT_LOCK",
  958. "AFTER_INT_LOCK",
  959. "BEFORE_INT_UNLOCK",
  960. "AFTER_INT_UNLOCK",
  961. "CALL_START",
  962. "MAIN_ENTRY",
  963. "VENUS_INIT_ENTRY",
  964. "VSYS_INIT_ENTRY",
  965. "BEFORE_XOS_CLK",
  966. "AFTER_XOS_CLK",
  967. "LOG_MUTEX_INIT",
  968. "CREATE_FRAMEWORK_ENTRY",
  969. "DTG_INIT",
  970. "IDLE_TASK_INIT",
  971. "VENUS_CORE_INIT",
  972. "HW_CORES_INIT",
  973. "RST_THREAD_INIT",
  974. "HOST_THREAD_INIT",
  975. "ALL_THREADS_INIT",
  976. "TASK_MEMPOOL",
  977. "SESSION_MUTEX",
  978. "SIGNALS_INIT",
  979. "RST_SIGNAL_INIT",
  980. "INTR_EN_HOST",
  981. "INTR_REG_HOST",
  982. "INTR_EN_DSP",
  983. "INTR_REG_DSP",
  984. "X2HSOFTINTEN",
  985. "H2XSOFTINTEN",
  986. "CPU2DSPINTEN",
  987. "DSP2CPUINT_SWRESET",
  988. "THREADS_START",
  989. "RST_THREAD_START",
  990. "HST_THREAD_START",
  991. "HST_THREAD_ENTRY"
  992. };
  993. static inline int __boot_firmware(struct iris_hfi_device *device)
  994. {
  995. int rc = 0, loop = 10;
  996. u32 ctrl_init_val = 0, ctrl_status = 0, count = 0, max_tries = 5000;
  997. u32 reg_gdsc;
  998. /*
  999. * Hand off control of regulators to h/w _after_ enabling clocks.
  1000. * Note that the GDSC will turn off when switching from normal
  1001. * (s/w triggered) to fast (HW triggered) unless the h/w vote is
  1002. * present. Since Iris isn't up yet, the GDSC will be off briefly.
  1003. */
  1004. if (__enable_hw_power_collapse(device))
  1005. dprintk(CVP_ERR, "Failed to enabled inter-frame PC\n");
  1006. if (!msm_cvp_fw_low_power_mode)
  1007. goto skip_core_power_check;
  1008. while (loop) {
  1009. reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
  1010. if (reg_gdsc & 0x80000000) {
  1011. usleep_range(100, 200);
  1012. loop--;
  1013. } else {
  1014. break;
  1015. }
  1016. }
  1017. if (!loop)
  1018. dprintk(CVP_ERR, "fail to power off CORE during resume\n");
  1019. skip_core_power_check:
  1020. ctrl_init_val = BIT(0);
  1021. /* RUMI: CVP_CTRL_INIT in MPTest has bit 0 and 3 set */
  1022. __write_register(device, CVP_CTRL_INIT, ctrl_init_val);
  1023. while (!(ctrl_status & CVP_CTRL_INIT_STATUS__M) && count < max_tries) {
  1024. ctrl_status = __read_register(device, CVP_CTRL_STATUS);
  1025. if ((ctrl_status & CVP_CTRL_ERROR_STATUS__M) == 0x4) {
  1026. dprintk(CVP_ERR, "invalid setting for UC_REGION\n");
  1027. rc = -ENODATA;
  1028. break;
  1029. }
  1030. /* Reduce to 50, 100 on silicon */
  1031. usleep_range(50, 100);
  1032. count++;
  1033. }
  1034. if (!(ctrl_status & CVP_CTRL_INIT_STATUS__M)) {
  1035. ctrl_init_val = __read_register(device, CVP_CTRL_INIT);
  1036. dprintk(CVP_ERR,
  1037. "Failed to boot FW status: %x %x %s\n",
  1038. ctrl_status, ctrl_init_val,
  1039. boot_states[(ctrl_status >> 9) & 0x3f]);
  1040. check_tensilica_in_reset(device);
  1041. rc = -ENODEV;
  1042. }
  1043. /* Enable interrupt before sending commands to tensilica */
  1044. __write_register(device, CVP_CPU_CS_H2XSOFTINTEN, 0x1);
  1045. __write_register(device, CVP_CPU_CS_X2RPMh, 0x0);
  1046. return rc;
  1047. }
  1048. static int iris_hfi_resume(void *dev)
  1049. {
  1050. int rc = 0;
  1051. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1052. if (!device) {
  1053. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1054. return -EINVAL;
  1055. }
  1056. dprintk(CVP_CORE, "Resuming Iris\n");
  1057. mutex_lock(&device->lock);
  1058. rc = __resume(device);
  1059. mutex_unlock(&device->lock);
  1060. return rc;
  1061. }
  1062. static int iris_hfi_suspend(void *dev)
  1063. {
  1064. int rc = 0;
  1065. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1066. if (!device) {
  1067. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1068. return -EINVAL;
  1069. } else if (!device->res->sw_power_collapsible) {
  1070. return -ENOTSUPP;
  1071. }
  1072. dprintk(CVP_CORE, "Suspending Iris\n");
  1073. mutex_lock(&device->lock);
  1074. rc = __power_collapse(device, true);
  1075. if (rc) {
  1076. dprintk(CVP_WARN, "%s: Iris is busy\n", __func__);
  1077. rc = -EBUSY;
  1078. }
  1079. mutex_unlock(&device->lock);
  1080. /* Cancel pending delayed works if any */
  1081. if (!rc)
  1082. cancel_delayed_work(&iris_hfi_pm_work);
  1083. return rc;
  1084. }
  1085. static void cvp_dump_csr(struct iris_hfi_device *dev)
  1086. {
  1087. u32 reg;
  1088. if (!dev)
  1089. return;
  1090. if (!dev->power_enabled || dev->reg_dumped)
  1091. return;
  1092. reg = __read_register(dev, CVP_WRAPPER_CPU_STATUS);
  1093. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_STATUS: %x\n", reg);
  1094. reg = __read_register(dev, CVP_CPU_CS_SCIACMDARG0);
  1095. dprintk(CVP_ERR, "CVP_CPU_CS_SCIACMDARG0: %x\n", reg);
  1096. reg = __read_register(dev, CVP_WRAPPER_INTR_STATUS);
  1097. dprintk(CVP_ERR, "CVP_WRAPPER_INTR_STATUS: %x\n", reg);
  1098. reg = __read_register(dev, CVP_CPU_CS_H2ASOFTINT);
  1099. dprintk(CVP_ERR, "CVP_CPU_CS_H2ASOFTINT: %x\n", reg);
  1100. reg = __read_register(dev, CVP_CPU_CS_A2HSOFTINT);
  1101. dprintk(CVP_ERR, "CVP_CPU_CS_A2HSOFTINT: %x\n", reg);
  1102. reg = __read_register(dev, CVP_CC_MVS1C_GDSCR);
  1103. dprintk(CVP_ERR, "CVP_CC_MVS1C_GDSCR: %x\n", reg);
  1104. reg = __read_register(dev, CVP_CC_MVS1C_CBCR);
  1105. dprintk(CVP_ERR, "CVP_CC_MVS1C_CBCR: %x\n", reg);
  1106. reg = __read_register(dev, CVP_WRAPPER_CPU_CLOCK_CONFIG);
  1107. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_CLOCK_CONFIG: %x\n", reg);
  1108. reg = __read_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  1109. dprintk(CVP_ERR, "CVP_WRAPPER_CORE_CLOCK_CONFIG: %x\n", reg);
  1110. dev->reg_dumped = true;
  1111. }
  1112. static int iris_hfi_flush_debug_queue(void *dev)
  1113. {
  1114. int rc = 0;
  1115. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1116. if (!device) {
  1117. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1118. return -EINVAL;
  1119. }
  1120. mutex_lock(&device->lock);
  1121. if (!device->power_enabled) {
  1122. dprintk(CVP_WARN, "%s: iris power off\n", __func__);
  1123. rc = -EINVAL;
  1124. goto exit;
  1125. }
  1126. cvp_dump_csr(device);
  1127. __flush_debug_queue(device, NULL);
  1128. exit:
  1129. mutex_unlock(&device->lock);
  1130. return rc;
  1131. }
  1132. static int iris_hfi_scale_clocks(void *dev, u32 freq)
  1133. {
  1134. int rc = 0;
  1135. struct iris_hfi_device *device = dev;
  1136. if (!device) {
  1137. dprintk(CVP_ERR, "Invalid args: %pK\n", device);
  1138. return -EINVAL;
  1139. }
  1140. mutex_lock(&device->lock);
  1141. if (__resume(device)) {
  1142. dprintk(CVP_ERR, "Resume from power collapse failed\n");
  1143. rc = -ENODEV;
  1144. goto exit;
  1145. }
  1146. rc = msm_cvp_set_clocks_impl(device, freq);
  1147. exit:
  1148. mutex_unlock(&device->lock);
  1149. return rc;
  1150. }
  1151. /* Writes into cmdq without raising an interrupt */
  1152. static int __iface_cmdq_write_relaxed(struct iris_hfi_device *device,
  1153. void *pkt, bool *requires_interrupt)
  1154. {
  1155. struct cvp_iface_q_info *q_info;
  1156. struct cvp_hal_cmd_pkt_hdr *cmd_packet;
  1157. int result = -E2BIG;
  1158. if (!device || !pkt) {
  1159. dprintk(CVP_ERR, "Invalid Params\n");
  1160. return -EINVAL;
  1161. }
  1162. __strict_check(device);
  1163. if (!__core_in_valid_state(device)) {
  1164. dprintk(CVP_ERR, "%s - fw not in init state\n", __func__);
  1165. result = -EINVAL;
  1166. goto err_q_null;
  1167. }
  1168. cmd_packet = (struct cvp_hal_cmd_pkt_hdr *)pkt;
  1169. device->last_packet_type = cmd_packet->packet_type;
  1170. q_info = &device->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1171. if (!q_info) {
  1172. dprintk(CVP_ERR, "cannot write to shared Q's\n");
  1173. goto err_q_null;
  1174. }
  1175. if (!q_info->q_array.align_virtual_addr) {
  1176. dprintk(CVP_ERR, "cannot write to shared CMD Q's\n");
  1177. result = -ENODATA;
  1178. goto err_q_null;
  1179. }
  1180. if (__resume(device)) {
  1181. dprintk(CVP_ERR, "%s: Power on failed\n", __func__);
  1182. goto err_q_write;
  1183. }
  1184. if (!__write_queue(q_info, (u8 *)pkt, requires_interrupt)) {
  1185. if (device->res->sw_power_collapsible) {
  1186. cancel_delayed_work(&iris_hfi_pm_work);
  1187. if (!queue_delayed_work(device->iris_pm_workq,
  1188. &iris_hfi_pm_work,
  1189. msecs_to_jiffies(
  1190. device->res->msm_cvp_pwr_collapse_delay))) {
  1191. dprintk(CVP_PWR,
  1192. "PM work already scheduled\n");
  1193. }
  1194. }
  1195. result = 0;
  1196. } else {
  1197. dprintk(CVP_ERR, "__iface_cmdq_write: queue full\n");
  1198. }
  1199. err_q_write:
  1200. err_q_null:
  1201. return result;
  1202. }
  1203. static int __iface_cmdq_write(struct iris_hfi_device *device, void *pkt)
  1204. {
  1205. bool needs_interrupt = false;
  1206. int rc = __iface_cmdq_write_relaxed(device, pkt, &needs_interrupt);
  1207. if (!rc && needs_interrupt) {
  1208. /* Consumer of cmdq prefers that we raise an interrupt */
  1209. rc = 0;
  1210. if (!__is_ctl_power_on(device))
  1211. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1212. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1213. }
  1214. return rc;
  1215. }
  1216. static int __iface_msgq_read(struct iris_hfi_device *device, void *pkt)
  1217. {
  1218. u32 tx_req_is_set = 0;
  1219. int rc = 0;
  1220. struct cvp_iface_q_info *q_info;
  1221. if (!pkt) {
  1222. dprintk(CVP_ERR, "Invalid Params\n");
  1223. return -EINVAL;
  1224. }
  1225. __strict_check(device);
  1226. if (!__core_in_valid_state(device)) {
  1227. dprintk(CVP_WARN, "%s - fw not in init state\n", __func__);
  1228. rc = -EINVAL;
  1229. goto read_error_null;
  1230. }
  1231. q_info = &device->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1232. if (q_info->q_array.align_virtual_addr == NULL) {
  1233. dprintk(CVP_ERR, "cannot read from shared MSG Q's\n");
  1234. rc = -ENODATA;
  1235. goto read_error_null;
  1236. }
  1237. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1238. if (tx_req_is_set) {
  1239. if (!__is_ctl_power_on(device))
  1240. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1241. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1242. }
  1243. rc = 0;
  1244. } else
  1245. rc = -ENODATA;
  1246. read_error_null:
  1247. return rc;
  1248. }
  1249. static int __iface_dbgq_read(struct iris_hfi_device *device, void *pkt)
  1250. {
  1251. u32 tx_req_is_set = 0;
  1252. int rc = 0;
  1253. struct cvp_iface_q_info *q_info;
  1254. if (!pkt) {
  1255. dprintk(CVP_ERR, "Invalid Params\n");
  1256. return -EINVAL;
  1257. }
  1258. __strict_check(device);
  1259. q_info = &device->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1260. if (q_info->q_array.align_virtual_addr == NULL) {
  1261. dprintk(CVP_ERR, "cannot read from shared DBG Q's\n");
  1262. rc = -ENODATA;
  1263. goto dbg_error_null;
  1264. }
  1265. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1266. if (tx_req_is_set) {
  1267. if (!__is_ctl_power_on(device))
  1268. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1269. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1270. }
  1271. rc = 0;
  1272. } else
  1273. rc = -ENODATA;
  1274. dbg_error_null:
  1275. return rc;
  1276. }
  1277. static void __set_queue_hdr_defaults(struct cvp_hfi_queue_header *q_hdr)
  1278. {
  1279. q_hdr->qhdr_status = 0x1;
  1280. q_hdr->qhdr_type = CVP_IFACEQ_DFLT_QHDR;
  1281. q_hdr->qhdr_q_size = CVP_IFACEQ_QUEUE_SIZE / 4;
  1282. q_hdr->qhdr_pkt_size = 0;
  1283. q_hdr->qhdr_rx_wm = 0x1;
  1284. q_hdr->qhdr_tx_wm = 0x1;
  1285. q_hdr->qhdr_rx_req = 0x1;
  1286. q_hdr->qhdr_tx_req = 0x0;
  1287. q_hdr->qhdr_rx_irq_status = 0x0;
  1288. q_hdr->qhdr_tx_irq_status = 0x0;
  1289. q_hdr->qhdr_read_idx = 0x0;
  1290. q_hdr->qhdr_write_idx = 0x0;
  1291. }
  1292. /*
  1293. *Unused, keep for reference
  1294. */
  1295. /*
  1296. static void __interface_dsp_queues_release(struct iris_hfi_device *device)
  1297. {
  1298. int i;
  1299. struct msm_cvp_smem *mem_data = &device->dsp_iface_q_table.mem_data;
  1300. struct context_bank_info *cb = mem_data->mapping_info.cb_info;
  1301. if (!device->dsp_iface_q_table.align_virtual_addr) {
  1302. dprintk(CVP_ERR, "%s: already released\n", __func__);
  1303. return;
  1304. }
  1305. dma_unmap_single_attrs(cb->dev, mem_data->device_addr,
  1306. mem_data->size, DMA_BIDIRECTIONAL, 0);
  1307. dma_free_coherent(device->res->mem_cdsp.dev, mem_data->size,
  1308. mem_data->kvaddr, mem_data->dma_handle);
  1309. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1310. device->dsp_iface_queues[i].q_hdr = NULL;
  1311. device->dsp_iface_queues[i].q_array.align_virtual_addr = NULL;
  1312. device->dsp_iface_queues[i].q_array.align_device_addr = 0;
  1313. }
  1314. device->dsp_iface_q_table.align_virtual_addr = NULL;
  1315. device->dsp_iface_q_table.align_device_addr = 0;
  1316. }
  1317. */
  1318. static int __interface_dsp_queues_init(struct iris_hfi_device *dev)
  1319. {
  1320. int rc = 0;
  1321. u32 i;
  1322. struct cvp_iface_q_info *iface_q;
  1323. int offset = 0;
  1324. phys_addr_t fw_bias = 0;
  1325. size_t q_size;
  1326. struct msm_cvp_smem *mem_data;
  1327. void *kvaddr;
  1328. dma_addr_t dma_handle;
  1329. dma_addr_t iova;
  1330. struct context_bank_info *cb;
  1331. q_size = ALIGN(QUEUE_SIZE, SZ_1M);
  1332. mem_data = &dev->dsp_iface_q_table.mem_data;
  1333. if (mem_data->kvaddr) {
  1334. memset((void *)mem_data->kvaddr, 0, q_size);
  1335. cvp_dsp_init_hfi_queue_hdr(dev);
  1336. return 0;
  1337. }
  1338. /* Allocate dsp queues from CDSP device memory */
  1339. kvaddr = dma_alloc_coherent(dev->res->mem_cdsp.dev, q_size,
  1340. &dma_handle, GFP_KERNEL);
  1341. if (IS_ERR_OR_NULL(kvaddr)) {
  1342. dprintk(CVP_ERR, "%s: failed dma allocation\n", __func__);
  1343. goto fail_dma_alloc;
  1344. }
  1345. cb = msm_cvp_smem_get_context_bank(dev->res, SMEM_CDSP);
  1346. if (!cb) {
  1347. dprintk(CVP_ERR,
  1348. "%s: failed to get DSP context bank\n", __func__);
  1349. goto fail_dma_map;
  1350. }
  1351. iova = dma_map_single_attrs(cb->dev, phys_to_virt(dma_handle),
  1352. q_size, DMA_BIDIRECTIONAL, 0);
  1353. if (dma_mapping_error(cb->dev, iova)) {
  1354. dprintk(CVP_ERR, "%s: failed dma mapping\n", __func__);
  1355. goto fail_dma_map;
  1356. }
  1357. dprintk(CVP_DSP,
  1358. "%s: kvaddr %pK dma_handle %#llx iova %#llx size %zd\n",
  1359. __func__, kvaddr, dma_handle, iova, q_size);
  1360. memset(mem_data, 0, sizeof(struct msm_cvp_smem));
  1361. mem_data->kvaddr = kvaddr;
  1362. mem_data->device_addr = iova;
  1363. mem_data->dma_handle = dma_handle;
  1364. mem_data->size = q_size;
  1365. mem_data->mapping_info.cb_info = cb;
  1366. if (!is_iommu_present(dev->res))
  1367. fw_bias = dev->cvp_hal_data->firmware_base;
  1368. dev->dsp_iface_q_table.align_virtual_addr = kvaddr;
  1369. dev->dsp_iface_q_table.align_device_addr = iova - fw_bias;
  1370. dev->dsp_iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1371. offset = dev->dsp_iface_q_table.mem_size;
  1372. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1373. iface_q = &dev->dsp_iface_queues[i];
  1374. iface_q->q_array.align_device_addr = iova + offset - fw_bias;
  1375. iface_q->q_array.align_virtual_addr = kvaddr + offset;
  1376. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1377. offset += iface_q->q_array.mem_size;
  1378. spin_lock_init(&iface_q->hfi_lock);
  1379. }
  1380. cvp_dsp_init_hfi_queue_hdr(dev);
  1381. return rc;
  1382. fail_dma_map:
  1383. dma_free_coherent(dev->res->mem_cdsp.dev, q_size, kvaddr, dma_handle);
  1384. fail_dma_alloc:
  1385. return -ENOMEM;
  1386. }
  1387. static void __interface_queues_release(struct iris_hfi_device *device)
  1388. {
  1389. #ifdef CONFIG_EVA_TVM
  1390. int i;
  1391. struct cvp_hfi_mem_map_table *qdss;
  1392. struct cvp_hfi_mem_map *mem_map;
  1393. int num_entries = device->res->qdss_addr_set.count;
  1394. unsigned long mem_map_table_base_addr;
  1395. struct context_bank_info *cb;
  1396. if (device->qdss.align_virtual_addr) {
  1397. qdss = (struct cvp_hfi_mem_map_table *)
  1398. device->qdss.align_virtual_addr;
  1399. qdss->mem_map_num_entries = num_entries;
  1400. mem_map_table_base_addr =
  1401. device->qdss.align_device_addr +
  1402. sizeof(struct cvp_hfi_mem_map_table);
  1403. qdss->mem_map_table_base_addr =
  1404. (u32)mem_map_table_base_addr;
  1405. if ((unsigned long)qdss->mem_map_table_base_addr !=
  1406. mem_map_table_base_addr) {
  1407. dprintk(CVP_ERR,
  1408. "Invalid mem_map_table_base_addr %#lx",
  1409. mem_map_table_base_addr);
  1410. }
  1411. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1412. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1413. for (i = 0; cb && i < num_entries; i++) {
  1414. iommu_unmap(cb->domain,
  1415. mem_map[i].virtual_addr,
  1416. mem_map[i].size);
  1417. }
  1418. __smem_free(device, &device->qdss.mem_data);
  1419. }
  1420. __smem_free(device, &device->iface_q_table.mem_data);
  1421. __smem_free(device, &device->sfr.mem_data);
  1422. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1423. device->iface_queues[i].q_hdr = NULL;
  1424. device->iface_queues[i].q_array.align_virtual_addr = NULL;
  1425. device->iface_queues[i].q_array.align_device_addr = 0;
  1426. }
  1427. device->iface_q_table.align_virtual_addr = NULL;
  1428. device->iface_q_table.align_device_addr = 0;
  1429. device->qdss.align_virtual_addr = NULL;
  1430. device->qdss.align_device_addr = 0;
  1431. device->sfr.align_virtual_addr = NULL;
  1432. device->sfr.align_device_addr = 0;
  1433. device->mem_addr.align_virtual_addr = NULL;
  1434. device->mem_addr.align_device_addr = 0;
  1435. #endif
  1436. }
  1437. static int __get_qdss_iommu_virtual_addr(struct iris_hfi_device *dev,
  1438. struct cvp_hfi_mem_map *mem_map,
  1439. struct iommu_domain *domain)
  1440. {
  1441. int i;
  1442. int rc = 0;
  1443. dma_addr_t iova = QDSS_IOVA_START;
  1444. int num_entries = dev->res->qdss_addr_set.count;
  1445. struct addr_range *qdss_addr_tbl = dev->res->qdss_addr_set.addr_tbl;
  1446. if (!num_entries)
  1447. return -ENODATA;
  1448. for (i = 0; i < num_entries; i++) {
  1449. if (domain) {
  1450. rc = iommu_map(domain, iova,
  1451. qdss_addr_tbl[i].start,
  1452. qdss_addr_tbl[i].size,
  1453. IOMMU_READ | IOMMU_WRITE);
  1454. if (rc) {
  1455. dprintk(CVP_ERR,
  1456. "IOMMU QDSS mapping failed for addr %#x\n",
  1457. qdss_addr_tbl[i].start);
  1458. rc = -ENOMEM;
  1459. break;
  1460. }
  1461. } else {
  1462. iova = qdss_addr_tbl[i].start;
  1463. }
  1464. mem_map[i].virtual_addr = (u32)iova;
  1465. mem_map[i].physical_addr = qdss_addr_tbl[i].start;
  1466. mem_map[i].size = qdss_addr_tbl[i].size;
  1467. mem_map[i].attr = 0x0;
  1468. iova += mem_map[i].size;
  1469. }
  1470. if (i < num_entries) {
  1471. dprintk(CVP_ERR,
  1472. "QDSS mapping failed, Freeing other entries %d\n", i);
  1473. for (--i; domain && i >= 0; i--) {
  1474. iommu_unmap(domain,
  1475. mem_map[i].virtual_addr,
  1476. mem_map[i].size);
  1477. }
  1478. }
  1479. return rc;
  1480. }
  1481. static void __setup_ucregion_memory_map(struct iris_hfi_device *device)
  1482. {
  1483. __write_register(device, CVP_UC_REGION_ADDR,
  1484. (u32)device->iface_q_table.align_device_addr);
  1485. __write_register(device, CVP_UC_REGION_SIZE, SHARED_QSIZE);
  1486. __write_register(device, CVP_QTBL_ADDR,
  1487. (u32)device->iface_q_table.align_device_addr);
  1488. __write_register(device, CVP_QTBL_INFO, 0x01);
  1489. if (device->sfr.align_device_addr)
  1490. __write_register(device, CVP_SFR_ADDR,
  1491. (u32)device->sfr.align_device_addr);
  1492. if (device->qdss.align_device_addr)
  1493. __write_register(device, CVP_MMAP_ADDR,
  1494. (u32)device->qdss.align_device_addr);
  1495. call_iris_op(device, setup_dsp_uc_memmap, device);
  1496. }
  1497. static void __hfi_queue_init(struct iris_hfi_device *dev)
  1498. {
  1499. int i, offset = 0;
  1500. struct cvp_hfi_queue_table_header *q_tbl_hdr;
  1501. struct cvp_iface_q_info *iface_q;
  1502. struct cvp_hfi_queue_header *q_hdr;
  1503. if (!dev)
  1504. return;
  1505. offset += dev->iface_q_table.mem_size;
  1506. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1507. iface_q = &dev->iface_queues[i];
  1508. iface_q->q_array.align_device_addr =
  1509. dev->iface_q_table.align_device_addr + offset;
  1510. iface_q->q_array.align_virtual_addr =
  1511. dev->iface_q_table.align_virtual_addr + offset;
  1512. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1513. offset += iface_q->q_array.mem_size;
  1514. iface_q->q_hdr = CVP_IFACEQ_GET_QHDR_START_ADDR(
  1515. dev->iface_q_table.align_virtual_addr, i);
  1516. __set_queue_hdr_defaults(iface_q->q_hdr);
  1517. spin_lock_init(&iface_q->hfi_lock);
  1518. }
  1519. q_tbl_hdr = (struct cvp_hfi_queue_table_header *)
  1520. dev->iface_q_table.align_virtual_addr;
  1521. q_tbl_hdr->qtbl_version = 0;
  1522. q_tbl_hdr->device_addr = (void *)dev;
  1523. strlcpy(q_tbl_hdr->name, "msm_cvp", sizeof(q_tbl_hdr->name));
  1524. q_tbl_hdr->qtbl_size = CVP_IFACEQ_TABLE_SIZE;
  1525. q_tbl_hdr->qtbl_qhdr0_offset =
  1526. sizeof(struct cvp_hfi_queue_table_header);
  1527. q_tbl_hdr->qtbl_qhdr_size = sizeof(struct cvp_hfi_queue_header);
  1528. q_tbl_hdr->qtbl_num_q = CVP_IFACEQ_NUMQ;
  1529. q_tbl_hdr->qtbl_num_active_q = CVP_IFACEQ_NUMQ;
  1530. iface_q = &dev->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1531. q_hdr = iface_q->q_hdr;
  1532. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1533. q_hdr->qhdr_type |= HFI_Q_ID_HOST_TO_CTRL_CMD_Q;
  1534. iface_q = &dev->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1535. q_hdr = iface_q->q_hdr;
  1536. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1537. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_MSG_Q;
  1538. iface_q = &dev->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1539. q_hdr = iface_q->q_hdr;
  1540. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1541. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q;
  1542. /*
  1543. * Set receive request to zero on debug queue as there is no
  1544. * need of interrupt from cvp hardware for debug messages
  1545. */
  1546. q_hdr->qhdr_rx_req = 0;
  1547. }
  1548. static void __sfr_init(struct iris_hfi_device *dev)
  1549. {
  1550. struct cvp_hfi_sfr_struct *vsfr;
  1551. if (!dev)
  1552. return;
  1553. vsfr = (struct cvp_hfi_sfr_struct *) dev->sfr.align_virtual_addr;
  1554. if (vsfr)
  1555. vsfr->bufSize = ALIGNED_SFR_SIZE;
  1556. }
  1557. static int __interface_queues_init(struct iris_hfi_device *dev)
  1558. {
  1559. int rc = 0;
  1560. struct cvp_hfi_mem_map_table *qdss;
  1561. struct cvp_hfi_mem_map *mem_map;
  1562. struct cvp_mem_addr *mem_addr;
  1563. int num_entries = dev->res->qdss_addr_set.count;
  1564. phys_addr_t fw_bias = 0;
  1565. size_t q_size;
  1566. unsigned long mem_map_table_base_addr;
  1567. struct context_bank_info *cb;
  1568. q_size = SHARED_QSIZE - ALIGNED_SFR_SIZE - ALIGNED_QDSS_SIZE;
  1569. mem_addr = &dev->mem_addr;
  1570. if (!is_iommu_present(dev->res))
  1571. fw_bias = dev->cvp_hal_data->firmware_base;
  1572. if (dev->iface_q_table.align_virtual_addr) {
  1573. memset((void *)dev->iface_q_table.align_virtual_addr,
  1574. 0, q_size);
  1575. goto hfi_queue_init;
  1576. }
  1577. rc = __smem_alloc(dev, mem_addr, q_size, 1, SMEM_UNCACHED);
  1578. if (rc) {
  1579. dprintk(CVP_ERR, "iface_q_table_alloc_fail\n");
  1580. goto fail_alloc_queue;
  1581. }
  1582. dev->iface_q_table.align_virtual_addr = mem_addr->align_virtual_addr;
  1583. dev->iface_q_table.align_device_addr = mem_addr->align_device_addr -
  1584. fw_bias;
  1585. dev->iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1586. dev->iface_q_table.mem_data = mem_addr->mem_data;
  1587. hfi_queue_init:
  1588. __hfi_queue_init(dev);
  1589. if (dev->sfr.align_virtual_addr) {
  1590. memset((void *)dev->sfr.align_virtual_addr,
  1591. 0, ALIGNED_SFR_SIZE);
  1592. goto sfr_init;
  1593. }
  1594. rc = __smem_alloc(dev, mem_addr, ALIGNED_SFR_SIZE, 1, SMEM_UNCACHED);
  1595. if (rc) {
  1596. dprintk(CVP_WARN, "sfr_alloc_fail: SFR not will work\n");
  1597. dev->sfr.align_device_addr = 0;
  1598. } else {
  1599. dev->sfr.align_device_addr = mem_addr->align_device_addr -
  1600. fw_bias;
  1601. dev->sfr.align_virtual_addr = mem_addr->align_virtual_addr;
  1602. dev->sfr.mem_size = ALIGNED_SFR_SIZE;
  1603. dev->sfr.mem_data = mem_addr->mem_data;
  1604. }
  1605. sfr_init:
  1606. __sfr_init(dev);
  1607. if (dev->qdss.align_virtual_addr)
  1608. goto dsp_hfi_queue_init;
  1609. if ((msm_cvp_fw_debug_mode & HFI_DEBUG_MODE_QDSS) && num_entries) {
  1610. rc = __smem_alloc(dev, mem_addr, ALIGNED_QDSS_SIZE, 1,
  1611. SMEM_UNCACHED);
  1612. if (rc) {
  1613. dprintk(CVP_WARN,
  1614. "qdss_alloc_fail: QDSS messages logging will not work\n");
  1615. dev->qdss.align_device_addr = 0;
  1616. } else {
  1617. dev->qdss.align_device_addr =
  1618. mem_addr->align_device_addr - fw_bias;
  1619. dev->qdss.align_virtual_addr =
  1620. mem_addr->align_virtual_addr;
  1621. dev->qdss.mem_size = ALIGNED_QDSS_SIZE;
  1622. dev->qdss.mem_data = mem_addr->mem_data;
  1623. }
  1624. }
  1625. if (dev->qdss.align_virtual_addr) {
  1626. qdss =
  1627. (struct cvp_hfi_mem_map_table *)dev->qdss.align_virtual_addr;
  1628. qdss->mem_map_num_entries = num_entries;
  1629. mem_map_table_base_addr = dev->qdss.align_device_addr +
  1630. sizeof(struct cvp_hfi_mem_map_table);
  1631. qdss->mem_map_table_base_addr = mem_map_table_base_addr;
  1632. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1633. cb = msm_cvp_smem_get_context_bank(dev->res, 0);
  1634. if (!cb) {
  1635. dprintk(CVP_ERR,
  1636. "%s: failed to get context bank\n", __func__);
  1637. return -EINVAL;
  1638. }
  1639. rc = __get_qdss_iommu_virtual_addr(dev, mem_map, cb->domain);
  1640. if (rc) {
  1641. dprintk(CVP_ERR,
  1642. "IOMMU mapping failed, Freeing qdss memdata\n");
  1643. __smem_free(dev, &dev->qdss.mem_data);
  1644. dev->qdss.align_virtual_addr = NULL;
  1645. dev->qdss.align_device_addr = 0;
  1646. }
  1647. }
  1648. dsp_hfi_queue_init:
  1649. rc = __interface_dsp_queues_init(dev);
  1650. if (rc) {
  1651. dprintk(CVP_ERR, "dsp_queues_init failed\n");
  1652. goto fail_alloc_queue;
  1653. }
  1654. __setup_ucregion_memory_map(dev);
  1655. return 0;
  1656. fail_alloc_queue:
  1657. return -ENOMEM;
  1658. }
  1659. static int __sys_set_debug(struct iris_hfi_device *device, u32 debug)
  1660. {
  1661. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1662. int rc = 0;
  1663. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1664. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1665. rc = call_hfi_pkt_op(device, sys_debug_config, pkt, debug);
  1666. if (rc) {
  1667. dprintk(CVP_WARN,
  1668. "Debug mode setting to FW failed\n");
  1669. return -ENOTEMPTY;
  1670. }
  1671. if (__iface_cmdq_write(device, pkt))
  1672. return -ENOTEMPTY;
  1673. return 0;
  1674. }
  1675. static int __sys_set_idle_indicator(struct iris_hfi_device *device,
  1676. bool enable)
  1677. {
  1678. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1679. int rc = 0;
  1680. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1681. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1682. rc = call_hfi_pkt_op(device, sys_set_idle_indicator, pkt, enable);
  1683. if (__iface_cmdq_write(device, pkt))
  1684. return -ENOTEMPTY;
  1685. return 0;
  1686. }
  1687. static int __sys_set_coverage(struct iris_hfi_device *device, u32 mode)
  1688. {
  1689. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1690. int rc = 0;
  1691. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1692. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1693. rc = call_hfi_pkt_op(device, sys_coverage_config,
  1694. pkt, mode);
  1695. if (rc) {
  1696. dprintk(CVP_WARN,
  1697. "Coverage mode setting to FW failed\n");
  1698. return -ENOTEMPTY;
  1699. }
  1700. if (__iface_cmdq_write(device, pkt)) {
  1701. dprintk(CVP_WARN, "Failed to send coverage pkt to f/w\n");
  1702. return -ENOTEMPTY;
  1703. }
  1704. return 0;
  1705. }
  1706. static int __sys_set_power_control(struct iris_hfi_device *device,
  1707. bool enable)
  1708. {
  1709. struct regulator_info *rinfo;
  1710. bool supported = false;
  1711. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1712. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1713. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1714. iris_hfi_for_each_regulator(device, rinfo) {
  1715. if (rinfo->has_hw_power_collapse) {
  1716. supported = true;
  1717. break;
  1718. }
  1719. }
  1720. if (!supported)
  1721. return 0;
  1722. call_hfi_pkt_op(device, sys_power_control, pkt, enable);
  1723. if (__iface_cmdq_write(device, pkt))
  1724. return -ENOTEMPTY;
  1725. return 0;
  1726. }
  1727. static void cvp_pm_qos_update(struct iris_hfi_device *device, bool vote_on)
  1728. {
  1729. u32 latency, off_vote_cnt;
  1730. int i, err = 0;
  1731. spin_lock(&device->res->pm_qos.lock);
  1732. off_vote_cnt = device->res->pm_qos.off_vote_cnt;
  1733. spin_unlock(&device->res->pm_qos.lock);
  1734. if (vote_on && off_vote_cnt)
  1735. return;
  1736. latency = vote_on ? device->res->pm_qos.latency_us :
  1737. PM_QOS_RESUME_LATENCY_DEFAULT_VALUE;
  1738. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  1739. for (i = 0; i < device->res->pm_qos.silver_count; i++) {
  1740. if (!cpu_possible(device->res->pm_qos.silver_cores[i]))
  1741. continue;
  1742. err = dev_pm_qos_update_request(
  1743. &device->res->pm_qos.pm_qos_hdls[i],
  1744. latency);
  1745. if (err < 0) {
  1746. if (vote_on) {
  1747. dprintk(CVP_WARN,
  1748. "pm qos on failed %d\n", err);
  1749. } else {
  1750. dprintk(CVP_WARN,
  1751. "pm qos off failed %d\n", err);
  1752. }
  1753. }
  1754. }
  1755. }
  1756. static int iris_pm_qos_update(void *device)
  1757. {
  1758. struct iris_hfi_device *dev;
  1759. if (!device) {
  1760. dprintk(CVP_ERR, "%s Invalid device\n", __func__);
  1761. return -ENODEV;
  1762. }
  1763. dev = device;
  1764. mutex_lock(&dev->lock);
  1765. cvp_pm_qos_update(dev, true);
  1766. mutex_unlock(&dev->lock);
  1767. return 0;
  1768. }
  1769. static int __hwfence_regs_map(struct iris_hfi_device *device)
  1770. {
  1771. int rc = 0;
  1772. struct context_bank_info *cb;
  1773. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1774. if (!cb) {
  1775. dprintk(CVP_ERR, "%s: fail to get cb\n", __func__);
  1776. return -EINVAL;
  1777. }
  1778. if (device->res->reg_mappings.ipclite_phyaddr != 0) {
  1779. rc = iommu_map(cb->domain,
  1780. device->res->reg_mappings.ipclite_iova,
  1781. device->res->reg_mappings.ipclite_phyaddr,
  1782. device->res->reg_mappings.ipclite_size,
  1783. IOMMU_READ | IOMMU_WRITE);
  1784. if (rc) {
  1785. dprintk(CVP_ERR, "map ipclite fail %d %#x %#x %#x\n",
  1786. rc, device->res->reg_mappings.ipclite_iova,
  1787. device->res->reg_mappings.ipclite_phyaddr,
  1788. device->res->reg_mappings.ipclite_size);
  1789. return rc;
  1790. }
  1791. }
  1792. if (device->res->reg_mappings.hwmutex_phyaddr != 0) {
  1793. rc = iommu_map(cb->domain,
  1794. device->res->reg_mappings.hwmutex_iova,
  1795. device->res->reg_mappings.hwmutex_phyaddr,
  1796. device->res->reg_mappings.hwmutex_size,
  1797. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1798. if (rc) {
  1799. dprintk(CVP_ERR, "map hwmutex fail %d %#x %#x %#x\n",
  1800. rc, device->res->reg_mappings.hwmutex_iova,
  1801. device->res->reg_mappings.hwmutex_phyaddr,
  1802. device->res->reg_mappings.hwmutex_size);
  1803. return rc;
  1804. }
  1805. }
  1806. if (device->res->reg_mappings.aon_phyaddr != 0) {
  1807. rc = iommu_map(cb->domain,
  1808. device->res->reg_mappings.aon_iova,
  1809. device->res->reg_mappings.aon_phyaddr,
  1810. device->res->reg_mappings.aon_size,
  1811. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1812. if (rc) {
  1813. dprintk(CVP_ERR, "map aon fail %d %#x %#x %#x\n",
  1814. rc, device->res->reg_mappings.aon_iova,
  1815. device->res->reg_mappings.aon_phyaddr,
  1816. device->res->reg_mappings.aon_size);
  1817. return rc;
  1818. }
  1819. }
  1820. if (device->res->reg_mappings.timer_phyaddr != 0) {
  1821. rc = iommu_map(cb->domain,
  1822. device->res->reg_mappings.timer_iova,
  1823. device->res->reg_mappings.timer_phyaddr,
  1824. device->res->reg_mappings.timer_size,
  1825. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1826. if (rc) {
  1827. dprintk(CVP_ERR, "map timer fail %d %#x %#x %#x\n",
  1828. rc, device->res->reg_mappings.timer_iova,
  1829. device->res->reg_mappings.timer_phyaddr,
  1830. device->res->reg_mappings.timer_size);
  1831. return rc;
  1832. }
  1833. }
  1834. return rc;
  1835. }
  1836. static int __hwfence_regs_unmap(struct iris_hfi_device *device)
  1837. {
  1838. int rc = 0;
  1839. struct context_bank_info *cb;
  1840. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1841. if (!cb) {
  1842. dprintk(CVP_ERR, "%s: fail to get cb\n", __func__);
  1843. return -EINVAL;
  1844. }
  1845. if (device->res->reg_mappings.ipclite_iova != 0) {
  1846. iommu_unmap(cb->domain,
  1847. device->res->reg_mappings.ipclite_iova,
  1848. device->res->reg_mappings.ipclite_size);
  1849. }
  1850. if (device->res->reg_mappings.hwmutex_iova != 0) {
  1851. iommu_unmap(cb->domain,
  1852. device->res->reg_mappings.hwmutex_iova,
  1853. device->res->reg_mappings.hwmutex_size);
  1854. }
  1855. if (device->res->reg_mappings.aon_iova != 0) {
  1856. iommu_unmap(cb->domain,
  1857. device->res->reg_mappings.aon_iova,
  1858. device->res->reg_mappings.aon_size);
  1859. }
  1860. if (device->res->reg_mappings.timer_iova != 0) {
  1861. iommu_unmap(cb->domain,
  1862. device->res->reg_mappings.timer_iova,
  1863. device->res->reg_mappings.timer_size);
  1864. }
  1865. return rc;
  1866. }
  1867. static int iris_hfi_core_init(void *device)
  1868. {
  1869. int rc = 0;
  1870. u32 ipcc_iova;
  1871. struct cvp_hfi_cmd_sys_init_packet pkt;
  1872. struct cvp_hfi_cmd_sys_get_property_packet version_pkt;
  1873. struct iris_hfi_device *dev;
  1874. if (!device) {
  1875. dprintk(CVP_ERR, "Invalid device\n");
  1876. return -ENODEV;
  1877. }
  1878. dev = device;
  1879. dprintk(CVP_CORE, "Core initializing\n");
  1880. pm_stay_awake(dev->res->pdev->dev.parent);
  1881. mutex_lock(&dev->lock);
  1882. dev->bus_vote.data =
  1883. kzalloc(sizeof(struct cvp_bus_vote_data), GFP_KERNEL);
  1884. if (!dev->bus_vote.data) {
  1885. dprintk(CVP_ERR, "Bus vote data memory is not allocated\n");
  1886. rc = -ENOMEM;
  1887. goto err_no_mem;
  1888. }
  1889. dev->bus_vote.data_count = 1;
  1890. dev->bus_vote.data->power_mode = CVP_POWER_TURBO;
  1891. __hwfence_regs_map(dev);
  1892. rc = __power_on_init(dev);
  1893. if (rc) {
  1894. dprintk(CVP_ERR, "Failed to power on init EVA\n");
  1895. goto err_load_fw;
  1896. }
  1897. rc = cvp_synx_recover();
  1898. if (rc) {
  1899. dprintk(CVP_ERR, "Failed to recover synx\n");
  1900. goto err_core_init;
  1901. }
  1902. /* mmrm registration */
  1903. if (msm_cvp_mmrm_enabled) {
  1904. rc = msm_cvp_mmrm_register(device);
  1905. if (rc) {
  1906. dprintk(CVP_ERR, "Failed to register mmrm client\n");
  1907. goto err_core_init;
  1908. }
  1909. }
  1910. __set_state(dev, IRIS_STATE_INIT);
  1911. dev->reg_dumped = false;
  1912. dprintk(CVP_CORE, "Dev_Virt: %pa, Reg_Virt: %pK\n",
  1913. &dev->cvp_hal_data->firmware_base,
  1914. dev->cvp_hal_data->register_base);
  1915. rc = __interface_queues_init(dev);
  1916. if (rc) {
  1917. dprintk(CVP_ERR, "failed to init queues\n");
  1918. rc = -ENOMEM;
  1919. goto err_core_init;
  1920. }
  1921. cvp_register_va_md_region();
  1922. // Add node for dev struct
  1923. add_va_node_to_list(CVP_QUEUE_DUMP, dev,
  1924. sizeof(struct iris_hfi_device),
  1925. "iris_hfi_device-dev", false);
  1926. add_queue_header_to_va_md_list((void*)dev);
  1927. add_hfi_queue_to_va_md_list((void*)dev);
  1928. rc = msm_cvp_map_ipcc_regs(&ipcc_iova);
  1929. if (!rc) {
  1930. dprintk(CVP_CORE, "IPCC iova 0x%x\n", ipcc_iova);
  1931. __write_register(dev, CVP_MMAP_ADDR, ipcc_iova);
  1932. }
  1933. rc = __load_fw(dev);
  1934. if (rc) {
  1935. dprintk(CVP_ERR, "Failed to load Iris FW\n");
  1936. goto err_core_init;
  1937. }
  1938. rc = __boot_firmware(dev);
  1939. if (rc) {
  1940. dprintk(CVP_ERR, "Failed to start core\n");
  1941. rc = -ENODEV;
  1942. goto err_core_init;
  1943. }
  1944. dev->version = __read_register(dev, CVP_VERSION_INFO);
  1945. rc = call_hfi_pkt_op(dev, sys_init, &pkt, 0);
  1946. if (rc) {
  1947. dprintk(CVP_ERR, "Failed to create sys init pkt\n");
  1948. goto err_core_init;
  1949. }
  1950. if (__iface_cmdq_write(dev, &pkt)) {
  1951. rc = -ENOTEMPTY;
  1952. goto err_core_init;
  1953. }
  1954. rc = call_hfi_pkt_op(dev, sys_image_version, &version_pkt);
  1955. if (rc || __iface_cmdq_write(dev, &version_pkt))
  1956. dprintk(CVP_WARN, "Failed to send image version pkt to f/w\n");
  1957. __sys_set_debug(device, msm_cvp_fw_debug);
  1958. __enable_subcaches(device);
  1959. __set_subcaches(device);
  1960. __set_ubwc_config(device);
  1961. __sys_set_idle_indicator(device, true);
  1962. if (dev->res->pm_qos.latency_us) {
  1963. int err = 0;
  1964. u32 i, cpu;
  1965. dev->res->pm_qos.pm_qos_hdls = kcalloc(
  1966. dev->res->pm_qos.silver_count,
  1967. sizeof(struct dev_pm_qos_request),
  1968. GFP_KERNEL);
  1969. if (!dev->res->pm_qos.pm_qos_hdls) {
  1970. dprintk(CVP_WARN, "Failed allocate pm_qos_hdls\n");
  1971. goto pm_qos_bail;
  1972. }
  1973. for (i = 0; i < dev->res->pm_qos.silver_count; i++) {
  1974. cpu = dev->res->pm_qos.silver_cores[i];
  1975. if (!cpu_possible(cpu))
  1976. continue;
  1977. err = dev_pm_qos_add_request(
  1978. get_cpu_device(cpu),
  1979. &dev->res->pm_qos.pm_qos_hdls[i],
  1980. DEV_PM_QOS_RESUME_LATENCY,
  1981. dev->res->pm_qos.latency_us);
  1982. if (err < 0)
  1983. dprintk(CVP_WARN,
  1984. "%s pm_qos_add_req %d failed\n",
  1985. __func__, i);
  1986. }
  1987. }
  1988. pm_qos_bail:
  1989. mutex_unlock(&dev->lock);
  1990. cvp_dsp_send_hfi_queue();
  1991. pm_relax(dev->res->pdev->dev.parent);
  1992. dprintk(CVP_CORE, "Core inited successfully\n");
  1993. return 0;
  1994. err_core_init:
  1995. __set_state(dev, IRIS_STATE_DEINIT);
  1996. __unload_fw(dev);
  1997. if (dev->mmrm_cvp)
  1998. {
  1999. msm_cvp_mmrm_deregister(dev);
  2000. }
  2001. err_load_fw:
  2002. __hwfence_regs_unmap(dev);
  2003. err_no_mem:
  2004. dprintk(CVP_ERR, "Core init failed\n");
  2005. mutex_unlock(&dev->lock);
  2006. pm_relax(dev->res->pdev->dev.parent);
  2007. return rc;
  2008. }
  2009. static int iris_hfi_core_release(void *dev)
  2010. {
  2011. int rc = 0, i;
  2012. struct iris_hfi_device *device = dev;
  2013. struct cvp_hal_session *session, *next;
  2014. struct dev_pm_qos_request *qos_hdl;
  2015. u32 ipcc_iova;
  2016. if (!device) {
  2017. dprintk(CVP_ERR, "invalid device\n");
  2018. return -ENODEV;
  2019. }
  2020. mutex_lock(&device->lock);
  2021. dprintk(CVP_WARN, "Core releasing\n");
  2022. if (device->res->pm_qos.latency_us &&
  2023. device->res->pm_qos.pm_qos_hdls) {
  2024. for (i = 0; i < device->res->pm_qos.silver_count; i++) {
  2025. if (!cpu_possible(device->res->pm_qos.silver_cores[i]))
  2026. continue;
  2027. qos_hdl = &device->res->pm_qos.pm_qos_hdls[i];
  2028. if ((qos_hdl != NULL) && dev_pm_qos_request_active(qos_hdl))
  2029. dev_pm_qos_remove_request(qos_hdl);
  2030. }
  2031. kfree(device->res->pm_qos.pm_qos_hdls);
  2032. device->res->pm_qos.pm_qos_hdls = NULL;
  2033. }
  2034. __resume(device);
  2035. __set_state(device, IRIS_STATE_DEINIT);
  2036. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  2037. if (rc)
  2038. dprintk(CVP_WARN, "Failed to suspend cvp FW%d\n", rc);
  2039. __dsp_shutdown(device);
  2040. __disable_subcaches(device);
  2041. ipcc_iova = __read_register(device, CVP_MMAP_ADDR);
  2042. msm_cvp_unmap_ipcc_regs(ipcc_iova);
  2043. __unload_fw(device);
  2044. __hwfence_regs_unmap(device);
  2045. if (msm_cvp_mmrm_enabled) {
  2046. rc = msm_cvp_mmrm_deregister(device);
  2047. if (rc) {
  2048. dprintk(CVP_ERR,
  2049. "%s: Failed msm_cvp_mmrm_deregister:%d\n",
  2050. __func__, rc);
  2051. }
  2052. }
  2053. /* unlink all sessions from device */
  2054. list_for_each_entry_safe(session, next, &device->sess_head, list) {
  2055. list_del(&session->list);
  2056. session->device = NULL;
  2057. }
  2058. dprintk(CVP_CORE, "Core released successfully\n");
  2059. mutex_unlock(&device->lock);
  2060. return rc;
  2061. }
  2062. static void __core_clear_interrupt(struct iris_hfi_device *device)
  2063. {
  2064. u32 intr_status = 0, mask = 0;
  2065. if (!device) {
  2066. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2067. return;
  2068. }
  2069. intr_status = __read_register(device, CVP_WRAPPER_INTR_STATUS);
  2070. mask = (CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK | CVP_FATAL_INTR_BMSK);
  2071. if (intr_status & mask) {
  2072. device->intr_status |= intr_status;
  2073. device->reg_count++;
  2074. dprintk(CVP_CORE,
  2075. "INTERRUPT for device: %pK: times: %d status: %d\n",
  2076. device, device->reg_count, intr_status);
  2077. } else {
  2078. device->spur_count++;
  2079. }
  2080. __write_register(device, CVP_CPU_CS_A2HSOFTINTCLR, 1);
  2081. }
  2082. static int iris_hfi_core_trigger_ssr(void *device,
  2083. enum hal_ssr_trigger_type type)
  2084. {
  2085. struct cvp_hfi_cmd_sys_test_ssr_packet pkt;
  2086. int rc = 0;
  2087. struct iris_hfi_device *dev;
  2088. cvp_free_va_md_list();
  2089. if (!device) {
  2090. dprintk(CVP_ERR, "invalid device\n");
  2091. return -ENODEV;
  2092. }
  2093. dev = device;
  2094. if (mutex_trylock(&dev->lock)) {
  2095. rc = call_hfi_pkt_op(dev, ssr_cmd, type, &pkt);
  2096. if (rc) {
  2097. dprintk(CVP_ERR, "%s: failed to create packet\n",
  2098. __func__);
  2099. goto err_create_pkt;
  2100. }
  2101. if (__iface_cmdq_write(dev, &pkt))
  2102. rc = -ENOTEMPTY;
  2103. } else {
  2104. return -EAGAIN;
  2105. }
  2106. err_create_pkt:
  2107. mutex_unlock(&dev->lock);
  2108. return rc;
  2109. }
  2110. static void __set_default_sys_properties(struct iris_hfi_device *device)
  2111. {
  2112. if (__sys_set_debug(device, msm_cvp_fw_debug))
  2113. dprintk(CVP_WARN, "Setting fw_debug msg ON failed\n");
  2114. if (__sys_set_power_control(device, msm_cvp_fw_low_power_mode))
  2115. dprintk(CVP_WARN, "Setting h/w power collapse ON failed\n");
  2116. }
  2117. static void __session_clean(struct cvp_hal_session *session)
  2118. {
  2119. struct cvp_hal_session *temp, *next;
  2120. struct iris_hfi_device *device;
  2121. if (!session || !session->device) {
  2122. dprintk(CVP_WARN, "%s: invalid params\n", __func__);
  2123. return;
  2124. }
  2125. device = session->device;
  2126. dprintk(CVP_SESS, "deleted the session: %pK\n", session);
  2127. /*
  2128. * session might have been removed from the device list in
  2129. * core_release, so check and remove if it is in the list
  2130. */
  2131. list_for_each_entry_safe(temp, next, &device->sess_head, list) {
  2132. if (session == temp) {
  2133. list_del(&session->list);
  2134. break;
  2135. }
  2136. }
  2137. /* Poison the session handle with zeros */
  2138. *session = (struct cvp_hal_session){ {0} };
  2139. kfree(session);
  2140. }
  2141. static int iris_hfi_session_clean(void *session)
  2142. {
  2143. struct cvp_hal_session *sess_close;
  2144. struct iris_hfi_device *device;
  2145. if (!session) {
  2146. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2147. return -EINVAL;
  2148. }
  2149. sess_close = session;
  2150. device = sess_close->device;
  2151. if (!device) {
  2152. dprintk(CVP_ERR, "Invalid device handle %s\n", __func__);
  2153. return -EINVAL;
  2154. }
  2155. mutex_lock(&device->lock);
  2156. __session_clean(sess_close);
  2157. mutex_unlock(&device->lock);
  2158. return 0;
  2159. }
  2160. static int iris_debug_hook(void *device)
  2161. {
  2162. struct iris_hfi_device *dev = device;
  2163. u32 val;
  2164. if (!device) {
  2165. dprintk(CVP_ERR, "%s Invalid device\n", __func__);
  2166. return -ENODEV;
  2167. }
  2168. //__write_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0x11);
  2169. //__write_register(dev, CVP_WRAPPER_TZ_CPU_CLOCK_CONFIG, 0x1);
  2170. dprintk(CVP_ERR, "Halt Tensilica and core and axi\n");
  2171. return 0;
  2172. /******* FDU & MPU *****/
  2173. #define CVP0_CVP_SS_FDU_SECURE_ENABLE 0x90
  2174. #define CVP0_CVP_SS_MPU_SECURE_ENABLE 0x94
  2175. #define CVP0_CVP_SS_ARP_THREAD_0_SECURE_ENABLE 0xA0
  2176. #define CVP0_CVP_SS_ARP_THREAD_1_SECURE_ENABLE 0xA4
  2177. #define CVP0_CVP_SS_ARP_THREAD_2_SECURE_ENABLE 0xA8
  2178. #define CVP0_CVP_SS_ARP_THREAD_3_SECURE_ENABLE 0xAC
  2179. val = __read_register(dev, CVP0_CVP_SS_FDU_SECURE_ENABLE);
  2180. dprintk(CVP_ERR, "FDU_SECURE_ENABLE %#x\n", val);
  2181. val = __read_register(dev, CVP0_CVP_SS_MPU_SECURE_ENABLE);
  2182. dprintk(CVP_ERR, "MPU_SECURE_ENABLE %#x\n", val);
  2183. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_0_SECURE_ENABLE);
  2184. dprintk(CVP_ERR, "ARP_THREAD_0_SECURE_ENABLE %#x\n", val);
  2185. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_1_SECURE_ENABLE);
  2186. dprintk(CVP_ERR, "ARP_THREAD_1_SECURE_ENABLE %#x\n", val);
  2187. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_2_SECURE_ENABLE);
  2188. dprintk(CVP_ERR, "ARP_THREAD_2_SECURE_ENABLE %#x\n", val);
  2189. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_3_SECURE_ENABLE);
  2190. dprintk(CVP_ERR, "ARP_THREAD_3_SECURE_ENABLE %#x\n", val);
  2191. if (true)
  2192. return 0;
  2193. /***** GCE *******
  2194. * Bit 0 of below register is CDM secure enable for GCE
  2195. * CDM buffer will be in CB4 if set
  2196. */
  2197. #define CVP_GCE_GCE_SS_CP_CTL 0x51100
  2198. /* STATUS bit0 && CFG bit 4 of below register set,
  2199. * expect pixel buffers in CB3,
  2200. * otherwise in CB0
  2201. * CFG bit 9:8 b01 -> LMC input in CB3
  2202. * CFG bit 9:8 b10 -> LMC input in CB4
  2203. */
  2204. #define CVP_GCE0_CP_STATUS 0x51080
  2205. #define CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG 0x52020
  2206. val = __read_register(dev, CVP_GCE_GCE_SS_CP_CTL);
  2207. dprintk(CVP_ERR, "CVP_GCE_GCE_SS_CP_CTL %#x\n", val);
  2208. val = __read_register(dev, CVP_GCE0_CP_STATUS);
  2209. dprintk(CVP_ERR, "CVP_GCE0_CP_STATUS %#x\n", val);
  2210. val = __read_register(dev, CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG);
  2211. dprintk(CVP_ERR, "CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2212. /***** RGE *****
  2213. * Bit 0 of below regiser is CDM secure enable for RGE
  2214. * CDM buffer to be in CB4 i fset
  2215. */
  2216. #define CVP_RGE0_TOPRGE_CP_CTL 0x31010
  2217. /* CFG bit 4 && IN bit 0:
  2218. * if both are set, expect CB3 or CB4 depending on IN 6:4 field
  2219. * either is clear, expect CB0
  2220. */
  2221. #define CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG 0x32020
  2222. #define CVP_RGE0_TOPSPARE_IN 0x311F4
  2223. val = __read_register(dev, CVP_RGE0_TOPRGE_CP_CTL);
  2224. dprintk(CVP_ERR, "CVP_RGE0_TOPRGE_CP_CTL %#x\n", val);
  2225. val = __read_register(dev, CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2226. dprintk(CVP_ERR, "CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2227. val = __read_register(dev, CVP_RGE0_TOPSPARE_IN);
  2228. dprintk(CVP_ERR, "CVP_RGE0_TOPSPARE_IN %#x\n", val);
  2229. /****** VADL ******
  2230. * Bit 0 of below register is CDM secure enable for VADL
  2231. * CDM buffer will bei in CB4 if set
  2232. */
  2233. #define CVP_VADL0_VADL_SS_CP_CTL 0x21010
  2234. /* Below registers are used the same way as RGE */
  2235. #define CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG 0x22020
  2236. #define CVP_VADL0_SPARE_IN 0x211F4
  2237. val = __read_register(dev, CVP_VADL0_VADL_SS_CP_CTL);
  2238. dprintk(CVP_ERR, "CVP_VADL0_VADL_SS_CP_CTL %#x\n", val);
  2239. val = __read_register(dev, CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2240. dprintk(CVP_ERR, "CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2241. val = __read_register(dev, CVP_VADL0_SPARE_IN);
  2242. dprintk(CVP_ERR, "CVP_VADL0_SPARE_IN %#x\n", val);
  2243. /****** ITOF *****
  2244. * Below registers are used the same way as RGE
  2245. */
  2246. #define CVP_ITOF0_TOF_SS_CP_CTL 0x41010
  2247. #define CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG 0x42020
  2248. #define CVP_ITOF0_TOF_SS_SPARE_IN 0x411F4
  2249. val = __read_register(dev, CVP_ITOF0_TOF_SS_CP_CTL);
  2250. dprintk(CVP_ERR, "CVP_ITOF0_TOF_SS_CP_CTL %#x\n", val);
  2251. val = __read_register(dev, CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2252. dprintk(CVP_ERR, "CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2253. val = __read_register(dev, CVP_ITOF0_TOF_SS_SPARE_IN);
  2254. dprintk(CVP_ERR, "CVP_ITOF0_TOF_SS_SPARE_IN %#x\n", val);
  2255. return 0;
  2256. }
  2257. static int iris_hfi_session_init(void *device, void *session_id,
  2258. void **new_session)
  2259. {
  2260. struct cvp_hfi_cmd_sys_session_init_packet pkt;
  2261. struct iris_hfi_device *dev;
  2262. struct cvp_hal_session *s;
  2263. if (!device || !new_session) {
  2264. dprintk(CVP_ERR, "%s - invalid input\n", __func__);
  2265. return -EINVAL;
  2266. }
  2267. dev = device;
  2268. mutex_lock(&dev->lock);
  2269. s = kzalloc(sizeof(*s), GFP_KERNEL);
  2270. if (!s) {
  2271. dprintk(CVP_ERR, "new session fail: Out of memory\n");
  2272. goto err_session_init_fail;
  2273. }
  2274. s->session_id = session_id;
  2275. s->device = dev;
  2276. dprintk(CVP_SESS,
  2277. "%s: inst %pK, session %pK\n", __func__, session_id, s);
  2278. list_add_tail(&s->list, &dev->sess_head);
  2279. __set_default_sys_properties(device);
  2280. if (call_hfi_pkt_op(dev, session_init, &pkt, s)) {
  2281. dprintk(CVP_ERR, "session_init: failed to create packet\n");
  2282. goto err_session_init_fail;
  2283. }
  2284. *new_session = s;
  2285. if (__iface_cmdq_write(dev, &pkt))
  2286. goto err_session_init_fail;
  2287. mutex_unlock(&dev->lock);
  2288. return 0;
  2289. err_session_init_fail:
  2290. if (s)
  2291. __session_clean(s);
  2292. *new_session = NULL;
  2293. mutex_unlock(&dev->lock);
  2294. return -EINVAL;
  2295. }
  2296. static int __send_session_cmd(struct cvp_hal_session *session, int pkt_type)
  2297. {
  2298. struct cvp_hal_session_cmd_pkt pkt;
  2299. int rc = 0;
  2300. struct iris_hfi_device *device = session->device;
  2301. if (!__is_session_valid(device, session, __func__))
  2302. return -ECONNRESET;
  2303. rc = call_hfi_pkt_op(device, session_cmd,
  2304. &pkt, pkt_type, session);
  2305. if (rc == -EPERM)
  2306. return 0;
  2307. if (rc) {
  2308. dprintk(CVP_ERR, "send session cmd: create pkt failed\n");
  2309. goto err_create_pkt;
  2310. }
  2311. if (__iface_cmdq_write(session->device, &pkt))
  2312. rc = -ENOTEMPTY;
  2313. err_create_pkt:
  2314. return rc;
  2315. }
  2316. static int iris_hfi_session_end(void *session)
  2317. {
  2318. struct cvp_hal_session *sess;
  2319. struct iris_hfi_device *device;
  2320. int rc = 0;
  2321. if (!session) {
  2322. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2323. return -EINVAL;
  2324. }
  2325. sess = session;
  2326. device = sess->device;
  2327. if (!device) {
  2328. dprintk(CVP_ERR, "Invalid session %s\n", __func__);
  2329. return -EINVAL;
  2330. }
  2331. mutex_lock(&device->lock);
  2332. if (msm_cvp_fw_coverage) {
  2333. if (__sys_set_coverage(sess->device, msm_cvp_fw_coverage))
  2334. dprintk(CVP_WARN, "Fw_coverage msg ON failed\n");
  2335. }
  2336. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_END);
  2337. mutex_unlock(&device->lock);
  2338. return rc;
  2339. }
  2340. static int iris_hfi_session_abort(void *sess)
  2341. {
  2342. struct cvp_hal_session *session = sess;
  2343. struct iris_hfi_device *device;
  2344. int rc = 0;
  2345. if (!session || !session->device) {
  2346. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2347. return -EINVAL;
  2348. }
  2349. device = session->device;
  2350. mutex_lock(&device->lock);
  2351. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_ABORT);
  2352. mutex_unlock(&device->lock);
  2353. return rc;
  2354. }
  2355. static int iris_hfi_session_set_buffers(void *sess, u32 iova, u32 size)
  2356. {
  2357. struct cvp_hfi_cmd_session_set_buffers_packet pkt;
  2358. int rc = 0;
  2359. struct cvp_hal_session *session = sess;
  2360. struct iris_hfi_device *device;
  2361. if (!session || !session->device || !iova || !size) {
  2362. dprintk(CVP_ERR, "Invalid Params\n");
  2363. return -EINVAL;
  2364. }
  2365. device = session->device;
  2366. mutex_lock(&device->lock);
  2367. if (!__is_session_valid(device, session, __func__)) {
  2368. rc = -ECONNRESET;
  2369. goto err_create_pkt;
  2370. }
  2371. rc = call_hfi_pkt_op(device, session_set_buffers,
  2372. &pkt, session, iova, size);
  2373. if (rc) {
  2374. dprintk(CVP_ERR, "set buffers: failed to create packet\n");
  2375. goto err_create_pkt;
  2376. }
  2377. if (__iface_cmdq_write(session->device, &pkt))
  2378. rc = -ENOTEMPTY;
  2379. err_create_pkt:
  2380. mutex_unlock(&device->lock);
  2381. return rc;
  2382. }
  2383. static int iris_hfi_session_release_buffers(void *sess)
  2384. {
  2385. struct cvp_session_release_buffers_packet pkt;
  2386. int rc = 0;
  2387. struct cvp_hal_session *session = sess;
  2388. struct iris_hfi_device *device;
  2389. if (!session || !session->device) {
  2390. dprintk(CVP_ERR, "Invalid Params\n");
  2391. return -EINVAL;
  2392. }
  2393. device = session->device;
  2394. mutex_lock(&device->lock);
  2395. if (!__is_session_valid(device, session, __func__)) {
  2396. rc = -ECONNRESET;
  2397. goto err_create_pkt;
  2398. }
  2399. rc = call_hfi_pkt_op(device, session_release_buffers, &pkt, session);
  2400. if (rc) {
  2401. dprintk(CVP_ERR, "release buffers: failed to create packet\n");
  2402. goto err_create_pkt;
  2403. }
  2404. if (__iface_cmdq_write(session->device, &pkt))
  2405. rc = -ENOTEMPTY;
  2406. err_create_pkt:
  2407. mutex_unlock(&device->lock);
  2408. return rc;
  2409. }
  2410. static int iris_hfi_session_send(void *sess,
  2411. struct eva_kmd_hfi_packet *in_pkt)
  2412. {
  2413. int rc = 0;
  2414. struct eva_kmd_hfi_packet pkt;
  2415. struct cvp_hal_session *session = sess;
  2416. struct iris_hfi_device *device;
  2417. if (!session || !session->device) {
  2418. dprintk(CVP_ERR, "invalid session");
  2419. return -ENODEV;
  2420. }
  2421. device = session->device;
  2422. mutex_lock(&device->lock);
  2423. if (!__is_session_valid(device, session, __func__)) {
  2424. rc = -ECONNRESET;
  2425. goto err_send_pkt;
  2426. }
  2427. rc = call_hfi_pkt_op(device, session_send,
  2428. &pkt, session, in_pkt);
  2429. if (rc) {
  2430. dprintk(CVP_ERR,
  2431. "failed to create pkt\n");
  2432. goto err_send_pkt;
  2433. }
  2434. if (__iface_cmdq_write(session->device, &pkt))
  2435. rc = -ENOTEMPTY;
  2436. err_send_pkt:
  2437. mutex_unlock(&device->lock);
  2438. return rc;
  2439. return rc;
  2440. }
  2441. static int iris_hfi_session_flush(void *sess)
  2442. {
  2443. struct cvp_hal_session *session = sess;
  2444. struct iris_hfi_device *device;
  2445. int rc = 0;
  2446. if (!session || !session->device) {
  2447. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2448. return -EINVAL;
  2449. }
  2450. device = session->device;
  2451. mutex_lock(&device->lock);
  2452. rc = __send_session_cmd(session, HFI_CMD_SESSION_CVP_FLUSH);
  2453. mutex_unlock(&device->lock);
  2454. return rc;
  2455. }
  2456. static int iris_hfi_session_start(void *sess)
  2457. {
  2458. struct cvp_hal_session *session = sess;
  2459. struct iris_hfi_device *device;
  2460. int rc = 0;
  2461. if (!session || !session->device) {
  2462. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2463. return -EINVAL;
  2464. }
  2465. device = session->device;
  2466. mutex_lock(&device->lock);
  2467. rc = __send_session_cmd(session, HFI_CMD_SESSION_EVA_START);
  2468. mutex_unlock(&device->lock);
  2469. return rc;
  2470. }
  2471. static int iris_hfi_session_stop(void *sess)
  2472. {
  2473. struct cvp_hal_session *session = sess;
  2474. struct iris_hfi_device *device;
  2475. int rc = 0;
  2476. if (!session || !session->device) {
  2477. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2478. return -EINVAL;
  2479. }
  2480. device = session->device;
  2481. mutex_lock(&device->lock);
  2482. rc = __send_session_cmd(session, HFI_CMD_SESSION_EVA_STOP);
  2483. mutex_unlock(&device->lock);
  2484. return rc;
  2485. }
  2486. static void __process_fatal_error(
  2487. struct iris_hfi_device *device)
  2488. {
  2489. struct msm_cvp_cb_cmd_done cmd_done = {0};
  2490. device->callback(HAL_SYS_ERROR, &cmd_done);
  2491. }
  2492. static int __prepare_pc(struct iris_hfi_device *device)
  2493. {
  2494. int rc = 0;
  2495. struct cvp_hfi_cmd_sys_pc_prep_packet pkt;
  2496. rc = call_hfi_pkt_op(device, sys_pc_prep, &pkt);
  2497. if (rc) {
  2498. dprintk(CVP_ERR, "Failed to create sys pc prep pkt\n");
  2499. goto err_pc_prep;
  2500. }
  2501. if (__iface_cmdq_write(device, &pkt))
  2502. rc = -ENOTEMPTY;
  2503. if (rc)
  2504. dprintk(CVP_ERR, "Failed to prepare iris for power off");
  2505. err_pc_prep:
  2506. return rc;
  2507. }
  2508. static void iris_hfi_pm_handler(struct work_struct *work)
  2509. {
  2510. int rc = 0;
  2511. struct msm_cvp_core *core;
  2512. struct iris_hfi_device *device;
  2513. core = cvp_driver->cvp_core;
  2514. if (core)
  2515. device = core->dev_ops->hfi_device_data;
  2516. else
  2517. return;
  2518. if (!device) {
  2519. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2520. return;
  2521. }
  2522. dprintk(CVP_PWR,
  2523. "Entering %s\n", __func__);
  2524. /*
  2525. * It is ok to check this variable outside the lock since
  2526. * it is being updated in this context only
  2527. */
  2528. if (device->skip_pc_count >= CVP_MAX_PC_SKIP_COUNT) {
  2529. dprintk(CVP_WARN, "Failed to PC for %d times\n",
  2530. device->skip_pc_count);
  2531. device->skip_pc_count = 0;
  2532. __process_fatal_error(device);
  2533. return;
  2534. }
  2535. mutex_lock(&device->lock);
  2536. if (gfa_cv.state == DSP_SUSPEND)
  2537. rc = __power_collapse(device, true);
  2538. else
  2539. rc = __power_collapse(device, false);
  2540. mutex_unlock(&device->lock);
  2541. switch (rc) {
  2542. case 0:
  2543. device->skip_pc_count = 0;
  2544. /* Cancel pending delayed works if any */
  2545. cancel_delayed_work(&iris_hfi_pm_work);
  2546. dprintk(CVP_PWR, "%s: power collapse successful!\n",
  2547. __func__);
  2548. break;
  2549. case -EBUSY:
  2550. device->skip_pc_count = 0;
  2551. dprintk(CVP_PWR, "%s: retry PC as cvp is busy\n", __func__);
  2552. queue_delayed_work(device->iris_pm_workq,
  2553. &iris_hfi_pm_work, msecs_to_jiffies(
  2554. device->res->msm_cvp_pwr_collapse_delay));
  2555. break;
  2556. case -EAGAIN:
  2557. device->skip_pc_count++;
  2558. dprintk(CVP_WARN, "%s: retry power collapse (count %d)\n",
  2559. __func__, device->skip_pc_count);
  2560. queue_delayed_work(device->iris_pm_workq,
  2561. &iris_hfi_pm_work, msecs_to_jiffies(
  2562. device->res->msm_cvp_pwr_collapse_delay));
  2563. break;
  2564. default:
  2565. dprintk(CVP_ERR, "%s: power collapse failed\n", __func__);
  2566. break;
  2567. }
  2568. }
  2569. static int __power_collapse(struct iris_hfi_device *device, bool force)
  2570. {
  2571. int rc = 0;
  2572. u32 wfi_status = 0, idle_status = 0, pc_ready = 0;
  2573. int count = 0;
  2574. const int max_tries = 150;
  2575. if (!device) {
  2576. dprintk(CVP_ERR, "%s: invalid params\n", __func__);
  2577. return -EINVAL;
  2578. }
  2579. if (!device->power_enabled) {
  2580. dprintk(CVP_PWR, "%s: Power already disabled\n",
  2581. __func__);
  2582. goto exit;
  2583. }
  2584. rc = __core_in_valid_state(device);
  2585. if (!rc) {
  2586. dprintk(CVP_WARN,
  2587. "Core is in bad state, Skipping power collapse\n");
  2588. return -EINVAL;
  2589. }
  2590. rc = __dsp_suspend(device, force);
  2591. if (rc == -EBUSY)
  2592. goto exit;
  2593. else if (rc)
  2594. goto skip_power_off;
  2595. __flush_debug_queue(device, device->raw_packet);
  2596. pc_ready = __read_register(device, CVP_CTRL_STATUS) &
  2597. CVP_CTRL_STATUS_PC_READY;
  2598. if (!pc_ready) {
  2599. wfi_status = __read_register(device,
  2600. CVP_WRAPPER_CPU_STATUS);
  2601. idle_status = __read_register(device,
  2602. CVP_CTRL_STATUS);
  2603. if (!(wfi_status & BIT(0))) {
  2604. dprintk(CVP_WARN,
  2605. "Skipping PC as wfi_status (%#x) bit not set\n",
  2606. wfi_status);
  2607. goto skip_power_off;
  2608. }
  2609. if (!(idle_status & BIT(30))) {
  2610. dprintk(CVP_WARN,
  2611. "Skipping PC as idle_status (%#x) bit not set\n",
  2612. idle_status);
  2613. goto skip_power_off;
  2614. }
  2615. rc = __prepare_pc(device);
  2616. if (rc) {
  2617. dprintk(CVP_WARN, "Failed PC %d\n", rc);
  2618. goto skip_power_off;
  2619. }
  2620. while (count < max_tries) {
  2621. wfi_status = __read_register(device,
  2622. CVP_WRAPPER_CPU_STATUS);
  2623. pc_ready = __read_register(device,
  2624. CVP_CTRL_STATUS);
  2625. if ((wfi_status & BIT(0)) && (pc_ready &
  2626. CVP_CTRL_STATUS_PC_READY))
  2627. break;
  2628. usleep_range(150, 250);
  2629. count++;
  2630. }
  2631. if (count == max_tries) {
  2632. dprintk(CVP_ERR,
  2633. "Skip PC. Core is not ready (%#x, %#x)\n",
  2634. wfi_status, pc_ready);
  2635. goto skip_power_off;
  2636. }
  2637. } else {
  2638. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  2639. if (!(wfi_status & BIT(0))) {
  2640. dprintk(CVP_WARN,
  2641. "Skip PC as wfi_status (%#x) bit not set\n",
  2642. wfi_status);
  2643. goto skip_power_off;
  2644. }
  2645. }
  2646. rc = __suspend(device);
  2647. if (rc)
  2648. dprintk(CVP_ERR, "Failed __suspend\n");
  2649. exit:
  2650. return rc;
  2651. skip_power_off:
  2652. dprintk(CVP_PWR, "Skip PC(%#x, %#x, %#x)\n",
  2653. wfi_status, idle_status, pc_ready);
  2654. __flush_debug_queue(device, device->raw_packet);
  2655. return -EAGAIN;
  2656. }
  2657. static void __process_sys_error(struct iris_hfi_device *device)
  2658. {
  2659. struct cvp_hfi_sfr_struct *vsfr = NULL;
  2660. vsfr = (struct cvp_hfi_sfr_struct *)device->sfr.align_virtual_addr;
  2661. if (vsfr) {
  2662. void *p = memchr(vsfr->rg_data, '\0', vsfr->bufSize);
  2663. /*
  2664. * SFR isn't guaranteed to be NULL terminated
  2665. * since SYS_ERROR indicates that Iris is in the
  2666. * process of crashing.
  2667. */
  2668. if (p == NULL)
  2669. vsfr->rg_data[vsfr->bufSize - 1] = '\0';
  2670. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2671. vsfr->rg_data);
  2672. }
  2673. }
  2674. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet)
  2675. {
  2676. bool local_packet = false;
  2677. enum cvp_msg_prio log_level = CVP_FW;
  2678. if (!device) {
  2679. dprintk(CVP_ERR, "%s: Invalid params\n", __func__);
  2680. return;
  2681. }
  2682. if (!packet) {
  2683. packet = kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  2684. if (!packet) {
  2685. dprintk(CVP_ERR, "In %s() Fail to allocate mem\n",
  2686. __func__);
  2687. return;
  2688. }
  2689. local_packet = true;
  2690. /*
  2691. * Local packek is used when something FATAL occurred.
  2692. * It is good to print these logs by default.
  2693. */
  2694. log_level = CVP_ERR;
  2695. }
  2696. #define SKIP_INVALID_PKT(pkt_size, payload_size, pkt_hdr_size) ({ \
  2697. if (pkt_size < pkt_hdr_size || \
  2698. payload_size < MIN_PAYLOAD_SIZE || \
  2699. payload_size > \
  2700. (pkt_size - pkt_hdr_size + sizeof(u8))) { \
  2701. dprintk(CVP_ERR, \
  2702. "%s: invalid msg size - %d\n", \
  2703. __func__, pkt->msg_size); \
  2704. continue; \
  2705. } \
  2706. })
  2707. while (!__iface_dbgq_read(device, packet)) {
  2708. struct cvp_hfi_packet_header *pkt =
  2709. (struct cvp_hfi_packet_header *) packet;
  2710. if (pkt->size < sizeof(struct cvp_hfi_packet_header)) {
  2711. dprintk(CVP_ERR, "Invalid pkt size - %s\n",
  2712. __func__);
  2713. continue;
  2714. }
  2715. if (pkt->packet_type == HFI_MSG_SYS_DEBUG) {
  2716. struct cvp_hfi_msg_sys_debug_packet *pkt =
  2717. (struct cvp_hfi_msg_sys_debug_packet *) packet;
  2718. SKIP_INVALID_PKT(pkt->size,
  2719. pkt->msg_size, sizeof(*pkt));
  2720. /*
  2721. * All fw messages starts with new line character. This
  2722. * causes dprintk to print this message in two lines
  2723. * in the kernel log. Ignoring the first character
  2724. * from the message fixes this to print it in a single
  2725. * line.
  2726. */
  2727. pkt->rg_msg_data[pkt->msg_size-1] = '\0';
  2728. dprintk(log_level, "%s", &pkt->rg_msg_data[1]);
  2729. }
  2730. }
  2731. #undef SKIP_INVALID_PKT
  2732. if (local_packet)
  2733. kfree(packet);
  2734. }
  2735. static bool __is_session_valid(struct iris_hfi_device *device,
  2736. struct cvp_hal_session *session, const char *func)
  2737. {
  2738. struct cvp_hal_session *temp = NULL;
  2739. if (!device || !session)
  2740. goto invalid;
  2741. list_for_each_entry(temp, &device->sess_head, list)
  2742. if (session == temp)
  2743. return true;
  2744. invalid:
  2745. dprintk(CVP_WARN, "%s: device %pK, invalid session %pK\n",
  2746. func, device, session);
  2747. return false;
  2748. }
  2749. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  2750. u32 session_id)
  2751. {
  2752. struct cvp_hal_session *temp = NULL;
  2753. list_for_each_entry(temp, &device->sess_head, list) {
  2754. if (session_id == hash32_ptr(temp))
  2755. return temp;
  2756. }
  2757. return NULL;
  2758. }
  2759. #define _INVALID_MSG_ "Unrecognized MSG (%#x) session (%pK), discarding\n"
  2760. #define _INVALID_STATE_ "Ignore responses from %d to %d invalid state\n"
  2761. #define _DEVFREQ_FAIL_ "Failed to add devfreq device bus %s governor %s: %d\n"
  2762. static void process_system_msg(struct msm_cvp_cb_info *info,
  2763. struct iris_hfi_device *device,
  2764. void *raw_packet)
  2765. {
  2766. struct cvp_hal_sys_init_done sys_init_done = {0};
  2767. switch (info->response_type) {
  2768. case HAL_SYS_ERROR:
  2769. __process_sys_error(device);
  2770. break;
  2771. case HAL_SYS_RELEASE_RESOURCE_DONE:
  2772. dprintk(CVP_CORE, "Received SYS_RELEASE_RESOURCE\n");
  2773. break;
  2774. case HAL_SYS_INIT_DONE:
  2775. dprintk(CVP_CORE, "Received SYS_INIT_DONE\n");
  2776. sys_init_done.capabilities =
  2777. device->sys_init_capabilities;
  2778. cvp_hfi_process_sys_init_done_prop_read(
  2779. (struct cvp_hfi_msg_sys_init_done_packet *)
  2780. raw_packet, &sys_init_done);
  2781. info->response.cmd.data.sys_init_done = sys_init_done;
  2782. break;
  2783. default:
  2784. break;
  2785. }
  2786. }
  2787. static void **get_session_id(struct msm_cvp_cb_info *info)
  2788. {
  2789. void **session_id = NULL;
  2790. /* For session-related packets, validate session */
  2791. switch (info->response_type) {
  2792. case HAL_SESSION_INIT_DONE:
  2793. case HAL_SESSION_END_DONE:
  2794. case HAL_SESSION_ABORT_DONE:
  2795. case HAL_SESSION_START_DONE:
  2796. case HAL_SESSION_STOP_DONE:
  2797. case HAL_SESSION_FLUSH_DONE:
  2798. case HAL_SESSION_SET_BUFFER_DONE:
  2799. case HAL_SESSION_SUSPEND_DONE:
  2800. case HAL_SESSION_RESUME_DONE:
  2801. case HAL_SESSION_SET_PROP_DONE:
  2802. case HAL_SESSION_GET_PROP_DONE:
  2803. case HAL_SESSION_RELEASE_BUFFER_DONE:
  2804. case HAL_SESSION_REGISTER_BUFFER_DONE:
  2805. case HAL_SESSION_UNREGISTER_BUFFER_DONE:
  2806. case HAL_SESSION_PROPERTY_INFO:
  2807. case HAL_SESSION_EVENT_CHANGE:
  2808. case HAL_SESSION_DUMP_NOTIFY:
  2809. case HAL_SESSION_ERROR:
  2810. session_id = &info->response.cmd.session_id;
  2811. break;
  2812. case HAL_RESPONSE_UNUSED:
  2813. default:
  2814. session_id = NULL;
  2815. break;
  2816. }
  2817. return session_id;
  2818. }
  2819. static void print_msg_hdr(void *hdr)
  2820. {
  2821. struct cvp_hfi_msg_session_hdr *new_hdr =
  2822. (struct cvp_hfi_msg_session_hdr *)hdr;
  2823. dprintk(CVP_HFI, "HFI MSG received: %x %x %x %x %x %x %x %#llx\n",
  2824. new_hdr->size, new_hdr->packet_type,
  2825. new_hdr->session_id,
  2826. new_hdr->client_data.transaction_id,
  2827. new_hdr->client_data.data1,
  2828. new_hdr->client_data.data2,
  2829. new_hdr->error_type,
  2830. new_hdr->client_data.kdata);
  2831. }
  2832. static int __response_handler(struct iris_hfi_device *device)
  2833. {
  2834. struct msm_cvp_cb_info *packets;
  2835. int packet_count = 0;
  2836. u8 *raw_packet = NULL;
  2837. bool requeue_pm_work = true;
  2838. if (!device || device->state != IRIS_STATE_INIT)
  2839. return 0;
  2840. packets = device->response_pkt;
  2841. raw_packet = device->raw_packet;
  2842. if (!raw_packet || !packets) {
  2843. dprintk(CVP_ERR,
  2844. "%s: Invalid args : Res pkt = %pK, Raw pkt = %pK\n",
  2845. __func__, packets, raw_packet);
  2846. return 0;
  2847. }
  2848. if (device->intr_status & CVP_FATAL_INTR_BMSK) {
  2849. struct cvp_hfi_sfr_struct *vsfr = (struct cvp_hfi_sfr_struct *)
  2850. device->sfr.align_virtual_addr;
  2851. struct msm_cvp_cb_info info = {
  2852. .response_type = HAL_SYS_WATCHDOG_TIMEOUT,
  2853. .response.cmd = {
  2854. .device_id = 0,
  2855. }
  2856. };
  2857. if (vsfr)
  2858. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2859. vsfr->rg_data);
  2860. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CPU_NOC_BMSK)
  2861. dprintk(CVP_ERR, "Received Xtensa NOC error\n");
  2862. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CORE_NOC_BMSK)
  2863. dprintk(CVP_ERR, "Received CVP core NOC error\n");
  2864. if (device->intr_status & CVP_WRAPPER_INTR_MASK_A2HWD_BMSK)
  2865. dprintk(CVP_ERR, "Received CVP watchdog timeout\n");
  2866. packets[packet_count++] = info;
  2867. goto exit;
  2868. }
  2869. /* Bleed the msg queue dry of packets */
  2870. while (!__iface_msgq_read(device, raw_packet)) {
  2871. void **session_id = NULL;
  2872. struct msm_cvp_cb_info *info = &packets[packet_count++];
  2873. struct cvp_hfi_msg_session_hdr *hdr =
  2874. (struct cvp_hfi_msg_session_hdr *)raw_packet;
  2875. int rc = 0;
  2876. print_msg_hdr(hdr);
  2877. rc = cvp_hfi_process_msg_packet(0, raw_packet, info);
  2878. if (rc) {
  2879. dprintk(CVP_WARN,
  2880. "Corrupt/unknown packet found, discarding\n");
  2881. --packet_count;
  2882. continue;
  2883. } else if (info->response_type == HAL_NO_RESP) {
  2884. --packet_count;
  2885. continue;
  2886. }
  2887. /* Process the packet types that we're interested in */
  2888. process_system_msg(info, device, raw_packet);
  2889. session_id = get_session_id(info);
  2890. /*
  2891. * hfi_process_msg_packet provides a session_id that's a hashed
  2892. * value of struct cvp_hal_session, we need to coerce the hashed
  2893. * value back to pointer that we can use. Ideally, hfi_process\
  2894. * _msg_packet should take care of this, but it doesn't have
  2895. * required information for it
  2896. */
  2897. if (session_id) {
  2898. struct cvp_hal_session *session = NULL;
  2899. if (upper_32_bits((uintptr_t)*session_id) != 0) {
  2900. dprintk(CVP_ERR,
  2901. "Upper 32-bits != 0 for sess_id=%pK\n",
  2902. *session_id);
  2903. }
  2904. session = __get_session(device,
  2905. (u32)(uintptr_t)*session_id);
  2906. if (!session) {
  2907. dprintk(CVP_ERR, _INVALID_MSG_,
  2908. info->response_type,
  2909. *session_id);
  2910. --packet_count;
  2911. continue;
  2912. }
  2913. *session_id = session->session_id;
  2914. }
  2915. if (packet_count >= cvp_max_packets) {
  2916. dprintk(CVP_WARN,
  2917. "Too many packets in message queue!\n");
  2918. break;
  2919. }
  2920. /* do not read packets after sys error packet */
  2921. if (info->response_type == HAL_SYS_ERROR)
  2922. break;
  2923. }
  2924. if (requeue_pm_work && device->res->sw_power_collapsible) {
  2925. cancel_delayed_work(&iris_hfi_pm_work);
  2926. if (!queue_delayed_work(device->iris_pm_workq,
  2927. &iris_hfi_pm_work,
  2928. msecs_to_jiffies(
  2929. device->res->msm_cvp_pwr_collapse_delay))) {
  2930. dprintk(CVP_ERR, "PM work already scheduled\n");
  2931. }
  2932. }
  2933. exit:
  2934. __flush_debug_queue(device, raw_packet);
  2935. return packet_count;
  2936. }
  2937. irqreturn_t iris_hfi_core_work_handler(int irq, void *data)
  2938. {
  2939. struct msm_cvp_core *core;
  2940. struct iris_hfi_device *device;
  2941. int num_responses = 0, i = 0;
  2942. u32 intr_status;
  2943. static bool warning_on = true;
  2944. core = cvp_driver->cvp_core;
  2945. if (core)
  2946. device = core->dev_ops->hfi_device_data;
  2947. else
  2948. return IRQ_HANDLED;
  2949. mutex_lock(&device->lock);
  2950. if (!__core_in_valid_state(device)) {
  2951. if (warning_on) {
  2952. dprintk(CVP_WARN, "%s Core not in init state\n",
  2953. __func__);
  2954. warning_on = false;
  2955. }
  2956. goto err_no_work;
  2957. }
  2958. warning_on = true;
  2959. if (!device->callback) {
  2960. dprintk(CVP_ERR, "No interrupt callback function: %pK\n",
  2961. device);
  2962. goto err_no_work;
  2963. }
  2964. if (__resume(device)) {
  2965. dprintk(CVP_ERR, "%s: Power enable failed\n", __func__);
  2966. goto err_no_work;
  2967. }
  2968. __core_clear_interrupt(device);
  2969. num_responses = __response_handler(device);
  2970. dprintk(CVP_HFI, "%s:: cvp_driver_debug num_responses = %d ",
  2971. __func__, num_responses);
  2972. err_no_work:
  2973. /* Keep the interrupt status before releasing device lock */
  2974. intr_status = device->intr_status;
  2975. mutex_unlock(&device->lock);
  2976. /*
  2977. * Issue the callbacks outside of the locked contex to preserve
  2978. * re-entrancy.
  2979. */
  2980. for (i = 0; !IS_ERR_OR_NULL(device->response_pkt) &&
  2981. i < num_responses; ++i) {
  2982. struct msm_cvp_cb_info *r = &device->response_pkt[i];
  2983. void *rsp = (void *)&r->response;
  2984. if (!__core_in_valid_state(device)) {
  2985. dprintk(CVP_ERR,
  2986. _INVALID_STATE_, (i + 1), num_responses);
  2987. break;
  2988. }
  2989. dprintk(CVP_HFI, "Processing response %d of %d, type %d\n",
  2990. (i + 1), num_responses, r->response_type);
  2991. /* callback = void cvp_handle_cmd_response() */
  2992. device->callback(r->response_type, rsp);
  2993. }
  2994. /* We need re-enable the irq which was disabled in ISR handler */
  2995. if (!(intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  2996. enable_irq(device->cvp_hal_data->irq);
  2997. return IRQ_HANDLED;
  2998. }
  2999. irqreturn_t cvp_hfi_isr(int irq, void *dev)
  3000. {
  3001. disable_irq_nosync(irq);
  3002. return IRQ_WAKE_THREAD;
  3003. }
  3004. static void iris_hfi_wd_work_handler(struct work_struct *work)
  3005. {
  3006. struct msm_cvp_core *core;
  3007. struct iris_hfi_device *device;
  3008. struct msm_cvp_cb_cmd_done response = {0};
  3009. enum hal_command_response cmd = HAL_SYS_WATCHDOG_TIMEOUT;
  3010. core = cvp_driver->cvp_core;
  3011. if (core)
  3012. device = core->dev_ops->hfi_device_data;
  3013. else
  3014. return;
  3015. if (msm_cvp_hw_wd_recovery) {
  3016. dprintk(CVP_ERR, "Cleaning up as HW WD recovery is enable %d\n",
  3017. msm_cvp_hw_wd_recovery);
  3018. response.device_id = 0;
  3019. handle_sys_error(cmd, (void *) &response);
  3020. enable_irq(device->cvp_hal_data->irq_wd);
  3021. }
  3022. else {
  3023. dprintk(CVP_ERR, "Crashing the device as HW WD recovery is disable %d\n",
  3024. msm_cvp_hw_wd_recovery);
  3025. BUG_ON(1);
  3026. }
  3027. }
  3028. static DECLARE_WORK(iris_hfi_wd_work, iris_hfi_wd_work_handler);
  3029. irqreturn_t iris_hfi_isr_wd(int irq, void *dev)
  3030. {
  3031. struct iris_hfi_device *device = dev;
  3032. dprintk(CVP_ERR, "Got HW WDOG IRQ at %llu! \n", get_aon_time());
  3033. disable_irq_nosync(irq);
  3034. queue_work(device->cvp_workq, &iris_hfi_wd_work);
  3035. return IRQ_HANDLED;
  3036. }
  3037. static int __init_reset_clk(struct msm_cvp_platform_resources *res,
  3038. int reset_index)
  3039. {
  3040. int rc = 0;
  3041. struct reset_control *rst;
  3042. struct reset_info *rst_info;
  3043. struct reset_set *rst_set = &res->reset_set;
  3044. if (!rst_set->reset_tbl)
  3045. return 0;
  3046. rst_info = &rst_set->reset_tbl[reset_index];
  3047. rst = rst_info->rst;
  3048. dprintk(CVP_PWR, "reset_clk: name %s rst %pK required_stage=%d\n",
  3049. rst_set->reset_tbl[reset_index].name, rst, rst_info->required_stage);
  3050. if (rst)
  3051. goto skip_reset_init;
  3052. if (rst_info->required_stage == CVP_ON_USE) {
  3053. rst = reset_control_get_exclusive_released(&res->pdev->dev,
  3054. rst_set->reset_tbl[reset_index].name);
  3055. if (IS_ERR(rst)) {
  3056. rc = PTR_ERR(rst);
  3057. dprintk(CVP_ERR, "reset get exclusive fail %d\n", rc);
  3058. return rc;
  3059. }
  3060. dprintk(CVP_PWR, "reset_clk: name %s get exclusive rst %llx\n",
  3061. rst_set->reset_tbl[reset_index].name, rst);
  3062. } else if (rst_info->required_stage == CVP_ON_INIT) {
  3063. rst = devm_reset_control_get(&res->pdev->dev,
  3064. rst_set->reset_tbl[reset_index].name);
  3065. if (IS_ERR(rst)) {
  3066. rc = PTR_ERR(rst);
  3067. dprintk(CVP_ERR, "reset get fail %d\n", rc);
  3068. return rc;
  3069. }
  3070. dprintk(CVP_PWR, "reset_clk: name %s get rst %llx\n",
  3071. rst_set->reset_tbl[reset_index].name, rst);
  3072. } else {
  3073. dprintk(CVP_ERR, "Invalid reset stage\n");
  3074. return -EINVAL;
  3075. }
  3076. rst_set->reset_tbl[reset_index].rst = rst;
  3077. rst_info->state = RESET_INIT;
  3078. return 0;
  3079. skip_reset_init:
  3080. return rc;
  3081. }
  3082. static int __reset_control_assert_name(struct iris_hfi_device *device,
  3083. const char *name)
  3084. {
  3085. struct reset_info *rcinfo = NULL;
  3086. int rc = 0;
  3087. bool found = false;
  3088. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3089. if (strcmp(rcinfo->name, name))
  3090. continue;
  3091. found = true;
  3092. rc = reset_control_assert(rcinfo->rst);
  3093. if (rc)
  3094. dprintk(CVP_ERR,
  3095. "%s: failed to assert reset control (%s), rc = %d\n",
  3096. __func__, rcinfo->name, rc);
  3097. else
  3098. dprintk(CVP_PWR, "%s: assert reset control (%s)\n",
  3099. __func__, rcinfo->name);
  3100. break;
  3101. }
  3102. if (!found) {
  3103. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3104. __func__, name);
  3105. rc = -EINVAL;
  3106. }
  3107. return rc;
  3108. }
  3109. static int __reset_control_deassert_name(struct iris_hfi_device *device,
  3110. const char *name)
  3111. {
  3112. struct reset_info *rcinfo = NULL;
  3113. int rc = 0;
  3114. bool found = false;
  3115. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3116. if (strcmp(rcinfo->name, name))
  3117. continue;
  3118. found = true;
  3119. rc = reset_control_deassert(rcinfo->rst);
  3120. if (rc)
  3121. dprintk(CVP_ERR,
  3122. "%s: deassert reset control for (%s) failed, rc %d\n",
  3123. __func__, rcinfo->name, rc);
  3124. else
  3125. dprintk(CVP_PWR, "%s: deassert reset control (%s)\n",
  3126. __func__, rcinfo->name);
  3127. break;
  3128. }
  3129. if (!found) {
  3130. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3131. __func__, name);
  3132. rc = -EINVAL;
  3133. }
  3134. return rc;
  3135. }
  3136. static int __reset_control_acquire(struct iris_hfi_device *device,
  3137. const char *name)
  3138. {
  3139. struct reset_info *rcinfo = NULL;
  3140. int rc = 0;
  3141. bool found = false;
  3142. int max_retries = 10;
  3143. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3144. if (strcmp(rcinfo->name, name))
  3145. continue;
  3146. found = true;
  3147. if (rcinfo->state == RESET_ACQUIRED)
  3148. return rc;
  3149. acquire_again:
  3150. rc = reset_control_acquire(rcinfo->rst);
  3151. if (rc) {
  3152. if (rc == -EBUSY) {
  3153. usleep_range(500, 1000);
  3154. max_retries--;
  3155. if (max_retries) {
  3156. goto acquire_again;
  3157. } else {
  3158. dprintk(CVP_ERR,
  3159. "%s acquire %s -EBUSY\n",
  3160. __func__, rcinfo->name);
  3161. rc = -EINVAL;
  3162. }
  3163. } else {
  3164. dprintk(CVP_ERR,
  3165. "%s: acquire failed (%s) rc %d\n",
  3166. __func__, rcinfo->name, rc);
  3167. rc = -EINVAL;
  3168. }
  3169. } else {
  3170. dprintk(CVP_PWR, "%s: reset acquire succeed (%s)\n",
  3171. __func__, rcinfo->name);
  3172. rcinfo->state = RESET_ACQUIRED;
  3173. }
  3174. break;
  3175. }
  3176. if (!found) {
  3177. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3178. __func__, name);
  3179. rc = -EINVAL;
  3180. }
  3181. return rc;
  3182. }
  3183. static int __reset_control_release(struct iris_hfi_device *device,
  3184. const char *name)
  3185. {
  3186. struct reset_info *rcinfo = NULL;
  3187. int rc = 0;
  3188. bool found = false;
  3189. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3190. if (strcmp(rcinfo->name, name))
  3191. continue;
  3192. found = true;
  3193. if (rcinfo->state != RESET_ACQUIRED) {
  3194. dprintk(CVP_WARN, "Double releasing reset clk?\n");
  3195. return -EINVAL;
  3196. }
  3197. reset_control_release(rcinfo->rst);
  3198. dprintk(CVP_PWR, "%s: reset release succeed (%s)\n",
  3199. __func__, rcinfo->name);
  3200. rcinfo->state = RESET_RELEASED;
  3201. break;
  3202. }
  3203. if (!found) {
  3204. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3205. __func__, name);
  3206. rc = -EINVAL;
  3207. }
  3208. return rc;
  3209. }
  3210. static void __deinit_bus(struct iris_hfi_device *device)
  3211. {
  3212. struct bus_info *bus = NULL;
  3213. if (!device)
  3214. return;
  3215. kfree(device->bus_vote.data);
  3216. device->bus_vote = CVP_DEFAULT_BUS_VOTE;
  3217. iris_hfi_for_each_bus_reverse(device, bus) {
  3218. dev_set_drvdata(bus->dev, NULL);
  3219. icc_put(bus->client);
  3220. bus->client = NULL;
  3221. }
  3222. }
  3223. static int __init_bus(struct iris_hfi_device *device)
  3224. {
  3225. struct bus_info *bus = NULL;
  3226. int rc = 0;
  3227. if (!device)
  3228. return -EINVAL;
  3229. iris_hfi_for_each_bus(device, bus) {
  3230. /*
  3231. * This is stupid, but there's no other easy way to ahold
  3232. * of struct bus_info in iris_hfi_devfreq_*()
  3233. */
  3234. WARN(dev_get_drvdata(bus->dev), "%s's drvdata already set\n",
  3235. dev_name(bus->dev));
  3236. dev_set_drvdata(bus->dev, device);
  3237. bus->client = icc_get(&device->res->pdev->dev,
  3238. bus->master, bus->slave);
  3239. if (IS_ERR_OR_NULL(bus->client)) {
  3240. rc = PTR_ERR(bus->client) ?: -EBADHANDLE;
  3241. dprintk(CVP_ERR, "Failed to register bus %s: %d\n",
  3242. bus->name, rc);
  3243. bus->client = NULL;
  3244. goto err_add_dev;
  3245. }
  3246. }
  3247. return 0;
  3248. err_add_dev:
  3249. __deinit_bus(device);
  3250. return rc;
  3251. }
  3252. static void __deinit_regulators(struct iris_hfi_device *device)
  3253. {
  3254. struct regulator_info *rinfo = NULL;
  3255. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3256. if (rinfo->regulator) {
  3257. regulator_put(rinfo->regulator);
  3258. rinfo->regulator = NULL;
  3259. }
  3260. }
  3261. }
  3262. static int __init_regulators(struct iris_hfi_device *device)
  3263. {
  3264. int rc = 0;
  3265. struct regulator_info *rinfo = NULL;
  3266. iris_hfi_for_each_regulator(device, rinfo) {
  3267. rinfo->regulator = regulator_get(&device->res->pdev->dev,
  3268. rinfo->name);
  3269. if (IS_ERR_OR_NULL(rinfo->regulator)) {
  3270. rc = PTR_ERR(rinfo->regulator) ?: -EBADHANDLE;
  3271. dprintk(CVP_ERR, "Failed to get regulator: %s\n",
  3272. rinfo->name);
  3273. rinfo->regulator = NULL;
  3274. goto err_reg_get;
  3275. }
  3276. }
  3277. return 0;
  3278. err_reg_get:
  3279. __deinit_regulators(device);
  3280. return rc;
  3281. }
  3282. static void __deinit_subcaches(struct iris_hfi_device *device)
  3283. {
  3284. struct subcache_info *sinfo = NULL;
  3285. if (!device) {
  3286. dprintk(CVP_ERR, "deinit_subcaches: invalid device %pK\n",
  3287. device);
  3288. goto exit;
  3289. }
  3290. if (!is_sys_cache_present(device))
  3291. goto exit;
  3292. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3293. if (sinfo->subcache) {
  3294. dprintk(CVP_CORE, "deinit_subcaches: %s\n",
  3295. sinfo->name);
  3296. llcc_slice_putd(sinfo->subcache);
  3297. sinfo->subcache = NULL;
  3298. }
  3299. }
  3300. exit:
  3301. return;
  3302. }
  3303. static int __init_subcaches(struct iris_hfi_device *device)
  3304. {
  3305. int rc = 0;
  3306. struct subcache_info *sinfo = NULL;
  3307. if (!device) {
  3308. dprintk(CVP_ERR, "init_subcaches: invalid device %pK\n",
  3309. device);
  3310. return -EINVAL;
  3311. }
  3312. if (!is_sys_cache_present(device))
  3313. return 0;
  3314. iris_hfi_for_each_subcache(device, sinfo) {
  3315. if (!strcmp("cvp", sinfo->name)) {
  3316. sinfo->subcache = llcc_slice_getd(LLCC_CVP);
  3317. } else if (!strcmp("cvpfw", sinfo->name)) {
  3318. sinfo->subcache = llcc_slice_getd(LLCC_CVPFW);
  3319. } else {
  3320. dprintk(CVP_ERR, "Invalid subcache name %s\n",
  3321. sinfo->name);
  3322. }
  3323. if (IS_ERR_OR_NULL(sinfo->subcache)) {
  3324. rc = PTR_ERR(sinfo->subcache) ?
  3325. PTR_ERR(sinfo->subcache) : -EBADHANDLE;
  3326. dprintk(CVP_ERR,
  3327. "init_subcaches: invalid subcache: %s rc %d\n",
  3328. sinfo->name, rc);
  3329. sinfo->subcache = NULL;
  3330. goto err_subcache_get;
  3331. }
  3332. dprintk(CVP_CORE, "init_subcaches: %s\n",
  3333. sinfo->name);
  3334. }
  3335. return 0;
  3336. err_subcache_get:
  3337. __deinit_subcaches(device);
  3338. return rc;
  3339. }
  3340. static int __init_resources(struct iris_hfi_device *device,
  3341. struct msm_cvp_platform_resources *res)
  3342. {
  3343. int i, rc = 0;
  3344. rc = __init_regulators(device);
  3345. if (rc) {
  3346. dprintk(CVP_ERR, "Failed to get all regulators\n");
  3347. return -ENODEV;
  3348. }
  3349. rc = msm_cvp_init_clocks(device);
  3350. if (rc) {
  3351. dprintk(CVP_ERR, "Failed to init clocks\n");
  3352. rc = -ENODEV;
  3353. goto err_init_clocks;
  3354. }
  3355. for (i = 0; i < device->res->reset_set.count; i++) {
  3356. rc = __init_reset_clk(res, i);
  3357. if (rc) {
  3358. dprintk(CVP_ERR, "Failed to init reset clocks\n");
  3359. rc = -ENODEV;
  3360. goto err_init_reset_clk;
  3361. }
  3362. }
  3363. rc = __init_bus(device);
  3364. if (rc) {
  3365. dprintk(CVP_ERR, "Failed to init bus: %d\n", rc);
  3366. goto err_init_bus;
  3367. }
  3368. rc = __init_subcaches(device);
  3369. if (rc)
  3370. dprintk(CVP_WARN, "Failed to init subcaches: %d\n", rc);
  3371. device->sys_init_capabilities =
  3372. kzalloc(sizeof(struct msm_cvp_capability)
  3373. * CVP_MAX_SESSIONS, GFP_KERNEL);
  3374. return rc;
  3375. err_init_reset_clk:
  3376. err_init_bus:
  3377. msm_cvp_deinit_clocks(device);
  3378. err_init_clocks:
  3379. __deinit_regulators(device);
  3380. return rc;
  3381. }
  3382. static void __deinit_resources(struct iris_hfi_device *device)
  3383. {
  3384. __deinit_subcaches(device);
  3385. __deinit_bus(device);
  3386. msm_cvp_deinit_clocks(device);
  3387. __deinit_regulators(device);
  3388. kfree(device->sys_init_capabilities);
  3389. device->sys_init_capabilities = NULL;
  3390. }
  3391. static int __disable_regulator_impl(struct regulator_info *rinfo,
  3392. struct iris_hfi_device *device)
  3393. {
  3394. int rc = 0;
  3395. dprintk(CVP_PWR, "Disabling regulator %s\n", rinfo->name);
  3396. /*
  3397. * This call is needed. Driver needs to acquire the control back
  3398. * from HW in order to disable the regualtor. Else the behavior
  3399. * is unknown.
  3400. */
  3401. rc = __acquire_regulator(rinfo, device);
  3402. if (rc) {
  3403. /*
  3404. * This is somewhat fatal, but nothing we can do
  3405. * about it. We can't disable the regulator w/o
  3406. * getting it back under s/w control
  3407. */
  3408. dprintk(CVP_WARN,
  3409. "Failed to acquire control on %s\n",
  3410. rinfo->name);
  3411. goto disable_regulator_failed;
  3412. }
  3413. rc = regulator_disable(rinfo->regulator);
  3414. if (rc) {
  3415. dprintk(CVP_WARN,
  3416. "Failed to disable %s: %d\n",
  3417. rinfo->name, rc);
  3418. goto disable_regulator_failed;
  3419. }
  3420. return 0;
  3421. disable_regulator_failed:
  3422. /* Bring attention to this issue */
  3423. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3424. return rc;
  3425. }
  3426. static int __disable_hw_power_collapse(struct iris_hfi_device *device)
  3427. {
  3428. int rc = 0;
  3429. if (!msm_cvp_fw_low_power_mode) {
  3430. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3431. return 0;
  3432. }
  3433. rc = __take_back_regulators(device);
  3434. if (rc)
  3435. dprintk(CVP_WARN,
  3436. "%s : Failed to disable HW power collapse %d\n",
  3437. __func__, rc);
  3438. return rc;
  3439. }
  3440. static int __enable_hw_power_collapse(struct iris_hfi_device *device)
  3441. {
  3442. int rc = 0;
  3443. if (!msm_cvp_fw_low_power_mode) {
  3444. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3445. return 0;
  3446. }
  3447. rc = __hand_off_regulators(device);
  3448. if (rc)
  3449. dprintk(CVP_WARN,
  3450. "%s : Failed to enable HW power collapse %d\n",
  3451. __func__, rc);
  3452. return rc;
  3453. }
  3454. static int __enable_regulator(struct iris_hfi_device *device,
  3455. const char *name)
  3456. {
  3457. int rc = 0;
  3458. struct regulator_info *rinfo;
  3459. iris_hfi_for_each_regulator(device, rinfo) {
  3460. if (strcmp(rinfo->name, name))
  3461. continue;
  3462. rc = regulator_enable(rinfo->regulator);
  3463. if (rc) {
  3464. dprintk(CVP_ERR, "Failed to enable %s: %d\n",
  3465. rinfo->name, rc);
  3466. return rc;
  3467. }
  3468. if (!regulator_is_enabled(rinfo->regulator)) {
  3469. dprintk(CVP_ERR,"%s: regulator %s not enabled\n",
  3470. __func__, rinfo->name);
  3471. regulator_disable(rinfo->regulator);
  3472. return -EINVAL;
  3473. }
  3474. dprintk(CVP_PWR, "Enabled regulator %s\n", rinfo->name);
  3475. return 0;
  3476. }
  3477. dprintk(CVP_ERR, "regulator %s not found\n", name);
  3478. return -EINVAL;
  3479. }
  3480. static int __disable_regulator(struct iris_hfi_device *device,
  3481. const char *name)
  3482. {
  3483. struct regulator_info *rinfo;
  3484. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3485. if (strcmp(rinfo->name, name))
  3486. continue;
  3487. __disable_regulator_impl(rinfo, device);
  3488. dprintk(CVP_PWR, "%s Disabled regulator %s\n", __func__, name);
  3489. return 0;
  3490. }
  3491. dprintk(CVP_ERR, "%s regulator %s not found\n", __func__, name);
  3492. return -EINVAL;
  3493. }
  3494. static int __enable_subcaches(struct iris_hfi_device *device)
  3495. {
  3496. int rc = 0;
  3497. u32 c = 0;
  3498. struct subcache_info *sinfo;
  3499. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3500. return 0;
  3501. /* Activate subcaches */
  3502. iris_hfi_for_each_subcache(device, sinfo) {
  3503. rc = llcc_slice_activate(sinfo->subcache);
  3504. if (rc) {
  3505. dprintk(CVP_WARN, "Failed to activate %s: %d\n",
  3506. sinfo->name, rc);
  3507. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3508. goto err_activate_fail;
  3509. }
  3510. sinfo->isactive = true;
  3511. dprintk(CVP_CORE, "Activated subcache %s\n", sinfo->name);
  3512. c++;
  3513. }
  3514. dprintk(CVP_CORE, "Activated %d Subcaches to CVP\n", c);
  3515. return 0;
  3516. err_activate_fail:
  3517. __release_subcaches(device);
  3518. __disable_subcaches(device);
  3519. return 0;
  3520. }
  3521. static int __set_subcaches(struct iris_hfi_device *device)
  3522. {
  3523. int rc = 0;
  3524. u32 c = 0;
  3525. struct subcache_info *sinfo;
  3526. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3527. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3528. struct cvp_hfi_resource_subcache_type *sc_res;
  3529. struct cvp_resource_hdr rhdr;
  3530. if (device->res->sys_cache_res_set || msm_cvp_syscache_disable) {
  3531. dprintk(CVP_CORE, "Subcaches already set or disabled\n");
  3532. return 0;
  3533. }
  3534. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3535. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3536. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3537. iris_hfi_for_each_subcache(device, sinfo) {
  3538. if (sinfo->isactive) {
  3539. sc_res[c].size = sinfo->subcache->slice_size;
  3540. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3541. c++;
  3542. }
  3543. }
  3544. /* Set resource to CVP for activated subcaches */
  3545. if (c) {
  3546. dprintk(CVP_CORE, "Setting %d Subcaches\n", c);
  3547. rhdr.resource_handle = sc_res_info; /* cookie */
  3548. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3549. sc_res_info->num_entries = c;
  3550. rc = __core_set_resource(device, &rhdr, (void *)sc_res_info);
  3551. if (rc) {
  3552. dprintk(CVP_WARN, "Failed to set subcaches %d\n", rc);
  3553. goto err_fail_set_subacaches;
  3554. }
  3555. iris_hfi_for_each_subcache(device, sinfo) {
  3556. if (sinfo->isactive)
  3557. sinfo->isset = true;
  3558. }
  3559. dprintk(CVP_CORE, "Set Subcaches done to CVP\n");
  3560. device->res->sys_cache_res_set = true;
  3561. }
  3562. return 0;
  3563. err_fail_set_subacaches:
  3564. __disable_subcaches(device);
  3565. return 0;
  3566. }
  3567. static int __release_subcaches(struct iris_hfi_device *device)
  3568. {
  3569. struct subcache_info *sinfo;
  3570. int rc = 0;
  3571. u32 c = 0;
  3572. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3573. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3574. struct cvp_hfi_resource_subcache_type *sc_res;
  3575. struct cvp_resource_hdr rhdr;
  3576. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3577. return 0;
  3578. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3579. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3580. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3581. /* Release resource command to Iris */
  3582. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3583. if (sinfo->isset) {
  3584. /* Update the entry */
  3585. sc_res[c].size = sinfo->subcache->slice_size;
  3586. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3587. c++;
  3588. sinfo->isset = false;
  3589. }
  3590. }
  3591. if (c > 0) {
  3592. dprintk(CVP_CORE, "Releasing %d subcaches\n", c);
  3593. rhdr.resource_handle = sc_res_info; /* cookie */
  3594. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3595. rc = __core_release_resource(device, &rhdr);
  3596. if (rc)
  3597. dprintk(CVP_WARN,
  3598. "Failed to release %d subcaches\n", c);
  3599. }
  3600. device->res->sys_cache_res_set = false;
  3601. return 0;
  3602. }
  3603. static int __disable_subcaches(struct iris_hfi_device *device)
  3604. {
  3605. struct subcache_info *sinfo;
  3606. int rc = 0;
  3607. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3608. return 0;
  3609. /* De-activate subcaches */
  3610. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3611. if (sinfo->isactive) {
  3612. dprintk(CVP_CORE, "De-activate subcache %s\n",
  3613. sinfo->name);
  3614. rc = llcc_slice_deactivate(sinfo->subcache);
  3615. if (rc) {
  3616. dprintk(CVP_WARN,
  3617. "Failed to de-activate %s: %d\n",
  3618. sinfo->name, rc);
  3619. }
  3620. sinfo->isactive = false;
  3621. }
  3622. }
  3623. return 0;
  3624. }
  3625. static void interrupt_init_iris2(struct iris_hfi_device *device)
  3626. {
  3627. u32 mask_val = 0;
  3628. /* All interrupts should be disabled initially 0x1F6 : Reset value */
  3629. mask_val = __read_register(device, CVP_WRAPPER_INTR_MASK);
  3630. /* Write 0 to unmask CPU and WD interrupts */
  3631. mask_val &= ~(CVP_FATAL_INTR_BMSK | CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK);
  3632. __write_register(device, CVP_WRAPPER_INTR_MASK, mask_val);
  3633. dprintk(CVP_REG, "Init irq: reg: %x, mask value %x\n",
  3634. CVP_WRAPPER_INTR_MASK, mask_val);
  3635. mask_val = 0;
  3636. mask_val = __read_register(device, CVP_SS_IRQ_MASK);
  3637. mask_val &= ~(CVP_SS_INTR_BMASK);
  3638. __write_register(device, CVP_SS_IRQ_MASK, mask_val);
  3639. dprintk(CVP_REG, "Init irq_wd: reg: %x, mask value %x\n",
  3640. CVP_SS_IRQ_MASK, mask_val);
  3641. }
  3642. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device)
  3643. {
  3644. /* initialize DSP QTBL & UCREGION with CPU queues */
  3645. __write_register(device, HFI_DSP_QTBL_ADDR,
  3646. (u32)device->dsp_iface_q_table.align_device_addr);
  3647. __write_register(device, HFI_DSP_UC_REGION_ADDR,
  3648. (u32)device->dsp_iface_q_table.align_device_addr);
  3649. __write_register(device, HFI_DSP_UC_REGION_SIZE,
  3650. device->dsp_iface_q_table.mem_data.size);
  3651. }
  3652. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device)
  3653. {
  3654. __write_register(device, CVP_WRAPPER_CPU_CLOCK_CONFIG, 0);
  3655. }
  3656. static int __set_ubwc_config(struct iris_hfi_device *device)
  3657. {
  3658. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  3659. int rc = 0;
  3660. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  3661. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  3662. if (!device->res->ubwc_config)
  3663. return 0;
  3664. rc = call_hfi_pkt_op(device, sys_ubwc_config, pkt,
  3665. device->res->ubwc_config);
  3666. if (rc) {
  3667. dprintk(CVP_WARN,
  3668. "ubwc config setting to FW failed\n");
  3669. rc = -ENOTEMPTY;
  3670. goto fail_to_set_ubwc_config;
  3671. }
  3672. if (__iface_cmdq_write(device, pkt)) {
  3673. rc = -ENOTEMPTY;
  3674. goto fail_to_set_ubwc_config;
  3675. }
  3676. fail_to_set_ubwc_config:
  3677. return rc;
  3678. }
  3679. static int __power_on_controller(struct iris_hfi_device *device)
  3680. {
  3681. int rc = 0;
  3682. rc = __enable_regulator(device, "cvp");
  3683. if (rc) {
  3684. dprintk(CVP_ERR, "Failed to enable ctrler: %d\n", rc);
  3685. return rc;
  3686. }
  3687. rc = msm_cvp_prepare_enable_clk(device, "sleep_clk");
  3688. if (rc) {
  3689. dprintk(CVP_ERR, "Failed to enable sleep clk: %d\n", rc);
  3690. goto fail_reset_clks;
  3691. }
  3692. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_axi_reset");
  3693. if (rc)
  3694. dprintk(CVP_ERR, "%s: assert cvp_axi_reset failed\n", __func__);
  3695. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_core_reset");
  3696. if (rc)
  3697. dprintk(CVP_ERR, "%s: assert cvp_core_reset failed\n", __func__);
  3698. /* wait for deassert */
  3699. usleep_range(300, 400);
  3700. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_axi_reset");
  3701. if (rc)
  3702. dprintk(CVP_ERR, "%s: de-assert cvp_axi_reset failed\n", __func__);
  3703. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_core_reset");
  3704. if (rc)
  3705. dprintk(CVP_ERR, "%s: de-assert cvp_core_reset failed\n", __func__);
  3706. rc = msm_cvp_prepare_enable_clk(device, "gcc_video_axi1");
  3707. if (rc) {
  3708. dprintk(CVP_ERR, "Failed to enable axi1 clk: %d\n", rc);
  3709. goto fail_reset_clks;
  3710. }
  3711. rc = msm_cvp_prepare_enable_clk(device, "cvp_clk");
  3712. if (rc) {
  3713. dprintk(CVP_ERR, "Failed to enable cvp_clk: %d\n", rc);
  3714. goto fail_enable_clk;
  3715. }
  3716. dprintk(CVP_PWR, "EVA controller powered on\n");
  3717. return 0;
  3718. fail_enable_clk:
  3719. msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
  3720. fail_reset_clks:
  3721. __disable_regulator(device, "cvp");
  3722. return rc;
  3723. }
  3724. static int __power_on_core(struct iris_hfi_device *device)
  3725. {
  3726. int rc = 0;
  3727. rc = __enable_regulator(device, "cvp-core");
  3728. if (rc) {
  3729. dprintk(CVP_ERR, "Failed to enable core: %d\n", rc);
  3730. return rc;
  3731. }
  3732. rc = msm_cvp_prepare_enable_clk(device, "video_cc_mvs1_clk_src");
  3733. if (rc) {
  3734. dprintk(CVP_ERR, "Failed to enable video_cc_mvs1_clk_src:%d\n",
  3735. rc);
  3736. __disable_regulator(device, "cvp-core");
  3737. return rc;
  3738. }
  3739. rc = msm_cvp_prepare_enable_clk(device, "core_clk");
  3740. if (rc) {
  3741. dprintk(CVP_ERR, "Failed to enable core_clk: %d\n", rc);
  3742. __disable_regulator(device, "cvp-core");
  3743. return rc;
  3744. }
  3745. /*#ifdef CONFIG_EVA_PINEAPPLE
  3746. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_ARCG_CONTROL, 0);
  3747. __write_register(device, CVP_NOC_RCGCONTROLLER_HYSTERESIS_LOW, 0x2f);
  3748. __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 1);
  3749. __write_register(device, CVP_NOC_RCGCONTROLLER_MAINCTL_LOW, 1);
  3750. usleep_range(50, 100);
  3751. __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 0);
  3752. #endif*/
  3753. dprintk(CVP_PWR, "EVA core powered on\n");
  3754. return 0;
  3755. }
  3756. static int __iris_power_on(struct iris_hfi_device *device)
  3757. {
  3758. int rc = 0;
  3759. u32 reg_gdsc, reg_cbcr, spare_val;
  3760. if (device->power_enabled)
  3761. return 0;
  3762. /* Vote for all hardware resources */
  3763. rc = __vote_buses(device, device->bus_vote.data,
  3764. device->bus_vote.data_count);
  3765. if (rc) {
  3766. dprintk(CVP_ERR, "Failed to vote buses, err: %d\n", rc);
  3767. goto fail_vote_buses;
  3768. }
  3769. rc = __power_on_controller(device);
  3770. if (rc)
  3771. goto fail_enable_controller;
  3772. rc = __power_on_core(device);
  3773. if (rc)
  3774. goto fail_enable_core;
  3775. rc = msm_cvp_scale_clocks(device);
  3776. if (rc) {
  3777. dprintk(CVP_WARN,
  3778. "Failed to scale clocks, perf may regress\n");
  3779. rc = 0;
  3780. } else {
  3781. dprintk(CVP_PWR, "Done with scaling\n");
  3782. }
  3783. /*Do not access registers before this point!*/
  3784. device->power_enabled = true;
  3785. /*
  3786. * Re-program all of the registers that get reset as a result of
  3787. * regulator_disable() and _enable()
  3788. * calling below function requires CORE powered on
  3789. */
  3790. rc = __set_registers(device);
  3791. if (rc)
  3792. goto fail_enable_core;
  3793. dprintk(CVP_CORE, "Done with register set\n");
  3794. reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
  3795. reg_cbcr = __read_register(device, CVP_CC_MVS1_CBCR);
  3796. if (!(reg_gdsc & 0x80000000) || (reg_cbcr & 0x80000000)) {
  3797. rc = -EINVAL;
  3798. dprintk(CVP_ERR, "CORE power on failed gdsc %x cbcr %x\n",
  3799. reg_gdsc, reg_cbcr);
  3800. goto fail_enable_core;
  3801. }
  3802. reg_gdsc = __read_register(device, CVP_CC_MVS1C_GDSCR);
  3803. reg_cbcr = __read_register(device, CVP_CC_MVS1C_CBCR);
  3804. if (!(reg_gdsc & 0x80000000) || (reg_cbcr & 0x80000000)) {
  3805. rc = -EINVAL;
  3806. dprintk(CVP_ERR, "CTRL power on failed gdsc %x cbcr %x\n",
  3807. reg_gdsc, reg_cbcr);
  3808. goto fail_enable_core;
  3809. }
  3810. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  3811. if ((spare_val & 0x2) != 0) {
  3812. usleep_range(2000, 3000);
  3813. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  3814. if ((spare_val & 0x2) != 0) {
  3815. dprintk(CVP_ERR, "WRAPPER_SPARE non-zero %#x\n", spare_val);
  3816. rc = -EINVAL;
  3817. goto fail_enable_core;
  3818. }
  3819. }
  3820. call_iris_op(device, interrupt_init, device);
  3821. dprintk(CVP_CORE, "Done with interrupt enabling\n");
  3822. device->intr_status = 0;
  3823. enable_irq(device->cvp_hal_data->irq);
  3824. __write_register(device,
  3825. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x7);
  3826. pr_info_ratelimited(CVP_DBG_TAG "cvp (eva) powered on\n", "pwr");
  3827. return 0;
  3828. fail_enable_core:
  3829. __power_off_controller(device);
  3830. fail_enable_controller:
  3831. __unvote_buses(device);
  3832. fail_vote_buses:
  3833. device->power_enabled = false;
  3834. return rc;
  3835. }
  3836. static inline int __suspend(struct iris_hfi_device *device)
  3837. {
  3838. int rc = 0;
  3839. if (!device) {
  3840. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  3841. return -EINVAL;
  3842. } else if (!device->power_enabled) {
  3843. dprintk(CVP_PWR, "Power already disabled\n");
  3844. return 0;
  3845. }
  3846. dprintk(CVP_PWR, "Entering suspend\n");
  3847. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  3848. if (rc) {
  3849. dprintk(CVP_WARN, "Failed to suspend cvp core %d\n", rc);
  3850. goto err_tzbsp_suspend;
  3851. }
  3852. __disable_subcaches(device);
  3853. call_iris_op(device, power_off, device);
  3854. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  3855. cvp_pm_qos_update(device, false);
  3856. return rc;
  3857. err_tzbsp_suspend:
  3858. return rc;
  3859. }
  3860. static void __print_sidebandmanager_regs(struct iris_hfi_device *device)
  3861. {
  3862. u32 sbm_ln0_low, axi_cbcr;
  3863. u32 main_sbm_ln0_low = 0xdeadbeef, main_sbm_ln0_high = 0xdeadbeef;
  3864. u32 main_sbm_ln1_high = 0xdeadbeef, cpu_cs_x2rpmh;
  3865. int rc;
  3866. sbm_ln0_low =
  3867. __read_register(device, CVP_NOC_SBM_SENSELN0_LOW);
  3868. cpu_cs_x2rpmh = __read_register(device, CVP_CPU_CS_X2RPMh);
  3869. __write_register(device, CVP_CPU_CS_X2RPMh,
  3870. (cpu_cs_x2rpmh | CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK));
  3871. usleep_range(500, 1000);
  3872. cpu_cs_x2rpmh = __read_register(device, CVP_CPU_CS_X2RPMh);
  3873. if (!(cpu_cs_x2rpmh & CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK)) {
  3874. dprintk(CVP_WARN,
  3875. "failed set CVP_CPU_CS_X2RPMH mask %x\n",
  3876. cpu_cs_x2rpmh);
  3877. goto exit;
  3878. }
  3879. axi_cbcr = __read_gcc_register(device, CVP_GCC_VIDEO_AXI1_CBCR);
  3880. if (axi_cbcr & 0x80000000) {
  3881. dprintk(CVP_WARN, "failed to turn on AXI clock %x\n",
  3882. axi_cbcr);
  3883. goto exit;
  3884. }
  3885. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  3886. if (rc) {
  3887. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  3888. goto exit;
  3889. }
  3890. main_sbm_ln0_low = __read_register(device,
  3891. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_LOW);
  3892. main_sbm_ln0_high = __read_register(device,
  3893. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_HIGH);
  3894. main_sbm_ln1_high = __read_register(device,
  3895. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN1_HIGH);
  3896. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  3897. exit:
  3898. cpu_cs_x2rpmh = cpu_cs_x2rpmh & (~CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK);
  3899. __write_register(device, CVP_CPU_CS_X2RPMh, cpu_cs_x2rpmh);
  3900. dprintk(CVP_WARN, "Sidebandmanager regs %x %x %x %x %x\n",
  3901. sbm_ln0_low, main_sbm_ln0_low,
  3902. main_sbm_ln0_high, main_sbm_ln1_high,
  3903. cpu_cs_x2rpmh);
  3904. }
  3905. static int __power_off_controller(struct iris_hfi_device *device)
  3906. {
  3907. u32 lpi_status, reg_status = 0, count = 0, max_count = 1000;
  3908. u32 sbm_ln0_low;
  3909. int rc;
  3910. u32 spare_val, spare_status;
  3911. /* HPG 6.2.2 Step 1 */
  3912. __write_register(device, CVP_CPU_CS_X2RPMh, 0x3);
  3913. /* HPG 6.2.2 Step 2, noc to low power */
  3914. /* New addition to put CPU/Tensilica to low power */
  3915. reg_status = 0;
  3916. count = 0;
  3917. __write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x1);
  3918. while (!reg_status && count < max_count) {
  3919. lpi_status =
  3920. __read_register(device,
  3921. CVP_WRAPPER_CPU_NOC_LPI_STATUS);
  3922. reg_status = lpi_status & BIT(0);
  3923. /* Wait for CPU noc lpi status to be set */
  3924. usleep_range(50, 100);
  3925. count++;
  3926. }
  3927. sbm_ln0_low = __read_register(device, CVP_NOC_SBM_SENSELN0_LOW);
  3928. dprintk(CVP_PWR,
  3929. "CPU Noc: lpi_status %x noc_status %x (count %d) 0x%x\n",
  3930. lpi_status, reg_status, count, sbm_ln0_low);
  3931. if (count == max_count) {
  3932. u32 pc_ready, wfi_status;
  3933. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  3934. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  3935. dprintk(CVP_WARN,
  3936. "CPU NOC not in qaccept status %x %x %x %x\n",
  3937. reg_status, lpi_status, wfi_status, pc_ready);
  3938. __print_sidebandmanager_regs(device);
  3939. }
  3940. /* HPG 6.2.2 Step 3, debug bridge to low power BYPASSED */
  3941. /* HPG 6.2.2 Step 4, debug bridge to lpi release */
  3942. __write_register(device,
  3943. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x0);
  3944. lpi_status = 0x1;
  3945. count = 0;
  3946. while (lpi_status && count < max_count) {
  3947. lpi_status = __read_register(device,
  3948. CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
  3949. usleep_range(50, 100);
  3950. count++;
  3951. }
  3952. dprintk(CVP_PWR,
  3953. "DBLP Release: lpi_status %d(count %d)\n",
  3954. lpi_status, count);
  3955. if (count == max_count) {
  3956. dprintk(CVP_WARN,
  3957. "DBLP Release: lpi_status %x\n", lpi_status);
  3958. }
  3959. /* PDXFIFO reset: addition for Kailua / Lanai */
  3960. __write_register(device, CVP_WRAPPER_AXI_CLOCK_CONFIG, 0x3);
  3961. __write_register(device, CVP_WRAPPER_QNS4PDXFIFO_RESET, 0x1);
  3962. __write_register(device, CVP_WRAPPER_QNS4PDXFIFO_RESET, 0x0);
  3963. __write_register(device, CVP_WRAPPER_AXI_CLOCK_CONFIG, 0x0);
  3964. /* HPG 6.2.2 Step 5 */
  3965. msm_cvp_disable_unprepare_clk(device, "cvp_clk");
  3966. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_axi_reset");
  3967. if (rc)
  3968. dprintk(CVP_ERR, "%s: assert cvp_axi_reset failed\n", __func__);
  3969. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_core_reset");
  3970. if (rc)
  3971. dprintk(CVP_ERR, "%s: assert cvp_core_reset failed\n", __func__);
  3972. /* wait for deassert */
  3973. usleep_range(1000, 1050);
  3974. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_axi_reset");
  3975. if (rc)
  3976. dprintk(CVP_ERR, "%s: de-assert cvp_axi_reset failed\n", __func__);
  3977. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_core_reset");
  3978. if (rc)
  3979. dprintk(CVP_ERR, "%s: de-assert cvp_core_reset failed\n", __func__);
  3980. /* disable EVA NoC clock */
  3981. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL, 0x1);
  3982. /* enable EVA NoC reset */
  3983. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_SW_RESET, 0x1);
  3984. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  3985. if (rc) {
  3986. dprintk(CVP_ERR, "FATAL ERROR, HPG step 17 to 20 will be bypassed\n");
  3987. goto skip_xo_reset;
  3988. }
  3989. spare_status = 0x1;
  3990. while (spare_status != 0x0) {
  3991. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  3992. spare_status = spare_val & 0x2;
  3993. usleep_range(50, 100);
  3994. }
  3995. __write_register(device, CVP_AON_WRAPPER_SPARE, 0x1);
  3996. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_xo_reset");
  3997. if (rc)
  3998. dprintk(CVP_ERR, "%s: assert cvp_xo_reset failed\n", __func__);
  3999. /* de-assert EVA_NoC reset */
  4000. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_SW_RESET, 0x0);
  4001. /* de-assert EVA video_cc XO reset and enable video_cc XO clock after 125us */
  4002. usleep_range(200, 300);
  4003. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_xo_reset");
  4004. if (rc)
  4005. dprintk(CVP_ERR, "%s: de-assert cvp_xo_reset failed\n", __func__);
  4006. /* clear XO mask bit - this step was missing in previous sequence */
  4007. __write_register(device, CVP_AON_WRAPPER_SPARE, 0x0);
  4008. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4009. skip_xo_reset:
  4010. /* enable EVA NoC clock */
  4011. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL, 0x0);
  4012. /* De-assert EVA_CTL Force Sleep Retention */
  4013. usleep_range(400, 500);
  4014. /* HPG 6.2.2 Step 6 */
  4015. __disable_regulator(device, "cvp");
  4016. /* HPG 6.2.2 Step 7 */
  4017. rc = msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
  4018. if (rc) {
  4019. dprintk(CVP_ERR, "Failed to enable axi1 clk: %d\n", rc);
  4020. }
  4021. rc = msm_cvp_disable_unprepare_clk(device, "sleep_clk");
  4022. if (rc) {
  4023. dprintk(CVP_ERR, "Failed to disable sleep clk: %d\n", rc);
  4024. }
  4025. return 0;
  4026. }
  4027. static int __power_off_core(struct iris_hfi_device *device)
  4028. {
  4029. u32 reg_status = 0, lpi_status, config, value = 0, count = 0;
  4030. u32 warn_flag = 0, max_count = 10;
  4031. value = __read_register(device, CVP_CC_MVS1_GDSCR);
  4032. if (!(value & 0x80000000)) {
  4033. /*
  4034. * Core has been powered off by f/w.
  4035. * Check NOC reset registers to ensure
  4036. * NO outstanding NoC transactions
  4037. */
  4038. value = __read_register(device, CVP_NOC_RESET_ACK);
  4039. if (value) {
  4040. dprintk(CVP_WARN,
  4041. "Core off with NOC RESET ACK non-zero %x\n",
  4042. value);
  4043. __print_sidebandmanager_regs(device);
  4044. }
  4045. __disable_regulator(device, "cvp-core");
  4046. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4047. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4048. return 0;
  4049. } else if (!(value & 0x2)) {
  4050. /*
  4051. * HW_CONTROL PC disabled, then core is powered on for
  4052. * CVP NoC access
  4053. */
  4054. __disable_regulator(device, "cvp-core");
  4055. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4056. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4057. return 0;
  4058. }
  4059. dprintk(CVP_PWR, "Driver controls Core power off now\n");
  4060. /*
  4061. * check to make sure core clock branch enabled else
  4062. * we cannot read core idle register
  4063. */
  4064. config = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4065. if (config) {
  4066. dprintk(CVP_PWR,
  4067. "core clock config not enabled, enable it to access core\n");
  4068. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0);
  4069. }
  4070. /*
  4071. * add MNoC idle check before collapsing MVS1 per HPG update
  4072. * poll for NoC DMA idle -> HPG 6.2.1
  4073. *
  4074. */
  4075. do {
  4076. value = __read_register(device, CVP_SS_IDLE_STATUS);
  4077. if (value & 0x400000)
  4078. break;
  4079. else
  4080. usleep_range(1000, 2000);
  4081. count++;
  4082. } while (count < max_count);
  4083. if (count == max_count) {
  4084. dprintk(CVP_WARN, "Core fail to go idle %x\n", value);
  4085. warn_flag = 1;
  4086. }
  4087. count = 0;
  4088. max_count = 1000;
  4089. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x1);
  4090. while (!reg_status && count < max_count) {
  4091. lpi_status =
  4092. __read_register(device,
  4093. CVP_AON_WRAPPER_CVP_NOC_LPI_STATUS);
  4094. reg_status = lpi_status & BIT(0);
  4095. /* Wait for Core noc lpi status to be set */
  4096. usleep_range(50, 100);
  4097. count++;
  4098. }
  4099. dprintk(CVP_PWR,
  4100. "Core Noc: lpi_status %x noc_status %x (count %d)\n",
  4101. lpi_status, reg_status, count);
  4102. if (count == max_count) {
  4103. u32 pc_ready, wfi_status;
  4104. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  4105. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  4106. dprintk(CVP_WARN,
  4107. "Core NOC not in qaccept status %x %x %x %x\n",
  4108. reg_status, lpi_status, wfi_status, pc_ready);
  4109. __print_sidebandmanager_regs(device);
  4110. }
  4111. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x0);
  4112. if (warn_flag)
  4113. __print_sidebandmanager_regs(device);
  4114. /* Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ) */
  4115. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x3);
  4116. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x2);
  4117. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x0);
  4118. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, config);
  4119. __disable_hw_power_collapse(device);
  4120. usleep_range(100, 200);
  4121. __disable_regulator(device, "cvp-core");
  4122. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4123. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4124. return 0;
  4125. }
  4126. static void power_off_iris2(struct iris_hfi_device *device)
  4127. {
  4128. if (!device->power_enabled || !device->res->sw_power_collapsible)
  4129. return;
  4130. if (!(device->intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  4131. disable_irq_nosync(device->cvp_hal_data->irq);
  4132. device->intr_status = 0;
  4133. __power_off_core(device);
  4134. __power_off_controller(device);
  4135. if (__unvote_buses(device))
  4136. dprintk(CVP_WARN, "Failed to unvote for buses\n");
  4137. /*Do not access registers after this point!*/
  4138. device->power_enabled = false;
  4139. pr_info(CVP_DBG_TAG "cvp (eva) power collapsed\n", "pwr");
  4140. }
  4141. static inline int __resume(struct iris_hfi_device *device)
  4142. {
  4143. int rc = 0;
  4144. struct msm_cvp_core *core;
  4145. if (!device) {
  4146. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  4147. return -EINVAL;
  4148. } else if (device->power_enabled) {
  4149. goto exit;
  4150. } else if (!__core_in_valid_state(device)) {
  4151. dprintk(CVP_PWR, "iris_hfi_device in deinit state.");
  4152. return -EINVAL;
  4153. }
  4154. core = cvp_driver->cvp_core;
  4155. dprintk(CVP_PWR, "Resuming from power collapse\n");
  4156. rc = __iris_power_on(device);
  4157. if (rc) {
  4158. dprintk(CVP_ERR, "Failed to power on cvp\n");
  4159. goto err_iris_power_on;
  4160. }
  4161. __setup_ucregion_memory_map(device);
  4162. /* RUMI: set CVP_CTRL_INIT register to disable synx in FW */
  4163. /* Reboot the firmware */
  4164. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESUME);
  4165. if (rc) {
  4166. dprintk(CVP_ERR, "Failed to resume cvp core %d\n", rc);
  4167. goto err_set_cvp_state;
  4168. }
  4169. /* Wait for boot completion */
  4170. rc = __boot_firmware(device);
  4171. if (rc) {
  4172. dprintk(CVP_ERR, "Failed to reset cvp core\n");
  4173. goto err_reset_core;
  4174. }
  4175. /*
  4176. * Work around for H/W bug, need to reprogram these registers once
  4177. * firmware is out reset
  4178. */
  4179. __set_threshold_registers(device);
  4180. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  4181. cvp_pm_qos_update(device, true);
  4182. __sys_set_debug(device, msm_cvp_fw_debug);
  4183. __enable_subcaches(device);
  4184. __set_subcaches(device);
  4185. __dsp_resume(device);
  4186. dprintk(CVP_PWR, "Resumed from power collapse\n");
  4187. exit:
  4188. /* Don't reset skip_pc_count for SYS_PC_PREP cmd */
  4189. if (device->last_packet_type != HFI_CMD_SYS_PC_PREP)
  4190. device->skip_pc_count = 0;
  4191. return rc;
  4192. err_reset_core:
  4193. __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  4194. err_set_cvp_state:
  4195. call_iris_op(device, power_off, device);
  4196. err_iris_power_on:
  4197. dprintk(CVP_ERR, "Failed to resume from power collapse\n");
  4198. return rc;
  4199. }
  4200. static int __power_on_init(struct iris_hfi_device *device)
  4201. {
  4202. int rc = 0;
  4203. /* Initialize resources */
  4204. rc = __init_resources(device, device->res);
  4205. if (rc) {
  4206. dprintk(CVP_ERR, "Failed to init resources: %d\n", rc);
  4207. return rc;
  4208. }
  4209. rc = __initialize_packetization(device);
  4210. if (rc) {
  4211. dprintk(CVP_ERR, "Failed to initialize packetization\n");
  4212. goto fail_iris_init;
  4213. }
  4214. rc = __iris_power_on(device);
  4215. if (rc) {
  4216. dprintk(CVP_ERR, "Failed to power on iris in in load_fw\n");
  4217. goto fail_iris_init;
  4218. }
  4219. return rc;
  4220. fail_iris_init:
  4221. __deinit_resources(device);
  4222. return rc;
  4223. }
  4224. static int __load_fw(struct iris_hfi_device *device)
  4225. {
  4226. int rc = 0;
  4227. if ((!device->res->use_non_secure_pil && !device->res->firmware_base)
  4228. || device->res->use_non_secure_pil) {
  4229. rc = load_cvp_fw_impl(device);
  4230. if (rc)
  4231. goto fail_load_fw;
  4232. }
  4233. return rc;
  4234. fail_load_fw:
  4235. call_iris_op(device, power_off, device);
  4236. return rc;
  4237. }
  4238. static void __unload_fw(struct iris_hfi_device *device)
  4239. {
  4240. if (!device->resources.fw.cookie)
  4241. return;
  4242. cancel_delayed_work(&iris_hfi_pm_work);
  4243. if (device->state != IRIS_STATE_DEINIT)
  4244. flush_workqueue(device->iris_pm_workq);
  4245. unload_cvp_fw_impl(device);
  4246. __interface_queues_release(device);
  4247. call_iris_op(device, power_off, device);
  4248. __deinit_resources(device);
  4249. dprintk(CVP_WARN, "Firmware unloaded\n");
  4250. }
  4251. static int iris_hfi_get_fw_info(void *dev, struct cvp_hal_fw_info *fw_info)
  4252. {
  4253. int i = 0;
  4254. struct iris_hfi_device *device = dev;
  4255. if (!device || !fw_info) {
  4256. dprintk(CVP_ERR,
  4257. "%s Invalid parameter: device = %pK fw_info = %pK\n",
  4258. __func__, device, fw_info);
  4259. return -EINVAL;
  4260. }
  4261. mutex_lock(&device->lock);
  4262. while (cvp_driver->fw_version[i++] != 'V' && i < CVP_VERSION_LENGTH)
  4263. ;
  4264. if (i == CVP_VERSION_LENGTH - 1) {
  4265. dprintk(CVP_WARN, "Iris version string is not proper\n");
  4266. fw_info->version[0] = '\0';
  4267. goto fail_version_string;
  4268. }
  4269. memcpy(&fw_info->version[0], &cvp_driver->fw_version[0],
  4270. CVP_VERSION_LENGTH);
  4271. fw_info->version[CVP_VERSION_LENGTH - 1] = '\0';
  4272. fail_version_string:
  4273. dprintk(CVP_CORE, "F/W version retrieved : %s\n", fw_info->version);
  4274. fw_info->base_addr = device->cvp_hal_data->firmware_base;
  4275. fw_info->register_base = device->res->register_base;
  4276. fw_info->register_size = device->cvp_hal_data->register_size;
  4277. fw_info->irq = device->cvp_hal_data->irq;
  4278. mutex_unlock(&device->lock);
  4279. return 0;
  4280. }
  4281. static int iris_hfi_get_core_capabilities(void *dev)
  4282. {
  4283. dprintk(CVP_CORE, "%s not supported yet!\n", __func__);
  4284. return 0;
  4285. }
  4286. static const char * const mid_names[16] = {
  4287. "CVP_FW",
  4288. "ARP_DATA",
  4289. "CVP_MPU_PIXEL",
  4290. "CVP_MPU_NON_PIXEL",
  4291. "CVP_FDU_PIXEL",
  4292. "CVP_FDU_NON_PIXEL",
  4293. "CVP_GCE_PIXEL",
  4294. "CVP_GCE_NON_PIXEL",
  4295. "CVP_TOF_PIXEL",
  4296. "CVP_TOF_NON_PIXEL",
  4297. "CVP_VADL_PIXEL",
  4298. "CVP_VADL_NON_PIXEL",
  4299. "CVP_RGE_NON_PIXEL",
  4300. "CVP_CDM",
  4301. "Invalid",
  4302. "Invalid"
  4303. };
  4304. static void __print_reg_details(u32 val)
  4305. {
  4306. u32 mid, sid;
  4307. mid = (val >> 5) & 0xF;
  4308. sid = (val >> 2) & 0x7;
  4309. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
  4310. dprintk(CVP_ERR, "Sub-client:%s, SID: %d\n", mid_names[mid], sid);
  4311. }
  4312. static void __err_log(bool logging, u32 *data, const char *name, u32 val)
  4313. {
  4314. if (logging)
  4315. *data = val;
  4316. dprintk(CVP_ERR, "%s: %#x\n", name, val);
  4317. }
  4318. static void __noc_error_info_iris2(struct iris_hfi_device *device)
  4319. {
  4320. struct msm_cvp_core *core;
  4321. struct cvp_noc_log *noc_log;
  4322. u32 val = 0, regi, regii, regiii;
  4323. bool log_required = false;
  4324. int rc;
  4325. core = cvp_driver->cvp_core;
  4326. if (!core->ssr_count && core->resources.max_ssr_allowed > 1)
  4327. log_required = true;
  4328. noc_log = &core->log.noc_log;
  4329. if (noc_log->used) {
  4330. dprintk(CVP_WARN, "Data already in NoC log, skip logging\n");
  4331. return;
  4332. }
  4333. noc_log->used = 1;
  4334. __disable_hw_power_collapse(device);
  4335. val = __read_register(device, CVP_CC_MVS1_GDSCR);
  4336. regi = __read_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL);
  4337. regii = __read_register(device, CVP_CC_MVS1_CBCR);
  4338. regiii = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4339. dprintk(CVP_ERR, "noc reg check: %#x %#x %#x %#x\n",
  4340. val, regi, regii, regiii);
  4341. val = __read_register(device, CVP_NOC_ERR_SWID_LOW_OFFS);
  4342. __err_log(log_required, &noc_log->err_ctrl_swid_low,
  4343. "CVP_NOC_ERL_MAIN_SWID_LOW", val);
  4344. val = __read_register(device, CVP_NOC_ERR_SWID_HIGH_OFFS);
  4345. __err_log(log_required, &noc_log->err_ctrl_swid_high,
  4346. "CVP_NOC_ERL_MAIN_SWID_HIGH", val);
  4347. val = __read_register(device, CVP_NOC_ERR_MAINCTL_LOW_OFFS);
  4348. __err_log(log_required, &noc_log->err_ctrl_mainctl_low,
  4349. "CVP_NOC_ERL_MAIN_MAINCTL_LOW", val);
  4350. val = __read_register(device, CVP_NOC_ERR_ERRVLD_LOW_OFFS);
  4351. __err_log(log_required, &noc_log->err_ctrl_errvld_low,
  4352. "CVP_NOC_ERL_MAIN_ERRVLD_LOW", val);
  4353. val = __read_register(device, CVP_NOC_ERR_ERRCLR_LOW_OFFS);
  4354. __err_log(log_required, &noc_log->err_ctrl_errclr_low,
  4355. "CVP_NOC_ERL_MAIN_ERRCLR_LOW", val);
  4356. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_LOW_OFFS);
  4357. __err_log(log_required, &noc_log->err_ctrl_errlog0_low,
  4358. "CVP_NOC_ERL_MAIN_ERRLOG0_LOW", val);
  4359. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_HIGH_OFFS);
  4360. __err_log(log_required, &noc_log->err_ctrl_errlog0_high,
  4361. "CVP_NOC_ERL_MAIN_ERRLOG0_HIGH", val);
  4362. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_LOW_OFFS);
  4363. __err_log(log_required, &noc_log->err_ctrl_errlog1_low,
  4364. "CVP_NOC_ERL_MAIN_ERRLOG1_LOW", val);
  4365. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_HIGH_OFFS);
  4366. __err_log(log_required, &noc_log->err_ctrl_errlog1_high,
  4367. "CVP_NOC_ERL_MAIN_ERRLOG1_HIGH", val);
  4368. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_LOW_OFFS);
  4369. __err_log(log_required, &noc_log->err_ctrl_errlog2_low,
  4370. "CVP_NOC_ERL_MAIN_ERRLOG2_LOW", val);
  4371. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_HIGH_OFFS);
  4372. __err_log(log_required, &noc_log->err_ctrl_errlog2_high,
  4373. "CVP_NOC_ERL_MAIN_ERRLOG2_HIGH", val);
  4374. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_LOW_OFFS);
  4375. __err_log(log_required, &noc_log->err_ctrl_errlog3_low,
  4376. "CVP_NOC_ERL_MAIN_ERRLOG3_LOW", val);
  4377. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_HIGH_OFFS);
  4378. __err_log(log_required, &noc_log->err_ctrl_errlog3_high,
  4379. "CVP_NOC_ERL_MAIN_ERRLOG3_HIGH", val);
  4380. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4381. if (rc) {
  4382. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  4383. return;
  4384. }
  4385. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_LOW_OFFS);
  4386. __err_log(log_required, &noc_log->err_core_swid_low,
  4387. "CVP_NOC__CORE_ERL_MAIN_SWID_LOW", val);
  4388. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_HIGH_OFFS);
  4389. __err_log(log_required, &noc_log->err_core_swid_high,
  4390. "CVP_NOC_CORE_ERL_MAIN_SWID_HIGH", val);
  4391. val = __read_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS);
  4392. __err_log(log_required, &noc_log->err_core_mainctl_low,
  4393. "CVP_NOC_CORE_ERL_MAIN_MAINCTL_LOW", val);
  4394. val = __read_register(device, CVP_NOC_CORE_ERR_ERRVLD_LOW_OFFS);
  4395. __err_log(log_required, &noc_log->err_core_errvld_low,
  4396. "CVP_NOC_CORE_ERL_MAIN_ERRVLD_LOW", val);
  4397. val = __read_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS);
  4398. __err_log(log_required, &noc_log->err_core_errclr_low,
  4399. "CVP_NOC_CORE_ERL_MAIN_ERRCLR_LOW", val);
  4400. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_LOW_OFFS);
  4401. __err_log(log_required, &noc_log->err_core_errlog0_low,
  4402. "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_LOW", val);
  4403. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_HIGH_OFFS);
  4404. __err_log(log_required, &noc_log->err_core_errlog0_high,
  4405. "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_HIGH", val);
  4406. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_LOW_OFFS);
  4407. __err_log(log_required, &noc_log->err_core_errlog1_low,
  4408. "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_LOW", val);
  4409. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_HIGH_OFFS);
  4410. __err_log(log_required, &noc_log->err_core_errlog1_high,
  4411. "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_HIGH", val);
  4412. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_LOW_OFFS);
  4413. __err_log(log_required, &noc_log->err_core_errlog2_low,
  4414. "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_LOW", val);
  4415. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_HIGH_OFFS);
  4416. __err_log(log_required, &noc_log->err_core_errlog2_high,
  4417. "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_HIGH", val);
  4418. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_LOW_OFFS);
  4419. __err_log(log_required, &noc_log->err_core_errlog3_low,
  4420. "CORE ERRLOG3_LOW, below details", val);
  4421. __print_reg_details(val);
  4422. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_HIGH_OFFS);
  4423. __err_log(log_required, &noc_log->err_core_errlog3_high,
  4424. "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_HIGH", val);
  4425. __write_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS, 0x1);
  4426. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4427. #define CVP_SS_CLK_HALT 0x8
  4428. #define CVP_SS_CLK_EN 0xC
  4429. #define CVP_SS_ARP_TEST_BUS_CONTROL 0x700
  4430. #define CVP_SS_ARP_TEST_BUS_REGISTER 0x704
  4431. #define CVP_DMA_TEST_BUS_CONTROL 0x66A0
  4432. #define CVP_DMA_TEST_BUS_REGISTER 0x66A4
  4433. #define CVP_VPU_WRAPPER_CORE_CONFIG 0xB0088
  4434. __write_register(device, CVP_SS_CLK_HALT, 0);
  4435. __write_register(device, CVP_SS_CLK_EN, 0x3f);
  4436. __write_register(device, CVP_VPU_WRAPPER_CORE_CONFIG, 0);
  4437. }
  4438. static int iris_hfi_noc_error_info(void *dev)
  4439. {
  4440. struct iris_hfi_device *device;
  4441. if (!dev) {
  4442. dprintk(CVP_ERR, "%s: null device\n", __func__);
  4443. return -EINVAL;
  4444. }
  4445. device = dev;
  4446. mutex_lock(&device->lock);
  4447. dprintk(CVP_ERR, "%s: non error information\n", __func__);
  4448. call_iris_op(device, noc_error_info, device);
  4449. mutex_unlock(&device->lock);
  4450. return 0;
  4451. }
  4452. static int __initialize_packetization(struct iris_hfi_device *device)
  4453. {
  4454. int rc = 0;
  4455. if (!device || !device->res) {
  4456. dprintk(CVP_ERR, "%s - invalid param\n", __func__);
  4457. return -EINVAL;
  4458. }
  4459. device->packetization_type = HFI_PACKETIZATION_4XX;
  4460. device->pkt_ops = cvp_hfi_get_pkt_ops_handle(
  4461. device->packetization_type);
  4462. if (!device->pkt_ops) {
  4463. rc = -EINVAL;
  4464. dprintk(CVP_ERR, "Failed to get pkt_ops handle\n");
  4465. }
  4466. return rc;
  4467. }
  4468. void __init_cvp_ops(struct iris_hfi_device *device)
  4469. {
  4470. device->hal_ops = &hal_ops;
  4471. }
  4472. static struct iris_hfi_device *__add_device(struct msm_cvp_platform_resources *res,
  4473. hfi_cmd_response_callback callback)
  4474. {
  4475. struct iris_hfi_device *hdevice = NULL;
  4476. int rc = 0;
  4477. if (!res || !callback) {
  4478. dprintk(CVP_ERR, "Invalid Parameters\n");
  4479. return NULL;
  4480. }
  4481. hdevice = kzalloc(sizeof(*hdevice), GFP_KERNEL);
  4482. if (!hdevice) {
  4483. dprintk(CVP_ERR, "failed to allocate new device\n");
  4484. goto exit;
  4485. }
  4486. hdevice->response_pkt = kmalloc_array(cvp_max_packets,
  4487. sizeof(*hdevice->response_pkt), GFP_KERNEL);
  4488. if (!hdevice->response_pkt) {
  4489. dprintk(CVP_ERR, "failed to allocate response_pkt\n");
  4490. goto err_cleanup;
  4491. }
  4492. hdevice->raw_packet =
  4493. kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  4494. if (!hdevice->raw_packet) {
  4495. dprintk(CVP_ERR, "failed to allocate raw packet\n");
  4496. goto err_cleanup;
  4497. }
  4498. rc = vm_manager.vm_ops->vm_init_reg_and_irq(hdevice, res);
  4499. if (rc)
  4500. goto err_cleanup;
  4501. hdevice->res = res;
  4502. hdevice->callback = callback;
  4503. __init_cvp_ops(hdevice);
  4504. hdevice->cvp_workq = create_singlethread_workqueue(
  4505. "msm_cvp_workerq_iris");
  4506. if (!hdevice->cvp_workq) {
  4507. dprintk(CVP_ERR, ": create cvp workq failed\n");
  4508. goto err_cleanup;
  4509. }
  4510. hdevice->iris_pm_workq = create_singlethread_workqueue(
  4511. "pm_workerq_iris");
  4512. if (!hdevice->iris_pm_workq) {
  4513. dprintk(CVP_ERR, ": create pm workq failed\n");
  4514. goto err_cleanup;
  4515. }
  4516. mutex_init(&hdevice->lock);
  4517. INIT_LIST_HEAD(&hdevice->sess_head);
  4518. return hdevice;
  4519. err_cleanup:
  4520. if (hdevice->iris_pm_workq)
  4521. destroy_workqueue(hdevice->iris_pm_workq);
  4522. if (hdevice->cvp_workq)
  4523. destroy_workqueue(hdevice->cvp_workq);
  4524. kfree(hdevice->response_pkt);
  4525. kfree(hdevice->raw_packet);
  4526. kfree(hdevice);
  4527. exit:
  4528. return NULL;
  4529. }
  4530. static struct iris_hfi_device *__get_device(struct msm_cvp_platform_resources *res,
  4531. hfi_cmd_response_callback callback)
  4532. {
  4533. if (!res || !callback) {
  4534. dprintk(CVP_ERR, "Invalid params: %pK %pK\n", res, callback);
  4535. return NULL;
  4536. }
  4537. return __add_device(res, callback);
  4538. }
  4539. void cvp_iris_hfi_delete_device(void *device)
  4540. {
  4541. struct msm_cvp_core *core;
  4542. struct iris_hfi_device *dev = NULL;
  4543. if (!device)
  4544. return;
  4545. core = cvp_driver->cvp_core;
  4546. if (core)
  4547. dev = core->dev_ops->hfi_device_data;
  4548. if (!dev)
  4549. return;
  4550. mutex_destroy(&dev->lock);
  4551. destroy_workqueue(dev->cvp_workq);
  4552. destroy_workqueue(dev->iris_pm_workq);
  4553. free_irq(dev->cvp_hal_data->irq, dev);
  4554. iounmap(dev->cvp_hal_data->register_base);
  4555. iounmap(dev->cvp_hal_data->gcc_reg_base);
  4556. kfree(dev->cvp_hal_data);
  4557. kfree(dev->response_pkt);
  4558. kfree(dev->raw_packet);
  4559. kfree(dev);
  4560. }
  4561. static int iris_hfi_validate_session(void *sess, const char *func)
  4562. {
  4563. struct cvp_hal_session *session = sess;
  4564. int rc = 0;
  4565. struct iris_hfi_device *device;
  4566. if (!session || !session->device) {
  4567. dprintk(CVP_ERR, " %s Invalid Params %pK\n", __func__, session);
  4568. return -EINVAL;
  4569. }
  4570. device = session->device;
  4571. mutex_lock(&device->lock);
  4572. if (!__is_session_valid(device, session, func))
  4573. rc = -ECONNRESET;
  4574. mutex_unlock(&device->lock);
  4575. return rc;
  4576. }
  4577. static void iris_init_hfi_callbacks(struct cvp_hfi_ops *ops_tbl)
  4578. {
  4579. ops_tbl->core_init = iris_hfi_core_init;
  4580. ops_tbl->core_release = iris_hfi_core_release;
  4581. ops_tbl->core_trigger_ssr = iris_hfi_core_trigger_ssr;
  4582. ops_tbl->session_init = iris_hfi_session_init;
  4583. ops_tbl->session_end = iris_hfi_session_end;
  4584. ops_tbl->session_start = iris_hfi_session_start;
  4585. ops_tbl->session_stop = iris_hfi_session_stop;
  4586. ops_tbl->session_abort = iris_hfi_session_abort;
  4587. ops_tbl->session_clean = iris_hfi_session_clean;
  4588. ops_tbl->session_set_buffers = iris_hfi_session_set_buffers;
  4589. ops_tbl->session_release_buffers = iris_hfi_session_release_buffers;
  4590. ops_tbl->session_send = iris_hfi_session_send;
  4591. ops_tbl->session_flush = iris_hfi_session_flush;
  4592. ops_tbl->scale_clocks = iris_hfi_scale_clocks;
  4593. ops_tbl->vote_bus = iris_hfi_vote_buses;
  4594. ops_tbl->get_fw_info = iris_hfi_get_fw_info;
  4595. ops_tbl->get_core_capabilities = iris_hfi_get_core_capabilities;
  4596. ops_tbl->suspend = iris_hfi_suspend;
  4597. ops_tbl->resume = iris_hfi_resume;
  4598. ops_tbl->flush_debug_queue = iris_hfi_flush_debug_queue;
  4599. ops_tbl->noc_error_info = iris_hfi_noc_error_info;
  4600. ops_tbl->validate_session = iris_hfi_validate_session;
  4601. ops_tbl->pm_qos_update = iris_pm_qos_update;
  4602. ops_tbl->debug_hook = iris_debug_hook;
  4603. }
  4604. int cvp_iris_hfi_initialize(struct cvp_hfi_ops *ops_tbl,
  4605. struct msm_cvp_platform_resources *res,
  4606. hfi_cmd_response_callback callback)
  4607. {
  4608. int rc = 0;
  4609. if (!ops_tbl || !res || !callback) {
  4610. dprintk(CVP_ERR, "Invalid params: %pK %pK %pK\n",
  4611. ops_tbl, res, callback);
  4612. rc = -EINVAL;
  4613. goto err_iris_hfi_init;
  4614. }
  4615. ops_tbl->hfi_device_data = __get_device(res, callback);
  4616. if (IS_ERR_OR_NULL(ops_tbl->hfi_device_data)) {
  4617. rc = PTR_ERR(ops_tbl->hfi_device_data) ?: -EINVAL;
  4618. goto err_iris_hfi_init;
  4619. }
  4620. iris_init_hfi_callbacks(ops_tbl);
  4621. err_iris_hfi_init:
  4622. return rc;
  4623. }