dp_main.c 161 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include "dp_ipa.h"
  52. #define DP_INTR_POLL_TIMER_MS 10
  53. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  54. #define DP_MCS_LENGTH (6*MAX_MCS)
  55. #define DP_NSS_LENGTH (6*SS_COUNT)
  56. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  57. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  58. #define DP_MAX_MCS_STRING_LEN 30
  59. #define DP_CURR_FW_STATS_AVAIL 19
  60. #define DP_HTT_DBG_EXT_STATS_MAX 256
  61. #ifdef IPA_OFFLOAD
  62. /* Exclude IPA rings from the interrupt context */
  63. #define TX_RING_MASK_VAL 0xb
  64. #define RX_RING_MASK_VAL 0x7
  65. #else
  66. #define TX_RING_MASK_VAL 0xF
  67. #define RX_RING_MASK_VAL 0xF
  68. #endif
  69. bool rx_hash = 1;
  70. qdf_declare_param(rx_hash, bool);
  71. #define STR_MAXLEN 64
  72. #define DP_PPDU_STATS_CFG_ALL 0xffff
  73. /**
  74. * default_dscp_tid_map - Default DSCP-TID mapping
  75. *
  76. * DSCP TID AC
  77. * 000000 0 WME_AC_BE
  78. * 001000 1 WME_AC_BK
  79. * 010000 1 WME_AC_BK
  80. * 011000 0 WME_AC_BE
  81. * 100000 5 WME_AC_VI
  82. * 101000 5 WME_AC_VI
  83. * 110000 6 WME_AC_VO
  84. * 111000 6 WME_AC_VO
  85. */
  86. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  87. 0, 0, 0, 0, 0, 0, 0, 0,
  88. 1, 1, 1, 1, 1, 1, 1, 1,
  89. 1, 1, 1, 1, 1, 1, 1, 1,
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 5, 5, 5, 5, 5, 5, 5, 5,
  92. 5, 5, 5, 5, 5, 5, 5, 5,
  93. 6, 6, 6, 6, 6, 6, 6, 6,
  94. 6, 6, 6, 6, 6, 6, 6, 6,
  95. };
  96. /*
  97. * struct dp_rate_debug
  98. *
  99. * @mcs_type: print string for a given mcs
  100. * @valid: valid mcs rate?
  101. */
  102. struct dp_rate_debug {
  103. char mcs_type[DP_MAX_MCS_STRING_LEN];
  104. uint8_t valid;
  105. };
  106. #define MCS_VALID 1
  107. #define MCS_INVALID 0
  108. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  109. {
  110. {"CCK 11 Mbps Long ", MCS_VALID},
  111. {"CCK 5.5 Mbps Long ", MCS_VALID},
  112. {"CCK 2 Mbps Long ", MCS_VALID},
  113. {"CCK 1 Mbps Long ", MCS_VALID},
  114. {"CCK 11 Mbps Short ", MCS_VALID},
  115. {"CCK 5.5 Mbps Short", MCS_VALID},
  116. {"CCK 2 Mbps Short ", MCS_VALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_INVALID},
  119. {"INVALID ", MCS_INVALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_INVALID},
  122. {"INVALID ", MCS_VALID},
  123. },
  124. {
  125. {"OFDM 48 Mbps", MCS_VALID},
  126. {"OFDM 24 Mbps", MCS_VALID},
  127. {"OFDM 12 Mbps", MCS_VALID},
  128. {"OFDM 6 Mbps ", MCS_VALID},
  129. {"OFDM 54 Mbps", MCS_VALID},
  130. {"OFDM 36 Mbps", MCS_VALID},
  131. {"OFDM 18 Mbps", MCS_VALID},
  132. {"OFDM 9 Mbps ", MCS_VALID},
  133. {"INVALID ", MCS_INVALID},
  134. {"INVALID ", MCS_INVALID},
  135. {"INVALID ", MCS_INVALID},
  136. {"INVALID ", MCS_INVALID},
  137. {"INVALID ", MCS_VALID},
  138. },
  139. {
  140. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  141. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  142. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  143. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  144. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  145. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  146. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  147. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  148. {"INVALID ", MCS_INVALID},
  149. {"INVALID ", MCS_INVALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_INVALID},
  152. {"INVALID ", MCS_VALID},
  153. },
  154. {
  155. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  156. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  157. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  158. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  159. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  160. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  161. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  162. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  163. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  164. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  165. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  166. {"VHT MCS 11 (1024-QAM 5/6)", MCS_VALID},
  167. {"INVALID ", MCS_VALID},
  168. },
  169. {
  170. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  171. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  172. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  173. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  174. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  175. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  176. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  177. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  178. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  179. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  180. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  181. {"HE MCS 11 (1024-QAM 5/6)", MCS_VALID},
  182. {"INVALID ", MCS_VALID},
  183. }
  184. };
  185. /**
  186. * @brief Cpu ring map types
  187. */
  188. enum dp_cpu_ring_map_types {
  189. DP_DEFAULT_MAP,
  190. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  191. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  192. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  193. DP_CPU_RING_MAP_MAX
  194. };
  195. /**
  196. * @brief Cpu to tx ring map
  197. */
  198. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  199. {0x0, 0x1, 0x2, 0x0},
  200. {0x1, 0x2, 0x1, 0x2},
  201. {0x0, 0x2, 0x0, 0x2},
  202. {0x2, 0x2, 0x2, 0x2}
  203. };
  204. /**
  205. * @brief Select the type of statistics
  206. */
  207. enum dp_stats_type {
  208. STATS_FW = 0,
  209. STATS_HOST = 1,
  210. STATS_TYPE_MAX = 2,
  211. };
  212. /**
  213. * @brief General Firmware statistics options
  214. *
  215. */
  216. enum dp_fw_stats {
  217. TXRX_FW_STATS_INVALID = -1,
  218. };
  219. /**
  220. * dp_stats_mapping_table - Firmware and Host statistics
  221. * currently supported
  222. */
  223. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  224. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  235. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  242. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  243. /* Last ENUM for HTT FW STATS */
  244. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  245. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  247. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  248. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  250. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  251. {TXRX_FW_STATS_INVALID, TXRX_SRNG_PTR_STATS},
  252. };
  253. /**
  254. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  255. * @ring_num: ring num of the ring being queried
  256. * @grp_mask: the grp_mask array for the ring type in question.
  257. *
  258. * The grp_mask array is indexed by group number and the bit fields correspond
  259. * to ring numbers. We are finding which interrupt group a ring belongs to.
  260. *
  261. * Return: the index in the grp_mask array with the ring number.
  262. * -QDF_STATUS_E_NOENT if no entry is found
  263. */
  264. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  265. {
  266. int ext_group_num;
  267. int mask = 1 << ring_num;
  268. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  269. ext_group_num++) {
  270. if (mask & grp_mask[ext_group_num])
  271. return ext_group_num;
  272. }
  273. return -QDF_STATUS_E_NOENT;
  274. }
  275. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  276. enum hal_ring_type ring_type,
  277. int ring_num)
  278. {
  279. int *grp_mask;
  280. switch (ring_type) {
  281. case WBM2SW_RELEASE:
  282. /* dp_tx_comp_handler - soc->tx_comp_ring */
  283. if (ring_num < 3)
  284. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  285. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  286. else if (ring_num == 3) {
  287. /* sw treats this as a separate ring type */
  288. grp_mask = &soc->wlan_cfg_ctx->
  289. int_rx_wbm_rel_ring_mask[0];
  290. ring_num = 0;
  291. } else {
  292. qdf_assert(0);
  293. return -QDF_STATUS_E_NOENT;
  294. }
  295. break;
  296. case REO_EXCEPTION:
  297. /* dp_rx_err_process - &soc->reo_exception_ring */
  298. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  299. break;
  300. case REO_DST:
  301. /* dp_rx_process - soc->reo_dest_ring */
  302. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  303. break;
  304. case REO_STATUS:
  305. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  306. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  307. break;
  308. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  309. case RXDMA_MONITOR_STATUS:
  310. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  311. case RXDMA_MONITOR_DST:
  312. /* dp_mon_process */
  313. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  314. break;
  315. case RXDMA_DST:
  316. /* dp_rxdma_err_process */
  317. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  318. break;
  319. case RXDMA_BUF:
  320. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  321. break;
  322. case RXDMA_MONITOR_BUF:
  323. /* TODO: support low_thresh interrupt */
  324. return -QDF_STATUS_E_NOENT;
  325. break;
  326. case TCL_DATA:
  327. case TCL_CMD:
  328. case REO_CMD:
  329. case SW2WBM_RELEASE:
  330. case WBM_IDLE_LINK:
  331. /* normally empty SW_TO_HW rings */
  332. return -QDF_STATUS_E_NOENT;
  333. break;
  334. case TCL_STATUS:
  335. case REO_REINJECT:
  336. /* misc unused rings */
  337. return -QDF_STATUS_E_NOENT;
  338. break;
  339. case CE_SRC:
  340. case CE_DST:
  341. case CE_DST_STATUS:
  342. /* CE_rings - currently handled by hif */
  343. default:
  344. return -QDF_STATUS_E_NOENT;
  345. break;
  346. }
  347. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  348. }
  349. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  350. *ring_params, int ring_type, int ring_num)
  351. {
  352. int msi_group_number;
  353. int msi_data_count;
  354. int ret;
  355. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  356. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  357. &msi_data_count, &msi_data_start,
  358. &msi_irq_start);
  359. if (ret)
  360. return;
  361. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  362. ring_num);
  363. if (msi_group_number < 0) {
  364. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  365. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  366. ring_type, ring_num);
  367. ring_params->msi_addr = 0;
  368. ring_params->msi_data = 0;
  369. return;
  370. }
  371. if (msi_group_number > msi_data_count) {
  372. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  373. FL("2 msi_groups will share an msi; msi_group_num %d"),
  374. msi_group_number);
  375. QDF_ASSERT(0);
  376. }
  377. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  378. ring_params->msi_addr = addr_low;
  379. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  380. ring_params->msi_data = (msi_group_number % msi_data_count)
  381. + msi_data_start;
  382. ring_params->flags |= HAL_SRNG_MSI_INTR;
  383. }
  384. /**
  385. * dp_print_ast_stats() - Dump AST table contents
  386. * @soc: Datapath soc handle
  387. *
  388. * return void
  389. */
  390. #ifdef FEATURE_WDS
  391. static void dp_print_ast_stats(struct dp_soc *soc)
  392. {
  393. uint8_t i;
  394. uint8_t num_entries = 0;
  395. struct dp_vdev *vdev;
  396. struct dp_pdev *pdev;
  397. struct dp_peer *peer;
  398. struct dp_ast_entry *ase, *tmp_ase;
  399. DP_PRINT_STATS("AST Stats:");
  400. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  401. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  402. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  403. DP_PRINT_STATS("AST Table:");
  404. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  405. pdev = soc->pdev_list[i];
  406. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  407. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  408. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  409. DP_PRINT_STATS("%6d mac_addr = %pM"
  410. " peer_mac_addr = %pM"
  411. " type = %d"
  412. " next_hop = %d"
  413. " is_active = %d"
  414. " is_bss = %d",
  415. ++num_entries,
  416. ase->mac_addr.raw,
  417. ase->peer->mac_addr.raw,
  418. ase->type,
  419. ase->next_hop,
  420. ase->is_active,
  421. ase->is_bss);
  422. }
  423. }
  424. }
  425. }
  426. }
  427. #else
  428. static void dp_print_ast_stats(struct dp_soc *soc)
  429. {
  430. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  431. return;
  432. }
  433. #endif
  434. /*
  435. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  436. */
  437. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  438. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  439. {
  440. void *hal_soc = soc->hal_soc;
  441. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  442. /* TODO: See if we should get align size from hal */
  443. uint32_t ring_base_align = 8;
  444. struct hal_srng_params ring_params;
  445. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  446. /* TODO: Currently hal layer takes care of endianness related settings.
  447. * See if these settings need to passed from DP layer
  448. */
  449. ring_params.flags = 0;
  450. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  451. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  452. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  453. srng->hal_srng = NULL;
  454. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  455. srng->num_entries = num_entries;
  456. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  457. soc->osdev, soc->osdev->dev, srng->alloc_size,
  458. &(srng->base_paddr_unaligned));
  459. if (!srng->base_vaddr_unaligned) {
  460. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  461. FL("alloc failed - ring_type: %d, ring_num %d"),
  462. ring_type, ring_num);
  463. return QDF_STATUS_E_NOMEM;
  464. }
  465. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  466. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  467. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  468. ((unsigned long)(ring_params.ring_base_vaddr) -
  469. (unsigned long)srng->base_vaddr_unaligned);
  470. ring_params.num_entries = num_entries;
  471. if (soc->intr_mode == DP_INTR_MSI) {
  472. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  473. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  474. FL("Using MSI for ring_type: %d, ring_num %d"),
  475. ring_type, ring_num);
  476. } else {
  477. ring_params.msi_data = 0;
  478. ring_params.msi_addr = 0;
  479. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  480. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  481. ring_type, ring_num);
  482. }
  483. /*
  484. * Setup interrupt timer and batch counter thresholds for
  485. * interrupt mitigation based on ring type
  486. */
  487. if (ring_type == REO_DST) {
  488. ring_params.intr_timer_thres_us =
  489. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  490. ring_params.intr_batch_cntr_thres_entries =
  491. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  492. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  493. ring_params.intr_timer_thres_us =
  494. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  495. ring_params.intr_batch_cntr_thres_entries =
  496. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  497. } else {
  498. ring_params.intr_timer_thres_us =
  499. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  500. ring_params.intr_batch_cntr_thres_entries =
  501. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  502. }
  503. /* Enable low threshold interrupts for rx buffer rings (regular and
  504. * monitor buffer rings.
  505. * TODO: See if this is required for any other ring
  506. */
  507. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  508. /* TODO: Setting low threshold to 1/8th of ring size
  509. * see if this needs to be configurable
  510. */
  511. ring_params.low_threshold = num_entries >> 3;
  512. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  513. ring_params.intr_timer_thres_us = 0x1000;
  514. }
  515. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  516. mac_id, &ring_params);
  517. return 0;
  518. }
  519. /**
  520. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  521. * Any buffers allocated and attached to ring entries are expected to be freed
  522. * before calling this function.
  523. */
  524. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  525. int ring_type, int ring_num)
  526. {
  527. if (!srng->hal_srng) {
  528. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  529. FL("Ring type: %d, num:%d not setup"),
  530. ring_type, ring_num);
  531. return;
  532. }
  533. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  534. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  535. srng->alloc_size,
  536. srng->base_vaddr_unaligned,
  537. srng->base_paddr_unaligned, 0);
  538. srng->hal_srng = NULL;
  539. }
  540. /* TODO: Need this interface from HIF */
  541. void *hif_get_hal_handle(void *hif_handle);
  542. /*
  543. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  544. * @dp_ctx: DP SOC handle
  545. * @budget: Number of frames/descriptors that can be processed in one shot
  546. *
  547. * Return: remaining budget/quota for the soc device
  548. */
  549. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  550. {
  551. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  552. struct dp_soc *soc = int_ctx->soc;
  553. int ring = 0;
  554. uint32_t work_done = 0;
  555. int budget = dp_budget;
  556. uint8_t tx_mask = int_ctx->tx_ring_mask;
  557. uint8_t rx_mask = int_ctx->rx_ring_mask;
  558. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  559. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  560. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  561. uint32_t remaining_quota = dp_budget;
  562. struct dp_pdev *pdev = NULL;
  563. /* Process Tx completion interrupts first to return back buffers */
  564. while (tx_mask) {
  565. if (tx_mask & 0x1) {
  566. work_done = dp_tx_comp_handler(soc,
  567. soc->tx_comp_ring[ring].hal_srng,
  568. remaining_quota);
  569. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  570. "tx mask 0x%x ring %d, budget %d, work_done %d",
  571. tx_mask, ring, budget, work_done);
  572. budget -= work_done;
  573. if (budget <= 0)
  574. goto budget_done;
  575. remaining_quota = budget;
  576. }
  577. tx_mask = tx_mask >> 1;
  578. ring++;
  579. }
  580. /* Process REO Exception ring interrupt */
  581. if (rx_err_mask) {
  582. work_done = dp_rx_err_process(soc,
  583. soc->reo_exception_ring.hal_srng,
  584. remaining_quota);
  585. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  586. "REO Exception Ring: work_done %d budget %d",
  587. work_done, budget);
  588. budget -= work_done;
  589. if (budget <= 0) {
  590. goto budget_done;
  591. }
  592. remaining_quota = budget;
  593. }
  594. /* Process Rx WBM release ring interrupt */
  595. if (rx_wbm_rel_mask) {
  596. work_done = dp_rx_wbm_err_process(soc,
  597. soc->rx_rel_ring.hal_srng, remaining_quota);
  598. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  599. "WBM Release Ring: work_done %d budget %d",
  600. work_done, budget);
  601. budget -= work_done;
  602. if (budget <= 0) {
  603. goto budget_done;
  604. }
  605. remaining_quota = budget;
  606. }
  607. /* Process Rx interrupts */
  608. if (rx_mask) {
  609. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  610. if (rx_mask & (1 << ring)) {
  611. work_done = dp_rx_process(int_ctx,
  612. soc->reo_dest_ring[ring].hal_srng,
  613. remaining_quota);
  614. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  615. "rx mask 0x%x ring %d, work_done %d budget %d",
  616. rx_mask, ring, work_done, budget);
  617. budget -= work_done;
  618. if (budget <= 0)
  619. goto budget_done;
  620. remaining_quota = budget;
  621. }
  622. }
  623. for (ring = 0; ring < MAX_RX_MAC_RINGS; ring++) {
  624. /* Need to check on this, why is required */
  625. work_done = dp_rxdma_err_process(soc, ring,
  626. remaining_quota);
  627. budget -= work_done;
  628. }
  629. }
  630. if (reo_status_mask)
  631. dp_reo_status_ring_handler(soc);
  632. /* Process LMAC interrupts */
  633. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  634. pdev = soc->pdev_list[ring];
  635. if (pdev == NULL)
  636. continue;
  637. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  638. work_done = dp_mon_process(soc, ring, remaining_quota);
  639. budget -= work_done;
  640. if (budget <= 0)
  641. goto budget_done;
  642. remaining_quota = budget;
  643. }
  644. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  645. work_done = dp_rxdma_err_process(soc, ring,
  646. remaining_quota);
  647. budget -= work_done;
  648. if (budget <= 0)
  649. goto budget_done;
  650. remaining_quota = budget;
  651. }
  652. if (int_ctx->host2rxdma_ring_mask & (1 << ring)) {
  653. union dp_rx_desc_list_elem_t *desc_list = NULL;
  654. union dp_rx_desc_list_elem_t *tail = NULL;
  655. struct dp_srng *rx_refill_buf_ring =
  656. &pdev->rx_refill_buf_ring;
  657. DP_STATS_INC(pdev, replenish.low_thresh_intrs, 1);
  658. dp_rx_buffers_replenish(soc, ring,
  659. rx_refill_buf_ring,
  660. &soc->rx_desc_buf[ring], 0,
  661. &desc_list, &tail, HAL_RX_BUF_RBM_SW3_BM);
  662. }
  663. }
  664. qdf_lro_flush(int_ctx->lro_ctx);
  665. budget_done:
  666. return dp_budget - budget;
  667. }
  668. #ifdef DP_INTR_POLL_BASED
  669. /* dp_interrupt_timer()- timer poll for interrupts
  670. *
  671. * @arg: SoC Handle
  672. *
  673. * Return:
  674. *
  675. */
  676. static void dp_interrupt_timer(void *arg)
  677. {
  678. struct dp_soc *soc = (struct dp_soc *) arg;
  679. int i;
  680. if (qdf_atomic_read(&soc->cmn_init_done)) {
  681. for (i = 0;
  682. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  683. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  684. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  685. }
  686. }
  687. /*
  688. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  689. * @txrx_soc: DP SOC handle
  690. *
  691. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  692. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  693. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  694. *
  695. * Return: 0 for success. nonzero for failure.
  696. */
  697. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  698. {
  699. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  700. int i;
  701. soc->intr_mode = DP_INTR_POLL;
  702. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  703. soc->intr_ctx[i].dp_intr_id = i;
  704. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  705. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  706. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  707. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  708. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  709. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  710. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  711. soc->intr_ctx[i].host2rxdma_ring_mask = 0x1;
  712. soc->intr_ctx[i].soc = soc;
  713. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  714. }
  715. qdf_timer_init(soc->osdev, &soc->int_timer,
  716. dp_interrupt_timer, (void *)soc,
  717. QDF_TIMER_TYPE_WAKE_APPS);
  718. return QDF_STATUS_SUCCESS;
  719. }
  720. #if defined(CONFIG_MCL)
  721. extern int con_mode_monitor;
  722. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  723. /*
  724. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  725. * @txrx_soc: DP SOC handle
  726. *
  727. * Call the appropriate attach function based on the mode of operation.
  728. * This is a WAR for enabling monitor mode.
  729. *
  730. * Return: 0 for success. nonzero for failure.
  731. */
  732. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  733. {
  734. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  735. if (!(soc->wlan_cfg_ctx->napi_enabled) ||
  736. con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  737. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  738. "%s: Poll mode", __func__);
  739. return dp_soc_interrupt_attach_poll(txrx_soc);
  740. } else {
  741. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  742. "%s: Interrupt mode", __func__);
  743. return dp_soc_interrupt_attach(txrx_soc);
  744. }
  745. }
  746. #else
  747. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  748. {
  749. return dp_soc_interrupt_attach_poll(txrx_soc);
  750. }
  751. #endif
  752. #endif
  753. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  754. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  755. {
  756. int j;
  757. int num_irq = 0;
  758. int tx_mask =
  759. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  760. int rx_mask =
  761. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  762. int rx_mon_mask =
  763. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  764. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  765. soc->wlan_cfg_ctx, intr_ctx_num);
  766. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  767. soc->wlan_cfg_ctx, intr_ctx_num);
  768. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  769. soc->wlan_cfg_ctx, intr_ctx_num);
  770. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  771. soc->wlan_cfg_ctx, intr_ctx_num);
  772. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  773. soc->wlan_cfg_ctx, intr_ctx_num);
  774. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  775. if (tx_mask & (1 << j)) {
  776. irq_id_map[num_irq++] =
  777. (wbm2host_tx_completions_ring1 - j);
  778. }
  779. if (rx_mask & (1 << j)) {
  780. irq_id_map[num_irq++] =
  781. (reo2host_destination_ring1 - j);
  782. }
  783. if (rxdma2host_ring_mask & (1 << j)) {
  784. irq_id_map[num_irq++] =
  785. rxdma2host_destination_ring_mac1 -
  786. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  787. }
  788. if (host2rxdma_ring_mask & (1 << j)) {
  789. irq_id_map[num_irq++] =
  790. host2rxdma_host_buf_ring_mac1 -
  791. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  792. }
  793. if (rx_mon_mask & (1 << j)) {
  794. irq_id_map[num_irq++] =
  795. ppdu_end_interrupts_mac1 -
  796. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  797. }
  798. if (rx_wbm_rel_ring_mask & (1 << j))
  799. irq_id_map[num_irq++] = wbm2host_rx_release;
  800. if (rx_err_ring_mask & (1 << j))
  801. irq_id_map[num_irq++] = reo2host_exception;
  802. if (reo_status_ring_mask & (1 << j))
  803. irq_id_map[num_irq++] = reo2host_status;
  804. }
  805. *num_irq_r = num_irq;
  806. }
  807. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  808. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  809. int msi_vector_count, int msi_vector_start)
  810. {
  811. int tx_mask = wlan_cfg_get_tx_ring_mask(
  812. soc->wlan_cfg_ctx, intr_ctx_num);
  813. int rx_mask = wlan_cfg_get_rx_ring_mask(
  814. soc->wlan_cfg_ctx, intr_ctx_num);
  815. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  816. soc->wlan_cfg_ctx, intr_ctx_num);
  817. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  818. soc->wlan_cfg_ctx, intr_ctx_num);
  819. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  820. soc->wlan_cfg_ctx, intr_ctx_num);
  821. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  822. soc->wlan_cfg_ctx, intr_ctx_num);
  823. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  824. soc->wlan_cfg_ctx, intr_ctx_num);
  825. unsigned int vector =
  826. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  827. int num_irq = 0;
  828. soc->intr_mode = DP_INTR_MSI;
  829. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  830. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask)
  831. irq_id_map[num_irq++] =
  832. pld_get_msi_irq(soc->osdev->dev, vector);
  833. *num_irq_r = num_irq;
  834. }
  835. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  836. int *irq_id_map, int *num_irq)
  837. {
  838. int msi_vector_count, ret;
  839. uint32_t msi_base_data, msi_vector_start;
  840. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  841. &msi_vector_count,
  842. &msi_base_data,
  843. &msi_vector_start);
  844. if (ret)
  845. return dp_soc_interrupt_map_calculate_integrated(soc,
  846. intr_ctx_num, irq_id_map, num_irq);
  847. else
  848. dp_soc_interrupt_map_calculate_msi(soc,
  849. intr_ctx_num, irq_id_map, num_irq,
  850. msi_vector_count, msi_vector_start);
  851. }
  852. /*
  853. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  854. * @txrx_soc: DP SOC handle
  855. *
  856. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  857. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  858. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  859. *
  860. * Return: 0 for success. nonzero for failure.
  861. */
  862. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  863. {
  864. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  865. int i = 0;
  866. int num_irq = 0;
  867. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  868. int ret = 0;
  869. /* Map of IRQ ids registered with one interrupt context */
  870. int irq_id_map[HIF_MAX_GRP_IRQ];
  871. int tx_mask =
  872. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  873. int rx_mask =
  874. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  875. int rx_mon_mask =
  876. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  877. int rx_err_ring_mask =
  878. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  879. int rx_wbm_rel_ring_mask =
  880. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  881. int reo_status_ring_mask =
  882. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  883. int rxdma2host_ring_mask =
  884. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  885. int host2rxdma_ring_mask =
  886. wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx, i);
  887. soc->intr_ctx[i].dp_intr_id = i;
  888. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  889. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  890. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  891. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  892. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  893. soc->intr_ctx[i].host2rxdma_ring_mask = host2rxdma_ring_mask;
  894. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  895. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  896. soc->intr_ctx[i].soc = soc;
  897. num_irq = 0;
  898. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  899. &num_irq);
  900. ret = hif_register_ext_group(soc->hif_handle,
  901. num_irq, irq_id_map, dp_service_srngs,
  902. &soc->intr_ctx[i], "dp_intr",
  903. HIF_EXEC_NAPI_TYPE, QCA_NAPI_DEF_SCALE_BIN_SHIFT);
  904. if (ret) {
  905. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  906. FL("failed, ret = %d"), ret);
  907. return QDF_STATUS_E_FAILURE;
  908. }
  909. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  910. }
  911. hif_configure_ext_group_interrupts(soc->hif_handle);
  912. return QDF_STATUS_SUCCESS;
  913. }
  914. /*
  915. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  916. * @txrx_soc: DP SOC handle
  917. *
  918. * Return: void
  919. */
  920. static void dp_soc_interrupt_detach(void *txrx_soc)
  921. {
  922. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  923. int i;
  924. if (soc->intr_mode == DP_INTR_POLL) {
  925. qdf_timer_stop(&soc->int_timer);
  926. qdf_timer_free(&soc->int_timer);
  927. } else {
  928. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  929. }
  930. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  931. soc->intr_ctx[i].tx_ring_mask = 0;
  932. soc->intr_ctx[i].rx_ring_mask = 0;
  933. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  934. soc->intr_ctx[i].rx_err_ring_mask = 0;
  935. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  936. soc->intr_ctx[i].reo_status_ring_mask = 0;
  937. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  938. soc->intr_ctx[i].host2rxdma_ring_mask = 0;
  939. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  940. }
  941. }
  942. #define AVG_MAX_MPDUS_PER_TID 128
  943. #define AVG_TIDS_PER_CLIENT 2
  944. #define AVG_FLOWS_PER_TID 2
  945. #define AVG_MSDUS_PER_FLOW 128
  946. #define AVG_MSDUS_PER_MPDU 4
  947. /*
  948. * Allocate and setup link descriptor pool that will be used by HW for
  949. * various link and queue descriptors and managed by WBM
  950. */
  951. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  952. {
  953. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  954. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  955. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  956. uint32_t num_mpdus_per_link_desc =
  957. hal_num_mpdus_per_link_desc(soc->hal_soc);
  958. uint32_t num_msdus_per_link_desc =
  959. hal_num_msdus_per_link_desc(soc->hal_soc);
  960. uint32_t num_mpdu_links_per_queue_desc =
  961. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  962. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  963. uint32_t total_link_descs, total_mem_size;
  964. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  965. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  966. uint32_t num_link_desc_banks;
  967. uint32_t last_bank_size = 0;
  968. uint32_t entry_size, num_entries;
  969. int i;
  970. uint32_t desc_id = 0;
  971. /* Only Tx queue descriptors are allocated from common link descriptor
  972. * pool Rx queue descriptors are not included in this because (REO queue
  973. * extension descriptors) they are expected to be allocated contiguously
  974. * with REO queue descriptors
  975. */
  976. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  977. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  978. num_mpdu_queue_descs = num_mpdu_link_descs /
  979. num_mpdu_links_per_queue_desc;
  980. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  981. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  982. num_msdus_per_link_desc;
  983. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  984. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  985. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  986. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  987. /* Round up to power of 2 */
  988. total_link_descs = 1;
  989. while (total_link_descs < num_entries)
  990. total_link_descs <<= 1;
  991. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  992. FL("total_link_descs: %u, link_desc_size: %d"),
  993. total_link_descs, link_desc_size);
  994. total_mem_size = total_link_descs * link_desc_size;
  995. total_mem_size += link_desc_align;
  996. if (total_mem_size <= max_alloc_size) {
  997. num_link_desc_banks = 0;
  998. last_bank_size = total_mem_size;
  999. } else {
  1000. num_link_desc_banks = (total_mem_size) /
  1001. (max_alloc_size - link_desc_align);
  1002. last_bank_size = total_mem_size %
  1003. (max_alloc_size - link_desc_align);
  1004. }
  1005. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1006. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1007. total_mem_size, num_link_desc_banks);
  1008. for (i = 0; i < num_link_desc_banks; i++) {
  1009. soc->link_desc_banks[i].base_vaddr_unaligned =
  1010. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1011. max_alloc_size,
  1012. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1013. soc->link_desc_banks[i].size = max_alloc_size;
  1014. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1015. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1016. ((unsigned long)(
  1017. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1018. link_desc_align));
  1019. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1020. soc->link_desc_banks[i].base_paddr_unaligned) +
  1021. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1022. (unsigned long)(
  1023. soc->link_desc_banks[i].base_vaddr_unaligned));
  1024. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1025. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1026. FL("Link descriptor memory alloc failed"));
  1027. goto fail;
  1028. }
  1029. }
  1030. if (last_bank_size) {
  1031. /* Allocate last bank in case total memory required is not exact
  1032. * multiple of max_alloc_size
  1033. */
  1034. soc->link_desc_banks[i].base_vaddr_unaligned =
  1035. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1036. last_bank_size,
  1037. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1038. soc->link_desc_banks[i].size = last_bank_size;
  1039. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1040. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1041. ((unsigned long)(
  1042. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1043. link_desc_align));
  1044. soc->link_desc_banks[i].base_paddr =
  1045. (unsigned long)(
  1046. soc->link_desc_banks[i].base_paddr_unaligned) +
  1047. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1048. (unsigned long)(
  1049. soc->link_desc_banks[i].base_vaddr_unaligned));
  1050. }
  1051. /* Allocate and setup link descriptor idle list for HW internal use */
  1052. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1053. total_mem_size = entry_size * total_link_descs;
  1054. if (total_mem_size <= max_alloc_size) {
  1055. void *desc;
  1056. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1057. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1058. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1059. FL("Link desc idle ring setup failed"));
  1060. goto fail;
  1061. }
  1062. hal_srng_access_start_unlocked(soc->hal_soc,
  1063. soc->wbm_idle_link_ring.hal_srng);
  1064. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1065. soc->link_desc_banks[i].base_paddr; i++) {
  1066. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1067. ((unsigned long)(
  1068. soc->link_desc_banks[i].base_vaddr) -
  1069. (unsigned long)(
  1070. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1071. / link_desc_size;
  1072. unsigned long paddr = (unsigned long)(
  1073. soc->link_desc_banks[i].base_paddr);
  1074. while (num_entries && (desc = hal_srng_src_get_next(
  1075. soc->hal_soc,
  1076. soc->wbm_idle_link_ring.hal_srng))) {
  1077. hal_set_link_desc_addr(desc,
  1078. LINK_DESC_COOKIE(desc_id, i), paddr);
  1079. num_entries--;
  1080. desc_id++;
  1081. paddr += link_desc_size;
  1082. }
  1083. }
  1084. hal_srng_access_end_unlocked(soc->hal_soc,
  1085. soc->wbm_idle_link_ring.hal_srng);
  1086. } else {
  1087. uint32_t num_scatter_bufs;
  1088. uint32_t num_entries_per_buf;
  1089. uint32_t rem_entries;
  1090. uint8_t *scatter_buf_ptr;
  1091. uint16_t scatter_buf_num;
  1092. soc->wbm_idle_scatter_buf_size =
  1093. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1094. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1095. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1096. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1097. soc->hal_soc, total_mem_size,
  1098. soc->wbm_idle_scatter_buf_size);
  1099. for (i = 0; i < num_scatter_bufs; i++) {
  1100. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1101. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1102. soc->wbm_idle_scatter_buf_size,
  1103. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1104. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1105. QDF_TRACE(QDF_MODULE_ID_DP,
  1106. QDF_TRACE_LEVEL_ERROR,
  1107. FL("Scatter list memory alloc failed"));
  1108. goto fail;
  1109. }
  1110. }
  1111. /* Populate idle list scatter buffers with link descriptor
  1112. * pointers
  1113. */
  1114. scatter_buf_num = 0;
  1115. scatter_buf_ptr = (uint8_t *)(
  1116. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1117. rem_entries = num_entries_per_buf;
  1118. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1119. soc->link_desc_banks[i].base_paddr; i++) {
  1120. uint32_t num_link_descs =
  1121. (soc->link_desc_banks[i].size -
  1122. ((unsigned long)(
  1123. soc->link_desc_banks[i].base_vaddr) -
  1124. (unsigned long)(
  1125. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1126. / link_desc_size;
  1127. unsigned long paddr = (unsigned long)(
  1128. soc->link_desc_banks[i].base_paddr);
  1129. while (num_link_descs) {
  1130. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1131. LINK_DESC_COOKIE(desc_id, i), paddr);
  1132. num_link_descs--;
  1133. desc_id++;
  1134. paddr += link_desc_size;
  1135. rem_entries--;
  1136. if (rem_entries) {
  1137. scatter_buf_ptr += entry_size;
  1138. } else {
  1139. rem_entries = num_entries_per_buf;
  1140. scatter_buf_num++;
  1141. if (scatter_buf_num >= num_scatter_bufs)
  1142. break;
  1143. scatter_buf_ptr = (uint8_t *)(
  1144. soc->wbm_idle_scatter_buf_base_vaddr[
  1145. scatter_buf_num]);
  1146. }
  1147. }
  1148. }
  1149. /* Setup link descriptor idle list in HW */
  1150. hal_setup_link_idle_list(soc->hal_soc,
  1151. soc->wbm_idle_scatter_buf_base_paddr,
  1152. soc->wbm_idle_scatter_buf_base_vaddr,
  1153. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1154. (uint32_t)(scatter_buf_ptr -
  1155. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1156. scatter_buf_num-1])), total_link_descs);
  1157. }
  1158. return 0;
  1159. fail:
  1160. if (soc->wbm_idle_link_ring.hal_srng) {
  1161. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1162. WBM_IDLE_LINK, 0);
  1163. }
  1164. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1165. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1166. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1167. soc->wbm_idle_scatter_buf_size,
  1168. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1169. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1170. }
  1171. }
  1172. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1173. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1174. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1175. soc->link_desc_banks[i].size,
  1176. soc->link_desc_banks[i].base_vaddr_unaligned,
  1177. soc->link_desc_banks[i].base_paddr_unaligned,
  1178. 0);
  1179. }
  1180. }
  1181. return QDF_STATUS_E_FAILURE;
  1182. }
  1183. /*
  1184. * Free link descriptor pool that was setup HW
  1185. */
  1186. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1187. {
  1188. int i;
  1189. if (soc->wbm_idle_link_ring.hal_srng) {
  1190. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1191. WBM_IDLE_LINK, 0);
  1192. }
  1193. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1194. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1195. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1196. soc->wbm_idle_scatter_buf_size,
  1197. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1198. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1199. }
  1200. }
  1201. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1202. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1203. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1204. soc->link_desc_banks[i].size,
  1205. soc->link_desc_banks[i].base_vaddr_unaligned,
  1206. soc->link_desc_banks[i].base_paddr_unaligned,
  1207. 0);
  1208. }
  1209. }
  1210. }
  1211. /* TODO: Following should be configurable */
  1212. #define WBM_RELEASE_RING_SIZE 64
  1213. #define TCL_CMD_RING_SIZE 32
  1214. #define TCL_STATUS_RING_SIZE 32
  1215. #if defined(QCA_WIFI_QCA6290)
  1216. #define REO_DST_RING_SIZE 1024
  1217. #else
  1218. #define REO_DST_RING_SIZE 2048
  1219. #endif
  1220. #define REO_REINJECT_RING_SIZE 32
  1221. #define RX_RELEASE_RING_SIZE 1024
  1222. #define REO_EXCEPTION_RING_SIZE 128
  1223. #define REO_CMD_RING_SIZE 32
  1224. #define REO_STATUS_RING_SIZE 32
  1225. #define RXDMA_BUF_RING_SIZE 1024
  1226. #define RXDMA_REFILL_RING_SIZE 4096
  1227. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1228. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1229. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1230. #define RXDMA_MONITOR_DESC_RING_SIZE 2048
  1231. #define RXDMA_ERR_DST_RING_SIZE 1024
  1232. /*
  1233. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1234. * @soc: Datapath SOC handle
  1235. *
  1236. * This is a timer function used to age out stale WDS nodes from
  1237. * AST table
  1238. */
  1239. #ifdef FEATURE_WDS
  1240. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1241. {
  1242. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1243. struct dp_pdev *pdev;
  1244. struct dp_vdev *vdev;
  1245. struct dp_peer *peer;
  1246. struct dp_ast_entry *ase, *temp_ase;
  1247. int i;
  1248. qdf_spin_lock_bh(&soc->ast_lock);
  1249. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1250. pdev = soc->pdev_list[i];
  1251. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1252. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1253. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1254. /*
  1255. * Do not expire static ast entries
  1256. */
  1257. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1258. continue;
  1259. if (ase->is_active) {
  1260. ase->is_active = FALSE;
  1261. continue;
  1262. }
  1263. DP_STATS_INC(soc, ast.aged_out, 1);
  1264. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1265. pdev->osif_pdev,
  1266. ase->mac_addr.raw);
  1267. dp_peer_del_ast(soc, ase);
  1268. }
  1269. }
  1270. }
  1271. }
  1272. qdf_spin_unlock_bh(&soc->ast_lock);
  1273. if (qdf_atomic_read(&soc->cmn_init_done))
  1274. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1275. }
  1276. /*
  1277. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1278. * @soc: Datapath SOC handle
  1279. *
  1280. * Return: None
  1281. */
  1282. static void dp_soc_wds_attach(struct dp_soc *soc)
  1283. {
  1284. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1285. dp_wds_aging_timer_fn, (void *)soc,
  1286. QDF_TIMER_TYPE_WAKE_APPS);
  1287. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1288. }
  1289. /*
  1290. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1291. * @txrx_soc: DP SOC handle
  1292. *
  1293. * Return: None
  1294. */
  1295. static void dp_soc_wds_detach(struct dp_soc *soc)
  1296. {
  1297. qdf_timer_stop(&soc->wds_aging_timer);
  1298. qdf_timer_free(&soc->wds_aging_timer);
  1299. }
  1300. #else
  1301. static void dp_soc_wds_attach(struct dp_soc *soc)
  1302. {
  1303. }
  1304. static void dp_soc_wds_detach(struct dp_soc *soc)
  1305. {
  1306. }
  1307. #endif
  1308. /*
  1309. * dp_soc_reset_ring_map() - Reset cpu ring map
  1310. * @soc: Datapath soc handler
  1311. *
  1312. * This api resets the default cpu ring map
  1313. */
  1314. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1315. {
  1316. uint8_t i;
  1317. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1318. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1319. if (nss_config == 1) {
  1320. /*
  1321. * Setting Tx ring map for one nss offloaded radio
  1322. */
  1323. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1324. } else if (nss_config == 2) {
  1325. /*
  1326. * Setting Tx ring for two nss offloaded radios
  1327. */
  1328. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1329. } else {
  1330. /*
  1331. * Setting Tx ring map for all nss offloaded radios
  1332. */
  1333. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1334. }
  1335. }
  1336. }
  1337. /*
  1338. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  1339. * @dp_soc - DP soc handle
  1340. * @ring_type - ring type
  1341. * @ring_num - ring_num
  1342. *
  1343. * return 0 or 1
  1344. */
  1345. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc, enum hal_ring_type ring_type, int ring_num)
  1346. {
  1347. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1348. uint8_t status = 0;
  1349. switch (ring_type) {
  1350. case WBM2SW_RELEASE:
  1351. case REO_DST:
  1352. case RXDMA_BUF:
  1353. status = ((nss_config) & (1 << ring_num));
  1354. break;
  1355. default:
  1356. break;
  1357. }
  1358. return status;
  1359. }
  1360. /*
  1361. * dp_soc_reset_intr_mask() - reset interrupt mask
  1362. * @dp_soc - DP Soc handle
  1363. *
  1364. * Return: Return void
  1365. */
  1366. static void dp_soc_reset_intr_mask(struct dp_soc *soc)
  1367. {
  1368. uint8_t j;
  1369. int *grp_mask = NULL;
  1370. int group_number, mask, num_ring;
  1371. /* number of tx ring */
  1372. num_ring = wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1373. /*
  1374. * group mask for tx completion ring.
  1375. */
  1376. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  1377. /* loop and reset the mask for only offloaded ring */
  1378. for (j = 0; j < num_ring; j++) {
  1379. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j)) {
  1380. continue;
  1381. }
  1382. /*
  1383. * Group number corresponding to tx offloaded ring.
  1384. */
  1385. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1386. if (group_number < 0) {
  1387. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1388. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1389. WBM2SW_RELEASE, j);
  1390. return;
  1391. }
  1392. /* reset the tx mask for offloaded ring */
  1393. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1394. mask &= (~(1 << j));
  1395. /*
  1396. * reset the interrupt mask for offloaded ring.
  1397. */
  1398. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1399. }
  1400. /* number of rx rings */
  1401. num_ring = wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1402. /*
  1403. * group mask for reo destination ring.
  1404. */
  1405. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  1406. /* loop and reset the mask for only offloaded ring */
  1407. for (j = 0; j < num_ring; j++) {
  1408. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j)) {
  1409. continue;
  1410. }
  1411. /*
  1412. * Group number corresponding to rx offloaded ring.
  1413. */
  1414. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1415. if (group_number < 0) {
  1416. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1417. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1418. REO_DST, j);
  1419. return;
  1420. }
  1421. /* set the interrupt mask for offloaded ring */
  1422. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1423. mask &= (~(1 << j));
  1424. /*
  1425. * set the interrupt mask to zero for rx offloaded radio.
  1426. */
  1427. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1428. }
  1429. /*
  1430. * group mask for Rx buffer refill ring
  1431. */
  1432. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  1433. /* loop and reset the mask for only offloaded ring */
  1434. for (j = 0; j < MAX_PDEV_CNT; j++) {
  1435. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF, j)) {
  1436. continue;
  1437. }
  1438. /*
  1439. * Group number corresponding to rx offloaded ring.
  1440. */
  1441. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1442. if (group_number < 0) {
  1443. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1444. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1445. REO_DST, j);
  1446. return;
  1447. }
  1448. /* set the interrupt mask for offloaded ring */
  1449. mask = wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  1450. group_number);
  1451. mask &= (~(1 << j));
  1452. /*
  1453. * set the interrupt mask to zero for rx offloaded radio.
  1454. */
  1455. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  1456. group_number, mask);
  1457. }
  1458. }
  1459. #ifdef IPA_OFFLOAD
  1460. /**
  1461. * dp_reo_remap_config() - configure reo remap register value based
  1462. * nss configuration.
  1463. * based on offload_radio value below remap configuration
  1464. * get applied.
  1465. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1466. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1467. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1468. * 3 - both Radios handled by NSS (remap not required)
  1469. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1470. *
  1471. * @remap1: output parameter indicates reo remap 1 register value
  1472. * @remap2: output parameter indicates reo remap 2 register value
  1473. * Return: bool type, true if remap is configured else false.
  1474. */
  1475. static bool dp_reo_remap_config(struct dp_soc *soc,
  1476. uint32_t *remap1,
  1477. uint32_t *remap2)
  1478. {
  1479. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1480. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1481. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1482. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1483. return true;
  1484. }
  1485. #else
  1486. static bool dp_reo_remap_config(struct dp_soc *soc,
  1487. uint32_t *remap1,
  1488. uint32_t *remap2)
  1489. {
  1490. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1491. switch (offload_radio) {
  1492. case 0:
  1493. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1494. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1495. (0x3 << 18) | (0x4 << 21)) << 8;
  1496. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1497. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1498. (0x3 << 18) | (0x4 << 21)) << 8;
  1499. break;
  1500. case 1:
  1501. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1502. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1503. (0x2 << 18) | (0x3 << 21)) << 8;
  1504. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1505. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1506. (0x4 << 18) | (0x2 << 21)) << 8;
  1507. break;
  1508. case 2:
  1509. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1510. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1511. (0x1 << 18) | (0x3 << 21)) << 8;
  1512. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1513. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1514. (0x4 << 18) | (0x1 << 21)) << 8;
  1515. break;
  1516. case 3:
  1517. /* return false if both radios are offloaded to NSS */
  1518. return false;
  1519. }
  1520. return true;
  1521. }
  1522. #endif
  1523. /*
  1524. * dp_soc_cmn_setup() - Common SoC level initializion
  1525. * @soc: Datapath SOC handle
  1526. *
  1527. * This is an internal function used to setup common SOC data structures,
  1528. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1529. */
  1530. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1531. {
  1532. int i;
  1533. struct hal_reo_params reo_params;
  1534. int tx_ring_size;
  1535. int tx_comp_ring_size;
  1536. if (qdf_atomic_read(&soc->cmn_init_done))
  1537. return 0;
  1538. if (dp_peer_find_attach(soc))
  1539. goto fail0;
  1540. if (dp_hw_link_desc_pool_setup(soc))
  1541. goto fail1;
  1542. /* Setup SRNG rings */
  1543. /* Common rings */
  1544. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1545. WBM_RELEASE_RING_SIZE)) {
  1546. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1547. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1548. goto fail1;
  1549. }
  1550. soc->num_tcl_data_rings = 0;
  1551. /* Tx data rings */
  1552. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1553. soc->num_tcl_data_rings =
  1554. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1555. tx_comp_ring_size =
  1556. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1557. tx_ring_size =
  1558. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1559. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1560. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1561. TCL_DATA, i, 0, tx_ring_size)) {
  1562. QDF_TRACE(QDF_MODULE_ID_DP,
  1563. QDF_TRACE_LEVEL_ERROR,
  1564. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1565. goto fail1;
  1566. }
  1567. /*
  1568. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1569. * count
  1570. */
  1571. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1572. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1573. QDF_TRACE(QDF_MODULE_ID_DP,
  1574. QDF_TRACE_LEVEL_ERROR,
  1575. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1576. goto fail1;
  1577. }
  1578. }
  1579. } else {
  1580. /* This will be incremented during per pdev ring setup */
  1581. soc->num_tcl_data_rings = 0;
  1582. }
  1583. if (dp_tx_soc_attach(soc)) {
  1584. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1585. FL("dp_tx_soc_attach failed"));
  1586. goto fail1;
  1587. }
  1588. /* TCL command and status rings */
  1589. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1590. TCL_CMD_RING_SIZE)) {
  1591. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1592. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1593. goto fail1;
  1594. }
  1595. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1596. TCL_STATUS_RING_SIZE)) {
  1597. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1598. FL("dp_srng_setup failed for tcl_status_ring"));
  1599. goto fail1;
  1600. }
  1601. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1602. * descriptors
  1603. */
  1604. /* Rx data rings */
  1605. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1606. soc->num_reo_dest_rings =
  1607. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1608. QDF_TRACE(QDF_MODULE_ID_DP,
  1609. QDF_TRACE_LEVEL_ERROR,
  1610. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1611. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1612. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1613. i, 0, REO_DST_RING_SIZE)) {
  1614. QDF_TRACE(QDF_MODULE_ID_DP,
  1615. QDF_TRACE_LEVEL_ERROR,
  1616. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1617. goto fail1;
  1618. }
  1619. }
  1620. } else {
  1621. /* This will be incremented during per pdev ring setup */
  1622. soc->num_reo_dest_rings = 0;
  1623. }
  1624. /* LMAC RxDMA to SW Rings configuration */
  1625. if (!wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx)) {
  1626. /* Only valid for MCL */
  1627. struct dp_pdev *pdev = soc->pdev_list[0];
  1628. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  1629. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring[i],
  1630. RXDMA_DST, 0, i, RXDMA_ERR_DST_RING_SIZE)) {
  1631. QDF_TRACE(QDF_MODULE_ID_DP,
  1632. QDF_TRACE_LEVEL_ERROR,
  1633. FL("dp_srng_setup failed for rxdma_err_dst_ring"));
  1634. goto fail1;
  1635. }
  1636. }
  1637. }
  1638. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1639. /* REO reinjection ring */
  1640. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1641. REO_REINJECT_RING_SIZE)) {
  1642. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1643. FL("dp_srng_setup failed for reo_reinject_ring"));
  1644. goto fail1;
  1645. }
  1646. /* Rx release ring */
  1647. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1648. RX_RELEASE_RING_SIZE)) {
  1649. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1650. FL("dp_srng_setup failed for rx_rel_ring"));
  1651. goto fail1;
  1652. }
  1653. /* Rx exception ring */
  1654. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1655. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1656. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1657. FL("dp_srng_setup failed for reo_exception_ring"));
  1658. goto fail1;
  1659. }
  1660. /* REO command and status rings */
  1661. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1662. REO_CMD_RING_SIZE)) {
  1663. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1664. FL("dp_srng_setup failed for reo_cmd_ring"));
  1665. goto fail1;
  1666. }
  1667. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1668. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1669. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1670. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1671. REO_STATUS_RING_SIZE)) {
  1672. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1673. FL("dp_srng_setup failed for reo_status_ring"));
  1674. goto fail1;
  1675. }
  1676. qdf_spinlock_create(&soc->ast_lock);
  1677. dp_soc_wds_attach(soc);
  1678. /* Reset the cpu ring map if radio is NSS offloaded */
  1679. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1680. dp_soc_reset_cpu_ring_map(soc);
  1681. dp_soc_reset_intr_mask(soc);
  1682. }
  1683. /* Setup HW REO */
  1684. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1685. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1686. /*
  1687. * Reo ring remap is not required if both radios
  1688. * are offloaded to NSS
  1689. */
  1690. if (!dp_reo_remap_config(soc,
  1691. &reo_params.remap1,
  1692. &reo_params.remap2))
  1693. goto out;
  1694. reo_params.rx_hash_enabled = true;
  1695. }
  1696. out:
  1697. hal_reo_setup(soc->hal_soc, &reo_params);
  1698. qdf_atomic_set(&soc->cmn_init_done, 1);
  1699. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1700. return 0;
  1701. fail1:
  1702. /*
  1703. * Cleanup will be done as part of soc_detach, which will
  1704. * be called on pdev attach failure
  1705. */
  1706. fail0:
  1707. return QDF_STATUS_E_FAILURE;
  1708. }
  1709. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1710. static void dp_lro_hash_setup(struct dp_soc *soc)
  1711. {
  1712. struct cdp_lro_hash_config lro_hash;
  1713. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1714. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1715. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1716. FL("LRO disabled RX hash disabled"));
  1717. return;
  1718. }
  1719. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1720. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1721. lro_hash.lro_enable = 1;
  1722. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1723. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1724. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1725. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1726. }
  1727. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW, FL("enabled"));
  1728. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1729. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1730. LRO_IPV4_SEED_ARR_SZ));
  1731. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1732. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1733. LRO_IPV6_SEED_ARR_SZ));
  1734. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  1735. "lro_hash: lro_enable: 0x%x tcp_flag 0x%x tcp_flag_mask 0x%x",
  1736. lro_hash.lro_enable, lro_hash.tcp_flag,
  1737. lro_hash.tcp_flag_mask);
  1738. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1739. QDF_TRACE_LEVEL_ERROR,
  1740. (void *)lro_hash.toeplitz_hash_ipv4,
  1741. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1742. LRO_IPV4_SEED_ARR_SZ));
  1743. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1744. QDF_TRACE_LEVEL_ERROR,
  1745. (void *)lro_hash.toeplitz_hash_ipv6,
  1746. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1747. LRO_IPV6_SEED_ARR_SZ));
  1748. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1749. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1750. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1751. (soc->osif_soc, &lro_hash);
  1752. }
  1753. /*
  1754. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1755. * @soc: data path SoC handle
  1756. * @pdev: Physical device handle
  1757. *
  1758. * Return: 0 - success, > 0 - failure
  1759. */
  1760. #ifdef QCA_HOST2FW_RXBUF_RING
  1761. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1762. struct dp_pdev *pdev)
  1763. {
  1764. int max_mac_rings =
  1765. wlan_cfg_get_num_mac_rings
  1766. (pdev->wlan_cfg_ctx);
  1767. int i;
  1768. for (i = 0; i < max_mac_rings; i++) {
  1769. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1770. "%s: pdev_id %d mac_id %d\n",
  1771. __func__, pdev->pdev_id, i);
  1772. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1773. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1774. QDF_TRACE(QDF_MODULE_ID_DP,
  1775. QDF_TRACE_LEVEL_ERROR,
  1776. FL("failed rx mac ring setup"));
  1777. return QDF_STATUS_E_FAILURE;
  1778. }
  1779. }
  1780. return QDF_STATUS_SUCCESS;
  1781. }
  1782. #else
  1783. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1784. struct dp_pdev *pdev)
  1785. {
  1786. return QDF_STATUS_SUCCESS;
  1787. }
  1788. #endif
  1789. /**
  1790. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1791. * @pdev - DP_PDEV handle
  1792. *
  1793. * Return: void
  1794. */
  1795. static inline void
  1796. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1797. {
  1798. uint8_t map_id;
  1799. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1800. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1801. sizeof(default_dscp_tid_map));
  1802. }
  1803. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1804. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1805. pdev->dscp_tid_map[map_id],
  1806. map_id);
  1807. }
  1808. }
  1809. /*
  1810. * dp_pdev_attach_wifi3() - attach txrx pdev
  1811. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1812. * @txrx_soc: Datapath SOC handle
  1813. * @htc_handle: HTC handle for host-target interface
  1814. * @qdf_osdev: QDF OS device
  1815. * @pdev_id: PDEV ID
  1816. *
  1817. * Return: DP PDEV handle on success, NULL on failure
  1818. */
  1819. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1820. struct cdp_cfg *ctrl_pdev,
  1821. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1822. {
  1823. int tx_ring_size;
  1824. int tx_comp_ring_size;
  1825. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1826. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1827. if (!pdev) {
  1828. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1829. FL("DP PDEV memory allocation failed"));
  1830. goto fail0;
  1831. }
  1832. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1833. if (!pdev->wlan_cfg_ctx) {
  1834. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1835. FL("pdev cfg_attach failed"));
  1836. qdf_mem_free(pdev);
  1837. goto fail0;
  1838. }
  1839. /*
  1840. * set nss pdev config based on soc config
  1841. */
  1842. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1843. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1844. pdev->soc = soc;
  1845. pdev->osif_pdev = ctrl_pdev;
  1846. pdev->pdev_id = pdev_id;
  1847. soc->pdev_list[pdev_id] = pdev;
  1848. soc->pdev_count++;
  1849. TAILQ_INIT(&pdev->vdev_list);
  1850. pdev->vdev_count = 0;
  1851. qdf_spinlock_create(&pdev->tx_mutex);
  1852. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1853. TAILQ_INIT(&pdev->neighbour_peers_list);
  1854. if (dp_soc_cmn_setup(soc)) {
  1855. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1856. FL("dp_soc_cmn_setup failed"));
  1857. goto fail1;
  1858. }
  1859. /* Setup per PDEV TCL rings if configured */
  1860. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1861. tx_ring_size =
  1862. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1863. tx_comp_ring_size =
  1864. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1865. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1866. pdev_id, pdev_id, tx_ring_size)) {
  1867. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1868. FL("dp_srng_setup failed for tcl_data_ring"));
  1869. goto fail1;
  1870. }
  1871. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1872. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1873. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1874. FL("dp_srng_setup failed for tx_comp_ring"));
  1875. goto fail1;
  1876. }
  1877. soc->num_tcl_data_rings++;
  1878. }
  1879. /* Tx specific init */
  1880. if (dp_tx_pdev_attach(pdev)) {
  1881. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1882. FL("dp_tx_pdev_attach failed"));
  1883. goto fail1;
  1884. }
  1885. /* Setup per PDEV REO rings if configured */
  1886. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1887. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1888. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1889. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1890. FL("dp_srng_setup failed for reo_dest_ringn"));
  1891. goto fail1;
  1892. }
  1893. soc->num_reo_dest_rings++;
  1894. }
  1895. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1896. RXDMA_REFILL_RING_SIZE)) {
  1897. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1898. FL("dp_srng_setup failed rx refill ring"));
  1899. goto fail1;
  1900. }
  1901. if (dp_rxdma_ring_setup(soc, pdev)) {
  1902. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1903. FL("RXDMA ring config failed"));
  1904. goto fail1;
  1905. }
  1906. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1907. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1908. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1909. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1910. goto fail1;
  1911. }
  1912. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1913. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1914. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1915. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1916. goto fail1;
  1917. }
  1918. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  1919. RXDMA_MONITOR_STATUS, 0, pdev_id,
  1920. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  1921. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1922. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  1923. goto fail1;
  1924. }
  1925. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  1926. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  1927. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1928. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  1929. goto fail1;
  1930. }
  1931. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx)) {
  1932. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring[0], RXDMA_DST,
  1933. 0, pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  1934. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1935. FL("dp_srng_setup failed for rxdma_err_dst_ring"));
  1936. goto fail1;
  1937. }
  1938. }
  1939. /* Setup second Rx refill buffer ring */
  1940. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring2, RXDMA_BUF, 2,
  1941. pdev->pdev_id, RXDMA_REFILL_RING_SIZE)) {
  1942. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1943. FL("dp_srng_setup failed second rx refill ring"));
  1944. goto fail1;
  1945. }
  1946. if (dp_ipa_ring_resource_setup(soc, pdev))
  1947. goto fail1;
  1948. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  1949. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1950. FL("dp_ipa_uc_attach failed"));
  1951. goto fail1;
  1952. }
  1953. /* Rx specific init */
  1954. if (dp_rx_pdev_attach(pdev)) {
  1955. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1956. FL("dp_rx_pdev_attach failed"));
  1957. goto fail0;
  1958. }
  1959. DP_STATS_INIT(pdev);
  1960. #ifndef CONFIG_WIN
  1961. /* MCL */
  1962. dp_local_peer_id_pool_init(pdev);
  1963. #endif
  1964. dp_dscp_tid_map_setup(pdev);
  1965. /* Rx monitor mode specific init */
  1966. if (dp_rx_pdev_mon_attach(pdev)) {
  1967. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1968. "dp_rx_pdev_attach failed\n");
  1969. goto fail1;
  1970. }
  1971. if (dp_wdi_event_attach(pdev)) {
  1972. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1973. "dp_wdi_evet_attach failed\n");
  1974. goto fail1;
  1975. }
  1976. /* set the reo destination during initialization */
  1977. pdev->reo_dest = pdev->pdev_id + 1;
  1978. return (struct cdp_pdev *)pdev;
  1979. fail1:
  1980. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  1981. fail0:
  1982. return NULL;
  1983. }
  1984. /*
  1985. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  1986. * @soc: data path SoC handle
  1987. * @pdev: Physical device handle
  1988. *
  1989. * Return: void
  1990. */
  1991. #ifdef QCA_HOST2FW_RXBUF_RING
  1992. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1993. struct dp_pdev *pdev)
  1994. {
  1995. int max_mac_rings =
  1996. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  1997. int i;
  1998. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  1999. max_mac_rings : MAX_RX_MAC_RINGS;
  2000. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2001. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2002. RXDMA_BUF, 1);
  2003. }
  2004. #else
  2005. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2006. struct dp_pdev *pdev)
  2007. {
  2008. }
  2009. #endif
  2010. /*
  2011. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2012. * @pdev: device object
  2013. *
  2014. * Return: void
  2015. */
  2016. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2017. {
  2018. struct dp_neighbour_peer *peer = NULL;
  2019. struct dp_neighbour_peer *temp_peer = NULL;
  2020. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2021. neighbour_peer_list_elem, temp_peer) {
  2022. /* delete this peer from the list */
  2023. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2024. peer, neighbour_peer_list_elem);
  2025. qdf_mem_free(peer);
  2026. }
  2027. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2028. }
  2029. /*
  2030. * dp_pdev_detach_wifi3() - detach txrx pdev
  2031. * @txrx_pdev: Datapath PDEV handle
  2032. * @force: Force detach
  2033. *
  2034. */
  2035. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2036. {
  2037. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2038. struct dp_soc *soc = pdev->soc;
  2039. dp_wdi_event_detach(pdev);
  2040. dp_tx_pdev_detach(pdev);
  2041. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2042. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2043. TCL_DATA, pdev->pdev_id);
  2044. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2045. WBM2SW_RELEASE, pdev->pdev_id);
  2046. }
  2047. dp_rx_pdev_detach(pdev);
  2048. dp_rx_pdev_mon_detach(pdev);
  2049. dp_neighbour_peers_detach(pdev);
  2050. qdf_spinlock_destroy(&pdev->tx_mutex);
  2051. dp_ipa_uc_detach(soc, pdev);
  2052. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring2, RXDMA_BUF, 2);
  2053. /* Cleanup per PDEV REO rings if configured */
  2054. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2055. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2056. REO_DST, pdev->pdev_id);
  2057. }
  2058. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2059. dp_rxdma_ring_cleanup(soc, pdev);
  2060. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2061. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2062. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2063. RXDMA_MONITOR_STATUS, 0);
  2064. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2065. RXDMA_MONITOR_DESC, 0);
  2066. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx)) {
  2067. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring[0], RXDMA_DST, 0);
  2068. } else {
  2069. int i;
  2070. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2071. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring[i],
  2072. RXDMA_DST, 0);
  2073. }
  2074. soc->pdev_list[pdev->pdev_id] = NULL;
  2075. soc->pdev_count--;
  2076. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2077. qdf_mem_free(pdev);
  2078. }
  2079. /*
  2080. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2081. * @soc: DP SOC handle
  2082. */
  2083. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2084. {
  2085. struct reo_desc_list_node *desc;
  2086. struct dp_rx_tid *rx_tid;
  2087. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2088. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2089. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2090. rx_tid = &desc->rx_tid;
  2091. qdf_mem_unmap_nbytes_single(soc->osdev,
  2092. rx_tid->hw_qdesc_paddr,
  2093. QDF_DMA_BIDIRECTIONAL,
  2094. rx_tid->hw_qdesc_alloc_size);
  2095. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2096. qdf_mem_free(desc);
  2097. }
  2098. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2099. qdf_list_destroy(&soc->reo_desc_freelist);
  2100. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2101. }
  2102. /*
  2103. * dp_soc_detach_wifi3() - Detach txrx SOC
  2104. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2105. */
  2106. static void dp_soc_detach_wifi3(void *txrx_soc)
  2107. {
  2108. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2109. int i;
  2110. qdf_atomic_set(&soc->cmn_init_done, 0);
  2111. qdf_flush_work(&soc->htt_stats.work);
  2112. qdf_disable_work(&soc->htt_stats.work);
  2113. /* Free pending htt stats messages */
  2114. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2115. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2116. if (soc->pdev_list[i])
  2117. dp_pdev_detach_wifi3(
  2118. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2119. }
  2120. dp_peer_find_detach(soc);
  2121. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2122. * SW descriptors
  2123. */
  2124. /* Free the ring memories */
  2125. /* Common rings */
  2126. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2127. dp_tx_soc_detach(soc);
  2128. /* Tx data rings */
  2129. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2130. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2131. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2132. TCL_DATA, i);
  2133. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2134. WBM2SW_RELEASE, i);
  2135. }
  2136. }
  2137. /* TCL command and status rings */
  2138. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2139. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2140. /* Rx data rings */
  2141. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2142. soc->num_reo_dest_rings =
  2143. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2144. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2145. /* TODO: Get number of rings and ring sizes
  2146. * from wlan_cfg
  2147. */
  2148. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2149. REO_DST, i);
  2150. }
  2151. }
  2152. /* REO reinjection ring */
  2153. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2154. /* Rx release ring */
  2155. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2156. /* Rx exception ring */
  2157. /* TODO: Better to store ring_type and ring_num in
  2158. * dp_srng during setup
  2159. */
  2160. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2161. /* REO command and status rings */
  2162. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2163. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2164. dp_hw_link_desc_pool_cleanup(soc);
  2165. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2166. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2167. htt_soc_detach(soc->htt_handle);
  2168. dp_reo_cmdlist_destroy(soc);
  2169. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2170. dp_reo_desc_freelist_destroy(soc);
  2171. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2172. dp_soc_wds_detach(soc);
  2173. qdf_spinlock_destroy(&soc->ast_lock);
  2174. qdf_mem_free(soc);
  2175. }
  2176. /*
  2177. * dp_rxdma_ring_config() - configure the RX DMA rings
  2178. *
  2179. * This function is used to configure the MAC rings.
  2180. * On MCL host provides buffers in Host2FW ring
  2181. * FW refills (copies) buffers to the ring and updates
  2182. * ring_idx in register
  2183. *
  2184. * @soc: data path SoC handle
  2185. *
  2186. * Return: void
  2187. */
  2188. #ifdef QCA_HOST2FW_RXBUF_RING
  2189. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2190. {
  2191. int i;
  2192. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2193. struct dp_pdev *pdev = soc->pdev_list[i];
  2194. if (pdev) {
  2195. int mac_id = 0;
  2196. int j;
  2197. bool dbs_enable = 0;
  2198. int max_mac_rings =
  2199. wlan_cfg_get_num_mac_rings
  2200. (pdev->wlan_cfg_ctx);
  2201. htt_srng_setup(soc->htt_handle, 0,
  2202. pdev->rx_refill_buf_ring.hal_srng,
  2203. RXDMA_BUF);
  2204. if (pdev->rx_refill_buf_ring2.hal_srng)
  2205. htt_srng_setup(soc->htt_handle, 0,
  2206. pdev->rx_refill_buf_ring2.hal_srng,
  2207. RXDMA_BUF);
  2208. if (soc->cdp_soc.ol_ops->
  2209. is_hw_dbs_2x2_capable) {
  2210. dbs_enable = soc->cdp_soc.ol_ops->
  2211. is_hw_dbs_2x2_capable(soc->psoc);
  2212. }
  2213. if (dbs_enable) {
  2214. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2215. QDF_TRACE_LEVEL_ERROR,
  2216. FL("DBS enabled max_mac_rings %d\n"),
  2217. max_mac_rings);
  2218. } else {
  2219. max_mac_rings = 1;
  2220. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2221. QDF_TRACE_LEVEL_ERROR,
  2222. FL("DBS disabled, max_mac_rings %d\n"),
  2223. max_mac_rings);
  2224. }
  2225. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2226. FL("pdev_id %d max_mac_rings %d\n"),
  2227. pdev->pdev_id, max_mac_rings);
  2228. for (j = 0; j < max_mac_rings; j++) {
  2229. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2230. QDF_TRACE_LEVEL_ERROR,
  2231. FL("mac_id %d\n"), mac_id);
  2232. htt_srng_setup(soc->htt_handle, mac_id,
  2233. pdev->rx_mac_buf_ring[j]
  2234. .hal_srng,
  2235. RXDMA_BUF);
  2236. htt_srng_setup(soc->htt_handle, mac_id,
  2237. pdev->rxdma_err_dst_ring[j]
  2238. .hal_srng,
  2239. RXDMA_DST);
  2240. mac_id++;
  2241. }
  2242. /* Configure monitor mode rings */
  2243. htt_srng_setup(soc->htt_handle, i,
  2244. pdev->rxdma_mon_buf_ring.hal_srng,
  2245. RXDMA_MONITOR_BUF);
  2246. htt_srng_setup(soc->htt_handle, i,
  2247. pdev->rxdma_mon_dst_ring.hal_srng,
  2248. RXDMA_MONITOR_DST);
  2249. htt_srng_setup(soc->htt_handle, i,
  2250. pdev->rxdma_mon_status_ring.hal_srng,
  2251. RXDMA_MONITOR_STATUS);
  2252. htt_srng_setup(soc->htt_handle, i,
  2253. pdev->rxdma_mon_desc_ring.hal_srng,
  2254. RXDMA_MONITOR_DESC);
  2255. }
  2256. }
  2257. }
  2258. #else
  2259. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2260. {
  2261. int i;
  2262. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2263. struct dp_pdev *pdev = soc->pdev_list[i];
  2264. if (pdev) {
  2265. int ring_idx = dp_get_ring_id_for_mac_id(soc, i);
  2266. htt_srng_setup(soc->htt_handle, i,
  2267. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2268. htt_srng_setup(soc->htt_handle, i,
  2269. pdev->rxdma_mon_buf_ring.hal_srng,
  2270. RXDMA_MONITOR_BUF);
  2271. htt_srng_setup(soc->htt_handle, i,
  2272. pdev->rxdma_mon_dst_ring.hal_srng,
  2273. RXDMA_MONITOR_DST);
  2274. htt_srng_setup(soc->htt_handle, i,
  2275. pdev->rxdma_mon_status_ring.hal_srng,
  2276. RXDMA_MONITOR_STATUS);
  2277. htt_srng_setup(soc->htt_handle, i,
  2278. pdev->rxdma_mon_desc_ring.hal_srng,
  2279. RXDMA_MONITOR_DESC);
  2280. htt_srng_setup(soc->htt_handle, i,
  2281. pdev->rxdma_err_dst_ring[ring_idx].hal_srng,
  2282. RXDMA_DST);
  2283. }
  2284. }
  2285. }
  2286. #endif
  2287. /*
  2288. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2289. * @txrx_soc: Datapath SOC handle
  2290. */
  2291. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2292. {
  2293. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2294. htt_soc_attach_target(soc->htt_handle);
  2295. dp_rxdma_ring_config(soc);
  2296. DP_STATS_INIT(soc);
  2297. /* initialize work queue for stats processing */
  2298. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2299. return 0;
  2300. }
  2301. /*
  2302. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2303. * @txrx_soc: Datapath SOC handle
  2304. */
  2305. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2306. {
  2307. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2308. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2309. }
  2310. /*
  2311. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2312. * @txrx_soc: Datapath SOC handle
  2313. * @nss_cfg: nss config
  2314. */
  2315. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2316. {
  2317. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2318. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2319. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2320. FL("nss-wifi<0> nss config is enabled"));
  2321. }
  2322. /*
  2323. * dp_vdev_attach_wifi3() - attach txrx vdev
  2324. * @txrx_pdev: Datapath PDEV handle
  2325. * @vdev_mac_addr: MAC address of the virtual interface
  2326. * @vdev_id: VDEV Id
  2327. * @wlan_op_mode: VDEV operating mode
  2328. *
  2329. * Return: DP VDEV handle on success, NULL on failure
  2330. */
  2331. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2332. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2333. {
  2334. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2335. struct dp_soc *soc = pdev->soc;
  2336. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2337. int tx_ring_size;
  2338. if (!vdev) {
  2339. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2340. FL("DP VDEV memory allocation failed"));
  2341. goto fail0;
  2342. }
  2343. vdev->pdev = pdev;
  2344. vdev->vdev_id = vdev_id;
  2345. vdev->opmode = op_mode;
  2346. vdev->osdev = soc->osdev;
  2347. vdev->osif_rx = NULL;
  2348. vdev->osif_rsim_rx_decap = NULL;
  2349. vdev->osif_get_key = NULL;
  2350. vdev->osif_rx_mon = NULL;
  2351. vdev->osif_tx_free_ext = NULL;
  2352. vdev->osif_vdev = NULL;
  2353. vdev->delete.pending = 0;
  2354. vdev->safemode = 0;
  2355. vdev->drop_unenc = 1;
  2356. vdev->sec_type = cdp_sec_type_none;
  2357. #ifdef notyet
  2358. vdev->filters_num = 0;
  2359. #endif
  2360. qdf_mem_copy(
  2361. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2362. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2363. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2364. vdev->dscp_tid_map_id = 0;
  2365. vdev->mcast_enhancement_en = 0;
  2366. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2367. /* TODO: Initialize default HTT meta data that will be used in
  2368. * TCL descriptors for packets transmitted from this VDEV
  2369. */
  2370. TAILQ_INIT(&vdev->peer_list);
  2371. /* add this vdev into the pdev's list */
  2372. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2373. pdev->vdev_count++;
  2374. dp_tx_vdev_attach(vdev);
  2375. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2376. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2377. goto fail1;
  2378. if ((soc->intr_mode == DP_INTR_POLL) &&
  2379. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2380. if (pdev->vdev_count == 1)
  2381. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2382. }
  2383. dp_lro_hash_setup(soc);
  2384. /* LRO */
  2385. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2386. wlan_op_mode_sta == vdev->opmode)
  2387. vdev->lro_enable = true;
  2388. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2389. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2390. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2391. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2392. DP_STATS_INIT(vdev);
  2393. return (struct cdp_vdev *)vdev;
  2394. fail1:
  2395. dp_tx_vdev_detach(vdev);
  2396. qdf_mem_free(vdev);
  2397. fail0:
  2398. return NULL;
  2399. }
  2400. /**
  2401. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2402. * @vdev: Datapath VDEV handle
  2403. * @osif_vdev: OSIF vdev handle
  2404. * @txrx_ops: Tx and Rx operations
  2405. *
  2406. * Return: DP VDEV handle on success, NULL on failure
  2407. */
  2408. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2409. void *osif_vdev,
  2410. struct ol_txrx_ops *txrx_ops)
  2411. {
  2412. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2413. vdev->osif_vdev = osif_vdev;
  2414. vdev->osif_rx = txrx_ops->rx.rx;
  2415. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2416. vdev->osif_get_key = txrx_ops->get_key;
  2417. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2418. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2419. #ifdef notyet
  2420. #if ATH_SUPPORT_WAPI
  2421. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2422. #endif
  2423. #endif
  2424. #ifdef UMAC_SUPPORT_PROXY_ARP
  2425. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2426. #endif
  2427. vdev->me_convert = txrx_ops->me_convert;
  2428. /* TODO: Enable the following once Tx code is integrated */
  2429. txrx_ops->tx.tx = dp_tx_send;
  2430. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  2431. "DP Vdev Register success");
  2432. }
  2433. /*
  2434. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2435. * @txrx_vdev: Datapath VDEV handle
  2436. * @callback: Callback OL_IF on completion of detach
  2437. * @cb_context: Callback context
  2438. *
  2439. */
  2440. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2441. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2442. {
  2443. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2444. struct dp_pdev *pdev = vdev->pdev;
  2445. struct dp_soc *soc = pdev->soc;
  2446. /* preconditions */
  2447. qdf_assert(vdev);
  2448. /* remove the vdev from its parent pdev's list */
  2449. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2450. /*
  2451. * Use peer_ref_mutex while accessing peer_list, in case
  2452. * a peer is in the process of being removed from the list.
  2453. */
  2454. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2455. /* check that the vdev has no peers allocated */
  2456. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2457. /* debug print - will be removed later */
  2458. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2459. FL("not deleting vdev object %pK (%pM)"
  2460. "until deletion finishes for all its peers"),
  2461. vdev, vdev->mac_addr.raw);
  2462. /* indicate that the vdev needs to be deleted */
  2463. vdev->delete.pending = 1;
  2464. vdev->delete.callback = callback;
  2465. vdev->delete.context = cb_context;
  2466. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2467. return;
  2468. }
  2469. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2470. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2471. vdev->vdev_id);
  2472. dp_tx_vdev_detach(vdev);
  2473. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2474. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  2475. qdf_mem_free(vdev);
  2476. if (callback)
  2477. callback(cb_context);
  2478. }
  2479. /*
  2480. * dp_peer_create_wifi3() - attach txrx peer
  2481. * @txrx_vdev: Datapath VDEV handle
  2482. * @peer_mac_addr: Peer MAC address
  2483. *
  2484. * Return: DP peeer handle on success, NULL on failure
  2485. */
  2486. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2487. uint8_t *peer_mac_addr)
  2488. {
  2489. struct dp_peer *peer;
  2490. int i;
  2491. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2492. struct dp_pdev *pdev;
  2493. struct dp_soc *soc;
  2494. /* preconditions */
  2495. qdf_assert(vdev);
  2496. qdf_assert(peer_mac_addr);
  2497. pdev = vdev->pdev;
  2498. soc = pdev->soc;
  2499. #ifdef notyet
  2500. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2501. soc->mempool_ol_ath_peer);
  2502. #else
  2503. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2504. #endif
  2505. if (!peer)
  2506. return NULL; /* failure */
  2507. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2508. TAILQ_INIT(&peer->ast_entry_list);
  2509. /* store provided params */
  2510. peer->vdev = vdev;
  2511. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2512. qdf_spinlock_create(&peer->peer_info_lock);
  2513. qdf_mem_copy(
  2514. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2515. /* TODO: See of rx_opt_proc is really required */
  2516. peer->rx_opt_proc = soc->rx_opt_proc;
  2517. /* initialize the peer_id */
  2518. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2519. peer->peer_ids[i] = HTT_INVALID_PEER;
  2520. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2521. qdf_atomic_init(&peer->ref_cnt);
  2522. /* keep one reference for attach */
  2523. qdf_atomic_inc(&peer->ref_cnt);
  2524. /* add this peer into the vdev's list */
  2525. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2526. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2527. /* TODO: See if hash based search is required */
  2528. dp_peer_find_hash_add(soc, peer);
  2529. /* Initialize the peer state */
  2530. peer->state = OL_TXRX_PEER_STATE_DISC;
  2531. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2532. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  2533. vdev, peer, peer->mac_addr.raw,
  2534. qdf_atomic_read(&peer->ref_cnt));
  2535. /*
  2536. * For every peer MAp message search and set if bss_peer
  2537. */
  2538. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2539. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2540. "vdev bss_peer!!!!");
  2541. peer->bss_peer = 1;
  2542. vdev->vap_bss_peer = peer;
  2543. }
  2544. #ifndef CONFIG_WIN
  2545. dp_local_peer_id_alloc(pdev, peer);
  2546. #endif
  2547. DP_STATS_INIT(peer);
  2548. return (void *)peer;
  2549. }
  2550. /*
  2551. * dp_peer_setup_wifi3() - initialize the peer
  2552. * @vdev_hdl: virtual device object
  2553. * @peer: Peer object
  2554. *
  2555. * Return: void
  2556. */
  2557. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2558. {
  2559. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2560. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2561. struct dp_pdev *pdev;
  2562. struct dp_soc *soc;
  2563. bool hash_based = 0;
  2564. enum cdp_host_reo_dest_ring reo_dest;
  2565. /* preconditions */
  2566. qdf_assert(vdev);
  2567. qdf_assert(peer);
  2568. pdev = vdev->pdev;
  2569. soc = pdev->soc;
  2570. dp_peer_rx_init(pdev, peer);
  2571. peer->last_assoc_rcvd = 0;
  2572. peer->last_disassoc_rcvd = 0;
  2573. peer->last_deauth_rcvd = 0;
  2574. /*
  2575. * hash based steering is disabled for Radios which are offloaded
  2576. * to NSS
  2577. */
  2578. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2579. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2580. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2581. FL("hash based steering for pdev: %d is %d\n"),
  2582. pdev->pdev_id, hash_based);
  2583. /*
  2584. * Below line of code will ensure the proper reo_dest ring is choosen
  2585. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  2586. */
  2587. reo_dest = pdev->reo_dest;
  2588. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2589. /* TODO: Check the destination ring number to be passed to FW */
  2590. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2591. pdev->osif_pdev, peer->mac_addr.raw,
  2592. peer->vdev->vdev_id, hash_based, reo_dest);
  2593. }
  2594. return;
  2595. }
  2596. /*
  2597. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2598. * @vdev_handle: virtual device object
  2599. * @htt_pkt_type: type of pkt
  2600. *
  2601. * Return: void
  2602. */
  2603. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2604. enum htt_cmn_pkt_type val)
  2605. {
  2606. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2607. vdev->tx_encap_type = val;
  2608. }
  2609. /*
  2610. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2611. * @vdev_handle: virtual device object
  2612. * @htt_pkt_type: type of pkt
  2613. *
  2614. * Return: void
  2615. */
  2616. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2617. enum htt_cmn_pkt_type val)
  2618. {
  2619. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2620. vdev->rx_decap_type = val;
  2621. }
  2622. /*
  2623. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2624. * @pdev_handle: physical device object
  2625. * @val: reo destination ring index (1 - 4)
  2626. *
  2627. * Return: void
  2628. */
  2629. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2630. enum cdp_host_reo_dest_ring val)
  2631. {
  2632. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2633. if (pdev)
  2634. pdev->reo_dest = val;
  2635. }
  2636. /*
  2637. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2638. * @pdev_handle: physical device object
  2639. *
  2640. * Return: reo destination ring index
  2641. */
  2642. static enum cdp_host_reo_dest_ring
  2643. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2644. {
  2645. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2646. if (pdev)
  2647. return pdev->reo_dest;
  2648. else
  2649. return cdp_host_reo_dest_ring_unknown;
  2650. }
  2651. #ifdef QCA_SUPPORT_SON
  2652. static void dp_son_peer_authorize(struct dp_peer *peer)
  2653. {
  2654. struct dp_soc *soc;
  2655. soc = peer->vdev->pdev->soc;
  2656. peer->peer_bs_inact_flag = 0;
  2657. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2658. return;
  2659. }
  2660. #else
  2661. static void dp_son_peer_authorize(struct dp_peer *peer)
  2662. {
  2663. return;
  2664. }
  2665. #endif
  2666. /*
  2667. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2668. * @pdev_handle: device object
  2669. * @val: value to be set
  2670. *
  2671. * Return: void
  2672. */
  2673. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2674. uint32_t val)
  2675. {
  2676. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2677. /* Enable/Disable smart mesh filtering. This flag will be checked
  2678. * during rx processing to check if packets are from NAC clients.
  2679. */
  2680. pdev->filter_neighbour_peers = val;
  2681. return 0;
  2682. }
  2683. /*
  2684. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2685. * address for smart mesh filtering
  2686. * @pdev_handle: device object
  2687. * @cmd: Add/Del command
  2688. * @macaddr: nac client mac address
  2689. *
  2690. * Return: void
  2691. */
  2692. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2693. uint32_t cmd, uint8_t *macaddr)
  2694. {
  2695. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2696. struct dp_neighbour_peer *peer = NULL;
  2697. if (!macaddr)
  2698. goto fail0;
  2699. /* Store address of NAC (neighbour peer) which will be checked
  2700. * against TA of received packets.
  2701. */
  2702. if (cmd == DP_NAC_PARAM_ADD) {
  2703. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2704. sizeof(*peer));
  2705. if (!peer) {
  2706. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2707. FL("DP neighbour peer node memory allocation failed"));
  2708. goto fail0;
  2709. }
  2710. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2711. macaddr, DP_MAC_ADDR_LEN);
  2712. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2713. /* add this neighbour peer into the list */
  2714. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2715. neighbour_peer_list_elem);
  2716. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2717. return 1;
  2718. } else if (cmd == DP_NAC_PARAM_DEL) {
  2719. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2720. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2721. neighbour_peer_list_elem) {
  2722. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2723. macaddr, DP_MAC_ADDR_LEN)) {
  2724. /* delete this peer from the list */
  2725. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2726. peer, neighbour_peer_list_elem);
  2727. qdf_mem_free(peer);
  2728. break;
  2729. }
  2730. }
  2731. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2732. return 1;
  2733. }
  2734. fail0:
  2735. return 0;
  2736. }
  2737. /*
  2738. * dp_get_sec_type() - Get the security type
  2739. * @peer: Datapath peer handle
  2740. * @sec_idx: Security id (mcast, ucast)
  2741. *
  2742. * return sec_type: Security type
  2743. */
  2744. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2745. {
  2746. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2747. return dpeer->security[sec_idx].sec_type;
  2748. }
  2749. /*
  2750. * dp_peer_authorize() - authorize txrx peer
  2751. * @peer_handle: Datapath peer handle
  2752. * @authorize
  2753. *
  2754. */
  2755. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2756. {
  2757. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2758. struct dp_soc *soc;
  2759. if (peer != NULL) {
  2760. soc = peer->vdev->pdev->soc;
  2761. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2762. dp_son_peer_authorize(peer);
  2763. peer->authorize = authorize ? 1 : 0;
  2764. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2765. }
  2766. }
  2767. /*
  2768. * dp_peer_unref_delete() - unref and delete peer
  2769. * @peer_handle: Datapath peer handle
  2770. *
  2771. */
  2772. void dp_peer_unref_delete(void *peer_handle)
  2773. {
  2774. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2775. struct dp_vdev *vdev = peer->vdev;
  2776. struct dp_pdev *pdev = vdev->pdev;
  2777. struct dp_soc *soc = pdev->soc;
  2778. struct dp_peer *tmppeer;
  2779. int found = 0;
  2780. uint16_t peer_id;
  2781. /*
  2782. * Hold the lock all the way from checking if the peer ref count
  2783. * is zero until the peer references are removed from the hash
  2784. * table and vdev list (if the peer ref count is zero).
  2785. * This protects against a new HL tx operation starting to use the
  2786. * peer object just after this function concludes it's done being used.
  2787. * Furthermore, the lock needs to be held while checking whether the
  2788. * vdev's list of peers is empty, to make sure that list is not modified
  2789. * concurrently with the empty check.
  2790. */
  2791. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2792. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2793. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  2794. peer, qdf_atomic_read(&peer->ref_cnt));
  2795. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2796. peer_id = peer->peer_ids[0];
  2797. /*
  2798. * Make sure that the reference to the peer in
  2799. * peer object map is removed
  2800. */
  2801. if (peer_id != HTT_INVALID_PEER)
  2802. soc->peer_id_to_obj_map[peer_id] = NULL;
  2803. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2804. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  2805. /* remove the reference to the peer from the hash table */
  2806. dp_peer_find_hash_remove(soc, peer);
  2807. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2808. if (tmppeer == peer) {
  2809. found = 1;
  2810. break;
  2811. }
  2812. }
  2813. if (found) {
  2814. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2815. peer_list_elem);
  2816. } else {
  2817. /*Ignoring the remove operation as peer not found*/
  2818. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2819. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  2820. peer, vdev, &peer->vdev->peer_list);
  2821. }
  2822. /* cleanup the peer data */
  2823. dp_peer_cleanup(vdev, peer);
  2824. /* check whether the parent vdev has no peers left */
  2825. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2826. /*
  2827. * Now that there are no references to the peer, we can
  2828. * release the peer reference lock.
  2829. */
  2830. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2831. /*
  2832. * Check if the parent vdev was waiting for its peers
  2833. * to be deleted, in order for it to be deleted too.
  2834. */
  2835. if (vdev->delete.pending) {
  2836. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2837. vdev->delete.callback;
  2838. void *vdev_delete_context =
  2839. vdev->delete.context;
  2840. QDF_TRACE(QDF_MODULE_ID_DP,
  2841. QDF_TRACE_LEVEL_INFO_HIGH,
  2842. FL("deleting vdev object %pK (%pM)"
  2843. " - its last peer is done"),
  2844. vdev, vdev->mac_addr.raw);
  2845. /* all peers are gone, go ahead and delete it */
  2846. qdf_mem_free(vdev);
  2847. if (vdev_delete_cb)
  2848. vdev_delete_cb(vdev_delete_context);
  2849. }
  2850. } else {
  2851. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2852. }
  2853. #ifdef notyet
  2854. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2855. #else
  2856. qdf_mem_free(peer);
  2857. #endif
  2858. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2859. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2860. vdev->vdev_id, peer->mac_addr.raw);
  2861. }
  2862. } else {
  2863. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2864. }
  2865. }
  2866. /*
  2867. * dp_peer_detach_wifi3() – Detach txrx peer
  2868. * @peer_handle: Datapath peer handle
  2869. * @bitmap: bitmap indicating special handling of request.
  2870. *
  2871. */
  2872. static void dp_peer_delete_wifi3(void *peer_handle, uint32_t bitmap)
  2873. {
  2874. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2875. /* redirect the peer's rx delivery function to point to a
  2876. * discard func
  2877. */
  2878. peer->rx_opt_proc = dp_rx_discard;
  2879. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2880. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  2881. #ifndef CONFIG_WIN
  2882. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2883. #endif
  2884. qdf_spinlock_destroy(&peer->peer_info_lock);
  2885. /*
  2886. * Remove the reference added during peer_attach.
  2887. * The peer will still be left allocated until the
  2888. * PEER_UNMAP message arrives to remove the other
  2889. * reference, added by the PEER_MAP message.
  2890. */
  2891. dp_peer_unref_delete(peer_handle);
  2892. }
  2893. /*
  2894. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2895. * @peer_handle: Datapath peer handle
  2896. *
  2897. */
  2898. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2899. {
  2900. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2901. return vdev->mac_addr.raw;
  2902. }
  2903. /*
  2904. * dp_vdev_set_wds() - Enable per packet stats
  2905. * @vdev_handle: DP VDEV handle
  2906. * @val: value
  2907. *
  2908. * Return: none
  2909. */
  2910. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2911. {
  2912. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2913. vdev->wds_enabled = val;
  2914. return 0;
  2915. }
  2916. /*
  2917. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2918. * @peer_handle: Datapath peer handle
  2919. *
  2920. */
  2921. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  2922. uint8_t vdev_id)
  2923. {
  2924. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  2925. struct dp_vdev *vdev = NULL;
  2926. if (qdf_unlikely(!pdev))
  2927. return NULL;
  2928. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2929. if (vdev->vdev_id == vdev_id)
  2930. break;
  2931. }
  2932. return (struct cdp_vdev *)vdev;
  2933. }
  2934. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  2935. {
  2936. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2937. return vdev->opmode;
  2938. }
  2939. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  2940. {
  2941. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2942. struct dp_pdev *pdev = vdev->pdev;
  2943. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  2944. }
  2945. /**
  2946. * dp_reset_monitor_mode() - Disable monitor mode
  2947. * @pdev_handle: Datapath PDEV handle
  2948. *
  2949. * Return: 0 on success, not 0 on failure
  2950. */
  2951. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  2952. {
  2953. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2954. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  2955. struct dp_soc *soc;
  2956. uint8_t pdev_id;
  2957. pdev_id = pdev->pdev_id;
  2958. soc = pdev->soc;
  2959. pdev->monitor_vdev = NULL;
  2960. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  2961. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2962. pdev->rxdma_mon_buf_ring.hal_srng,
  2963. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  2964. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2965. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  2966. RX_BUFFER_SIZE, &htt_tlv_filter);
  2967. return 0;
  2968. }
  2969. /**
  2970. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  2971. * @vdev_handle: Datapath VDEV handle
  2972. * @smart_monitor: Flag to denote if its smart monitor mode
  2973. *
  2974. * Return: 0 on success, not 0 on failure
  2975. */
  2976. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  2977. uint8_t smart_monitor)
  2978. {
  2979. /* Many monitor VAPs can exists in a system but only one can be up at
  2980. * anytime
  2981. */
  2982. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2983. struct dp_pdev *pdev;
  2984. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  2985. struct dp_soc *soc;
  2986. uint8_t pdev_id;
  2987. qdf_assert(vdev);
  2988. pdev = vdev->pdev;
  2989. pdev_id = pdev->pdev_id;
  2990. soc = pdev->soc;
  2991. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  2992. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  2993. pdev, pdev_id, soc, vdev);
  2994. /*Check if current pdev's monitor_vdev exists */
  2995. if (pdev->monitor_vdev) {
  2996. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2997. "vdev=%pK\n", vdev);
  2998. qdf_assert(vdev);
  2999. }
  3000. pdev->monitor_vdev = vdev;
  3001. /* If smart monitor mode, do not configure monitor ring */
  3002. if (smart_monitor)
  3003. return QDF_STATUS_SUCCESS;
  3004. htt_tlv_filter.mpdu_start = 1;
  3005. htt_tlv_filter.msdu_start = 1;
  3006. htt_tlv_filter.packet = 1;
  3007. htt_tlv_filter.msdu_end = 1;
  3008. htt_tlv_filter.mpdu_end = 1;
  3009. htt_tlv_filter.packet_header = 1;
  3010. htt_tlv_filter.attention = 1;
  3011. htt_tlv_filter.ppdu_start = 0;
  3012. htt_tlv_filter.ppdu_end = 0;
  3013. htt_tlv_filter.ppdu_end_user_stats = 0;
  3014. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3015. htt_tlv_filter.ppdu_end_status_done = 0;
  3016. htt_tlv_filter.header_per_msdu = 1;
  3017. htt_tlv_filter.enable_fp = 1;
  3018. htt_tlv_filter.enable_md = 0;
  3019. htt_tlv_filter.enable_mo = 1;
  3020. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3021. pdev->rxdma_mon_buf_ring.hal_srng,
  3022. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3023. htt_tlv_filter.mpdu_start = 1;
  3024. htt_tlv_filter.msdu_start = 1;
  3025. htt_tlv_filter.packet = 0;
  3026. htt_tlv_filter.msdu_end = 1;
  3027. htt_tlv_filter.mpdu_end = 1;
  3028. htt_tlv_filter.packet_header = 1;
  3029. htt_tlv_filter.attention = 1;
  3030. htt_tlv_filter.ppdu_start = 1;
  3031. htt_tlv_filter.ppdu_end = 1;
  3032. htt_tlv_filter.ppdu_end_user_stats = 1;
  3033. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3034. htt_tlv_filter.ppdu_end_status_done = 1;
  3035. htt_tlv_filter.header_per_msdu = 0;
  3036. htt_tlv_filter.enable_fp = 1;
  3037. htt_tlv_filter.enable_md = 0;
  3038. htt_tlv_filter.enable_mo = 1;
  3039. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3040. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3041. RX_BUFFER_SIZE, &htt_tlv_filter);
  3042. return QDF_STATUS_SUCCESS;
  3043. }
  3044. #ifdef MESH_MODE_SUPPORT
  3045. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3046. {
  3047. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3048. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3049. FL("val %d"), val);
  3050. vdev->mesh_vdev = val;
  3051. }
  3052. /*
  3053. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3054. * @vdev_hdl: virtual device object
  3055. * @val: value to be set
  3056. *
  3057. * Return: void
  3058. */
  3059. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3060. {
  3061. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3062. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3063. FL("val %d"), val);
  3064. vdev->mesh_rx_filter = val;
  3065. }
  3066. #endif
  3067. /*
  3068. * dp_aggregate_pdev_ctrl_frames_stats()- function to agreegate peer stats
  3069. * Current scope is bar recieved count
  3070. *
  3071. * @pdev_handle: DP_PDEV handle
  3072. *
  3073. * Return: void
  3074. */
  3075. #define STATS_PROC_TIMEOUT (HZ/10)
  3076. static void
  3077. dp_aggregate_pdev_ctrl_frames_stats(struct dp_pdev *pdev)
  3078. {
  3079. struct dp_vdev *vdev;
  3080. struct dp_peer *peer;
  3081. uint32_t waitcnt;
  3082. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3083. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3084. if (!peer) {
  3085. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3086. FL("DP Invalid Peer refernce"));
  3087. return;
  3088. }
  3089. waitcnt = 0;
  3090. dp_peer_rxtid_stats(peer, dp_rx_bar_stats_cb, pdev);
  3091. while (!(qdf_atomic_read(&(pdev->stats.cmd_complete)))
  3092. && waitcnt < 10) {
  3093. schedule_timeout_interruptible(
  3094. STATS_PROC_TIMEOUT);
  3095. waitcnt++;
  3096. }
  3097. qdf_atomic_set(&(pdev->stats.cmd_complete), 0);
  3098. }
  3099. }
  3100. }
  3101. /**
  3102. * dp_rx_bar_stats_cb(): BAR received stats callback
  3103. * @soc: SOC handle
  3104. * @cb_ctxt: Call back context
  3105. * @reo_status: Reo status
  3106. *
  3107. * return: void
  3108. */
  3109. void dp_rx_bar_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3110. union hal_reo_status *reo_status)
  3111. {
  3112. struct dp_pdev *pdev = (struct dp_pdev *)cb_ctxt;
  3113. struct hal_reo_queue_status *queue_status = &(reo_status->queue_status);
  3114. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3115. DP_TRACE_STATS(FATAL, "REO stats failure %d \n",
  3116. queue_status->header.status);
  3117. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3118. return;
  3119. }
  3120. pdev->stats.rx.bar_recv_cnt += queue_status->bar_rcvd_cnt;
  3121. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3122. }
  3123. /**
  3124. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3125. * @vdev: DP VDEV handle
  3126. *
  3127. * return: void
  3128. */
  3129. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3130. {
  3131. struct dp_peer *peer = NULL;
  3132. struct dp_soc *soc = vdev->pdev->soc;
  3133. int i;
  3134. uint8_t pream_type;
  3135. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3136. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3137. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3138. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3139. for (i = 0; i < MAX_MCS; i++) {
  3140. DP_STATS_AGGR(vdev, peer,
  3141. tx.pkt_type[pream_type].mcs_count[i]);
  3142. DP_STATS_AGGR(vdev, peer,
  3143. rx.pkt_type[pream_type].mcs_count[i]);
  3144. }
  3145. }
  3146. for (i = 0; i < MAX_BW; i++) {
  3147. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3148. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3149. }
  3150. for (i = 0; i < SS_COUNT; i++)
  3151. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3152. for (i = 0; i < WME_AC_MAX; i++) {
  3153. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3154. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3155. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3156. }
  3157. for (i = 0; i < MAX_GI; i++) {
  3158. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3159. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3160. }
  3161. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3162. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3163. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3164. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3165. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3166. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3167. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3168. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3169. DP_STATS_AGGR(vdev, peer, tx.retries);
  3170. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3171. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3172. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3173. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3174. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3175. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3176. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3177. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3178. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3179. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3180. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3181. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3182. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3183. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3184. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3185. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3186. peer->stats.rx.multicast.num;
  3187. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3188. peer->stats.rx.multicast.bytes;
  3189. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3190. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3191. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3192. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3193. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3194. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3195. vdev->stats.tx.last_ack_rssi =
  3196. peer->stats.tx.last_ack_rssi;
  3197. }
  3198. if (soc->cdp_soc.ol_ops->update_dp_stats)
  3199. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3200. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3201. }
  3202. /**
  3203. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3204. * @pdev: DP PDEV handle
  3205. *
  3206. * return: void
  3207. */
  3208. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3209. {
  3210. struct dp_vdev *vdev = NULL;
  3211. uint8_t i;
  3212. uint8_t pream_type;
  3213. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3214. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3215. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3216. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3217. dp_aggregate_vdev_stats(vdev);
  3218. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3219. for (i = 0; i < MAX_MCS; i++) {
  3220. DP_STATS_AGGR(pdev, vdev,
  3221. tx.pkt_type[pream_type].mcs_count[i]);
  3222. DP_STATS_AGGR(pdev, vdev,
  3223. rx.pkt_type[pream_type].mcs_count[i]);
  3224. }
  3225. }
  3226. for (i = 0; i < MAX_BW; i++) {
  3227. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3228. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3229. }
  3230. for (i = 0; i < SS_COUNT; i++)
  3231. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3232. for (i = 0; i < WME_AC_MAX; i++) {
  3233. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3234. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3235. DP_STATS_AGGR(pdev, vdev,
  3236. tx.excess_retries_ac[i]);
  3237. }
  3238. for (i = 0; i < MAX_GI; i++) {
  3239. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3240. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3241. }
  3242. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3243. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3244. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3245. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3246. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3247. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3248. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3249. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3250. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3251. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3252. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3253. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3254. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3255. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3256. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3257. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3258. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3259. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3260. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3261. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3262. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3263. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3264. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3265. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3266. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3267. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3268. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3269. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3270. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3271. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3272. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3273. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3274. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.nawds_mcast);
  3275. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3276. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3277. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3278. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3279. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3280. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3281. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3282. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3283. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3284. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3285. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3286. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3287. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3288. DP_STATS_AGGR(pdev, vdev,
  3289. tx_i.mcast_en.dropped_map_error);
  3290. DP_STATS_AGGR(pdev, vdev,
  3291. tx_i.mcast_en.dropped_self_mac);
  3292. DP_STATS_AGGR(pdev, vdev,
  3293. tx_i.mcast_en.dropped_send_fail);
  3294. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3295. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3296. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3297. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3298. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3299. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3300. DP_STATS_AGGR(pdev, vdev, tx_i.cce_classified);
  3301. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3302. pdev->stats.tx_i.dropped.dma_error +
  3303. pdev->stats.tx_i.dropped.ring_full +
  3304. pdev->stats.tx_i.dropped.enqueue_fail +
  3305. pdev->stats.tx_i.dropped.desc_na +
  3306. pdev->stats.tx_i.dropped.res_full;
  3307. pdev->stats.tx.last_ack_rssi =
  3308. vdev->stats.tx.last_ack_rssi;
  3309. pdev->stats.tx_i.tso.num_seg =
  3310. vdev->stats.tx_i.tso.num_seg;
  3311. }
  3312. }
  3313. /**
  3314. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3315. * @pdev: DP_PDEV Handle
  3316. *
  3317. * Return:void
  3318. */
  3319. static inline void
  3320. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3321. {
  3322. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3323. DP_PRINT_STATS("Received From Stack:");
  3324. DP_PRINT_STATS(" Packets = %d",
  3325. pdev->stats.tx_i.rcvd.num);
  3326. DP_PRINT_STATS(" Bytes = %d",
  3327. pdev->stats.tx_i.rcvd.bytes);
  3328. DP_PRINT_STATS("Processed:");
  3329. DP_PRINT_STATS(" Packets = %d",
  3330. pdev->stats.tx_i.processed.num);
  3331. DP_PRINT_STATS(" Bytes = %d",
  3332. pdev->stats.tx_i.processed.bytes);
  3333. DP_PRINT_STATS("Completions:");
  3334. DP_PRINT_STATS(" Packets = %d",
  3335. pdev->stats.tx.comp_pkt.num);
  3336. DP_PRINT_STATS(" Bytes = %d",
  3337. pdev->stats.tx.comp_pkt.bytes);
  3338. DP_PRINT_STATS("Dropped:");
  3339. DP_PRINT_STATS(" Total = %d",
  3340. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3341. DP_PRINT_STATS(" Dma_map_error = %d",
  3342. pdev->stats.tx_i.dropped.dma_error);
  3343. DP_PRINT_STATS(" Ring Full = %d",
  3344. pdev->stats.tx_i.dropped.ring_full);
  3345. DP_PRINT_STATS(" Descriptor Not available = %d",
  3346. pdev->stats.tx_i.dropped.desc_na);
  3347. DP_PRINT_STATS(" HW enqueue failed= %d",
  3348. pdev->stats.tx_i.dropped.enqueue_fail);
  3349. DP_PRINT_STATS(" Resources Full = %d",
  3350. pdev->stats.tx_i.dropped.res_full);
  3351. DP_PRINT_STATS(" FW removed = %d",
  3352. pdev->stats.tx.dropped.fw_rem);
  3353. DP_PRINT_STATS(" FW removed transmitted = %d",
  3354. pdev->stats.tx.dropped.fw_rem_tx);
  3355. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3356. pdev->stats.tx.dropped.fw_rem_notx);
  3357. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3358. pdev->stats.tx.dropped.age_out);
  3359. DP_PRINT_STATS("Scatter Gather:");
  3360. DP_PRINT_STATS(" Packets = %d",
  3361. pdev->stats.tx_i.sg.sg_pkt.num);
  3362. DP_PRINT_STATS(" Bytes = %d",
  3363. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3364. DP_PRINT_STATS(" Dropped By Host = %d",
  3365. pdev->stats.tx_i.sg.dropped_host);
  3366. DP_PRINT_STATS(" Dropped By Target = %d",
  3367. pdev->stats.tx_i.sg.dropped_target);
  3368. DP_PRINT_STATS("TSO:");
  3369. DP_PRINT_STATS(" Number of Segments = %d",
  3370. pdev->stats.tx_i.tso.num_seg);
  3371. DP_PRINT_STATS(" Packets = %d",
  3372. pdev->stats.tx_i.tso.tso_pkt.num);
  3373. DP_PRINT_STATS(" Bytes = %d",
  3374. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3375. DP_PRINT_STATS(" Dropped By Host = %d",
  3376. pdev->stats.tx_i.tso.dropped_host);
  3377. DP_PRINT_STATS("Mcast Enhancement:");
  3378. DP_PRINT_STATS(" Packets = %d",
  3379. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3380. DP_PRINT_STATS(" Bytes = %d",
  3381. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3382. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3383. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3384. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3385. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3386. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3387. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3388. DP_PRINT_STATS(" Unicast sent = %d",
  3389. pdev->stats.tx_i.mcast_en.ucast);
  3390. DP_PRINT_STATS("Raw:");
  3391. DP_PRINT_STATS(" Packets = %d",
  3392. pdev->stats.tx_i.raw.raw_pkt.num);
  3393. DP_PRINT_STATS(" Bytes = %d",
  3394. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3395. DP_PRINT_STATS(" DMA map error = %d",
  3396. pdev->stats.tx_i.raw.dma_map_error);
  3397. DP_PRINT_STATS("Reinjected:");
  3398. DP_PRINT_STATS(" Packets = %d",
  3399. pdev->stats.tx_i.reinject_pkts.num);
  3400. DP_PRINT_STATS("Bytes = %d\n",
  3401. pdev->stats.tx_i.reinject_pkts.bytes);
  3402. DP_PRINT_STATS("Inspected:");
  3403. DP_PRINT_STATS(" Packets = %d",
  3404. pdev->stats.tx_i.inspect_pkts.num);
  3405. DP_PRINT_STATS(" Bytes = %d",
  3406. pdev->stats.tx_i.inspect_pkts.bytes);
  3407. DP_PRINT_STATS("Nawds Multicast:");
  3408. DP_PRINT_STATS(" Packets = %d",
  3409. pdev->stats.tx_i.nawds_mcast.num);
  3410. DP_PRINT_STATS(" Bytes = %d",
  3411. pdev->stats.tx_i.nawds_mcast.bytes);
  3412. DP_PRINT_STATS("CCE Classified:");
  3413. DP_TRACE(FATAL, " CCE Classified Packets: %u",
  3414. pdev->stats.tx_i.cce_classified);
  3415. }
  3416. /**
  3417. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3418. * @pdev: DP_PDEV Handle
  3419. *
  3420. * Return: void
  3421. */
  3422. static inline void
  3423. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3424. {
  3425. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3426. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3427. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3428. pdev->stats.rx.rcvd_reo[0].num,
  3429. pdev->stats.rx.rcvd_reo[1].num,
  3430. pdev->stats.rx.rcvd_reo[2].num,
  3431. pdev->stats.rx.rcvd_reo[3].num);
  3432. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3433. pdev->stats.rx.rcvd_reo[0].bytes,
  3434. pdev->stats.rx.rcvd_reo[1].bytes,
  3435. pdev->stats.rx.rcvd_reo[2].bytes,
  3436. pdev->stats.rx.rcvd_reo[3].bytes);
  3437. DP_PRINT_STATS("Replenished:");
  3438. DP_PRINT_STATS(" Packets = %d",
  3439. pdev->stats.replenish.pkts.num);
  3440. DP_PRINT_STATS(" Bytes = %d",
  3441. pdev->stats.replenish.pkts.bytes);
  3442. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3443. pdev->stats.buf_freelist);
  3444. DP_PRINT_STATS(" Low threshold intr = %d",
  3445. pdev->stats.replenish.low_thresh_intrs);
  3446. DP_PRINT_STATS("Dropped:");
  3447. DP_PRINT_STATS(" msdu_not_done = %d",
  3448. pdev->stats.dropped.msdu_not_done);
  3449. DP_PRINT_STATS("Sent To Stack:");
  3450. DP_PRINT_STATS(" Packets = %d",
  3451. pdev->stats.rx.to_stack.num);
  3452. DP_PRINT_STATS(" Bytes = %d",
  3453. pdev->stats.rx.to_stack.bytes);
  3454. DP_PRINT_STATS("Multicast/Broadcast:");
  3455. DP_PRINT_STATS(" Packets = %d",
  3456. pdev->stats.rx.multicast.num);
  3457. DP_PRINT_STATS(" Bytes = %d",
  3458. pdev->stats.rx.multicast.bytes);
  3459. DP_PRINT_STATS("Errors:");
  3460. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3461. pdev->stats.replenish.rxdma_err);
  3462. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3463. pdev->stats.err.desc_alloc_fail);
  3464. /* Get bar_recv_cnt */
  3465. dp_aggregate_pdev_ctrl_frames_stats(pdev);
  3466. DP_PRINT_STATS("BAR Received Count: = %d",
  3467. pdev->stats.rx.bar_recv_cnt);
  3468. }
  3469. /**
  3470. * dp_print_soc_tx_stats(): Print SOC level stats
  3471. * @soc DP_SOC Handle
  3472. *
  3473. * Return: void
  3474. */
  3475. static inline void
  3476. dp_print_soc_tx_stats(struct dp_soc *soc)
  3477. {
  3478. DP_PRINT_STATS("SOC Tx Stats:\n");
  3479. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3480. soc->stats.tx.desc_in_use);
  3481. DP_PRINT_STATS("Invalid peer:");
  3482. DP_PRINT_STATS(" Packets = %d",
  3483. soc->stats.tx.tx_invalid_peer.num);
  3484. DP_PRINT_STATS(" Bytes = %d",
  3485. soc->stats.tx.tx_invalid_peer.bytes);
  3486. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3487. soc->stats.tx.tcl_ring_full[0],
  3488. soc->stats.tx.tcl_ring_full[1],
  3489. soc->stats.tx.tcl_ring_full[2]);
  3490. }
  3491. /**
  3492. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3493. * @soc: DP_SOC Handle
  3494. *
  3495. * Return:void
  3496. */
  3497. static inline void
  3498. dp_print_soc_rx_stats(struct dp_soc *soc)
  3499. {
  3500. uint32_t i;
  3501. char reo_error[DP_REO_ERR_LENGTH];
  3502. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3503. uint8_t index = 0;
  3504. DP_PRINT_STATS("SOC Rx Stats:\n");
  3505. DP_PRINT_STATS("Errors:\n");
  3506. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3507. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3508. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3509. DP_PRINT_STATS("Invalid RBM = %d",
  3510. soc->stats.rx.err.invalid_rbm);
  3511. DP_PRINT_STATS("Invalid Vdev = %d",
  3512. soc->stats.rx.err.invalid_vdev);
  3513. DP_PRINT_STATS("Invalid Pdev = %d",
  3514. soc->stats.rx.err.invalid_pdev);
  3515. DP_PRINT_STATS("Invalid Peer = %d",
  3516. soc->stats.rx.err.rx_invalid_peer.num);
  3517. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3518. soc->stats.rx.err.hal_ring_access_fail);
  3519. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3520. index += qdf_snprint(&rxdma_error[index],
  3521. DP_RXDMA_ERR_LENGTH - index,
  3522. " %d", soc->stats.rx.err.rxdma_error[i]);
  3523. }
  3524. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3525. rxdma_error);
  3526. index = 0;
  3527. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3528. index += qdf_snprint(&reo_error[index],
  3529. DP_REO_ERR_LENGTH - index,
  3530. " %d", soc->stats.rx.err.reo_error[i]);
  3531. }
  3532. DP_PRINT_STATS("REO Error(0-14):%s",
  3533. reo_error);
  3534. }
  3535. /**
  3536. * dp_print_ring_stat_from_hal(): Print hal level ring stats
  3537. * @soc: DP_SOC handle
  3538. * @srng: DP_SRNG handle
  3539. * @ring_name: SRNG name
  3540. *
  3541. * Return: void
  3542. */
  3543. static inline void
  3544. dp_print_ring_stat_from_hal(struct dp_soc *soc, struct dp_srng *srng,
  3545. char *ring_name)
  3546. {
  3547. uint32_t tailp;
  3548. uint32_t headp;
  3549. if (srng->hal_srng != NULL) {
  3550. hal_api_get_tphp(soc->hal_soc, srng->hal_srng, &tailp, &headp);
  3551. DP_PRINT_STATS("%s : Head pointer = %d Tail Pointer = %d\n",
  3552. ring_name, headp, tailp);
  3553. }
  3554. }
  3555. /**
  3556. * dp_print_ring_stats(): Print tail and head pointer
  3557. * @pdev: DP_PDEV handle
  3558. *
  3559. * Return:void
  3560. */
  3561. static inline void
  3562. dp_print_ring_stats(struct dp_pdev *pdev)
  3563. {
  3564. uint32_t i;
  3565. char ring_name[STR_MAXLEN + 1];
  3566. dp_print_ring_stat_from_hal(pdev->soc,
  3567. &pdev->soc->reo_exception_ring,
  3568. "Reo Exception Ring");
  3569. dp_print_ring_stat_from_hal(pdev->soc,
  3570. &pdev->soc->reo_reinject_ring,
  3571. "Reo Inject Ring");
  3572. dp_print_ring_stat_from_hal(pdev->soc,
  3573. &pdev->soc->reo_cmd_ring,
  3574. "Reo Command Ring");
  3575. dp_print_ring_stat_from_hal(pdev->soc,
  3576. &pdev->soc->reo_status_ring,
  3577. "Reo Status Ring");
  3578. dp_print_ring_stat_from_hal(pdev->soc,
  3579. &pdev->soc->rx_rel_ring,
  3580. "Rx Release ring");
  3581. dp_print_ring_stat_from_hal(pdev->soc,
  3582. &pdev->soc->tcl_cmd_ring,
  3583. "Tcl command Ring");
  3584. dp_print_ring_stat_from_hal(pdev->soc,
  3585. &pdev->soc->tcl_status_ring,
  3586. "Tcl Status Ring");
  3587. dp_print_ring_stat_from_hal(pdev->soc,
  3588. &pdev->soc->wbm_desc_rel_ring,
  3589. "Wbm Desc Rel Ring");
  3590. for (i = 0; i < MAX_REO_DEST_RINGS; i++) {
  3591. snprintf(ring_name, STR_MAXLEN, "Reo Dest Ring %d", i);
  3592. dp_print_ring_stat_from_hal(pdev->soc,
  3593. &pdev->soc->reo_dest_ring[i],
  3594. ring_name);
  3595. }
  3596. for (i = 0; i < pdev->soc->num_tcl_data_rings; i++) {
  3597. snprintf(ring_name, STR_MAXLEN, "Tcl Data Ring %d", i);
  3598. dp_print_ring_stat_from_hal(pdev->soc,
  3599. &pdev->soc->tcl_data_ring[i],
  3600. ring_name);
  3601. }
  3602. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3603. snprintf(ring_name, STR_MAXLEN, "Tx Comp Ring %d", i);
  3604. dp_print_ring_stat_from_hal(pdev->soc,
  3605. &pdev->soc->tx_comp_ring[i],
  3606. ring_name);
  3607. }
  3608. dp_print_ring_stat_from_hal(pdev->soc,
  3609. &pdev->rx_refill_buf_ring,
  3610. "Rx Refill Buf Ring");
  3611. dp_print_ring_stat_from_hal(pdev->soc,
  3612. &pdev->rx_refill_buf_ring2,
  3613. "Second Rx Refill Buf Ring");
  3614. dp_print_ring_stat_from_hal(pdev->soc,
  3615. &pdev->rxdma_mon_buf_ring,
  3616. "Rxdma Mon Buf Ring");
  3617. dp_print_ring_stat_from_hal(pdev->soc,
  3618. &pdev->rxdma_mon_dst_ring,
  3619. "Rxdma Mon Dst Ring");
  3620. dp_print_ring_stat_from_hal(pdev->soc,
  3621. &pdev->rxdma_mon_status_ring,
  3622. "Rxdma Mon Status Ring");
  3623. dp_print_ring_stat_from_hal(pdev->soc,
  3624. &pdev->rxdma_mon_desc_ring,
  3625. "Rxdma mon desc Ring");
  3626. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3627. snprintf(ring_name, STR_MAXLEN, "Rxdma err dst ring %d", i);
  3628. dp_print_ring_stat_from_hal(pdev->soc,
  3629. &pdev->rxdma_err_dst_ring[i],
  3630. ring_name);
  3631. }
  3632. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3633. snprintf(ring_name, STR_MAXLEN, "Rx mac buf ring %d", i);
  3634. dp_print_ring_stat_from_hal(pdev->soc,
  3635. &pdev->rx_mac_buf_ring[i],
  3636. ring_name);
  3637. }
  3638. }
  3639. /**
  3640. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3641. * @vdev: DP_VDEV handle
  3642. *
  3643. * Return:void
  3644. */
  3645. static inline void
  3646. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3647. {
  3648. struct dp_peer *peer = NULL;
  3649. DP_STATS_CLR(vdev->pdev);
  3650. DP_STATS_CLR(vdev->pdev->soc);
  3651. DP_STATS_CLR(vdev);
  3652. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3653. if (!peer)
  3654. return;
  3655. DP_STATS_CLR(peer);
  3656. }
  3657. }
  3658. /**
  3659. * dp_print_rx_rates(): Print Rx rate stats
  3660. * @vdev: DP_VDEV handle
  3661. *
  3662. * Return:void
  3663. */
  3664. static inline void
  3665. dp_print_rx_rates(struct dp_vdev *vdev)
  3666. {
  3667. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3668. uint8_t i, mcs, pkt_type;
  3669. uint8_t index = 0;
  3670. char nss[DP_NSS_LENGTH];
  3671. DP_PRINT_STATS("Rx Rate Info:\n");
  3672. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3673. index = 0;
  3674. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3675. if (!dp_rate_string[pkt_type][mcs].valid)
  3676. continue;
  3677. DP_PRINT_STATS(" %s = %d",
  3678. dp_rate_string[pkt_type][mcs].mcs_type,
  3679. pdev->stats.rx.pkt_type[pkt_type].
  3680. mcs_count[mcs]);
  3681. }
  3682. DP_PRINT_STATS("\n");
  3683. }
  3684. index = 0;
  3685. for (i = 0; i < SS_COUNT; i++) {
  3686. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3687. " %d", pdev->stats.rx.nss[i]);
  3688. }
  3689. DP_PRINT_STATS("NSS(0-7) = %s",
  3690. nss);
  3691. DP_PRINT_STATS("SGI ="
  3692. " 0.8us %d,"
  3693. " 0.4us %d,"
  3694. " 1.6us %d,"
  3695. " 3.2us %d,",
  3696. pdev->stats.rx.sgi_count[0],
  3697. pdev->stats.rx.sgi_count[1],
  3698. pdev->stats.rx.sgi_count[2],
  3699. pdev->stats.rx.sgi_count[3]);
  3700. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3701. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3702. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3703. DP_PRINT_STATS("Reception Type ="
  3704. " SU: %d,"
  3705. " MU_MIMO:%d,"
  3706. " MU_OFDMA:%d,"
  3707. " MU_OFDMA_MIMO:%d\n",
  3708. pdev->stats.rx.reception_type[0],
  3709. pdev->stats.rx.reception_type[1],
  3710. pdev->stats.rx.reception_type[2],
  3711. pdev->stats.rx.reception_type[3]);
  3712. DP_PRINT_STATS("Aggregation:\n");
  3713. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3714. pdev->stats.rx.ampdu_cnt);
  3715. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3716. pdev->stats.rx.non_ampdu_cnt);
  3717. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3718. pdev->stats.rx.amsdu_cnt);
  3719. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3720. pdev->stats.rx.non_amsdu_cnt);
  3721. }
  3722. /**
  3723. * dp_print_tx_rates(): Print tx rates
  3724. * @vdev: DP_VDEV handle
  3725. *
  3726. * Return:void
  3727. */
  3728. static inline void
  3729. dp_print_tx_rates(struct dp_vdev *vdev)
  3730. {
  3731. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3732. uint8_t mcs, pkt_type;
  3733. uint32_t index;
  3734. DP_PRINT_STATS("Tx Rate Info:\n");
  3735. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3736. index = 0;
  3737. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3738. if (!dp_rate_string[pkt_type][mcs].valid)
  3739. continue;
  3740. DP_PRINT_STATS(" %s = %d",
  3741. dp_rate_string[pkt_type][mcs].mcs_type,
  3742. pdev->stats.tx.pkt_type[pkt_type].
  3743. mcs_count[mcs]);
  3744. }
  3745. DP_PRINT_STATS("\n");
  3746. }
  3747. DP_PRINT_STATS("SGI ="
  3748. " 0.8us %d"
  3749. " 0.4us %d"
  3750. " 1.6us %d"
  3751. " 3.2us %d",
  3752. pdev->stats.tx.sgi_count[0],
  3753. pdev->stats.tx.sgi_count[1],
  3754. pdev->stats.tx.sgi_count[2],
  3755. pdev->stats.tx.sgi_count[3]);
  3756. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3757. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3758. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3759. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3760. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3761. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3762. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3763. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3764. DP_PRINT_STATS("Aggregation:\n");
  3765. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3766. pdev->stats.tx.amsdu_cnt);
  3767. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3768. pdev->stats.tx.non_amsdu_cnt);
  3769. }
  3770. /**
  3771. * dp_print_peer_stats():print peer stats
  3772. * @peer: DP_PEER handle
  3773. *
  3774. * return void
  3775. */
  3776. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3777. {
  3778. uint8_t i, mcs, pkt_type;
  3779. uint32_t index;
  3780. char nss[DP_NSS_LENGTH];
  3781. DP_PRINT_STATS("Node Tx Stats:\n");
  3782. DP_PRINT_STATS("Total Packet Completions = %d",
  3783. peer->stats.tx.comp_pkt.num);
  3784. DP_PRINT_STATS("Total Bytes Completions = %d",
  3785. peer->stats.tx.comp_pkt.bytes);
  3786. DP_PRINT_STATS("Success Packets = %d",
  3787. peer->stats.tx.tx_success.num);
  3788. DP_PRINT_STATS("Success Bytes = %d",
  3789. peer->stats.tx.tx_success.bytes);
  3790. DP_PRINT_STATS("Packets Failed = %d",
  3791. peer->stats.tx.tx_failed);
  3792. DP_PRINT_STATS("Packets In OFDMA = %d",
  3793. peer->stats.tx.ofdma);
  3794. DP_PRINT_STATS("Packets In STBC = %d",
  3795. peer->stats.tx.stbc);
  3796. DP_PRINT_STATS("Packets In LDPC = %d",
  3797. peer->stats.tx.ldpc);
  3798. DP_PRINT_STATS("Packet Retries = %d",
  3799. peer->stats.tx.retries);
  3800. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3801. peer->stats.tx.amsdu_cnt);
  3802. DP_PRINT_STATS("Last Packet RSSI = %d",
  3803. peer->stats.tx.last_ack_rssi);
  3804. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3805. peer->stats.tx.dropped.fw_rem);
  3806. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3807. peer->stats.tx.dropped.fw_rem_tx);
  3808. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3809. peer->stats.tx.dropped.fw_rem_notx);
  3810. DP_PRINT_STATS("Dropped : Age Out = %d",
  3811. peer->stats.tx.dropped.age_out);
  3812. DP_PRINT_STATS("NAWDS : ");
  3813. DP_PRINT_STATS(" Nawds multicast Drop Tx Packet = %d",
  3814. peer->stats.tx.nawds_mcast_drop);
  3815. DP_PRINT_STATS(" Nawds multicast Tx Packet Count = %d",
  3816. peer->stats.tx.nawds_mcast.num);
  3817. DP_PRINT_STATS(" Nawds multicast Tx Packet Bytes = %d",
  3818. peer->stats.tx.nawds_mcast.bytes);
  3819. DP_PRINT_STATS("Rate Info:");
  3820. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3821. index = 0;
  3822. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3823. if (!dp_rate_string[pkt_type][mcs].valid)
  3824. continue;
  3825. DP_PRINT_STATS(" %s = %d",
  3826. dp_rate_string[pkt_type][mcs].mcs_type,
  3827. peer->stats.tx.pkt_type[pkt_type].
  3828. mcs_count[mcs]);
  3829. }
  3830. DP_PRINT_STATS("\n");
  3831. }
  3832. DP_PRINT_STATS("SGI = "
  3833. " 0.8us %d"
  3834. " 0.4us %d"
  3835. " 1.6us %d"
  3836. " 3.2us %d",
  3837. peer->stats.tx.sgi_count[0],
  3838. peer->stats.tx.sgi_count[1],
  3839. peer->stats.tx.sgi_count[2],
  3840. peer->stats.tx.sgi_count[3]);
  3841. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3842. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3843. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3844. DP_PRINT_STATS("Aggregation:");
  3845. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3846. peer->stats.tx.amsdu_cnt);
  3847. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3848. peer->stats.tx.non_amsdu_cnt);
  3849. DP_PRINT_STATS("Node Rx Stats:");
  3850. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3851. peer->stats.rx.to_stack.num);
  3852. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3853. peer->stats.rx.to_stack.bytes);
  3854. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3855. DP_PRINT_STATS("Packets Received = %d",
  3856. peer->stats.rx.rcvd_reo[i].num);
  3857. DP_PRINT_STATS("Bytes Received = %d",
  3858. peer->stats.rx.rcvd_reo[i].bytes);
  3859. }
  3860. DP_PRINT_STATS("Multicast Packets Received = %d",
  3861. peer->stats.rx.multicast.num);
  3862. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3863. peer->stats.rx.multicast.bytes);
  3864. DP_PRINT_STATS("WDS Packets Received = %d",
  3865. peer->stats.rx.wds.num);
  3866. DP_PRINT_STATS("WDS Bytes Received = %d",
  3867. peer->stats.rx.wds.bytes);
  3868. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3869. peer->stats.rx.intra_bss.pkts.num);
  3870. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3871. peer->stats.rx.intra_bss.pkts.bytes);
  3872. DP_PRINT_STATS("Raw Packets Received = %d",
  3873. peer->stats.rx.raw.num);
  3874. DP_PRINT_STATS("Raw Bytes Received = %d",
  3875. peer->stats.rx.raw.bytes);
  3876. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3877. peer->stats.rx.err.mic_err);
  3878. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3879. peer->stats.rx.err.decrypt_err);
  3880. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3881. peer->stats.rx.non_ampdu_cnt);
  3882. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3883. peer->stats.rx.ampdu_cnt);
  3884. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3885. peer->stats.rx.non_amsdu_cnt);
  3886. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3887. peer->stats.rx.amsdu_cnt);
  3888. DP_PRINT_STATS("NAWDS : ");
  3889. DP_PRINT_STATS(" Nawds multicast Drop Rx Packet = %d",
  3890. peer->stats.rx.nawds_mcast_drop.num);
  3891. DP_PRINT_STATS(" Nawds multicast Drop Rx Packet Bytes = %d",
  3892. peer->stats.rx.nawds_mcast_drop.bytes);
  3893. DP_PRINT_STATS("SGI ="
  3894. " 0.8us %d"
  3895. " 0.4us %d"
  3896. " 1.6us %d"
  3897. " 3.2us %d",
  3898. peer->stats.rx.sgi_count[0],
  3899. peer->stats.rx.sgi_count[1],
  3900. peer->stats.rx.sgi_count[2],
  3901. peer->stats.rx.sgi_count[3]);
  3902. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3903. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3904. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3905. DP_PRINT_STATS("Reception Type ="
  3906. " SU %d,"
  3907. " MU_MIMO %d,"
  3908. " MU_OFDMA %d,"
  3909. " MU_OFDMA_MIMO %d",
  3910. peer->stats.rx.reception_type[0],
  3911. peer->stats.rx.reception_type[1],
  3912. peer->stats.rx.reception_type[2],
  3913. peer->stats.rx.reception_type[3]);
  3914. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3915. index = 0;
  3916. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3917. if (!dp_rate_string[pkt_type][mcs].valid)
  3918. continue;
  3919. DP_PRINT_STATS(" %s = %d",
  3920. dp_rate_string[pkt_type][mcs].mcs_type,
  3921. peer->stats.rx.pkt_type[pkt_type].
  3922. mcs_count[mcs]);
  3923. }
  3924. DP_PRINT_STATS("\n");
  3925. }
  3926. index = 0;
  3927. for (i = 0; i < SS_COUNT; i++) {
  3928. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3929. " %d", peer->stats.rx.nss[i]);
  3930. }
  3931. DP_PRINT_STATS("NSS(0-7) = %s",
  3932. nss);
  3933. DP_PRINT_STATS("Aggregation:");
  3934. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  3935. peer->stats.rx.ampdu_cnt);
  3936. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  3937. peer->stats.rx.non_ampdu_cnt);
  3938. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  3939. peer->stats.rx.amsdu_cnt);
  3940. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  3941. peer->stats.rx.non_amsdu_cnt);
  3942. }
  3943. /**
  3944. * dp_print_host_stats()- Function to print the stats aggregated at host
  3945. * @vdev_handle: DP_VDEV handle
  3946. * @type: host stats type
  3947. *
  3948. * Available Stat types
  3949. * TXRX_CLEAR_STATS : Clear the stats
  3950. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3951. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3952. * TXRX_TX_HOST_STATS: Print Tx Stats
  3953. * TXRX_RX_HOST_STATS: Print Rx Stats
  3954. * TXRX_AST_STATS: Print AST Stats
  3955. * TXRX_SRNG_PTR_STATS: Print SRNG ring pointer stats
  3956. *
  3957. * Return: 0 on success, print error message in case of failure
  3958. */
  3959. static int
  3960. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3961. {
  3962. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3963. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3964. dp_aggregate_pdev_stats(pdev);
  3965. switch (type) {
  3966. case TXRX_CLEAR_STATS:
  3967. dp_txrx_host_stats_clr(vdev);
  3968. break;
  3969. case TXRX_RX_RATE_STATS:
  3970. dp_print_rx_rates(vdev);
  3971. break;
  3972. case TXRX_TX_RATE_STATS:
  3973. dp_print_tx_rates(vdev);
  3974. break;
  3975. case TXRX_TX_HOST_STATS:
  3976. dp_print_pdev_tx_stats(pdev);
  3977. dp_print_soc_tx_stats(pdev->soc);
  3978. break;
  3979. case TXRX_RX_HOST_STATS:
  3980. dp_print_pdev_rx_stats(pdev);
  3981. dp_print_soc_rx_stats(pdev->soc);
  3982. break;
  3983. case TXRX_AST_STATS:
  3984. dp_print_ast_stats(pdev->soc);
  3985. break;
  3986. case TXRX_SRNG_PTR_STATS:
  3987. dp_print_ring_stats(pdev);
  3988. break;
  3989. default:
  3990. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3991. break;
  3992. }
  3993. return 0;
  3994. }
  3995. /*
  3996. * dp_get_host_peer_stats()- function to print peer stats
  3997. * @pdev_handle: DP_PDEV handle
  3998. * @mac_addr: mac address of the peer
  3999. *
  4000. * Return: void
  4001. */
  4002. static void
  4003. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  4004. {
  4005. struct dp_peer *peer;
  4006. uint8_t local_id;
  4007. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  4008. &local_id);
  4009. if (!peer) {
  4010. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  4011. "%s: Invalid peer\n", __func__);
  4012. return;
  4013. }
  4014. dp_print_peer_stats(peer);
  4015. dp_peer_rxtid_stats(peer, dp_rx_tid_stats_cb, NULL);
  4016. return;
  4017. }
  4018. /*
  4019. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  4020. * @pdev: DP_PDEV handle
  4021. *
  4022. * Return: void
  4023. */
  4024. static void
  4025. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  4026. {
  4027. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4028. htt_tlv_filter.mpdu_start = 0;
  4029. htt_tlv_filter.msdu_start = 0;
  4030. htt_tlv_filter.packet = 0;
  4031. htt_tlv_filter.msdu_end = 0;
  4032. htt_tlv_filter.mpdu_end = 0;
  4033. htt_tlv_filter.packet_header = 1;
  4034. htt_tlv_filter.attention = 1;
  4035. htt_tlv_filter.ppdu_start = 1;
  4036. htt_tlv_filter.ppdu_end = 1;
  4037. htt_tlv_filter.ppdu_end_user_stats = 1;
  4038. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4039. htt_tlv_filter.ppdu_end_status_done = 1;
  4040. htt_tlv_filter.enable_fp = 1;
  4041. htt_tlv_filter.enable_md = 0;
  4042. htt_tlv_filter.enable_mo = 0;
  4043. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  4044. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  4045. RX_BUFFER_SIZE, &htt_tlv_filter);
  4046. }
  4047. /*
  4048. * dp_config_debug_sniffer()- API to enable/disable debug sniffer
  4049. * @pdev_handle: DP_PDEV handle
  4050. * @val: user provided value
  4051. *
  4052. * Return: void
  4053. */
  4054. static void
  4055. dp_config_debug_sniffer(struct cdp_pdev *pdev_handle, int val)
  4056. {
  4057. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4058. switch (val) {
  4059. case 0:
  4060. pdev->tx_sniffer_enable = 0;
  4061. pdev->am_copy_mode = 0;
  4062. pdev->soc->process_tx_status = 0;
  4063. if (!pdev->enhanced_stats_en)
  4064. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4065. break;
  4066. case 1:
  4067. pdev->tx_sniffer_enable = 1;
  4068. pdev->am_copy_mode = 0;
  4069. pdev->soc->process_tx_status = 1;
  4070. dp_h2t_cfg_stats_msg_send(pdev, DP_PPDU_STATS_CFG_ALL);
  4071. break;
  4072. case 2:
  4073. pdev->am_copy_mode = 1;
  4074. pdev->tx_sniffer_enable = 0;
  4075. pdev->soc->process_tx_status = 1;
  4076. dp_ppdu_ring_cfg(pdev);
  4077. dp_h2t_cfg_stats_msg_send(pdev, DP_PPDU_STATS_CFG_ALL);
  4078. break;
  4079. default:
  4080. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4081. "Invalid value\n");
  4082. break;
  4083. }
  4084. }
  4085. /*
  4086. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  4087. * @pdev_handle: DP_PDEV handle
  4088. *
  4089. * Return: void
  4090. */
  4091. static void
  4092. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4093. {
  4094. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4095. pdev->enhanced_stats_en = 1;
  4096. dp_ppdu_ring_cfg(pdev);
  4097. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4098. }
  4099. /*
  4100. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  4101. * @pdev_handle: DP_PDEV handle
  4102. *
  4103. * Return: void
  4104. */
  4105. static void
  4106. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4107. {
  4108. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4109. pdev->enhanced_stats_en = 0;
  4110. if (!pdev->tx_sniffer_enable && !pdev->am_copy_mode)
  4111. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4112. }
  4113. /*
  4114. * dp_get_fw_peer_stats()- function to print peer stats
  4115. * @pdev_handle: DP_PDEV handle
  4116. * @mac_addr: mac address of the peer
  4117. * @cap: Type of htt stats requested
  4118. *
  4119. * Currently Supporting only MAC ID based requests Only
  4120. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  4121. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  4122. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  4123. *
  4124. * Return: void
  4125. */
  4126. static void
  4127. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  4128. uint32_t cap)
  4129. {
  4130. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4131. int i;
  4132. uint32_t config_param0 = 0;
  4133. uint32_t config_param1 = 0;
  4134. uint32_t config_param2 = 0;
  4135. uint32_t config_param3 = 0;
  4136. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  4137. config_param0 |= (1 << (cap + 1));
  4138. for (i = 0; i < HTT_PEER_STATS_MAX_TLV; i++) {
  4139. config_param1 |= (1 << i);
  4140. }
  4141. config_param2 |= (mac_addr[0] & 0x000000ff);
  4142. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  4143. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  4144. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  4145. config_param3 |= (mac_addr[4] & 0x000000ff);
  4146. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  4147. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  4148. config_param0, config_param1, config_param2,
  4149. config_param3);
  4150. }
  4151. /*
  4152. * dp_set_pdev_param: function to set parameters in pdev
  4153. * @pdev_handle: DP pdev handle
  4154. * @param: parameter type to be set
  4155. * @val: value of parameter to be set
  4156. *
  4157. * return: void
  4158. */
  4159. static void dp_set_pdev_param(struct cdp_pdev *pdev_handle,
  4160. enum cdp_pdev_param_type param, uint8_t val)
  4161. {
  4162. switch (param) {
  4163. case CDP_CONFIG_DEBUG_SNIFFER:
  4164. dp_config_debug_sniffer(pdev_handle, val);
  4165. break;
  4166. default:
  4167. break;
  4168. }
  4169. }
  4170. /*
  4171. * dp_set_vdev_param: function to set parameters in vdev
  4172. * @param: parameter type to be set
  4173. * @val: value of parameter to be set
  4174. *
  4175. * return: void
  4176. */
  4177. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  4178. enum cdp_vdev_param_type param, uint32_t val)
  4179. {
  4180. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4181. switch (param) {
  4182. case CDP_ENABLE_WDS:
  4183. vdev->wds_enabled = val;
  4184. break;
  4185. case CDP_ENABLE_NAWDS:
  4186. vdev->nawds_enabled = val;
  4187. break;
  4188. case CDP_ENABLE_MCAST_EN:
  4189. vdev->mcast_enhancement_en = val;
  4190. break;
  4191. case CDP_ENABLE_PROXYSTA:
  4192. vdev->proxysta_vdev = val;
  4193. break;
  4194. case CDP_UPDATE_TDLS_FLAGS:
  4195. vdev->tdls_link_connected = val;
  4196. break;
  4197. case CDP_CFG_WDS_AGING_TIMER:
  4198. if (val == 0)
  4199. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4200. else if (val != vdev->wds_aging_timer_val)
  4201. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4202. vdev->wds_aging_timer_val = val;
  4203. break;
  4204. case CDP_ENABLE_AP_BRIDGE:
  4205. if (wlan_op_mode_sta != vdev->opmode)
  4206. vdev->ap_bridge_enabled = val;
  4207. else
  4208. vdev->ap_bridge_enabled = false;
  4209. break;
  4210. case CDP_ENABLE_CIPHER:
  4211. vdev->sec_type = val;
  4212. break;
  4213. default:
  4214. break;
  4215. }
  4216. dp_tx_vdev_update_search_flags(vdev);
  4217. }
  4218. /**
  4219. * dp_peer_set_nawds: set nawds bit in peer
  4220. * @peer_handle: pointer to peer
  4221. * @value: enable/disable nawds
  4222. *
  4223. * return: void
  4224. */
  4225. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4226. {
  4227. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4228. peer->nawds_enabled = value;
  4229. }
  4230. /*
  4231. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4232. * @vdev_handle: DP_VDEV handle
  4233. * @map_id:ID of map that needs to be updated
  4234. *
  4235. * Return: void
  4236. */
  4237. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4238. uint8_t map_id)
  4239. {
  4240. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4241. vdev->dscp_tid_map_id = map_id;
  4242. return;
  4243. }
  4244. /**
  4245. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4246. * @pdev: DP_PDEV handle
  4247. * @map_id: ID of map that needs to be updated
  4248. * @tos: index value in map
  4249. * @tid: tid value passed by the user
  4250. *
  4251. * Return: void
  4252. */
  4253. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4254. uint8_t map_id, uint8_t tos, uint8_t tid)
  4255. {
  4256. uint8_t dscp;
  4257. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4258. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4259. pdev->dscp_tid_map[map_id][dscp] = tid;
  4260. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4261. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4262. map_id, dscp);
  4263. return;
  4264. }
  4265. /**
  4266. * dp_fw_stats_process(): Process TxRX FW stats request
  4267. * @vdev_handle: DP VDEV handle
  4268. * @req: stats request
  4269. *
  4270. * return: int
  4271. */
  4272. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle,
  4273. struct cdp_txrx_stats_req *req)
  4274. {
  4275. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4276. struct dp_pdev *pdev = NULL;
  4277. uint32_t stats = req->stats;
  4278. if (!vdev) {
  4279. DP_TRACE(NONE, "VDEV not found");
  4280. return 1;
  4281. }
  4282. pdev = vdev->pdev;
  4283. return dp_h2t_ext_stats_msg_send(pdev, stats, req->param0,
  4284. req->param1, req->param2, req->param3);
  4285. }
  4286. /**
  4287. * dp_txrx_stats_request - function to map to firmware and host stats
  4288. * @vdev: virtual handle
  4289. * @req: stats request
  4290. *
  4291. * Return: integer
  4292. */
  4293. static int dp_txrx_stats_request(struct cdp_vdev *vdev,
  4294. struct cdp_txrx_stats_req *req)
  4295. {
  4296. int host_stats;
  4297. int fw_stats;
  4298. enum cdp_stats stats;
  4299. if (!vdev || !req) {
  4300. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4301. "Invalid vdev/req instance");
  4302. return 0;
  4303. }
  4304. stats = req->stats;
  4305. if (stats >= CDP_TXRX_MAX_STATS)
  4306. return 0;
  4307. /*
  4308. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4309. * has to be updated if new FW HTT stats added
  4310. */
  4311. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4312. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4313. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4314. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4315. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4316. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4317. stats, fw_stats, host_stats);
  4318. if (fw_stats != TXRX_FW_STATS_INVALID) {
  4319. /* update request with FW stats type */
  4320. req->stats = fw_stats;
  4321. return dp_fw_stats_process(vdev, req);
  4322. }
  4323. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4324. (host_stats <= TXRX_HOST_STATS_MAX))
  4325. return dp_print_host_stats(vdev, host_stats);
  4326. else
  4327. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4328. "Wrong Input for TxRx Stats");
  4329. return 0;
  4330. }
  4331. /**
  4332. * dp_txrx_stats() - function to map to firmware and host stats
  4333. * @vdev: virtual handle
  4334. * @stats: type of statistics requested
  4335. *
  4336. * Return: integer
  4337. */
  4338. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4339. {
  4340. struct cdp_txrx_stats_req req = {0,};
  4341. req.stats = stats;
  4342. return dp_txrx_stats_request(vdev, &req);
  4343. }
  4344. /*
  4345. * dp_print_napi_stats(): NAPI stats
  4346. * @soc - soc handle
  4347. */
  4348. static void dp_print_napi_stats(struct dp_soc *soc)
  4349. {
  4350. hif_print_napi_stats(soc->hif_handle);
  4351. }
  4352. /*
  4353. * dp_print_per_ring_stats(): Packet count per ring
  4354. * @soc - soc handle
  4355. */
  4356. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4357. {
  4358. uint8_t core, ring;
  4359. uint64_t total_packets;
  4360. DP_TRACE(FATAL, "Reo packets per ring:");
  4361. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4362. total_packets = 0;
  4363. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4364. for (core = 0; core < NR_CPUS; core++) {
  4365. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4366. core, soc->stats.rx.ring_packets[core][ring]);
  4367. total_packets += soc->stats.rx.ring_packets[core][ring];
  4368. }
  4369. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4370. ring, total_packets);
  4371. }
  4372. }
  4373. /*
  4374. * dp_txrx_path_stats() - Function to display dump stats
  4375. * @soc - soc handle
  4376. *
  4377. * return: none
  4378. */
  4379. static void dp_txrx_path_stats(struct dp_soc *soc)
  4380. {
  4381. uint8_t error_code;
  4382. uint8_t loop_pdev;
  4383. struct dp_pdev *pdev;
  4384. uint8_t i;
  4385. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4386. pdev = soc->pdev_list[loop_pdev];
  4387. dp_aggregate_pdev_stats(pdev);
  4388. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4389. "Tx path Statistics:");
  4390. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4391. pdev->stats.tx_i.rcvd.num,
  4392. pdev->stats.tx_i.rcvd.bytes);
  4393. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4394. pdev->stats.tx_i.processed.num,
  4395. pdev->stats.tx_i.processed.bytes);
  4396. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4397. pdev->stats.tx.tx_success.num,
  4398. pdev->stats.tx.tx_success.bytes);
  4399. DP_TRACE(FATAL, "Dropped in host:");
  4400. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4401. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4402. DP_TRACE(FATAL, "Descriptor not available: %u",
  4403. pdev->stats.tx_i.dropped.desc_na);
  4404. DP_TRACE(FATAL, "Ring full: %u",
  4405. pdev->stats.tx_i.dropped.ring_full);
  4406. DP_TRACE(FATAL, "Enqueue fail: %u",
  4407. pdev->stats.tx_i.dropped.enqueue_fail);
  4408. DP_TRACE(FATAL, "DMA Error: %u",
  4409. pdev->stats.tx_i.dropped.dma_error);
  4410. DP_TRACE(FATAL, "Dropped in hardware:");
  4411. DP_TRACE(FATAL, "total packets dropped: %u",
  4412. pdev->stats.tx.tx_failed);
  4413. DP_TRACE(FATAL, "mpdu age out: %u",
  4414. pdev->stats.tx.dropped.age_out);
  4415. DP_TRACE(FATAL, "firmware removed: %u",
  4416. pdev->stats.tx.dropped.fw_rem);
  4417. DP_TRACE(FATAL, "firmware removed tx: %u",
  4418. pdev->stats.tx.dropped.fw_rem_tx);
  4419. DP_TRACE(FATAL, "firmware removed notx %u",
  4420. pdev->stats.tx.dropped.fw_rem_notx);
  4421. DP_TRACE(FATAL, "peer_invalid: %u",
  4422. pdev->soc->stats.tx.tx_invalid_peer.num);
  4423. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4424. DP_TRACE(FATAL, "Single Packet: %u",
  4425. pdev->stats.tx_comp_histogram.pkts_1);
  4426. DP_TRACE(FATAL, "2-20 Packets: %u",
  4427. pdev->stats.tx_comp_histogram.pkts_2_20);
  4428. DP_TRACE(FATAL, "21-40 Packets: %u",
  4429. pdev->stats.tx_comp_histogram.pkts_21_40);
  4430. DP_TRACE(FATAL, "41-60 Packets: %u",
  4431. pdev->stats.tx_comp_histogram.pkts_41_60);
  4432. DP_TRACE(FATAL, "61-80 Packets: %u",
  4433. pdev->stats.tx_comp_histogram.pkts_61_80);
  4434. DP_TRACE(FATAL, "81-100 Packets: %u",
  4435. pdev->stats.tx_comp_histogram.pkts_81_100);
  4436. DP_TRACE(FATAL, "101-200 Packets: %u",
  4437. pdev->stats.tx_comp_histogram.pkts_101_200);
  4438. DP_TRACE(FATAL, " 201+ Packets: %u",
  4439. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4440. DP_TRACE(FATAL, "Rx path statistics");
  4441. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4442. pdev->stats.rx.to_stack.num,
  4443. pdev->stats.rx.to_stack.bytes);
  4444. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4445. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4446. i, pdev->stats.rx.rcvd_reo[i].num,
  4447. pdev->stats.rx.rcvd_reo[i].bytes);
  4448. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4449. pdev->stats.rx.intra_bss.pkts.num,
  4450. pdev->stats.rx.intra_bss.pkts.bytes);
  4451. DP_TRACE(FATAL, "intra-bss fails %u msdus ( %u bytes),",
  4452. pdev->stats.rx.intra_bss.fail.num,
  4453. pdev->stats.rx.intra_bss.fail.bytes);
  4454. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4455. pdev->stats.rx.raw.num,
  4456. pdev->stats.rx.raw.bytes);
  4457. DP_TRACE(FATAL, "dropped: error %u msdus",
  4458. pdev->stats.rx.err.mic_err);
  4459. DP_TRACE(FATAL, "peer invalid %u",
  4460. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4461. DP_TRACE(FATAL, "Reo Statistics");
  4462. DP_TRACE(FATAL, "rbm error: %u msdus",
  4463. pdev->soc->stats.rx.err.invalid_rbm);
  4464. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4465. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4466. DP_TRACE(FATAL, "Reo errors");
  4467. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4468. error_code++) {
  4469. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4470. error_code,
  4471. pdev->soc->stats.rx.err.reo_error[error_code]);
  4472. }
  4473. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4474. error_code++) {
  4475. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4476. error_code,
  4477. pdev->soc->stats.rx.err
  4478. .rxdma_error[error_code]);
  4479. }
  4480. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4481. DP_TRACE(FATAL, "Single Packet: %u",
  4482. pdev->stats.rx_ind_histogram.pkts_1);
  4483. DP_TRACE(FATAL, "2-20 Packets: %u",
  4484. pdev->stats.rx_ind_histogram.pkts_2_20);
  4485. DP_TRACE(FATAL, "21-40 Packets: %u",
  4486. pdev->stats.rx_ind_histogram.pkts_21_40);
  4487. DP_TRACE(FATAL, "41-60 Packets: %u",
  4488. pdev->stats.rx_ind_histogram.pkts_41_60);
  4489. DP_TRACE(FATAL, "61-80 Packets: %u",
  4490. pdev->stats.rx_ind_histogram.pkts_61_80);
  4491. DP_TRACE(FATAL, "81-100 Packets: %u",
  4492. pdev->stats.rx_ind_histogram.pkts_81_100);
  4493. DP_TRACE(FATAL, "101-200 Packets: %u",
  4494. pdev->stats.rx_ind_histogram.pkts_101_200);
  4495. DP_TRACE(FATAL, " 201+ Packets: %u",
  4496. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4497. DP_TRACE_STATS(ERROR, "%s: tso_enable: %u lro_enable: %u rx_hash: %u napi_enable: %u",
  4498. __func__,
  4499. pdev->soc->wlan_cfg_ctx->tso_enabled,
  4500. pdev->soc->wlan_cfg_ctx->lro_enabled,
  4501. pdev->soc->wlan_cfg_ctx->rx_hash,
  4502. pdev->soc->wlan_cfg_ctx->napi_enabled);
  4503. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4504. DP_TRACE_STATS(ERROR, "%s: Tx flow stop queue: %u tx flow start queue offset: %u",
  4505. __func__,
  4506. pdev->soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold,
  4507. pdev->soc->wlan_cfg_ctx->tx_flow_start_queue_offset);
  4508. #endif
  4509. }
  4510. }
  4511. /*
  4512. * dp_txrx_dump_stats() - Dump statistics
  4513. * @value - Statistics option
  4514. */
  4515. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value,
  4516. enum qdf_stats_verbosity_level level)
  4517. {
  4518. struct dp_soc *soc =
  4519. (struct dp_soc *)psoc;
  4520. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4521. if (!soc) {
  4522. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4523. "%s: soc is NULL", __func__);
  4524. return QDF_STATUS_E_INVAL;
  4525. }
  4526. switch (value) {
  4527. case CDP_TXRX_PATH_STATS:
  4528. dp_txrx_path_stats(soc);
  4529. break;
  4530. case CDP_RX_RING_STATS:
  4531. dp_print_per_ring_stats(soc);
  4532. break;
  4533. case CDP_TXRX_TSO_STATS:
  4534. /* TODO: NOT IMPLEMENTED */
  4535. break;
  4536. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4537. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4538. break;
  4539. case CDP_DP_NAPI_STATS:
  4540. dp_print_napi_stats(soc);
  4541. break;
  4542. case CDP_TXRX_DESC_STATS:
  4543. /* TODO: NOT IMPLEMENTED */
  4544. break;
  4545. default:
  4546. status = QDF_STATUS_E_INVAL;
  4547. break;
  4548. }
  4549. return status;
  4550. }
  4551. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4552. /**
  4553. * dp_update_flow_control_parameters() - API to store datapath
  4554. * config parameters
  4555. * @soc: soc handle
  4556. * @cfg: ini parameter handle
  4557. *
  4558. * Return: void
  4559. */
  4560. static inline
  4561. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4562. struct cdp_config_params *params)
  4563. {
  4564. soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold =
  4565. params->tx_flow_stop_queue_threshold;
  4566. soc->wlan_cfg_ctx->tx_flow_start_queue_offset =
  4567. params->tx_flow_start_queue_offset;
  4568. }
  4569. #else
  4570. static inline
  4571. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4572. struct cdp_config_params *params)
  4573. {
  4574. }
  4575. #endif
  4576. /**
  4577. * dp_update_config_parameters() - API to store datapath
  4578. * config parameters
  4579. * @soc: soc handle
  4580. * @cfg: ini parameter handle
  4581. *
  4582. * Return: status
  4583. */
  4584. static
  4585. QDF_STATUS dp_update_config_parameters(struct cdp_soc *psoc,
  4586. struct cdp_config_params *params)
  4587. {
  4588. struct dp_soc *soc = (struct dp_soc *)psoc;
  4589. if (!(soc)) {
  4590. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4591. "%s: Invalid handle", __func__);
  4592. return QDF_STATUS_E_INVAL;
  4593. }
  4594. soc->wlan_cfg_ctx->tso_enabled = params->tso_enable;
  4595. soc->wlan_cfg_ctx->lro_enabled = params->lro_enable;
  4596. soc->wlan_cfg_ctx->rx_hash = params->flow_steering_enable;
  4597. soc->wlan_cfg_ctx->tcp_udp_checksumoffload =
  4598. params->tcp_udp_checksumoffload;
  4599. soc->wlan_cfg_ctx->napi_enabled = params->napi_enable;
  4600. dp_update_flow_control_parameters(soc, params);
  4601. return QDF_STATUS_SUCCESS;
  4602. }
  4603. static struct cdp_wds_ops dp_ops_wds = {
  4604. .vdev_set_wds = dp_vdev_set_wds,
  4605. };
  4606. /*
  4607. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4608. * @soc - datapath soc handle
  4609. * @peer - datapath peer handle
  4610. *
  4611. * Delete the AST entries belonging to a peer
  4612. */
  4613. #ifdef FEATURE_WDS
  4614. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4615. struct dp_peer *peer)
  4616. {
  4617. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4618. qdf_spin_lock_bh(&soc->ast_lock);
  4619. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4620. if (ast_entry->next_hop) {
  4621. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4622. peer->vdev->pdev->osif_pdev,
  4623. ast_entry->mac_addr.raw);
  4624. }
  4625. dp_peer_del_ast(soc, ast_entry);
  4626. }
  4627. qdf_spin_unlock_bh(&soc->ast_lock);
  4628. }
  4629. #else
  4630. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4631. struct dp_peer *peer)
  4632. {
  4633. }
  4634. #endif
  4635. /*
  4636. * dp_txrx_data_tx_cb_set(): set the callback for non standard tx
  4637. * @vdev_handle - datapath vdev handle
  4638. * @callback - callback function
  4639. * @ctxt: callback context
  4640. *
  4641. */
  4642. static void
  4643. dp_txrx_data_tx_cb_set(struct cdp_vdev *vdev_handle,
  4644. ol_txrx_data_tx_cb callback, void *ctxt)
  4645. {
  4646. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4647. vdev->tx_non_std_data_callback.func = callback;
  4648. vdev->tx_non_std_data_callback.ctxt = ctxt;
  4649. }
  4650. #ifdef CONFIG_WIN
  4651. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4652. {
  4653. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4654. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4655. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4656. dp_peer_delete_ast_entries(soc, peer);
  4657. }
  4658. #endif
  4659. static struct cdp_cmn_ops dp_ops_cmn = {
  4660. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4661. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4662. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4663. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4664. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4665. .txrx_peer_create = dp_peer_create_wifi3,
  4666. .txrx_peer_setup = dp_peer_setup_wifi3,
  4667. #ifdef CONFIG_WIN
  4668. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4669. #else
  4670. .txrx_peer_teardown = NULL,
  4671. #endif
  4672. .txrx_peer_delete = dp_peer_delete_wifi3,
  4673. .txrx_vdev_register = dp_vdev_register_wifi3,
  4674. .txrx_soc_detach = dp_soc_detach_wifi3,
  4675. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4676. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4677. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4678. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4679. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4680. .delba_process = dp_delba_process_wifi3,
  4681. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4682. .flush_cache_rx_queue = NULL,
  4683. /* TODO: get API's for dscp-tid need to be added*/
  4684. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4685. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4686. .txrx_stats = dp_txrx_stats,
  4687. .txrx_stats_request = dp_txrx_stats_request,
  4688. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4689. .display_stats = dp_txrx_dump_stats,
  4690. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4691. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4692. #ifdef DP_INTR_POLL_BASED
  4693. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4694. #else
  4695. .txrx_intr_attach = dp_soc_interrupt_attach,
  4696. #endif
  4697. .txrx_intr_detach = dp_soc_interrupt_detach,
  4698. .set_pn_check = dp_set_pn_check_wifi3,
  4699. .update_config_parameters = dp_update_config_parameters,
  4700. /* TODO: Add other functions */
  4701. .txrx_data_tx_cb_set = dp_txrx_data_tx_cb_set
  4702. };
  4703. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4704. .txrx_peer_authorize = dp_peer_authorize,
  4705. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4706. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4707. #ifdef MESH_MODE_SUPPORT
  4708. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4709. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4710. #endif
  4711. .txrx_set_vdev_param = dp_set_vdev_param,
  4712. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4713. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4714. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4715. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4716. .txrx_update_filter_neighbour_peers =
  4717. dp_update_filter_neighbour_peers,
  4718. .txrx_get_sec_type = dp_get_sec_type,
  4719. /* TODO: Add other functions */
  4720. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4721. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4722. .txrx_set_pdev_param = dp_set_pdev_param,
  4723. };
  4724. static struct cdp_me_ops dp_ops_me = {
  4725. #ifdef ATH_SUPPORT_IQUE
  4726. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4727. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4728. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4729. #endif
  4730. };
  4731. static struct cdp_mon_ops dp_ops_mon = {
  4732. .txrx_monitor_set_filter_ucast_data = NULL,
  4733. .txrx_monitor_set_filter_mcast_data = NULL,
  4734. .txrx_monitor_set_filter_non_data = NULL,
  4735. .txrx_monitor_get_filter_ucast_data = NULL,
  4736. .txrx_monitor_get_filter_mcast_data = NULL,
  4737. .txrx_monitor_get_filter_non_data = NULL,
  4738. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  4739. };
  4740. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4741. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4742. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4743. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4744. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4745. /* TODO */
  4746. };
  4747. static struct cdp_raw_ops dp_ops_raw = {
  4748. /* TODO */
  4749. };
  4750. #ifdef CONFIG_WIN
  4751. static struct cdp_pflow_ops dp_ops_pflow = {
  4752. /* TODO */
  4753. };
  4754. #endif /* CONFIG_WIN */
  4755. #ifdef FEATURE_RUNTIME_PM
  4756. /**
  4757. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  4758. * @opaque_pdev: DP pdev context
  4759. *
  4760. * DP is ready to runtime suspend if there are no pending TX packets.
  4761. *
  4762. * Return: QDF_STATUS
  4763. */
  4764. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  4765. {
  4766. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4767. struct dp_soc *soc = pdev->soc;
  4768. /* Call DP TX flow control API to check if there is any
  4769. pending packets */
  4770. if (soc->intr_mode == DP_INTR_POLL)
  4771. qdf_timer_stop(&soc->int_timer);
  4772. return QDF_STATUS_SUCCESS;
  4773. }
  4774. /**
  4775. * dp_runtime_resume() - ensure DP is ready to runtime resume
  4776. * @opaque_pdev: DP pdev context
  4777. *
  4778. * Resume DP for runtime PM.
  4779. *
  4780. * Return: QDF_STATUS
  4781. */
  4782. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  4783. {
  4784. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4785. struct dp_soc *soc = pdev->soc;
  4786. void *hal_srng;
  4787. int i;
  4788. if (soc->intr_mode == DP_INTR_POLL)
  4789. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4790. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  4791. hal_srng = soc->tcl_data_ring[i].hal_srng;
  4792. if (hal_srng) {
  4793. /* We actually only need to acquire the lock */
  4794. hal_srng_access_start(soc->hal_soc, hal_srng);
  4795. /* Update SRC ring head pointer for HW to send
  4796. all pending packets */
  4797. hal_srng_access_end(soc->hal_soc, hal_srng);
  4798. }
  4799. }
  4800. return QDF_STATUS_SUCCESS;
  4801. }
  4802. #endif /* FEATURE_RUNTIME_PM */
  4803. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4804. {
  4805. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4806. struct dp_soc *soc = pdev->soc;
  4807. if (soc->intr_mode == DP_INTR_POLL)
  4808. qdf_timer_stop(&soc->int_timer);
  4809. return QDF_STATUS_SUCCESS;
  4810. }
  4811. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4812. {
  4813. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4814. struct dp_soc *soc = pdev->soc;
  4815. if (soc->intr_mode == DP_INTR_POLL)
  4816. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4817. return QDF_STATUS_SUCCESS;
  4818. }
  4819. #ifndef CONFIG_WIN
  4820. static struct cdp_misc_ops dp_ops_misc = {
  4821. .tx_non_std = dp_tx_non_std,
  4822. .get_opmode = dp_get_opmode,
  4823. #ifdef FEATURE_RUNTIME_PM
  4824. .runtime_suspend = dp_runtime_suspend,
  4825. .runtime_resume = dp_runtime_resume,
  4826. #endif /* FEATURE_RUNTIME_PM */
  4827. };
  4828. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4829. /* WIFI 3.0 DP implement as required. */
  4830. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4831. .register_pause_cb = dp_txrx_register_pause_cb,
  4832. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4833. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4834. };
  4835. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4836. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4837. };
  4838. #ifdef IPA_OFFLOAD
  4839. static struct cdp_ipa_ops dp_ops_ipa = {
  4840. .ipa_get_resource = dp_ipa_get_resource,
  4841. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4842. .ipa_op_response = dp_ipa_op_response,
  4843. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4844. .ipa_get_stat = dp_ipa_get_stat,
  4845. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4846. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4847. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4848. .ipa_setup = dp_ipa_setup,
  4849. .ipa_cleanup = dp_ipa_cleanup,
  4850. .ipa_setup_iface = dp_ipa_setup_iface,
  4851. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4852. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4853. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4854. .ipa_set_perf_level = dp_ipa_set_perf_level
  4855. };
  4856. #endif
  4857. static struct cdp_bus_ops dp_ops_bus = {
  4858. .bus_suspend = dp_bus_suspend,
  4859. .bus_resume = dp_bus_resume
  4860. };
  4861. static struct cdp_ocb_ops dp_ops_ocb = {
  4862. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4863. };
  4864. static struct cdp_throttle_ops dp_ops_throttle = {
  4865. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4866. };
  4867. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4868. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4869. };
  4870. static struct cdp_cfg_ops dp_ops_cfg = {
  4871. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4872. };
  4873. static struct cdp_peer_ops dp_ops_peer = {
  4874. .register_peer = dp_register_peer,
  4875. .clear_peer = dp_clear_peer,
  4876. .find_peer_by_addr = dp_find_peer_by_addr,
  4877. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4878. .local_peer_id = dp_local_peer_id,
  4879. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4880. .peer_state_update = dp_peer_state_update,
  4881. .get_vdevid = dp_get_vdevid,
  4882. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4883. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4884. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4885. .get_peer_state = dp_get_peer_state,
  4886. .last_assoc_received = dp_get_last_assoc_received,
  4887. .last_disassoc_received = dp_get_last_disassoc_received,
  4888. .last_deauth_received = dp_get_last_deauth_received,
  4889. };
  4890. #endif
  4891. static struct cdp_ops dp_txrx_ops = {
  4892. .cmn_drv_ops = &dp_ops_cmn,
  4893. .ctrl_ops = &dp_ops_ctrl,
  4894. .me_ops = &dp_ops_me,
  4895. .mon_ops = &dp_ops_mon,
  4896. .host_stats_ops = &dp_ops_host_stats,
  4897. .wds_ops = &dp_ops_wds,
  4898. .raw_ops = &dp_ops_raw,
  4899. #ifdef CONFIG_WIN
  4900. .pflow_ops = &dp_ops_pflow,
  4901. #endif /* CONFIG_WIN */
  4902. #ifndef CONFIG_WIN
  4903. .misc_ops = &dp_ops_misc,
  4904. .cfg_ops = &dp_ops_cfg,
  4905. .flowctl_ops = &dp_ops_flowctl,
  4906. .l_flowctl_ops = &dp_ops_l_flowctl,
  4907. #ifdef IPA_OFFLOAD
  4908. .ipa_ops = &dp_ops_ipa,
  4909. #endif
  4910. .bus_ops = &dp_ops_bus,
  4911. .ocb_ops = &dp_ops_ocb,
  4912. .peer_ops = &dp_ops_peer,
  4913. .throttle_ops = &dp_ops_throttle,
  4914. .mob_stats_ops = &dp_ops_mob_stats,
  4915. #endif
  4916. };
  4917. /*
  4918. * dp_soc_set_txrx_ring_map()
  4919. * @dp_soc: DP handler for soc
  4920. *
  4921. * Return: Void
  4922. */
  4923. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4924. {
  4925. uint32_t i;
  4926. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4927. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4928. }
  4929. }
  4930. /*
  4931. * dp_soc_attach_wifi3() - Attach txrx SOC
  4932. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4933. * @htc_handle: Opaque HTC handle
  4934. * @hif_handle: Opaque HIF handle
  4935. * @qdf_osdev: QDF device
  4936. *
  4937. * Return: DP SOC handle on success, NULL on failure
  4938. */
  4939. /*
  4940. * Local prototype added to temporarily address warning caused by
  4941. * -Wmissing-prototypes. A more correct solution, namely to expose
  4942. * a prototype in an appropriate header file, will come later.
  4943. */
  4944. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4945. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4946. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4947. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4948. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4949. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4950. {
  4951. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4952. if (!soc) {
  4953. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4954. FL("DP SOC memory allocation failed"));
  4955. goto fail0;
  4956. }
  4957. soc->cdp_soc.ops = &dp_txrx_ops;
  4958. soc->cdp_soc.ol_ops = ol_ops;
  4959. soc->osif_soc = osif_soc;
  4960. soc->osdev = qdf_osdev;
  4961. soc->hif_handle = hif_handle;
  4962. soc->psoc = psoc;
  4963. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4964. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4965. soc->hal_soc, qdf_osdev);
  4966. if (!soc->htt_handle) {
  4967. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4968. FL("HTT attach failed"));
  4969. goto fail1;
  4970. }
  4971. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4972. if (!soc->wlan_cfg_ctx) {
  4973. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4974. FL("wlan_cfg_soc_attach failed"));
  4975. goto fail2;
  4976. }
  4977. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  4978. soc->cce_disable = false;
  4979. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4980. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->osif_soc,
  4981. CDP_CFG_MAX_PEER_ID);
  4982. if (ret != -EINVAL) {
  4983. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4984. }
  4985. ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->osif_soc,
  4986. CDP_CFG_CCE_DISABLE);
  4987. if (ret)
  4988. soc->cce_disable = true;
  4989. }
  4990. qdf_spinlock_create(&soc->peer_ref_mutex);
  4991. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4992. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4993. /* fill the tx/rx cpu ring map*/
  4994. dp_soc_set_txrx_ring_map(soc);
  4995. qdf_spinlock_create(&soc->htt_stats.lock);
  4996. /* initialize work queue for stats processing */
  4997. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4998. return (void *)soc;
  4999. fail2:
  5000. htt_soc_detach(soc->htt_handle);
  5001. fail1:
  5002. qdf_mem_free(soc);
  5003. fail0:
  5004. return NULL;
  5005. }
  5006. /*
  5007. * dp_get_pdev_for_mac_id() - Return pdev for mac_id
  5008. *
  5009. * @soc: handle to DP soc
  5010. * @mac_id: MAC id
  5011. *
  5012. * Return: Return pdev corresponding to MAC
  5013. */
  5014. void *dp_get_pdev_for_mac_id(struct dp_soc *soc, uint32_t mac_id)
  5015. {
  5016. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx))
  5017. return soc->pdev_list[mac_id];
  5018. /* Typically for MCL as there only 1 PDEV*/
  5019. return soc->pdev_list[0];
  5020. }
  5021. /*
  5022. * dp_get_ring_id_for_mac_id() - Return pdev for mac_id
  5023. *
  5024. * @soc: handle to DP soc
  5025. * @mac_id: MAC id
  5026. *
  5027. * Return: ring id
  5028. */
  5029. int dp_get_ring_id_for_mac_id(struct dp_soc *soc, uint32_t mac_id)
  5030. {
  5031. /*
  5032. * Single pdev using both MACs will operate on both MAC rings,
  5033. * which is the case for MCL.
  5034. */
  5035. if (!wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx))
  5036. return mac_id;
  5037. /* For WIN each PDEV will operate one ring, so index is zero. */
  5038. return 0;
  5039. }
  5040. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  5041. /*
  5042. * dp_set_pktlog_wifi3() - attach txrx vdev
  5043. * @pdev: Datapath PDEV handle
  5044. * @event: which event's notifications are being subscribed to
  5045. * @enable: WDI event subscribe or not. (True or False)
  5046. *
  5047. * Return: Success, NULL on failure
  5048. */
  5049. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  5050. bool enable)
  5051. {
  5052. struct dp_soc *soc = pdev->soc;
  5053. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  5054. if (enable) {
  5055. switch (event) {
  5056. case WDI_EVENT_RX_DESC:
  5057. if (pdev->monitor_vdev) {
  5058. /* Nothing needs to be done if monitor mode is
  5059. * enabled
  5060. */
  5061. return 0;
  5062. }
  5063. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  5064. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  5065. htt_tlv_filter.mpdu_start = 1;
  5066. htt_tlv_filter.msdu_start = 1;
  5067. htt_tlv_filter.msdu_end = 1;
  5068. htt_tlv_filter.mpdu_end = 1;
  5069. htt_tlv_filter.packet_header = 1;
  5070. htt_tlv_filter.attention = 1;
  5071. htt_tlv_filter.ppdu_start = 1;
  5072. htt_tlv_filter.ppdu_end = 1;
  5073. htt_tlv_filter.ppdu_end_user_stats = 1;
  5074. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  5075. htt_tlv_filter.ppdu_end_status_done = 1;
  5076. htt_tlv_filter.enable_fp = 1;
  5077. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5078. pdev->pdev_id,
  5079. pdev->rxdma_mon_status_ring.hal_srng,
  5080. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  5081. &htt_tlv_filter);
  5082. }
  5083. break;
  5084. case WDI_EVENT_LITE_RX:
  5085. if (pdev->monitor_vdev) {
  5086. /* Nothing needs to be done if monitor mode is
  5087. * enabled
  5088. */
  5089. return 0;
  5090. }
  5091. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  5092. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  5093. htt_tlv_filter.ppdu_start = 1;
  5094. htt_tlv_filter.ppdu_end = 1;
  5095. htt_tlv_filter.ppdu_end_user_stats = 1;
  5096. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  5097. htt_tlv_filter.ppdu_end_status_done = 1;
  5098. htt_tlv_filter.enable_fp = 1;
  5099. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5100. pdev->pdev_id,
  5101. pdev->rxdma_mon_status_ring.hal_srng,
  5102. RXDMA_MONITOR_STATUS,
  5103. RX_BUFFER_SIZE_PKTLOG_LITE,
  5104. &htt_tlv_filter);
  5105. }
  5106. break;
  5107. case WDI_EVENT_LITE_T2H:
  5108. if (pdev->monitor_vdev) {
  5109. /* Nothing needs to be done if monitor mode is
  5110. * enabled
  5111. */
  5112. return 0;
  5113. }
  5114. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  5115. * passing value 0xffff. Once these macros will define in htt
  5116. * header file will use proper macros
  5117. */
  5118. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  5119. break;
  5120. default:
  5121. /* Nothing needs to be done for other pktlog types */
  5122. break;
  5123. }
  5124. } else {
  5125. switch (event) {
  5126. case WDI_EVENT_RX_DESC:
  5127. case WDI_EVENT_LITE_RX:
  5128. if (pdev->monitor_vdev) {
  5129. /* Nothing needs to be done if monitor mode is
  5130. * enabled
  5131. */
  5132. return 0;
  5133. }
  5134. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  5135. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  5136. /* htt_tlv_filter is initialized to 0 */
  5137. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5138. pdev->pdev_id,
  5139. pdev->rxdma_mon_status_ring.hal_srng,
  5140. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  5141. &htt_tlv_filter);
  5142. }
  5143. break;
  5144. case WDI_EVENT_LITE_T2H:
  5145. if (pdev->monitor_vdev) {
  5146. /* Nothing needs to be done if monitor mode is
  5147. * enabled
  5148. */
  5149. return 0;
  5150. }
  5151. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  5152. * passing value 0. Once these macros will define in htt
  5153. * header file will use proper macros
  5154. */
  5155. dp_h2t_cfg_stats_msg_send(pdev, 0);
  5156. break;
  5157. default:
  5158. /* Nothing needs to be done for other pktlog types */
  5159. break;
  5160. }
  5161. }
  5162. return 0;
  5163. }
  5164. #endif