sde_plane.c 137 KB

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  1. /*
  2. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <linux/debugfs.h>
  21. #include <linux/dma-buf.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/msm_drm_pp.h>
  24. #include <linux/version.h>
  25. #include "msm_prop.h"
  26. #include "msm_drv.h"
  27. #include "sde_kms.h"
  28. #include "sde_fence.h"
  29. #include "sde_formats.h"
  30. #include "sde_hw_sspp.h"
  31. #include "sde_hw_catalog_format.h"
  32. #include "sde_trace.h"
  33. #include "sde_crtc.h"
  34. #include "sde_vbif.h"
  35. #include "sde_plane.h"
  36. #include "sde_color_processing.h"
  37. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  40. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  41. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  42. #define PHASE_STEP_SHIFT 21
  43. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  44. #define PHASE_RESIDUAL 15
  45. #define SHARP_STRENGTH_DEFAULT 32
  46. #define SHARP_EDGE_THR_DEFAULT 112
  47. #define SHARP_SMOOTH_THR_DEFAULT 8
  48. #define SHARP_NOISE_THR_DEFAULT 2
  49. #define SDE_NAME_SIZE 12
  50. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  51. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  52. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  53. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  54. /**
  55. * enum sde_plane_qos - Different qos configurations for each pipe
  56. *
  57. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  58. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  59. * this configuration is mutually exclusive from VBLANK_CTRL.
  60. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  61. */
  62. enum sde_plane_qos {
  63. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  64. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  65. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  66. };
  67. /*
  68. * struct sde_plane - local sde plane structure
  69. * @aspace: address space pointer
  70. * @csc_cfg: Decoded user configuration for csc
  71. * @csc_usr_ptr: Points to csc_cfg if valid user config available
  72. * @csc_ptr: Points to sde_csc_cfg structure to use for current
  73. * @mplane_list: List of multirect planes of the same pipe
  74. * @catalog: Points to sde catalog structure
  75. * @revalidate: force revalidation of all the plane properties
  76. * @xin_halt_forced_clk: whether or not clocks were forced on for xin halt
  77. * @blob_rot_caps: Pointer to rotator capability blob
  78. */
  79. struct sde_plane {
  80. struct drm_plane base;
  81. struct mutex lock;
  82. enum sde_sspp pipe;
  83. uint64_t features; /* capabilities from catalog */
  84. uint32_t perf_features; /* perf capabilities from catalog */
  85. uint32_t nformats;
  86. uint32_t formats[64];
  87. struct sde_hw_pipe *pipe_hw;
  88. struct sde_hw_pipe_cfg pipe_cfg;
  89. struct sde_hw_sharp_cfg sharp_cfg;
  90. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  91. uint32_t color_fill;
  92. bool is_error;
  93. bool is_rt_pipe;
  94. bool is_virtual;
  95. struct list_head mplane_list;
  96. struct sde_mdss_cfg *catalog;
  97. bool revalidate;
  98. bool xin_halt_forced_clk;
  99. struct sde_csc_cfg csc_cfg;
  100. struct sde_csc_cfg *csc_usr_ptr;
  101. struct sde_csc_cfg *csc_ptr;
  102. struct sde_hw_scaler3_cfg scaler3_cfg;
  103. struct sde_hw_pixel_ext pixel_ext;
  104. const struct sde_sspp_sub_blks *pipe_sblk;
  105. char pipe_name[SDE_NAME_SIZE];
  106. struct msm_property_info property_info;
  107. struct msm_property_data property_data[PLANE_PROP_COUNT];
  108. struct drm_property_blob *blob_info;
  109. struct drm_property_blob *blob_rot_caps;
  110. /* debugfs related stuff */
  111. struct dentry *debugfs_root;
  112. bool debugfs_default_scale;
  113. };
  114. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  115. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  116. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  117. {
  118. struct msm_drm_private *priv;
  119. if (!plane || !plane->dev)
  120. return NULL;
  121. priv = plane->dev->dev_private;
  122. if (!priv)
  123. return NULL;
  124. return to_sde_kms(priv->kms);
  125. }
  126. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  127. {
  128. struct drm_plane_state *pstate = NULL;
  129. struct drm_crtc *drm_crtc = NULL;
  130. struct sde_crtc *sde_crtc = NULL;
  131. struct sde_crtc_mixer *mixer = NULL;
  132. struct sde_hw_ctl *ctl = NULL;
  133. if (!plane) {
  134. DRM_ERROR("Invalid plane %pK\n", plane);
  135. return NULL;
  136. }
  137. pstate = plane->state;
  138. if (!pstate) {
  139. DRM_ERROR("Invalid plane state %pK\n", pstate);
  140. return NULL;
  141. }
  142. drm_crtc = pstate->crtc;
  143. if (!drm_crtc) {
  144. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  145. return NULL;
  146. }
  147. sde_crtc = to_sde_crtc(drm_crtc);
  148. if (!sde_crtc) {
  149. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  150. return NULL;
  151. }
  152. /* it will always return the first mixer and single CTL */
  153. mixer = sde_crtc->mixers;
  154. if (!mixer) {
  155. DRM_ERROR("invalid mixer %pK\n", mixer);
  156. return NULL;
  157. }
  158. ctl = mixer->hw_ctl;
  159. if (!mixer) {
  160. DRM_ERROR("invalid ctl %pK\n", ctl);
  161. return NULL;
  162. }
  163. return ctl;
  164. }
  165. static bool sde_plane_enabled(const struct drm_plane_state *state)
  166. {
  167. return state && state->fb && state->crtc;
  168. }
  169. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  170. {
  171. struct sde_plane *psde;
  172. if (!plane)
  173. return false;
  174. psde = to_sde_plane(plane);
  175. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  176. }
  177. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  178. enum sde_sspp_multirect_index rect_mode, bool enable)
  179. {
  180. struct sde_plane *psde;
  181. if (!plane)
  182. return;
  183. psde = to_sde_plane(plane);
  184. if (psde->pipe_hw->ops.set_src_split_order)
  185. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  186. rect_mode, enable);
  187. }
  188. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  189. {
  190. struct sde_plane *psde;
  191. struct sde_kms *sde_kms;
  192. struct msm_drm_private *priv;
  193. if (!plane || !plane->dev) {
  194. SDE_ERROR("invalid plane\n");
  195. return;
  196. }
  197. priv = plane->dev->dev_private;
  198. if (!priv || !priv->kms) {
  199. SDE_ERROR("invalid KMS reference\n");
  200. return;
  201. }
  202. sde_kms = to_sde_kms(priv->kms);
  203. psde = to_sde_plane(plane);
  204. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm);
  205. }
  206. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  207. struct drm_crtc *crtc,
  208. struct drm_framebuffer *fb)
  209. {
  210. struct sde_plane *psde;
  211. const struct sde_format *fmt = NULL;
  212. u32 frame_rate, qos_count, fps_index = 0, lut_index, creq_lut_index, index;
  213. struct sde_perf_cfg *perf;
  214. struct sde_plane_state *pstate;
  215. bool inline_rot = false;
  216. if (!plane || !fb) {
  217. SDE_ERROR("invalid arguments\n");
  218. return;
  219. }
  220. psde = to_sde_plane(plane);
  221. pstate = to_sde_plane_state(plane->state);
  222. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  223. SDE_ERROR("invalid arguments\n");
  224. return;
  225. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  226. return;
  227. }
  228. frame_rate = drm_mode_vrefresh(&crtc->mode);
  229. perf = &psde->catalog->perf;
  230. qos_count = perf->qos_refresh_count;
  231. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  232. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  233. (fps_index == qos_count - 1))
  234. break;
  235. fps_index++;
  236. }
  237. if (psde->is_rt_pipe) {
  238. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  239. inline_rot = (pstate->rotation & DRM_MODE_ROTATE_90);
  240. if (inline_rot && SDE_IS_IN_ROT_RESTRICTED_FMT(psde->catalog, fmt))
  241. lut_index = SDE_QOS_LUT_USAGE_INLINE_RESTRICTED_FMTS;
  242. else if (inline_rot)
  243. lut_index = SDE_QOS_LUT_USAGE_INLINE;
  244. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  245. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  246. else
  247. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  248. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  249. if (psde->scaler3_cfg.enable)
  250. creq_lut_index += SDE_CREQ_LUT_TYPE_QSEED;
  251. } else {
  252. lut_index = SDE_QOS_LUT_USAGE_NRT;
  253. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  254. }
  255. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  256. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[index];
  257. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[index];
  258. creq_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_CREQ_LUT_TYPE_MAX);
  259. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[creq_lut_index];
  260. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
  261. (fmt) ? fmt->base.pixel_format : 0,
  262. (fmt) ? fmt->fetch_mode : 0,
  263. psde->pipe_qos_cfg.danger_lut,
  264. psde->pipe_qos_cfg.safe_lut,
  265. psde->pipe_qos_cfg.creq_lut);
  266. SDE_DEBUG(
  267. "plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  268. plane->base.id,
  269. psde->pipe - SSPP_VIG0,
  270. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  271. fmt ? fmt->fetch_mode : -1,
  272. psde->pipe_qos_cfg.danger_lut,
  273. psde->pipe_qos_cfg.safe_lut,
  274. psde->pipe_qos_cfg.creq_lut);
  275. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  276. }
  277. /**
  278. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  279. * @plane: Pointer to drm plane
  280. * @enable: true to enable QoS control
  281. * @flags: QoS control mode (enum sde_plane_qos)
  282. */
  283. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  284. bool enable, u32 flags)
  285. {
  286. struct sde_plane *psde;
  287. if (!plane) {
  288. SDE_ERROR("invalid arguments\n");
  289. return;
  290. }
  291. psde = to_sde_plane(plane);
  292. if (!psde->pipe_hw || !psde->pipe_sblk) {
  293. SDE_ERROR("invalid arguments\n");
  294. return;
  295. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  296. return;
  297. }
  298. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  299. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  300. psde->pipe_qos_cfg.danger_vblank =
  301. psde->pipe_sblk->danger_vblank;
  302. psde->pipe_qos_cfg.vblank_en = enable;
  303. }
  304. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  305. /* this feature overrules previous VBLANK_CTRL */
  306. psde->pipe_qos_cfg.vblank_en = false;
  307. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  308. }
  309. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  310. psde->pipe_qos_cfg.danger_safe_en = enable;
  311. if (!psde->is_rt_pipe) {
  312. psde->pipe_qos_cfg.vblank_en = false;
  313. psde->pipe_qos_cfg.danger_safe_en = false;
  314. }
  315. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  316. plane->base.id,
  317. psde->pipe - SSPP_VIG0,
  318. psde->pipe_qos_cfg.danger_safe_en,
  319. psde->pipe_qos_cfg.vblank_en,
  320. psde->pipe_qos_cfg.creq_vblank,
  321. psde->pipe_qos_cfg.danger_vblank,
  322. psde->is_rt_pipe);
  323. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  324. &psde->pipe_qos_cfg);
  325. }
  326. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  327. {
  328. struct sde_plane *psde;
  329. if (!plane)
  330. return;
  331. psde = to_sde_plane(plane);
  332. psde->revalidate = enable;
  333. }
  334. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  335. {
  336. struct sde_plane *psde;
  337. int rc;
  338. if (!plane) {
  339. SDE_ERROR("invalid arguments\n");
  340. return -EINVAL;
  341. }
  342. psde = to_sde_plane(plane);
  343. if (!psde->is_rt_pipe)
  344. goto end;
  345. rc = pm_runtime_get_sync(plane->dev->dev);
  346. if (rc < 0) {
  347. SDE_ERROR("failed to enable power resource %d\n", rc);
  348. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  349. return rc;
  350. }
  351. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  352. pm_runtime_put_sync(plane->dev->dev);
  353. end:
  354. return 0;
  355. }
  356. /**
  357. * _sde_plane_set_ot_limit - set OT limit for the given plane
  358. * @plane: Pointer to drm plane
  359. * @crtc: Pointer to drm crtc
  360. */
  361. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  362. struct drm_crtc *crtc)
  363. {
  364. struct sde_plane *psde;
  365. struct sde_vbif_set_ot_params ot_params;
  366. struct msm_drm_private *priv;
  367. struct sde_kms *sde_kms;
  368. if (!plane || !plane->dev || !crtc) {
  369. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  370. !plane, !crtc);
  371. return;
  372. }
  373. priv = plane->dev->dev_private;
  374. if (!priv || !priv->kms) {
  375. SDE_ERROR("invalid KMS reference\n");
  376. return;
  377. }
  378. sde_kms = to_sde_kms(priv->kms);
  379. psde = to_sde_plane(plane);
  380. if (!psde->pipe_hw) {
  381. SDE_ERROR("invalid pipe reference\n");
  382. return;
  383. }
  384. memset(&ot_params, 0, sizeof(ot_params));
  385. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  386. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  387. ot_params.width = psde->pipe_cfg.src_rect.w;
  388. ot_params.height = psde->pipe_cfg.src_rect.h;
  389. ot_params.is_wfd = !psde->is_rt_pipe;
  390. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  391. ot_params.vbif_idx = VBIF_RT;
  392. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  393. ot_params.rd = true;
  394. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  395. }
  396. /**
  397. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  398. * @plane: Pointer to drm plane
  399. */
  400. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  401. {
  402. struct sde_plane *psde;
  403. struct sde_vbif_set_qos_params qos_params;
  404. struct msm_drm_private *priv;
  405. struct sde_kms *sde_kms;
  406. if (!plane || !plane->dev) {
  407. SDE_ERROR("invalid arguments\n");
  408. return;
  409. }
  410. priv = plane->dev->dev_private;
  411. if (!priv || !priv->kms) {
  412. SDE_ERROR("invalid KMS reference\n");
  413. return;
  414. }
  415. sde_kms = to_sde_kms(priv->kms);
  416. psde = to_sde_plane(plane);
  417. if (!psde->pipe_hw) {
  418. SDE_ERROR("invalid pipe reference\n");
  419. return;
  420. }
  421. memset(&qos_params, 0, sizeof(qos_params));
  422. qos_params.vbif_idx = VBIF_RT;
  423. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  424. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  425. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  426. qos_params.client_type = psde->is_rt_pipe ?
  427. VBIF_RT_CLIENT : VBIF_NRT_CLIENT;
  428. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  429. plane->base.id, qos_params.num,
  430. qos_params.vbif_idx,
  431. qos_params.xin_id, qos_params.client_type,
  432. qos_params.clk_ctrl);
  433. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  434. }
  435. /**
  436. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  437. * @plane: Pointer to drm plane
  438. * @pstate: Pointer to sde plane state
  439. */
  440. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  441. struct sde_plane_state *pstate)
  442. {
  443. struct sde_plane *psde;
  444. struct sde_hw_pipe_ts_cfg cfg;
  445. struct msm_drm_private *priv;
  446. struct sde_kms *sde_kms;
  447. if (!plane || !plane->dev) {
  448. SDE_ERROR("invalid arguments");
  449. return;
  450. }
  451. priv = plane->dev->dev_private;
  452. if (!priv || !priv->kms) {
  453. SDE_ERROR("invalid KMS reference\n");
  454. return;
  455. }
  456. sde_kms = to_sde_kms(priv->kms);
  457. psde = to_sde_plane(plane);
  458. if (!psde->pipe_hw) {
  459. SDE_ERROR("invalid pipe reference\n");
  460. return;
  461. }
  462. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  463. return;
  464. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  465. memset(&cfg, 0, sizeof(cfg));
  466. cfg.size = sde_plane_get_property(pstate,
  467. PLANE_PROP_PREFILL_SIZE);
  468. cfg.time = sde_plane_get_property(pstate,
  469. PLANE_PROP_PREFILL_TIME);
  470. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  471. plane->base.id, cfg.size, cfg.time);
  472. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  473. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  474. pstate->multirect_index);
  475. }
  476. /* helper to update a state's input fence pointer from the property */
  477. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  478. struct sde_plane_state *pstate, uint64_t fd)
  479. {
  480. if (!psde || !pstate) {
  481. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  482. !psde, !pstate);
  483. return;
  484. }
  485. /* clear previous reference */
  486. if (pstate->input_fence)
  487. sde_sync_put(pstate->input_fence);
  488. /* get fence pointer for later */
  489. if (fd == 0)
  490. pstate->input_fence = NULL;
  491. else
  492. pstate->input_fence = sde_sync_get(fd);
  493. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  494. }
  495. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  496. {
  497. struct sde_plane *psde;
  498. struct sde_plane_state *pstate;
  499. uint32_t prefix;
  500. void *input_fence;
  501. int ret = -EINVAL;
  502. signed long rc;
  503. if (!plane) {
  504. SDE_ERROR("invalid plane\n");
  505. } else if (!plane->state) {
  506. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  507. } else {
  508. psde = to_sde_plane(plane);
  509. pstate = to_sde_plane_state(plane->state);
  510. input_fence = pstate->input_fence;
  511. if (input_fence) {
  512. prefix = sde_sync_get_name_prefix(input_fence);
  513. rc = sde_sync_wait(input_fence, wait_ms);
  514. switch (rc) {
  515. case 0:
  516. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
  517. wait_ms, prefix, sde_plane_get_property(pstate,
  518. PLANE_PROP_INPUT_FENCE));
  519. psde->is_error = true;
  520. sde_kms_timeline_status(plane->dev);
  521. ret = -ETIMEDOUT;
  522. break;
  523. case -ERESTARTSYS:
  524. SDE_ERROR_PLANE(psde,
  525. "%ums wait interrupted on %08X\n",
  526. wait_ms, prefix);
  527. psde->is_error = true;
  528. ret = -ERESTARTSYS;
  529. break;
  530. case -EINVAL:
  531. SDE_ERROR_PLANE(psde,
  532. "invalid fence param for %08X\n",
  533. prefix);
  534. psde->is_error = true;
  535. ret = -EINVAL;
  536. break;
  537. case -EBADF:
  538. SDE_INFO("plane%d spec fd signaled on bind failure fd %lld\n",
  539. plane->base.id,
  540. sde_plane_get_property(pstate, PLANE_PROP_INPUT_FENCE));
  541. psde->is_error = true;
  542. ret = 0;
  543. break;
  544. default:
  545. SDE_DEBUG_PLANE(psde, "signaled\n");
  546. ret = 0;
  547. break;
  548. }
  549. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  550. } else {
  551. ret = 0;
  552. }
  553. }
  554. return ret;
  555. }
  556. /**
  557. * _sde_plane_get_aspace: gets the address space based on the
  558. * fb_translation mode property
  559. */
  560. static int _sde_plane_get_aspace(
  561. struct sde_plane *psde,
  562. struct sde_plane_state *pstate,
  563. struct msm_gem_address_space **aspace)
  564. {
  565. struct sde_kms *kms;
  566. int mode;
  567. if (!psde || !pstate || !aspace) {
  568. SDE_ERROR("invalid parameters\n");
  569. return -EINVAL;
  570. }
  571. kms = _sde_plane_get_kms(&psde->base);
  572. if (!kms) {
  573. SDE_ERROR("invalid kms\n");
  574. return -EINVAL;
  575. }
  576. mode = sde_plane_get_property(pstate,
  577. PLANE_PROP_FB_TRANSLATION_MODE);
  578. switch (mode) {
  579. case SDE_DRM_FB_NON_SEC:
  580. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  581. if (!aspace)
  582. return -EINVAL;
  583. break;
  584. case SDE_DRM_FB_SEC:
  585. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  586. if (!aspace)
  587. return -EINVAL;
  588. break;
  589. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  590. case SDE_DRM_FB_SEC_DIR_TRANS:
  591. *aspace = NULL;
  592. break;
  593. default:
  594. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  595. return -EFAULT;
  596. }
  597. return 0;
  598. }
  599. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  600. struct sde_plane_state *pstate,
  601. struct sde_hw_pipe_cfg *pipe_cfg,
  602. struct drm_framebuffer *fb)
  603. {
  604. struct sde_plane *psde;
  605. struct msm_gem_address_space *aspace = NULL;
  606. int ret, mode;
  607. bool secure = false;
  608. if (!plane || !pstate || !pipe_cfg || !fb) {
  609. SDE_ERROR(
  610. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  611. !plane, !pstate, !pipe_cfg, !fb);
  612. return;
  613. }
  614. psde = to_sde_plane(plane);
  615. if (!psde->pipe_hw) {
  616. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  617. return;
  618. }
  619. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  620. if (ret) {
  621. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  622. return;
  623. }
  624. /*
  625. * framebuffer prepare is deferred for prepare_fb calls that
  626. * happen during the transition from secure to non-secure.
  627. * Handle the prepare at this point for such cases. This can be
  628. * expected for one or two frames during the transition.
  629. */
  630. if (aspace && pstate->defer_prepare_fb) {
  631. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  632. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  633. if (ret) {
  634. SDE_ERROR_PLANE(psde,
  635. "failed to prepare framebuffer %d\n", ret);
  636. return;
  637. }
  638. pstate->defer_prepare_fb = false;
  639. }
  640. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  641. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  642. secure = true;
  643. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  644. if (ret == -EAGAIN)
  645. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  646. else if (ret) {
  647. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  648. /*
  649. * Force solid fill color on error. This is to prevent
  650. * smmu faults during secure session transition.
  651. */
  652. psde->is_error = true;
  653. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  654. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  655. pipe_cfg->layout.width,
  656. pipe_cfg->layout.height,
  657. pipe_cfg->layout.plane_addr[0],
  658. pipe_cfg->layout.plane_size[0],
  659. pipe_cfg->layout.plane_addr[1],
  660. pipe_cfg->layout.plane_size[1],
  661. pipe_cfg->layout.plane_addr[2],
  662. pipe_cfg->layout.plane_size[2],
  663. pipe_cfg->layout.plane_addr[3],
  664. pipe_cfg->layout.plane_size[3],
  665. pstate->multirect_index,
  666. secure);
  667. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  668. pstate->multirect_index);
  669. }
  670. }
  671. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  672. struct sde_plane_state *pstate)
  673. {
  674. struct sde_hw_scaler3_cfg *cfg;
  675. int ret = 0;
  676. if (!psde || !pstate) {
  677. SDE_ERROR("invalid args\n");
  678. return -EINVAL;
  679. }
  680. cfg = &psde->scaler3_cfg;
  681. cfg->dir_lut = msm_property_get_blob(
  682. &psde->property_info,
  683. &pstate->property_state, &cfg->dir_len,
  684. PLANE_PROP_SCALER_LUT_ED);
  685. cfg->cir_lut = msm_property_get_blob(
  686. &psde->property_info,
  687. &pstate->property_state, &cfg->cir_len,
  688. PLANE_PROP_SCALER_LUT_CIR);
  689. cfg->sep_lut = msm_property_get_blob(
  690. &psde->property_info,
  691. &pstate->property_state, &cfg->sep_len,
  692. PLANE_PROP_SCALER_LUT_SEP);
  693. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  694. ret = -ENODATA;
  695. return ret;
  696. }
  697. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  698. struct sde_plane_state *pstate)
  699. {
  700. struct sde_hw_scaler3_cfg *cfg;
  701. cfg = &psde->scaler3_cfg;
  702. cfg->sep_lut = msm_property_get_blob(
  703. &psde->property_info,
  704. &pstate->property_state, &cfg->sep_len,
  705. PLANE_PROP_SCALER_LUT_SEP);
  706. return cfg->sep_lut ? 0 : -ENODATA;
  707. }
  708. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  709. struct sde_plane_state *pstate, const struct sde_format *fmt,
  710. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  711. {
  712. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  713. struct sde_hw_scaler3_cfg *scale_cfg;
  714. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  715. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  716. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  717. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  718. chroma_subsmpl_h, chroma_subsmpl_v);
  719. return;
  720. }
  721. scale_cfg = &psde->scaler3_cfg;
  722. src_w = psde->pipe_cfg.src_rect.w;
  723. src_h = psde->pipe_cfg.src_rect.h;
  724. dst_w = psde->pipe_cfg.dst_rect.w;
  725. dst_h = psde->pipe_cfg.dst_rect.h;
  726. memset(scale_cfg, 0, sizeof(*scale_cfg));
  727. memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  728. /*
  729. * For inline rotation cases, scaler config is post-rotation,
  730. * so swap the dimensions here. However, pixel extension will
  731. * need pre-rotation settings, this will be corrected below
  732. * when calculating pixel extension settings.
  733. */
  734. if (inline_rotation)
  735. swap(src_w, src_h);
  736. decimated = DECIMATED_DIMENSION(src_w,
  737. psde->pipe_cfg.horz_decimation);
  738. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  739. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  740. decimated = DECIMATED_DIMENSION(src_h,
  741. psde->pipe_cfg.vert_decimation);
  742. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  743. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  744. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  745. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  746. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  747. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  748. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  749. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  750. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  751. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  752. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  753. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  754. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  755. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  756. for (i = 0; i < SDE_MAX_PLANES; i++) {
  757. /*
  758. * For inline rotation cases with pre-downscaling enabled
  759. * set x pre-downscale value if required. Only x direction
  760. * is currently supported. Use src_h as values have been swapped
  761. * and x direction corresponds to height value.
  762. */
  763. src_h_pre_down = src_h;
  764. if (pre_down_supported && inline_rotation) {
  765. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  766. src_h_pre_down = src_h / 2;
  767. }
  768. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  769. psde->pipe_cfg.horz_decimation);
  770. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  771. psde->pipe_cfg.vert_decimation);
  772. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  773. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  774. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  775. }
  776. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  777. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  778. /* For pixel extension we need the pre-rotated orientation */
  779. if (inline_rotation) {
  780. psde->pixel_ext.num_ext_pxls_top[i] =
  781. scale_cfg->src_width[i];
  782. psde->pixel_ext.num_ext_pxls_left[i] =
  783. scale_cfg->src_height[i];
  784. } else {
  785. psde->pixel_ext.num_ext_pxls_top[i] =
  786. scale_cfg->src_height[i];
  787. psde->pixel_ext.num_ext_pxls_left[i] =
  788. scale_cfg->src_width[i];
  789. }
  790. }
  791. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  792. && (src_w == dst_w) && !inline_rotation) ||
  793. pstate->multirect_mode)
  794. return;
  795. SDE_DEBUG_PLANE(psde,
  796. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  797. src_w, src_h, dst_w, dst_h,
  798. chroma_subsmpl_v, chroma_subsmpl_h,
  799. fmt->base.pixel_format);
  800. scale_cfg->dst_width = dst_w;
  801. scale_cfg->dst_height = dst_h;
  802. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  803. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  804. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  805. scale_cfg->lut_flag = 0;
  806. scale_cfg->blend_cfg = 1;
  807. scale_cfg->enable = 1;
  808. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  809. }
  810. /**
  811. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  812. * @psde: Pointer to SDE plane object
  813. * @src: Source size
  814. * @dst: Destination size
  815. * @phase_steps: Pointer to output array for phase steps
  816. * @filter: Pointer to output array for filter type
  817. * @fmt: Pointer to format definition
  818. * @chroma_subsampling: Subsampling amount for chroma channel
  819. *
  820. * Returns: 0 on success
  821. */
  822. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  823. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  824. enum sde_hw_filter *filter, const struct sde_format *fmt,
  825. uint32_t chroma_subsampling)
  826. {
  827. if (!psde || !phase_steps || !filter || !fmt) {
  828. SDE_ERROR(
  829. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  830. !psde, !phase_steps, !filter, !fmt);
  831. return -EINVAL;
  832. }
  833. /* calculate phase steps, leave init phase as zero */
  834. phase_steps[SDE_SSPP_COMP_0] =
  835. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  836. phase_steps[SDE_SSPP_COMP_1_2] =
  837. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  838. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  839. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  840. /* calculate scaler config, if necessary */
  841. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  842. filter[SDE_SSPP_COMP_3] =
  843. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  844. SDE_SCALE_FILTER_PCMN;
  845. if (SDE_FORMAT_IS_YUV(fmt)) {
  846. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  847. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  848. } else {
  849. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  850. filter[SDE_SSPP_COMP_1_2] =
  851. SDE_SCALE_FILTER_NEAREST;
  852. }
  853. } else {
  854. /* disable scaler */
  855. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  856. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  857. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  858. }
  859. return 0;
  860. }
  861. /**
  862. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  863. * @psde: Pointer to SDE plane object
  864. * @src: Source size
  865. * @dst: Destination size
  866. * @decimated_src: Source size after decimation, if any
  867. * @phase_steps: Pointer to output array for phase steps
  868. * @out_src: Output array for pixel extension values
  869. * @out_edge1: Output array for pixel extension first edge
  870. * @out_edge2: Output array for pixel extension second edge
  871. * @filter: Pointer to array for filter type
  872. * @fmt: Pointer to format definition
  873. * @chroma_subsampling: Subsampling amount for chroma channel
  874. * @post_compare: Whether to chroma subsampled source size for comparisions
  875. */
  876. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  877. uint32_t src, uint32_t dst, uint32_t decimated_src,
  878. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  879. int *out_edge2, enum sde_hw_filter *filter,
  880. const struct sde_format *fmt, uint32_t chroma_subsampling,
  881. bool post_compare)
  882. {
  883. int64_t edge1, edge2, caf;
  884. uint32_t src_work;
  885. int i, tmp;
  886. if (psde && phase_steps && out_src && out_edge1 &&
  887. out_edge2 && filter && fmt) {
  888. /* handle CAF for YUV formats */
  889. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  890. caf = PHASE_STEP_UNIT_SCALE;
  891. else
  892. caf = 0;
  893. for (i = 0; i < SDE_MAX_PLANES; i++) {
  894. src_work = decimated_src;
  895. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  896. src_work /= chroma_subsampling;
  897. if (post_compare)
  898. src = src_work;
  899. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  900. /* unity */
  901. edge1 = 0;
  902. edge2 = 0;
  903. } else if (dst >= src) {
  904. /* upscale */
  905. edge1 = (1 << PHASE_RESIDUAL);
  906. edge1 -= caf;
  907. edge2 = (1 << PHASE_RESIDUAL);
  908. edge2 += (dst - 1) * *(phase_steps + i);
  909. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  910. edge2 += caf;
  911. edge2 = -(edge2);
  912. } else {
  913. /* downscale */
  914. edge1 = 0;
  915. edge2 = (dst - 1) * *(phase_steps + i);
  916. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  917. edge2 += *(phase_steps + i);
  918. edge2 = -(edge2);
  919. }
  920. /* only enable CAF for luma plane */
  921. caf = 0;
  922. /* populate output arrays */
  923. *(out_src + i) = src_work;
  924. /* edge updates taken from __pxl_extn_helper */
  925. if (edge1 >= 0) {
  926. tmp = (uint32_t)edge1;
  927. tmp >>= PHASE_STEP_SHIFT;
  928. *(out_edge1 + i) = -tmp;
  929. } else {
  930. tmp = (uint32_t)(-edge1);
  931. *(out_edge1 + i) =
  932. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  933. PHASE_STEP_SHIFT;
  934. }
  935. if (edge2 >= 0) {
  936. tmp = (uint32_t)edge2;
  937. tmp >>= PHASE_STEP_SHIFT;
  938. *(out_edge2 + i) = -tmp;
  939. } else {
  940. tmp = (uint32_t)(-edge2);
  941. *(out_edge2 + i) =
  942. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  943. PHASE_STEP_SHIFT;
  944. }
  945. }
  946. }
  947. }
  948. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  949. {
  950. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  951. {
  952. /* S15.16 format */
  953. 0x00012A00, 0x00000000, 0x00019880,
  954. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  955. 0x00012A00, 0x00020480, 0x00000000,
  956. },
  957. /* signed bias */
  958. { 0xfff0, 0xff80, 0xff80,},
  959. { 0x0, 0x0, 0x0,},
  960. /* unsigned clamp */
  961. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  962. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  963. };
  964. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  965. {
  966. /* S15.16 format */
  967. 0x00012A00, 0x00000000, 0x00019880,
  968. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  969. 0x00012A00, 0x00020480, 0x00000000,
  970. },
  971. /* signed bias */
  972. { 0xffc0, 0xfe00, 0xfe00,},
  973. { 0x0, 0x0, 0x0,},
  974. /* unsigned clamp */
  975. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  976. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  977. };
  978. if (!psde) {
  979. SDE_ERROR("invalid plane\n");
  980. return;
  981. }
  982. /* revert to kernel default if override not available */
  983. if (psde->csc_usr_ptr)
  984. psde->csc_ptr = psde->csc_usr_ptr;
  985. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  986. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  987. else
  988. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  989. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  990. psde->csc_ptr->csc_mv[0],
  991. psde->csc_ptr->csc_mv[1],
  992. psde->csc_ptr->csc_mv[2]);
  993. }
  994. static void sde_color_process_plane_setup(struct drm_plane *plane)
  995. {
  996. struct sde_plane *psde;
  997. struct sde_plane_state *pstate;
  998. uint32_t hue, saturation, value, contrast;
  999. struct drm_msm_memcol *memcol = NULL;
  1000. struct drm_msm_3d_gamut *vig_gamut = NULL;
  1001. struct drm_msm_igc_lut *igc = NULL;
  1002. struct drm_msm_pgc_lut *gc = NULL;
  1003. size_t memcol_sz = 0, size = 0;
  1004. struct sde_hw_cp_cfg hw_cfg = {};
  1005. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1006. bool fp16_igc, fp16_unmult;
  1007. struct drm_msm_fp16_gc *fp16_gc = NULL;
  1008. struct drm_msm_fp16_csc *fp16_csc = NULL;
  1009. psde = to_sde_plane(plane);
  1010. pstate = to_sde_plane_state(plane->state);
  1011. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1012. if (psde->pipe_hw->ops.setup_pa_hue)
  1013. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1014. saturation = (uint32_t) sde_plane_get_property(pstate,
  1015. PLANE_PROP_SATURATION_ADJUST);
  1016. if (psde->pipe_hw->ops.setup_pa_sat)
  1017. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1018. value = (uint32_t) sde_plane_get_property(pstate,
  1019. PLANE_PROP_VALUE_ADJUST);
  1020. if (psde->pipe_hw->ops.setup_pa_val)
  1021. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1022. contrast = (uint32_t) sde_plane_get_property(pstate,
  1023. PLANE_PROP_CONTRAST_ADJUST);
  1024. if (psde->pipe_hw->ops.setup_pa_cont)
  1025. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1026. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1027. /* Skin memory color setup */
  1028. memcol = msm_property_get_blob(&psde->property_info,
  1029. &pstate->property_state,
  1030. &memcol_sz,
  1031. PLANE_PROP_SKIN_COLOR);
  1032. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1033. MEMCOLOR_SKIN, memcol);
  1034. /* Sky memory color setup */
  1035. memcol = msm_property_get_blob(&psde->property_info,
  1036. &pstate->property_state,
  1037. &memcol_sz,
  1038. PLANE_PROP_SKY_COLOR);
  1039. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1040. MEMCOLOR_SKY, memcol);
  1041. /* Foliage memory color setup */
  1042. memcol = msm_property_get_blob(&psde->property_info,
  1043. &pstate->property_state,
  1044. &memcol_sz,
  1045. PLANE_PROP_FOLIAGE_COLOR);
  1046. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1047. MEMCOLOR_FOLIAGE, memcol);
  1048. }
  1049. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1050. psde->pipe_hw->ops.setup_vig_gamut) {
  1051. vig_gamut = msm_property_get_blob(&psde->property_info,
  1052. &pstate->property_state,
  1053. &size,
  1054. PLANE_PROP_VIG_GAMUT);
  1055. hw_cfg.last_feature = 0;
  1056. hw_cfg.ctl = ctl;
  1057. hw_cfg.len = size;
  1058. hw_cfg.payload = vig_gamut;
  1059. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1060. }
  1061. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1062. psde->pipe_hw->ops.setup_vig_igc) {
  1063. igc = msm_property_get_blob(&psde->property_info,
  1064. &pstate->property_state,
  1065. &size,
  1066. PLANE_PROP_VIG_IGC);
  1067. hw_cfg.last_feature = 0;
  1068. hw_cfg.ctl = ctl;
  1069. hw_cfg.len = size;
  1070. hw_cfg.payload = igc;
  1071. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1072. }
  1073. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1074. psde->pipe_hw->ops.setup_dma_igc) {
  1075. igc = msm_property_get_blob(&psde->property_info,
  1076. &pstate->property_state,
  1077. &size,
  1078. PLANE_PROP_DMA_IGC);
  1079. hw_cfg.last_feature = 0;
  1080. hw_cfg.ctl = ctl;
  1081. hw_cfg.len = size;
  1082. hw_cfg.payload = igc;
  1083. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1084. pstate->multirect_index);
  1085. }
  1086. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1087. psde->pipe_hw->ops.setup_dma_gc) {
  1088. gc = msm_property_get_blob(&psde->property_info,
  1089. &pstate->property_state,
  1090. &size,
  1091. PLANE_PROP_DMA_GC);
  1092. hw_cfg.last_feature = 0;
  1093. hw_cfg.ctl = ctl;
  1094. hw_cfg.len = size;
  1095. hw_cfg.payload = gc;
  1096. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1097. pstate->multirect_index);
  1098. }
  1099. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1100. psde->pipe_hw->ops.setup_fp16_igc) {
  1101. fp16_igc = !!sde_plane_get_property(pstate,
  1102. PLANE_PROP_FP16_IGC);
  1103. hw_cfg.last_feature = 0;
  1104. hw_cfg.ctl = ctl;
  1105. hw_cfg.len = sizeof(bool);
  1106. hw_cfg.payload = &fp16_igc;
  1107. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1108. pstate->multirect_index, &hw_cfg);
  1109. }
  1110. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1111. psde->pipe_hw->ops.setup_fp16_gc) {
  1112. fp16_gc = msm_property_get_blob(&psde->property_info,
  1113. &pstate->property_state,
  1114. &size,
  1115. PLANE_PROP_FP16_GC);
  1116. hw_cfg.last_feature = 0;
  1117. hw_cfg.ctl = ctl;
  1118. hw_cfg.len = size;
  1119. hw_cfg.payload = fp16_gc;
  1120. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1121. pstate->multirect_index, &hw_cfg);
  1122. }
  1123. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1124. psde->pipe_hw->ops.setup_fp16_csc) {
  1125. fp16_csc = msm_property_get_blob(&psde->property_info,
  1126. &pstate->property_state,
  1127. &size,
  1128. PLANE_PROP_FP16_CSC);
  1129. hw_cfg.last_feature = 0;
  1130. hw_cfg.ctl = ctl;
  1131. hw_cfg.len = size;
  1132. hw_cfg.payload = fp16_csc;
  1133. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1134. pstate->multirect_index, &hw_cfg);
  1135. }
  1136. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1137. psde->pipe_hw->ops.setup_fp16_unmult) {
  1138. fp16_unmult = !!sde_plane_get_property(pstate,
  1139. PLANE_PROP_FP16_UNMULT);
  1140. hw_cfg.last_feature = 0;
  1141. hw_cfg.ctl = ctl;
  1142. hw_cfg.len = sizeof(bool);
  1143. hw_cfg.payload = &fp16_unmult;
  1144. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1145. pstate->multirect_index, &hw_cfg);
  1146. }
  1147. }
  1148. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1149. struct sde_plane_state *pstate,
  1150. const struct sde_format *fmt, bool color_fill)
  1151. {
  1152. struct sde_hw_pixel_ext *pe;
  1153. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1154. const struct drm_format_info *info = NULL;
  1155. if (!psde || !fmt || !pstate) {
  1156. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1157. !psde, !fmt, !pstate);
  1158. return;
  1159. }
  1160. memcpy(&psde->scaler3_cfg, &pstate->scaler3_cfg,
  1161. sizeof(psde->scaler3_cfg));
  1162. memcpy(&psde->pixel_ext, &pstate->pixel_ext,
  1163. sizeof(psde->pixel_ext));
  1164. info = drm_format_info(fmt->base.pixel_format);
  1165. pe = &psde->pixel_ext;
  1166. psde->pipe_cfg.horz_decimation =
  1167. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1168. psde->pipe_cfg.vert_decimation =
  1169. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1170. /* don't chroma subsample if decimating */
  1171. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1172. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1173. /* update scaler */
  1174. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1175. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1176. int rc = -EINVAL;
  1177. if (!color_fill && !psde->debugfs_default_scale)
  1178. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1179. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1180. _sde_plane_setup_scaler3_lut(psde, pstate);
  1181. if (rc || pstate->scaler_check_state !=
  1182. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1183. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1184. pstate->scaler_check_state,
  1185. psde->debugfs_default_scale, rc,
  1186. psde->pipe_cfg.src_rect.w,
  1187. psde->pipe_cfg.src_rect.h,
  1188. psde->pipe_cfg.dst_rect.w,
  1189. psde->pipe_cfg.dst_rect.h,
  1190. pstate->multirect_mode);
  1191. /* calculate default config for QSEED3 */
  1192. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1193. chroma_subsmpl_h, chroma_subsmpl_v);
  1194. }
  1195. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1196. color_fill || psde->debugfs_default_scale) {
  1197. uint32_t deci_dim, i;
  1198. /* calculate default configuration for QSEED2 */
  1199. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1200. SDE_DEBUG_PLANE(psde, "default config\n");
  1201. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1202. psde->pipe_cfg.horz_decimation);
  1203. _sde_plane_setup_scaler2(psde,
  1204. deci_dim,
  1205. psde->pipe_cfg.dst_rect.w,
  1206. pe->phase_step_x,
  1207. pe->horz_filter, fmt, chroma_subsmpl_h);
  1208. if (SDE_FORMAT_IS_YUV(fmt))
  1209. deci_dim &= ~0x1;
  1210. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1211. psde->pipe_cfg.dst_rect.w, deci_dim,
  1212. pe->phase_step_x,
  1213. pe->roi_w,
  1214. pe->num_ext_pxls_left,
  1215. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1216. chroma_subsmpl_h, 0);
  1217. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1218. psde->pipe_cfg.vert_decimation);
  1219. _sde_plane_setup_scaler2(psde,
  1220. deci_dim,
  1221. psde->pipe_cfg.dst_rect.h,
  1222. pe->phase_step_y,
  1223. pe->vert_filter, fmt, chroma_subsmpl_v);
  1224. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1225. psde->pipe_cfg.dst_rect.h, deci_dim,
  1226. pe->phase_step_y,
  1227. pe->roi_h,
  1228. pe->num_ext_pxls_top,
  1229. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1230. chroma_subsmpl_v, 1);
  1231. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1232. if (pe->num_ext_pxls_left[i] >= 0)
  1233. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1234. else
  1235. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1236. if (pe->num_ext_pxls_right[i] >= 0)
  1237. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1238. else
  1239. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1240. if (pe->num_ext_pxls_top[i] >= 0)
  1241. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1242. else
  1243. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1244. if (pe->num_ext_pxls_btm[i] >= 0)
  1245. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1246. else
  1247. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1248. }
  1249. }
  1250. if (psde->pipe_hw->ops.setup_pre_downscale)
  1251. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1252. &pstate->pre_down);
  1253. }
  1254. /**
  1255. * _sde_plane_color_fill - enables color fill on plane
  1256. * @psde: Pointer to SDE plane object
  1257. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1258. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1259. * Returns: 0 on success
  1260. */
  1261. static int _sde_plane_color_fill(struct sde_plane *psde,
  1262. uint32_t color, uint32_t alpha)
  1263. {
  1264. const struct sde_format *fmt;
  1265. const struct drm_plane *plane;
  1266. struct sde_plane_state *pstate;
  1267. bool blend_enable = true;
  1268. if (!psde || !psde->base.state) {
  1269. SDE_ERROR("invalid plane\n");
  1270. return -EINVAL;
  1271. }
  1272. if (!psde->pipe_hw) {
  1273. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1274. return -EINVAL;
  1275. }
  1276. plane = &psde->base;
  1277. pstate = to_sde_plane_state(plane->state);
  1278. SDE_DEBUG_PLANE(psde, "\n");
  1279. /*
  1280. * select fill format to match user property expectation,
  1281. * h/w only supports RGB variants
  1282. */
  1283. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1284. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1285. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1286. /* update sspp */
  1287. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1288. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1289. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1290. pstate->multirect_index);
  1291. /* override scaler/decimation if solid fill */
  1292. psde->pipe_cfg.src_rect.x = 0;
  1293. psde->pipe_cfg.src_rect.y = 0;
  1294. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1295. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1296. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1297. if (psde->pipe_hw->ops.setup_format)
  1298. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1299. fmt, blend_enable,
  1300. SDE_SSPP_SOLID_FILL,
  1301. pstate->multirect_index);
  1302. if (psde->pipe_hw->ops.setup_rects)
  1303. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1304. &psde->pipe_cfg,
  1305. pstate->multirect_index);
  1306. if (psde->pipe_hw->ops.setup_pe)
  1307. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1308. &psde->pixel_ext);
  1309. if (psde->pipe_hw->ops.setup_scaler &&
  1310. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1311. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1312. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1313. &psde->pipe_cfg, &psde->pixel_ext,
  1314. &psde->scaler3_cfg);
  1315. }
  1316. }
  1317. return 0;
  1318. }
  1319. /**
  1320. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1321. * @plane: Pointer to drm plane
  1322. * @state: Pointer to drm plane state to be validated
  1323. * return: 0 if success; error code otherwise
  1324. */
  1325. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1326. struct drm_plane_state *state)
  1327. {
  1328. struct sde_plane *psde;
  1329. struct sde_plane_state *pstate, *old_pstate;
  1330. int ret = 0;
  1331. u32 rotation;
  1332. if (!plane || !state) {
  1333. SDE_ERROR("invalid plane/state\n");
  1334. return -EINVAL;
  1335. }
  1336. psde = to_sde_plane(plane);
  1337. pstate = to_sde_plane_state(state);
  1338. old_pstate = to_sde_plane_state(plane->state);
  1339. /* check inline rotation and simplify the transform */
  1340. rotation = drm_rotation_simplify(
  1341. state->rotation,
  1342. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1343. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1344. if ((rotation & DRM_MODE_ROTATE_180) ||
  1345. (rotation & DRM_MODE_ROTATE_270)) {
  1346. SDE_ERROR_PLANE(psde,
  1347. "invalid rotation transform must be simplified 0x%x\n",
  1348. rotation);
  1349. ret = -EINVAL;
  1350. goto exit;
  1351. }
  1352. if (rotation & DRM_MODE_ROTATE_90) {
  1353. struct msm_drm_private *priv = plane->dev->dev_private;
  1354. struct sde_kms *sde_kms;
  1355. const struct msm_format *msm_fmt;
  1356. const struct sde_format *fmt;
  1357. struct sde_rect src;
  1358. bool q16_data = true;
  1359. POPULATE_RECT(&src, state->src_x, state->src_y,
  1360. state->src_w, state->src_h, q16_data);
  1361. /*
  1362. * DRM framework expects rotation flag in counter-clockwise
  1363. * direction and the HW expects in clockwise direction.
  1364. * Flip the flags to match with HW.
  1365. */
  1366. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1367. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1368. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1369. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1370. !psde->pipe_sblk->in_rot_maxheight ||
  1371. !psde->pipe_sblk->in_rot_format_list ||
  1372. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1373. SDE_ERROR_PLANE(psde,
  1374. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1375. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1376. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1377. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1378. !psde->pipe_sblk->in_rot_format_list,
  1379. !psde->pipe_sblk->in_rot_maxheight,
  1380. psde->features);
  1381. ret = -EINVAL;
  1382. goto exit;
  1383. }
  1384. /* check for valid height */
  1385. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1386. SDE_ERROR_PLANE(psde,
  1387. "invalid height for inline rot:%d max:%d\n",
  1388. src.h, psde->pipe_sblk->in_rot_maxheight);
  1389. ret = -EINVAL;
  1390. goto exit;
  1391. }
  1392. if (!sde_plane_enabled(state))
  1393. goto exit;
  1394. /* check for valid formats supported by inline rot */
  1395. sde_kms = to_sde_kms(priv->kms);
  1396. msm_fmt = msm_framebuffer_format(state->fb);
  1397. fmt = to_sde_format(msm_fmt);
  1398. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1399. psde->pipe_sblk->in_rot_format_list);
  1400. }
  1401. exit:
  1402. pstate->rotation = rotation;
  1403. return ret;
  1404. }
  1405. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1406. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1407. {
  1408. struct sde_plane *psde;
  1409. struct msm_drm_private *priv;
  1410. struct sde_vbif_set_xin_halt_params halt_params;
  1411. if (!plane || !plane->dev) {
  1412. SDE_ERROR("invalid arguments\n");
  1413. return false;
  1414. }
  1415. psde = to_sde_plane(plane);
  1416. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1417. SDE_ERROR("invalid pipe reference\n");
  1418. return false;
  1419. }
  1420. priv = plane->dev->dev_private;
  1421. if (!priv || !priv->kms) {
  1422. SDE_ERROR("invalid KMS reference\n");
  1423. return false;
  1424. }
  1425. memset(&halt_params, 0, sizeof(halt_params));
  1426. halt_params.vbif_idx = VBIF_RT;
  1427. halt_params.xin_id = xin_id;
  1428. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1429. halt_params.forced_on = halt_forced_clk;
  1430. halt_params.enable = enable;
  1431. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1432. }
  1433. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1434. {
  1435. struct sde_plane *psde;
  1436. if (!plane) {
  1437. SDE_ERROR("invalid plane\n");
  1438. return;
  1439. }
  1440. psde = to_sde_plane(plane);
  1441. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1442. SDE_ERROR("invalid pipe reference\n");
  1443. return;
  1444. }
  1445. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1446. psde->xin_halt_forced_clk =
  1447. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1448. psde->xin_halt_forced_clk, enable);
  1449. }
  1450. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1451. struct drm_crtc *crtc)
  1452. {
  1453. struct sde_plane *psde;
  1454. if (!plane || !crtc) {
  1455. SDE_ERROR("invalid plane/crtc\n");
  1456. return;
  1457. }
  1458. psde = to_sde_plane(plane);
  1459. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1460. return;
  1461. /* do all VBIF programming for the sec-ui allowed SSPP */
  1462. _sde_plane_set_qos_remap(plane);
  1463. _sde_plane_set_ot_limit(plane, crtc);
  1464. }
  1465. /**
  1466. * sde_plane_rot_install_properties - install plane rotator properties
  1467. * @plane: Pointer to drm plane
  1468. * @catalog: Pointer to mdss configuration
  1469. * return: none
  1470. */
  1471. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1472. struct sde_mdss_cfg *catalog)
  1473. {
  1474. struct sde_plane *psde = to_sde_plane(plane);
  1475. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1476. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1477. int ret = 0;
  1478. if (!plane || !psde) {
  1479. SDE_ERROR("invalid plane\n");
  1480. return;
  1481. } else if (!catalog) {
  1482. SDE_ERROR("invalid catalog\n");
  1483. return;
  1484. }
  1485. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1486. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1487. ret = drm_plane_create_rotation_property(plane,
  1488. DRM_MODE_ROTATE_0, supported_rotations);
  1489. if (ret) {
  1490. DRM_ERROR("create rotation property failed: %d\n", ret);
  1491. return;
  1492. }
  1493. }
  1494. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1495. {
  1496. struct sde_plane_state *pstate;
  1497. if (!drm_state)
  1498. return;
  1499. pstate = to_sde_plane_state(drm_state);
  1500. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1501. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1502. }
  1503. /**
  1504. * multi_rect validate API allows to validate only R0 and R1 RECT
  1505. * passing for each plane. Client of this API must not pass multiple
  1506. * plane which are not sharing same XIN client. Such calls will fail
  1507. * even though kernel client is passing valid multirect configuration.
  1508. */
  1509. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1510. {
  1511. struct sde_plane_state *pstate[R_MAX];
  1512. const struct drm_plane_state *drm_state[R_MAX];
  1513. struct sde_rect src[R_MAX], dst[R_MAX];
  1514. struct sde_plane *sde_plane[R_MAX];
  1515. const struct sde_format *fmt[R_MAX];
  1516. int xin_id[R_MAX];
  1517. bool q16_data = true;
  1518. int i, j, buffer_lines, width_threshold[R_MAX];
  1519. unsigned int max_tile_height = 1;
  1520. bool parallel_fetch_qualified = true;
  1521. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1522. const struct msm_format *msm_fmt;
  1523. bool const_alpha_enable = true;
  1524. for (i = 0; i < R_MAX; i++) {
  1525. drm_state[i] = i ? plane->r1 : plane->r0;
  1526. if (!drm_state[i]) {
  1527. SDE_ERROR("drm plane state is NULL\n");
  1528. return -EINVAL;
  1529. }
  1530. pstate[i] = to_sde_plane_state(drm_state[i]);
  1531. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1532. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1533. for (j = 0; j < i; j++) {
  1534. if (xin_id[i] != xin_id[j]) {
  1535. SDE_ERROR_PLANE(sde_plane[i],
  1536. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1537. j, xin_id[j], i, xin_id[i]);
  1538. return -EINVAL;
  1539. }
  1540. }
  1541. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1542. if (!msm_fmt) {
  1543. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1544. return -EINVAL;
  1545. }
  1546. fmt[i] = to_sde_format(msm_fmt);
  1547. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1548. (fmt[i]->tile_height > max_tile_height))
  1549. max_tile_height = fmt[i]->tile_height;
  1550. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1551. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1552. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1553. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1554. drm_state[i]->crtc_h, !q16_data);
  1555. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1556. SDE_ERROR_PLANE(sde_plane[i],
  1557. "scaling is not supported in multirect mode\n");
  1558. return -EINVAL;
  1559. }
  1560. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1561. SDE_ERROR_PLANE(sde_plane[i],
  1562. "inline rotation is not supported in mulirect mode\n");
  1563. return -EINVAL;
  1564. }
  1565. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1566. SDE_ERROR_PLANE(sde_plane[i],
  1567. "Unsupported format for multirect mode\n");
  1568. return -EINVAL;
  1569. }
  1570. /**
  1571. * SSPP PD_MEM is split half - one for each RECT.
  1572. * Tiled formats need 5 lines of buffering while fetching
  1573. * whereas linear formats need only 2 lines.
  1574. * So we cannot support more than half of the supported SSPP
  1575. * width for tiled formats.
  1576. */
  1577. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1578. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1579. width_threshold[i] /= 2;
  1580. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1581. parallel_fetch_qualified = false;
  1582. if (sde_plane[i]->is_virtual)
  1583. mode = sde_plane_get_property(pstate[i],
  1584. PLANE_PROP_MULTIRECT_MODE);
  1585. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1586. const_alpha_enable = false;
  1587. }
  1588. buffer_lines = 2 * max_tile_height;
  1589. /**
  1590. * fallback to driver mode selection logic if client is using
  1591. * multirect plane without setting property.
  1592. *
  1593. * validate multirect mode configuration based on rectangle
  1594. */
  1595. switch (mode) {
  1596. case SDE_SSPP_MULTIRECT_NONE:
  1597. if (parallel_fetch_qualified)
  1598. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1599. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1600. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1601. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1602. else
  1603. SDE_ERROR(
  1604. "planes(%d - %d) multirect mode selection fail\n",
  1605. drm_state[R0]->plane->base.id,
  1606. drm_state[R1]->plane->base.id);
  1607. break;
  1608. case SDE_SSPP_MULTIRECT_PARALLEL:
  1609. if (!parallel_fetch_qualified) {
  1610. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1611. drm_state[R0]->plane->base.id,
  1612. width_threshold[R0], src[R0].w);
  1613. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1614. drm_state[R1]->plane->base.id,
  1615. width_threshold[R1], src[R1].w);
  1616. SDE_ERROR("parallel fetch not qualified\n");
  1617. mode = SDE_SSPP_MULTIRECT_NONE;
  1618. }
  1619. break;
  1620. case SDE_SSPP_MULTIRECT_TIME_MX:
  1621. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1622. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1623. SDE_ERROR(
  1624. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1625. buffer_lines, drm_state[R0]->plane->base.id,
  1626. dst[R0].y, dst[R0].h);
  1627. SDE_ERROR(
  1628. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1629. buffer_lines, drm_state[R1]->plane->base.id,
  1630. dst[R1].y, dst[R1].h);
  1631. SDE_ERROR("time multiplexed fetch not qualified\n");
  1632. mode = SDE_SSPP_MULTIRECT_NONE;
  1633. }
  1634. break;
  1635. default:
  1636. SDE_ERROR("bad mode:%d selection\n", mode);
  1637. mode = SDE_SSPP_MULTIRECT_NONE;
  1638. break;
  1639. }
  1640. for (i = 0; i < R_MAX; i++) {
  1641. pstate[i]->multirect_mode = mode;
  1642. pstate[i]->const_alpha_en = const_alpha_enable;
  1643. }
  1644. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1645. return -EINVAL;
  1646. if (sde_plane[R0]->is_virtual) {
  1647. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1648. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1649. } else {
  1650. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1651. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1652. }
  1653. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1654. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1655. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1656. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1657. return 0;
  1658. }
  1659. /**
  1660. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1661. * @plane: Pointer to drm plane structure
  1662. * @ctl: Pointer to hardware control driver
  1663. * @set: set if true else clear
  1664. */
  1665. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1666. bool set)
  1667. {
  1668. if (!plane || !ctl) {
  1669. SDE_ERROR("invalid parameters\n");
  1670. return;
  1671. }
  1672. if (!ctl->ops.update_bitmask_sspp) {
  1673. SDE_ERROR("invalid ops\n");
  1674. return;
  1675. }
  1676. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1677. }
  1678. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1679. struct drm_plane_state *new_state)
  1680. {
  1681. struct drm_framebuffer *fb = new_state->fb;
  1682. struct sde_plane *psde = to_sde_plane(plane);
  1683. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1684. struct sde_hw_fmt_layout layout;
  1685. struct msm_gem_address_space *aspace;
  1686. int ret;
  1687. if (!fb)
  1688. return 0;
  1689. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1690. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1691. if (ret) {
  1692. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1693. return ret;
  1694. }
  1695. /* cache aspace */
  1696. pstate->aspace = aspace;
  1697. /*
  1698. * when transitioning from secure to non-secure,
  1699. * plane->prepare_fb happens before the commit. In such case,
  1700. * defer the prepare_fb and handled it late, during the commit
  1701. * after attaching the domains as part of the transition
  1702. */
  1703. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1704. true : false;
  1705. if (pstate->defer_prepare_fb) {
  1706. SDE_EVT32(DRMID(plane), psde->pipe);
  1707. SDE_DEBUG_PLANE(psde,
  1708. "domain not attached, prepare_fb handled later\n");
  1709. return 0;
  1710. }
  1711. if (pstate->aspace && fb) {
  1712. ret = msm_framebuffer_prepare(fb,
  1713. pstate->aspace);
  1714. if (ret) {
  1715. SDE_ERROR("failed to prepare framebuffer\n");
  1716. return ret;
  1717. }
  1718. }
  1719. /* validate framebuffer layout before commit */
  1720. ret = sde_format_populate_layout(pstate->aspace,
  1721. fb, &layout);
  1722. if (ret) {
  1723. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1724. return ret;
  1725. }
  1726. return 0;
  1727. }
  1728. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1729. struct drm_plane_state *old_state)
  1730. {
  1731. struct sde_plane *psde = to_sde_plane(plane);
  1732. struct sde_plane_state *old_pstate;
  1733. if (!old_state || !old_state->fb || !plane)
  1734. return;
  1735. old_pstate = to_sde_plane_state(old_state);
  1736. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1737. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1738. }
  1739. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1740. struct drm_plane_state *state,
  1741. struct drm_plane_state *old_state)
  1742. {
  1743. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1744. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1745. struct drm_framebuffer *fb, *old_fb;
  1746. /* no need to check it again */
  1747. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1748. return;
  1749. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1750. || psde->is_error) {
  1751. SDE_DEBUG_PLANE(psde,
  1752. "enabling/disabling full modeset required\n");
  1753. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1754. } else if (to_sde_plane_state(old_state)->pending) {
  1755. SDE_DEBUG_PLANE(psde, "still pending\n");
  1756. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1757. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1758. pstate->multirect_mode != old_pstate->multirect_mode) {
  1759. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1760. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1761. } else if (state->src_w != old_state->src_w ||
  1762. state->src_h != old_state->src_h ||
  1763. state->src_x != old_state->src_x ||
  1764. state->src_y != old_state->src_y) {
  1765. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1766. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1767. } else if (state->crtc_w != old_state->crtc_w ||
  1768. state->crtc_h != old_state->crtc_h ||
  1769. state->crtc_x != old_state->crtc_x ||
  1770. state->crtc_y != old_state->crtc_y) {
  1771. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1772. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1773. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1774. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1775. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1776. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1777. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1778. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1779. } else if (pstate->rotation != old_pstate->rotation) {
  1780. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1781. pstate->rotation, old_pstate->rotation);
  1782. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1783. }
  1784. fb = state->fb;
  1785. old_fb = old_state->fb;
  1786. if (!fb || !old_fb) {
  1787. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1788. } else if ((fb->format->format != old_fb->format->format) ||
  1789. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1790. SDE_DEBUG_PLANE(psde, "format change\n");
  1791. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1792. } else {
  1793. uint64_t new_mod = fb->modifier;
  1794. uint64_t old_mod = old_fb->modifier;
  1795. uint32_t *new_pitches = fb->pitches;
  1796. uint32_t *old_pitches = old_fb->pitches;
  1797. uint32_t *new_offset = fb->offsets;
  1798. uint32_t *old_offset = old_fb->offsets;
  1799. int i;
  1800. if (new_mod != old_mod) {
  1801. SDE_DEBUG_PLANE(psde,
  1802. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1803. new_mod, old_mod);
  1804. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1805. SDE_PLANE_DIRTY_RECTS;
  1806. }
  1807. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1808. if (new_pitches[i] != old_pitches[i]) {
  1809. SDE_DEBUG_PLANE(psde,
  1810. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1811. i, old_pitches[i], new_pitches[i]);
  1812. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1813. break;
  1814. }
  1815. }
  1816. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1817. if (new_offset[i] != old_offset[i]) {
  1818. SDE_DEBUG_PLANE(psde,
  1819. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1820. i, old_offset[i], new_offset[i]);
  1821. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1822. SDE_PLANE_DIRTY_RECTS;
  1823. break;
  1824. }
  1825. }
  1826. }
  1827. }
  1828. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1829. unsigned long base_addr, u32 size)
  1830. {
  1831. int ret = -EINVAL;
  1832. u32 addr;
  1833. struct sde_plane *psde = to_sde_plane(plane);
  1834. if (!psde || !base_addr || !size) {
  1835. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1836. return ret;
  1837. }
  1838. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1839. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1840. is_sde_plane_virtual(plane));
  1841. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1842. ret = 0;
  1843. }
  1844. return ret;
  1845. }
  1846. static inline bool _sde_plane_is_pre_downscale_enabled(
  1847. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1848. {
  1849. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1850. }
  1851. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1852. struct sde_plane_state *pstate,
  1853. const struct sde_format *fmt,
  1854. uint32_t img_w, uint32_t img_h,
  1855. uint32_t src_w, uint32_t src_h,
  1856. uint32_t deci_w, uint32_t deci_h)
  1857. {
  1858. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1859. bool pre_down_en;
  1860. int i;
  1861. if (!psde || !pstate || !fmt) {
  1862. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1863. return -EINVAL;
  1864. }
  1865. if (psde->debugfs_default_scale ||
  1866. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1867. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1868. return 0;
  1869. pd_cfg = &pstate->pre_down;
  1870. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1871. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1872. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1873. uint32_t hor_req_pixels, hor_fetch_pixels;
  1874. uint32_t vert_req_pixels, vert_fetch_pixels;
  1875. uint32_t src_w_tmp, src_h_tmp;
  1876. uint32_t scaler_w, scaler_h;
  1877. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1878. bool rot;
  1879. /* re-use color plane 1's config for plane 2 */
  1880. if (i == 2)
  1881. continue;
  1882. if (pre_down_en) {
  1883. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1884. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1885. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1886. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1887. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1888. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1889. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1890. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1891. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1892. i, pre_down_ratio_x, pre_down_ratio_y);
  1893. }
  1894. src_w_tmp = src_w;
  1895. src_h_tmp = src_h;
  1896. /*
  1897. * For chroma plane, width is half for the following sub sampled
  1898. * formats. Except in case of decimation, where hardware avoids
  1899. * 1 line of decimation instead of downsampling.
  1900. */
  1901. if (i == 1) {
  1902. if (!deci_w &&
  1903. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1904. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1905. src_w_tmp >>= 1;
  1906. if (!deci_h &&
  1907. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1908. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1909. src_h_tmp >>= 1;
  1910. }
  1911. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1912. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1913. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1914. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1915. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1916. deci_w);
  1917. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1918. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1919. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1920. deci_h);
  1921. if ((hor_req_pixels != hor_fetch_pixels) ||
  1922. (hor_fetch_pixels > img_w) ||
  1923. (vert_req_pixels != vert_fetch_pixels) ||
  1924. (vert_fetch_pixels > img_h)) {
  1925. SDE_ERROR_PLANE(psde,
  1926. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1927. hor_req_pixels, vert_req_pixels,
  1928. hor_fetch_pixels, vert_fetch_pixels,
  1929. img_w, img_h);
  1930. return -EINVAL;
  1931. }
  1932. /*
  1933. * swap the scaler src width & height for inline-rotation 90
  1934. * comparison with Pixel-Extension, as PE is based on
  1935. * pre-rotation and QSEED is based on post-rotation
  1936. */
  1937. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1938. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1939. : pstate->scaler3_cfg.src_width[i];
  1940. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1941. : pstate->scaler3_cfg.src_height[i];
  1942. /*
  1943. * Alpha plane can only be scaled using bilinear or pixel
  1944. * repeat/drop, src_width and src_height are only specified
  1945. * for Y and UV plane
  1946. */
  1947. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1948. vert_req_pixels / pre_down_ratio_y !=
  1949. scaler_h)) {
  1950. SDE_ERROR_PLANE(psde,
  1951. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1952. i, pstate->pixel_ext.roi_w[i],
  1953. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1954. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1955. return -EINVAL;
  1956. }
  1957. /*
  1958. * SSPP fetch , unpack output and QSEED3 input lines need
  1959. * to match for Y plane
  1960. */
  1961. if (i == 0 &&
  1962. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1963. BIT(SDE_DRM_DEINTERLACE)) &&
  1964. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1965. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1966. SDE_ERROR_PLANE(psde,
  1967. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1968. i, pstate->pixel_ext.roi_w[i],
  1969. pstate->pixel_ext.roi_h[i],
  1970. pstate->scaler3_cfg.src_width[i],
  1971. pstate->scaler3_cfg.src_height[i],
  1972. src_w, src_h);
  1973. return -EINVAL;
  1974. }
  1975. }
  1976. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1977. return 0;
  1978. }
  1979. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1980. {
  1981. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1982. }
  1983. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1984. struct sde_plane_state *pstate, struct sde_rect *dst,
  1985. u32 src_w, u32 src_h)
  1986. {
  1987. int ret = 0;
  1988. u32 min_ratio_numer, min_ratio_denom;
  1989. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1990. bool pd_x;
  1991. bool pd_y;
  1992. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1993. return ret;
  1994. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1995. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1996. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  1997. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  1998. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  1999. SDE_ERROR_PLANE(psde,
  2000. "hw does not support pre-downscale X: 0x%x\n",
  2001. psde->features);
  2002. ret = -EINVAL;
  2003. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  2004. SDE_ERROR_PLANE(psde,
  2005. "hw does not support pre-downscale Y: 0x%x\n",
  2006. psde->features);
  2007. ret = -EINVAL;
  2008. } else if (!min_ratio_numer || !min_ratio_denom) {
  2009. SDE_ERROR_PLANE(psde,
  2010. "min downscale ratio not set! %u / %u\n",
  2011. min_ratio_numer, min_ratio_denom);
  2012. ret = -EINVAL;
  2013. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2014. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2015. min_ratio_denom))) {
  2016. SDE_ERROR_PLANE(psde,
  2017. "failed min downscale-x check %u->%u, %u/%u\n",
  2018. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2019. ret = -EINVAL;
  2020. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2021. min_ratio_denom))) {
  2022. SDE_ERROR_PLANE(psde,
  2023. "failed min downscale-y check %u->%u, %u/%u\n",
  2024. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2025. ret = -EINVAL;
  2026. }
  2027. return ret;
  2028. }
  2029. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2030. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2031. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2032. u32 *max_numer_h, u32 *max_denom_h)
  2033. {
  2034. bool rotated, has_predown, default_scale;
  2035. const struct sde_sspp_sub_blks *sblk;
  2036. struct sde_hw_inline_pre_downscale_cfg *pd = NULL;
  2037. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2038. sblk = psde->pipe_sblk;
  2039. *max_numer_w = sblk->maxdwnscale;
  2040. *max_denom_w = 1;
  2041. *max_numer_h = sblk->maxdwnscale;
  2042. *max_denom_h = 1;
  2043. has_predown = _sde_plane_has_pre_downscale(psde);
  2044. if (has_predown)
  2045. pd = &pstate->pre_down;
  2046. default_scale = psde->debugfs_default_scale ||
  2047. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2048. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2049. /**
  2050. * Inline rotation has different max vertical downscaling limits since
  2051. * the source-width becomes the scaler's pre-downscaled source-height.
  2052. **/
  2053. if (rotated) {
  2054. if (pd != NULL && rt_client && has_predown) {
  2055. if (default_scale)
  2056. pd->pre_downscale_x_0 = (src_h >
  2057. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2058. *max_numer_h = pd->pre_downscale_x_0 ?
  2059. sblk->in_rot_maxdwnscale_rt_num :
  2060. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2061. *max_denom_h = pd->pre_downscale_x_0 ?
  2062. sblk->in_rot_maxdwnscale_rt_denom :
  2063. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2064. } else if (rt_client) {
  2065. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2066. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2067. } else {
  2068. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2069. }
  2070. }
  2071. }
  2072. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2073. struct sde_plane *psde, const struct sde_format *fmt,
  2074. struct sde_plane_state *pstate, struct sde_rect *src,
  2075. struct sde_rect *dst, u32 width, u32 height)
  2076. {
  2077. int ret = 0;
  2078. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2079. uint32_t scaler_src_w, scaler_src_h;
  2080. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2081. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2082. uint32_t max_upscale, max_linewidth;
  2083. bool inline_rotation, rt_client;
  2084. struct drm_crtc *crtc;
  2085. struct drm_crtc_state *new_cstate;
  2086. const struct sde_sspp_sub_blks *sblk;
  2087. if (!state || !state->state || !state->crtc) {
  2088. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2089. return -EINVAL;
  2090. }
  2091. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2092. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2093. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2094. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2095. /* with inline rotator, the source of the scaler is post-rotated */
  2096. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2097. if (inline_rotation) {
  2098. scaler_src_w = src_deci_h;
  2099. scaler_src_h = src_deci_w;
  2100. } else {
  2101. scaler_src_w = src_deci_w;
  2102. scaler_src_h = src_deci_h;
  2103. }
  2104. sblk = psde->pipe_sblk;
  2105. max_upscale = sblk->maxupscale;
  2106. if (inline_rotation)
  2107. max_linewidth = sblk->in_rot_maxheight;
  2108. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2109. max_linewidth = sblk->scaling_linewidth;
  2110. else
  2111. max_linewidth = sblk->maxlinewidth;
  2112. crtc = state->crtc;
  2113. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2114. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2115. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2116. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2117. &max_downscale_num_h, &max_downscale_denom_h);
  2118. /* decimation validation */
  2119. if ((deci_w || deci_h)
  2120. && ((deci_w > sblk->maxhdeciexp)
  2121. || (deci_h > sblk->maxvdeciexp))) {
  2122. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2123. ret = -EINVAL;
  2124. } else if ((deci_w || deci_h)
  2125. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2126. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2127. ret = -EINVAL;
  2128. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2129. ((src->w != dst->w) || (src->h != dst->h))) {
  2130. SDE_ERROR_PLANE(psde,
  2131. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2132. src->w, src->h, dst->w, dst->h);
  2133. ret = -EINVAL;
  2134. /* check scaler source width */
  2135. } else if (scaler_src_w > max_linewidth) {
  2136. SDE_ERROR_PLANE(psde,
  2137. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2138. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2139. ret = -E2BIG;
  2140. /* check max scaler capability */
  2141. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2142. ((scaler_src_h * max_upscale) < dst->h) ||
  2143. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2144. < scaler_src_w) ||
  2145. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2146. < scaler_src_h)) {
  2147. SDE_ERROR_PLANE(psde,
  2148. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2149. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2150. inline_rotation, max_downscale_num_w,
  2151. max_downscale_denom_w, max_downscale_num_h,
  2152. max_downscale_denom_h);
  2153. ret = -E2BIG;
  2154. /* check inline pre-downscale support */
  2155. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2156. pstate, dst, src_deci_w, src_deci_h)) {
  2157. ret = -EINVAL;
  2158. /* QSEED validation */
  2159. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2160. width, height, src->w, src->h,
  2161. deci_w, deci_h)) {
  2162. ret = -EINVAL;
  2163. }
  2164. return ret;
  2165. }
  2166. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2167. struct sde_plane_state *pstate, struct sde_rect *src,
  2168. const struct sde_format *fmt, int ret)
  2169. {
  2170. /* check excl rect configs */
  2171. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2172. struct sde_rect intersect;
  2173. /*
  2174. * Check exclusion rect against src rect.
  2175. * it must intersect with source rect.
  2176. */
  2177. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2178. if (intersect.w != pstate->excl_rect.w ||
  2179. intersect.h != pstate->excl_rect.h ||
  2180. SDE_FORMAT_IS_YUV(fmt)) {
  2181. SDE_ERROR_PLANE(psde,
  2182. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2183. pstate->excl_rect.x, pstate->excl_rect.y,
  2184. pstate->excl_rect.w, pstate->excl_rect.h,
  2185. src->x, src->y, src->w, src->h,
  2186. (char *)&fmt->base.pixel_format);
  2187. ret = -EINVAL;
  2188. }
  2189. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2190. pstate->excl_rect.x, pstate->excl_rect.y,
  2191. pstate->excl_rect.w, pstate->excl_rect.h);
  2192. }
  2193. return ret;
  2194. }
  2195. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2196. struct drm_plane_state *state)
  2197. {
  2198. struct sde_kms *sde_kms;
  2199. struct sde_splash_display *splash_display;
  2200. int i;
  2201. sde_kms = _sde_plane_get_kms(&psde->base);
  2202. if (!sde_kms || !state->crtc)
  2203. return 0;
  2204. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2205. splash_display = &sde_kms->splash_data.splash_display[i];
  2206. if (splash_display && splash_display->cont_splash_enabled &&
  2207. splash_display->encoder &&
  2208. state->crtc != splash_display->encoder->crtc) {
  2209. struct sde_sspp_index_info *pipe_info = &splash_display->pipe_info;
  2210. if (test_bit(psde->pipe, pipe_info->pipes) ||
  2211. test_bit(psde->pipe, pipe_info->virt_pipes)) {
  2212. SDE_ERROR_PLANE(psde, "pipe:%d used in cont-splash on crtc:%d\n",
  2213. psde->pipe,
  2214. splash_display->encoder->crtc->base.id);
  2215. return -EINVAL;
  2216. }
  2217. }
  2218. }
  2219. return 0;
  2220. }
  2221. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2222. const struct sde_format *fmt,
  2223. struct sde_rect src, struct sde_rect dst,
  2224. u32 width, u32 height)
  2225. {
  2226. int ret = 0;
  2227. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2228. if (SDE_FORMAT_IS_YUV(fmt) &&
  2229. (!(psde->features & SDE_SSPP_SCALER) ||
  2230. !(psde->features & (BIT(SDE_SSPP_CSC)
  2231. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2232. SDE_ERROR_PLANE(psde,
  2233. "plane doesn't have scaler/csc for yuv\n");
  2234. ret = -EINVAL;
  2235. /* check src bounds */
  2236. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2237. src.w < min_src_size || src.h < min_src_size ||
  2238. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2239. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2240. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2241. src.x, src.y, src.w, src.h);
  2242. ret = -E2BIG;
  2243. /* valid yuv image */
  2244. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2245. (src.w & 0x1) || (src.h & 0x1))) {
  2246. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2247. src.x, src.y, src.w, src.h);
  2248. ret = -EINVAL;
  2249. /* min dst support */
  2250. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2251. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2252. dst.x, dst.y, dst.w, dst.h);
  2253. ret = -EINVAL;
  2254. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2255. !psde->catalog->ubwc_rev) {
  2256. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2257. ret = -EINVAL;
  2258. }
  2259. return ret;
  2260. }
  2261. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2262. struct drm_plane_state *state)
  2263. {
  2264. int ret = 0;
  2265. struct sde_plane *psde;
  2266. struct sde_plane_state *pstate;
  2267. const struct msm_format *msm_fmt;
  2268. const struct sde_format *fmt;
  2269. struct sde_rect src, dst;
  2270. bool q16_data = true;
  2271. struct drm_framebuffer *fb;
  2272. u32 width;
  2273. u32 height;
  2274. psde = to_sde_plane(plane);
  2275. pstate = to_sde_plane_state(state);
  2276. if (!psde->pipe_sblk) {
  2277. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2278. return -EINVAL;
  2279. }
  2280. /* src values are in Q16 fixed point, convert to integer */
  2281. POPULATE_RECT(&src, state->src_x, state->src_y,
  2282. state->src_w, state->src_h, q16_data);
  2283. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2284. state->crtc_h, !q16_data);
  2285. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2286. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2287. if (!sde_plane_enabled(state))
  2288. goto modeset_update;
  2289. fb = state->fb;
  2290. width = fb ? state->fb->width : 0x0;
  2291. height = fb ? state->fb->height : 0x0;
  2292. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2293. plane->base.id,
  2294. pstate->rotation,
  2295. width, height,
  2296. fb ? (char *) &state->fb->format->format : 0x0,
  2297. fb ? state->fb->modifier : 0x0);
  2298. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2299. state->src_w >> 16, state->src_h >> 16,
  2300. state->src_x >> 16, state->src_y >> 16,
  2301. state->crtc_w, state->crtc_h,
  2302. state->crtc_x, state->crtc_y);
  2303. msm_fmt = msm_framebuffer_format(fb);
  2304. fmt = to_sde_format(msm_fmt);
  2305. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2306. height);
  2307. if (ret)
  2308. return ret;
  2309. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2310. &src, &dst, width, height);
  2311. if (ret)
  2312. return ret;
  2313. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2314. &src, fmt, ret);
  2315. if (ret)
  2316. return ret;
  2317. ret = _sde_plane_validate_shared_crtc(psde, state);
  2318. if (ret)
  2319. return ret;
  2320. pstate->const_alpha_en = fmt->alpha_enable &&
  2321. (SDE_DRM_BLEND_OP_OPAQUE !=
  2322. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2323. (pstate->stage != SDE_STAGE_0);
  2324. modeset_update:
  2325. if (!ret)
  2326. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2327. state, plane->state);
  2328. return ret;
  2329. }
  2330. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2331. static int sde_plane_atomic_check(struct drm_plane *plane,
  2332. struct drm_atomic_state *atomic_state)
  2333. #else
  2334. static int sde_plane_atomic_check(struct drm_plane *plane,
  2335. struct drm_plane_state *state)
  2336. #endif
  2337. {
  2338. int ret = 0;
  2339. struct sde_plane *psde;
  2340. struct sde_plane_state *pstate;
  2341. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2342. struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, plane);
  2343. #endif
  2344. if (!plane || !state) {
  2345. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2346. !plane, !state);
  2347. ret = -EINVAL;
  2348. goto exit;
  2349. }
  2350. psde = to_sde_plane(plane);
  2351. pstate = to_sde_plane_state(state);
  2352. SDE_DEBUG_PLANE(psde, "\n");
  2353. ret = sde_plane_rot_atomic_check(plane, state);
  2354. if (ret)
  2355. goto exit;
  2356. ret = sde_plane_sspp_atomic_check(plane, state);
  2357. exit:
  2358. return ret;
  2359. }
  2360. void sde_plane_flush(struct drm_plane *plane)
  2361. {
  2362. struct sde_plane *psde;
  2363. struct sde_plane_state *pstate;
  2364. if (!plane || !plane->state) {
  2365. SDE_ERROR("invalid plane\n");
  2366. return;
  2367. }
  2368. psde = to_sde_plane(plane);
  2369. pstate = to_sde_plane_state(plane->state);
  2370. /*
  2371. * These updates have to be done immediately before the plane flush
  2372. * timing, and may not be moved to the atomic_update/mode_set functions.
  2373. */
  2374. if (psde->is_error)
  2375. /* force white frame with 100% alpha pipe output on error */
  2376. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2377. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2378. /* force 100% alpha */
  2379. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2380. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2381. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2382. /* flag h/w flush complete */
  2383. if (plane->state)
  2384. pstate->pending = false;
  2385. }
  2386. /**
  2387. * sde_plane_set_error: enable/disable error condition
  2388. * @plane: pointer to drm_plane structure
  2389. */
  2390. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2391. {
  2392. struct sde_plane *psde;
  2393. if (!plane)
  2394. return;
  2395. psde = to_sde_plane(plane);
  2396. psde->is_error = error;
  2397. }
  2398. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2399. struct sde_plane_state *pstate)
  2400. {
  2401. struct drm_plane_state *state = psde->base.state;
  2402. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2403. struct sde_hw_pipe_sc_cfg *cfg = &pstate->sc_cfg;
  2404. bool prev_rd_en = cfg->rd_en;
  2405. u32 fb_cache_flag, fb_cache_type;
  2406. msm_framebuffer_get_cache_hint(state->fb, &fb_cache_flag, &fb_cache_type);
  2407. cfg->rd_en = false;
  2408. cfg->rd_scid = 0x0;
  2409. cfg->flags = SYS_CACHE_EN_FLAG | SYS_CACHE_SCID;
  2410. cfg->type = SDE_SYS_CACHE_NONE;
  2411. if ((sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache)
  2412. && ((pstate->static_cache_state == CACHE_STATE_FRAME_WRITE)
  2413. || (pstate->static_cache_state == CACHE_STATE_FRAME_READ))) {
  2414. cfg->rd_en = true;
  2415. cfg->rd_scid = sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2416. cfg->rd_noallocate = (pstate->static_cache_state == CACHE_STATE_FRAME_READ);
  2417. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2418. cfg->type = SDE_SYS_CACHE_DISP;
  2419. } else if ((sc_cfg[fb_cache_type].has_sys_cache)
  2420. && (fb_cache_flag & MSM_FB_CACHE_WRITE_EN)) {
  2421. cfg->rd_en = true;
  2422. cfg->rd_scid = sc_cfg[fb_cache_type].llcc_scid;
  2423. cfg->rd_noallocate = true;
  2424. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2425. cfg->type = fb_cache_type;
  2426. msm_framebuffer_set_cache_hint(state->fb, MSM_FB_CACHE_READ_EN, fb_cache_type);
  2427. }
  2428. if (!cfg->rd_en && !prev_rd_en)
  2429. return;
  2430. SDE_EVT32(DRMID(&psde->base), cfg->rd_scid, cfg->rd_en, cfg->rd_noallocate, cfg->flags,
  2431. fb_cache_flag, fb_cache_type);
  2432. psde->pipe_hw->ops.setup_sys_cache(psde->pipe_hw, cfg);
  2433. }
  2434. void sde_plane_static_img_control(struct drm_plane *plane,
  2435. enum sde_sys_cache_state state)
  2436. {
  2437. struct sde_plane *psde;
  2438. struct sde_plane_state *pstate;
  2439. if (!plane || !plane->state) {
  2440. SDE_ERROR("invalid plane\n");
  2441. return;
  2442. }
  2443. psde = to_sde_plane(plane);
  2444. pstate = to_sde_plane_state(plane->state);
  2445. pstate->static_cache_state = state;
  2446. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2447. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2448. }
  2449. static void _sde_plane_map_prop_to_dirty_bits(void)
  2450. {
  2451. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2452. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2453. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2454. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2455. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2456. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2457. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2458. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2459. plane_prop_array[PLANE_PROP_ZPOS] =
  2460. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2461. plane_prop_array[PLANE_PROP_UBWC_STATS_ROI] =
  2462. SDE_PLANE_DIRTY_RECTS;
  2463. plane_prop_array[PLANE_PROP_CSC_V1] =
  2464. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2465. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2466. SDE_PLANE_DIRTY_FORMAT;
  2467. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2468. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2469. SDE_PLANE_DIRTY_ALL;
  2470. /* no special action required */
  2471. plane_prop_array[PLANE_PROP_INFO] =
  2472. plane_prop_array[PLANE_PROP_ALPHA] =
  2473. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2474. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2475. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2476. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2477. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2478. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2479. SDE_PLANE_DIRTY_PERF;
  2480. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2481. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2482. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2483. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2484. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2485. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2486. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2487. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2488. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2489. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2490. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2491. SDE_PLANE_DIRTY_ALL;
  2492. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2493. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2494. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2495. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2496. }
  2497. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2498. struct sde_rect *src, struct sde_rect *dst)
  2499. {
  2500. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2501. u32 downscale = (src->h * 1000)/dst->h;
  2502. return (downscale > max_downscale) ? false : true;
  2503. }
  2504. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2505. struct sde_plane *psde, struct sde_plane_state *pstate,
  2506. struct sde_rect *src, struct sde_rect *dst)
  2507. {
  2508. struct sde_hw_pipe_uidle_cfg cfg;
  2509. u32 line_time = sde_crtc_get_line_time(crtc);
  2510. u32 fal1_target_idle_time_ns =
  2511. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2512. u32 fal10_target_idle_time_ns =
  2513. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2514. u32 fal10_threshold =
  2515. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2516. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2517. fal1_target_idle_time_ns) {
  2518. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2519. cfg.fal10_threshold = fal10_threshold;
  2520. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2521. cfg.fal1_threshold = min(1 +
  2522. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2523. psde->catalog->uidle_cfg.fal1_max_threshold);
  2524. cfg.fal_allowed_threshold = fal10_threshold +
  2525. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2526. } else {
  2527. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2528. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2529. fal1_target_idle_time_ns);
  2530. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2531. }
  2532. SDE_DEBUG_PLANE(psde,
  2533. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",
  2534. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2535. cfg.fal1_threshold, cfg.fal_allowed_threshold);
  2536. SDE_DEBUG_PLANE(psde,
  2537. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2538. line_time, fal1_target_idle_time_ns,
  2539. fal10_target_idle_time_ns,
  2540. psde->catalog->uidle_cfg.max_dwnscale);
  2541. SDE_EVT32_VERBOSE(cfg.enable,
  2542. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2543. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2544. psde->catalog->uidle_cfg.max_dwnscale);
  2545. psde->pipe_hw->ops.setup_uidle(
  2546. psde->pipe_hw, &cfg,
  2547. pstate->multirect_index);
  2548. }
  2549. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2550. struct sde_plane_state *pstate)
  2551. {
  2552. bool enable = false;
  2553. int mode = sde_plane_get_property(pstate,
  2554. PLANE_PROP_FB_TRANSLATION_MODE);
  2555. if ((mode == SDE_DRM_FB_SEC) ||
  2556. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2557. enable = true;
  2558. /* update secure session flag */
  2559. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2560. pstate->multirect_index,
  2561. enable);
  2562. }
  2563. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2564. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2565. {
  2566. const struct sde_format *fmt;
  2567. const struct msm_format *msm_fmt;
  2568. struct sde_plane *psde;
  2569. struct drm_plane_state *state;
  2570. struct sde_plane_state *pstate;
  2571. struct sde_rect src, dst;
  2572. const struct sde_rect *crtc_roi;
  2573. bool q16_data = true;
  2574. int idx;
  2575. psde = to_sde_plane(plane);
  2576. state = plane->state;
  2577. pstate = to_sde_plane_state(state);
  2578. msm_fmt = msm_framebuffer_format(fb);
  2579. if (!msm_fmt) {
  2580. SDE_ERROR("crtc%d plane%d: null format\n",
  2581. DRMID(crtc), DRMID(plane));
  2582. return;
  2583. }
  2584. fmt = to_sde_format(msm_fmt);
  2585. POPULATE_RECT(&src, state->src_x, state->src_y,
  2586. state->src_w, state->src_h, q16_data);
  2587. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2588. state->crtc_w, state->crtc_h, !q16_data);
  2589. SDE_DEBUG_PLANE(psde,
  2590. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2591. fb->base.id, src.x, src.y, src.w, src.h,
  2592. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2593. (char *)&fmt->base.pixel_format,
  2594. SDE_FORMAT_IS_UBWC(fmt));
  2595. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2596. BIT(SDE_DRM_DEINTERLACE)) {
  2597. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2598. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2599. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2600. src.h /= 2;
  2601. src.y = DIV_ROUND_UP(src.y, 2);
  2602. src.y &= ~0x1;
  2603. }
  2604. /*
  2605. * adjust layer mixer position of the sspp in the presence
  2606. * of a partial update to the active lm origin
  2607. */
  2608. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2609. dst.x -= crtc_roi->x;
  2610. dst.y -= crtc_roi->y;
  2611. /* check for UIDLE */
  2612. if (psde->pipe_hw->ops.setup_uidle)
  2613. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2614. psde->pipe_cfg.src_rect = src;
  2615. psde->pipe_cfg.dst_rect = dst;
  2616. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2617. /* check for color fill */
  2618. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2619. PLANE_PROP_COLOR_FILL);
  2620. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2621. /* skip remaining processing on color fill */
  2622. pstate->dirty = 0x0;
  2623. } else if (psde->pipe_hw->ops.setup_rects) {
  2624. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2625. &psde->pipe_cfg,
  2626. pstate->multirect_index);
  2627. }
  2628. if (psde->pipe_hw->ops.setup_pe &&
  2629. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2630. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2631. &psde->pixel_ext);
  2632. /**
  2633. * when programmed in multirect mode, scalar block will be
  2634. * bypassed. Still we need to update alpha and bitwidth
  2635. * ONLY for RECT0
  2636. */
  2637. if (psde->pipe_hw->ops.setup_scaler &&
  2638. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2639. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2640. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2641. &psde->pipe_cfg, &psde->pixel_ext,
  2642. &psde->scaler3_cfg);
  2643. }
  2644. /* update excl rect */
  2645. if (psde->pipe_hw->ops.setup_excl_rect)
  2646. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2647. &pstate->excl_rect,
  2648. pstate->multirect_index);
  2649. /* enable multirect config of corresponding rect */
  2650. if (psde->pipe_hw->ops.update_multirect)
  2651. psde->pipe_hw->ops.update_multirect(
  2652. psde->pipe_hw,
  2653. true,
  2654. pstate->multirect_index,
  2655. pstate->multirect_mode);
  2656. }
  2657. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2658. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2659. {
  2660. uint32_t src_flags = 0;
  2661. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2662. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2663. src_flags |= SDE_SSPP_FLIP_LR;
  2664. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2665. src_flags |= SDE_SSPP_FLIP_UD;
  2666. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2667. src_flags |= SDE_SSPP_ROT_90;
  2668. /* update format */
  2669. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2670. pstate->const_alpha_en, src_flags,
  2671. pstate->multirect_index);
  2672. if (psde->pipe_hw->ops.setup_cdp) {
  2673. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2674. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2675. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2676. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2677. cdp_cfg->ubwc_meta_enable =
  2678. SDE_FORMAT_IS_UBWC(fmt);
  2679. cdp_cfg->tile_amortize_enable =
  2680. SDE_FORMAT_IS_UBWC(fmt) ||
  2681. SDE_FORMAT_IS_TILE(fmt);
  2682. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2683. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2684. pstate->multirect_index);
  2685. }
  2686. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2687. /* update csc */
  2688. if (SDE_FORMAT_IS_YUV(fmt))
  2689. _sde_plane_setup_csc(psde);
  2690. else
  2691. psde->csc_ptr = 0;
  2692. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2693. uint32_t pma_mode = 0;
  2694. if (fmt->alpha_enable)
  2695. pma_mode = (uint32_t) sde_plane_get_property(
  2696. pstate, PLANE_PROP_INVERSE_PMA);
  2697. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2698. pstate->multirect_index, pma_mode);
  2699. }
  2700. if (psde->pipe_hw->ops.setup_dgm_csc)
  2701. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2702. pstate->multirect_index, psde->csc_usr_ptr);
  2703. if (psde->pipe_hw->ops.set_ubwc_stats_roi) {
  2704. if (SDE_FORMAT_IS_UBWC(fmt) && !SDE_FORMAT_IS_YUV(fmt))
  2705. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2706. pstate->multirect_index, &pstate->ubwc_stats_roi);
  2707. else
  2708. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2709. pstate->multirect_index, NULL);
  2710. }
  2711. }
  2712. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2713. {
  2714. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2715. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2716. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2717. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2718. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2719. &psde->sharp_cfg);
  2720. }
  2721. static void _sde_plane_update_properties(struct drm_plane *plane,
  2722. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2723. {
  2724. uint32_t nplanes;
  2725. const struct msm_format *msm_fmt;
  2726. const struct sde_format *fmt;
  2727. struct sde_plane *psde;
  2728. struct drm_plane_state *state;
  2729. struct sde_plane_state *pstate;
  2730. psde = to_sde_plane(plane);
  2731. state = plane->state;
  2732. pstate = to_sde_plane_state(state);
  2733. if (!pstate) {
  2734. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2735. return;
  2736. }
  2737. msm_fmt = msm_framebuffer_format(fb);
  2738. if (!msm_fmt) {
  2739. SDE_ERROR("crtc%d plane%d: null format\n",
  2740. DRMID(crtc), DRMID(plane));
  2741. return;
  2742. }
  2743. fmt = to_sde_format(msm_fmt);
  2744. nplanes = fmt->num_planes;
  2745. /* update secure session flag */
  2746. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2747. _sde_plane_update_secure_session(psde, pstate);
  2748. /* update roi config */
  2749. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2750. _sde_plane_update_roi_config(plane, crtc, fb);
  2751. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2752. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2753. psde->pipe_hw->ops.setup_format)
  2754. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2755. sde_color_process_plane_setup(plane);
  2756. /* update sharpening */
  2757. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2758. psde->pipe_hw->ops.setup_sharpening)
  2759. _sde_plane_update_sharpening(psde);
  2760. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2761. SDE_PLANE_DIRTY_FORMAT))
  2762. _sde_plane_set_qos_lut(plane, crtc, fb);
  2763. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2764. _sde_plane_set_ot_limit(plane, crtc);
  2765. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2766. _sde_plane_set_ts_prefill(plane, pstate);
  2767. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2768. _sde_plane_set_qos_remap(plane);
  2769. /* clear dirty */
  2770. pstate->dirty = 0x0;
  2771. }
  2772. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2773. struct drm_plane_state *old_state)
  2774. {
  2775. struct sde_plane *psde;
  2776. struct drm_plane_state *state;
  2777. struct sde_plane_state *pstate;
  2778. struct sde_plane_state *old_pstate;
  2779. struct drm_crtc *crtc;
  2780. struct drm_framebuffer *fb;
  2781. int idx;
  2782. int dirty_prop_flag;
  2783. bool is_rt;
  2784. if (!plane) {
  2785. SDE_ERROR("invalid plane\n");
  2786. return -EINVAL;
  2787. } else if (!plane->state) {
  2788. SDE_ERROR("invalid plane state\n");
  2789. return -EINVAL;
  2790. } else if (!old_state) {
  2791. SDE_ERROR("invalid old state\n");
  2792. return -EINVAL;
  2793. }
  2794. psde = to_sde_plane(plane);
  2795. state = plane->state;
  2796. pstate = to_sde_plane_state(state);
  2797. old_pstate = to_sde_plane_state(old_state);
  2798. crtc = state->crtc;
  2799. fb = state->fb;
  2800. if (!crtc || !fb) {
  2801. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2802. !crtc, !fb);
  2803. return -EINVAL;
  2804. }
  2805. SDE_DEBUG(
  2806. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2807. plane->base.id,
  2808. state->fb->width, state->fb->height,
  2809. (char *) &state->fb->format->format,
  2810. state->fb->modifier,
  2811. state->src_w >> 16, state->src_h >> 16,
  2812. state->src_x >> 16, state->src_y >> 16,
  2813. pstate->rotation,
  2814. state->crtc_w, state->crtc_h,
  2815. state->crtc_x, state->crtc_y);
  2816. /* force reprogramming of all the parameters, if the flag is set */
  2817. if (psde->revalidate) {
  2818. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2819. plane->base.id);
  2820. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2821. psde->revalidate = false;
  2822. }
  2823. /* determine what needs to be refreshed */
  2824. mutex_lock(&psde->property_info.property_lock);
  2825. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2826. &pstate->property_state)) >= 0) {
  2827. dirty_prop_flag = plane_prop_array[idx];
  2828. pstate->dirty |= dirty_prop_flag;
  2829. }
  2830. mutex_unlock(&psde->property_info.property_lock);
  2831. /**
  2832. * since plane_atomic_check is invoked before crtc_atomic_check
  2833. * in the commit sequence, all the parameters for updating the
  2834. * plane dirty flag will not be available during
  2835. * plane_atomic_check as some features params are updated
  2836. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2837. * before sspp update.
  2838. */
  2839. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2840. old_state);
  2841. /* re-program the output rects always if partial update roi changed */
  2842. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2843. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2844. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2845. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2846. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2847. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2848. if (is_rt != psde->is_rt_pipe || crtc->state->mode_changed) {
  2849. psde->is_rt_pipe = is_rt;
  2850. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2851. }
  2852. /* early out if nothing dirty */
  2853. if (!pstate->dirty)
  2854. return 0;
  2855. pstate->pending = true;
  2856. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2857. _sde_plane_update_properties(plane, crtc, fb);
  2858. return 0;
  2859. }
  2860. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2861. struct drm_plane_state *old_state)
  2862. {
  2863. struct sde_plane *psde;
  2864. struct drm_plane_state *state;
  2865. struct sde_plane_state *pstate;
  2866. u32 multirect_index = SDE_SSPP_RECT_0;
  2867. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  2868. u32 blend_type;
  2869. if (!plane) {
  2870. SDE_ERROR("invalid plane\n");
  2871. return;
  2872. } else if (!plane->state) {
  2873. SDE_ERROR("invalid plane state\n");
  2874. return;
  2875. } else if (!old_state) {
  2876. SDE_ERROR("invalid old state\n");
  2877. return;
  2878. }
  2879. psde = to_sde_plane(plane);
  2880. state = plane->state;
  2881. pstate = to_sde_plane_state(state);
  2882. blend_type = sde_plane_get_property(pstate,
  2883. PLANE_PROP_BLEND_OP);
  2884. /* some of the color features are dependent on plane with skip blend.
  2885. * if skip blend plane is being disabled, we need to disable color properties.
  2886. */
  2887. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  2888. skip_blend_plane.valid_plane = false;
  2889. skip_blend_plane.plane = SSPP_NONE;
  2890. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  2891. sde_crtc_disable_cp_features(old_state->crtc);
  2892. }
  2893. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2894. pstate->multirect_mode);
  2895. pstate->pending = true;
  2896. if (is_sde_plane_virtual(plane))
  2897. multirect_index = SDE_SSPP_RECT_1;
  2898. /* disable multirect config of corresponding rect */
  2899. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2900. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2901. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2902. }
  2903. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2904. static void _sde_plane_atomic_update(struct drm_plane *plane,
  2905. struct drm_plane_state *old_state)
  2906. #else
  2907. static void sde_plane_atomic_update(struct drm_plane *plane,
  2908. struct drm_plane_state *old_state)
  2909. #endif
  2910. {
  2911. struct sde_plane *psde;
  2912. struct drm_plane_state *state;
  2913. if (!plane) {
  2914. SDE_ERROR("invalid plane\n");
  2915. return;
  2916. } else if (!plane->state) {
  2917. SDE_ERROR("invalid plane state\n");
  2918. return;
  2919. }
  2920. psde = to_sde_plane(plane);
  2921. psde->is_error = false;
  2922. state = plane->state;
  2923. SDE_DEBUG_PLANE(psde, "\n");
  2924. if (!sde_plane_enabled(state)) {
  2925. _sde_plane_atomic_disable(plane, old_state);
  2926. } else {
  2927. int ret;
  2928. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2929. /* atomic_check should have ensured that this doesn't fail */
  2930. WARN_ON(ret < 0);
  2931. }
  2932. }
  2933. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2934. static void sde_plane_atomic_update(struct drm_plane *plane,
  2935. struct drm_atomic_state *atomic_state)
  2936. {
  2937. struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(atomic_state, plane);
  2938. _sde_plane_atomic_update(plane, old_state);
  2939. }
  2940. #endif
  2941. void sde_plane_restore(struct drm_plane *plane)
  2942. {
  2943. struct sde_plane *psde;
  2944. if (!plane || !plane->state) {
  2945. SDE_ERROR("invalid plane\n");
  2946. return;
  2947. }
  2948. psde = to_sde_plane(plane);
  2949. /*
  2950. * Revalidate is only true here if idle PC occurred and
  2951. * there is no plane state update in current commit cycle.
  2952. */
  2953. if (!psde->revalidate)
  2954. return;
  2955. SDE_DEBUG_PLANE(psde, "\n");
  2956. /* last plane state is same as current state */
  2957. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2958. _sde_plane_atomic_update(plane, plane->state);
  2959. #else
  2960. sde_plane_atomic_update(plane, plane->state);
  2961. #endif
  2962. }
  2963. bool sde_plane_is_cache_required(struct drm_plane *plane,
  2964. enum sde_sys_cache_type type)
  2965. {
  2966. struct sde_plane_state *pstate;
  2967. if (!plane || !plane->state) {
  2968. SDE_ERROR("invalid plane\n");
  2969. return false;
  2970. }
  2971. pstate = to_sde_plane_state(plane->state);
  2972. /* check if llcc is required for the plane */
  2973. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  2974. return true;
  2975. else
  2976. return false;
  2977. }
  2978. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  2979. {
  2980. char feature_name[256];
  2981. if (psde->pipe_sblk->maxhdeciexp) {
  2982. msm_property_install_range(&psde->property_info,
  2983. "h_decimate", 0x0, 0,
  2984. psde->pipe_sblk->maxhdeciexp, 0,
  2985. PLANE_PROP_H_DECIMATE);
  2986. }
  2987. if (psde->pipe_sblk->maxvdeciexp) {
  2988. msm_property_install_range(&psde->property_info,
  2989. "v_decimate", 0x0, 0,
  2990. psde->pipe_sblk->maxvdeciexp, 0,
  2991. PLANE_PROP_V_DECIMATE);
  2992. }
  2993. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  2994. msm_property_install_range(
  2995. &psde->property_info, "scaler_v2",
  2996. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2997. msm_property_install_blob(&psde->property_info,
  2998. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  2999. msm_property_install_blob(&psde->property_info,
  3000. "lut_cir", 0,
  3001. PLANE_PROP_SCALER_LUT_CIR);
  3002. msm_property_install_blob(&psde->property_info,
  3003. "lut_sep", 0,
  3004. PLANE_PROP_SCALER_LUT_SEP);
  3005. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  3006. msm_property_install_range(
  3007. &psde->property_info, "scaler_v2",
  3008. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3009. msm_property_install_blob(&psde->property_info,
  3010. "lut_sep", 0,
  3011. PLANE_PROP_SCALER_LUT_SEP);
  3012. } else if (psde->features & SDE_SSPP_SCALER) {
  3013. msm_property_install_range(
  3014. &psde->property_info, "scaler_v1", 0x0,
  3015. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  3016. }
  3017. if (psde->features & BIT(SDE_SSPP_CSC) ||
  3018. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  3019. msm_property_install_volatile_range(
  3020. &psde->property_info, "csc_v1", 0x0,
  3021. 0, ~0, 0, PLANE_PROP_CSC_V1);
  3022. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  3023. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3024. "SDE_SSPP_HUE_V",
  3025. psde->pipe_sblk->hsic_blk.version >> 16);
  3026. msm_property_install_range(&psde->property_info,
  3027. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3028. PLANE_PROP_HUE_ADJUST);
  3029. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3030. "SDE_SSPP_SATURATION_V",
  3031. psde->pipe_sblk->hsic_blk.version >> 16);
  3032. msm_property_install_range(&psde->property_info,
  3033. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3034. PLANE_PROP_SATURATION_ADJUST);
  3035. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3036. "SDE_SSPP_VALUE_V",
  3037. psde->pipe_sblk->hsic_blk.version >> 16);
  3038. msm_property_install_range(&psde->property_info,
  3039. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3040. PLANE_PROP_VALUE_ADJUST);
  3041. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3042. "SDE_SSPP_CONTRAST_V",
  3043. psde->pipe_sblk->hsic_blk.version >> 16);
  3044. msm_property_install_range(&psde->property_info,
  3045. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3046. PLANE_PROP_CONTRAST_ADJUST);
  3047. }
  3048. }
  3049. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3050. struct sde_kms_info *info)
  3051. {
  3052. char feature_name[256];
  3053. bool is_master = !psde->is_virtual;
  3054. if ((is_master &&
  3055. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3056. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3057. msm_property_install_range(&psde->property_info,
  3058. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3059. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3060. }
  3061. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3062. msm_property_install_volatile_range(
  3063. &psde->property_info, "csc_dma_v1", 0x0,
  3064. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3065. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3066. }
  3067. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3068. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3069. "SDE_SSPP_SKIN_COLOR_V",
  3070. psde->pipe_sblk->memcolor_blk.version >> 16);
  3071. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3072. PLANE_PROP_SKIN_COLOR);
  3073. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3074. "SDE_SSPP_SKY_COLOR_V",
  3075. psde->pipe_sblk->memcolor_blk.version >> 16);
  3076. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3077. PLANE_PROP_SKY_COLOR);
  3078. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3079. "SDE_SSPP_FOLIAGE_COLOR_V",
  3080. psde->pipe_sblk->memcolor_blk.version >> 16);
  3081. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3082. PLANE_PROP_FOLIAGE_COLOR);
  3083. }
  3084. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3085. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3086. "SDE_VIG_3D_LUT_GAMUT_V",
  3087. psde->pipe_sblk->gamut_blk.version >> 16);
  3088. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3089. PLANE_PROP_VIG_GAMUT);
  3090. }
  3091. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3092. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3093. "SDE_VIG_1D_LUT_IGC_V",
  3094. psde->pipe_sblk->igc_blk[0].version >> 16);
  3095. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3096. PLANE_PROP_VIG_IGC);
  3097. }
  3098. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3099. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3100. "SDE_DGM_1D_LUT_IGC_V",
  3101. psde->pipe_sblk->igc_blk[0].version >> 16);
  3102. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3103. PLANE_PROP_DMA_IGC);
  3104. }
  3105. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3106. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3107. "SDE_DGM_1D_LUT_GC_V",
  3108. psde->pipe_sblk->gc_blk[0].version >> 16);
  3109. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3110. PLANE_PROP_DMA_GC);
  3111. }
  3112. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3113. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3114. "SDE_SSPP_FP16_IGC_V",
  3115. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3116. msm_property_install_range(&psde->property_info, feature_name,
  3117. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3118. }
  3119. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3120. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3121. "SDE_SSPP_FP16_GC_V",
  3122. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3123. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3124. PLANE_PROP_FP16_GC);
  3125. }
  3126. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3127. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3128. "SDE_SSPP_FP16_CSC_V",
  3129. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3130. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3131. PLANE_PROP_FP16_CSC);
  3132. }
  3133. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3134. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3135. "SDE_SSPP_FP16_UNMULT_V",
  3136. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3137. msm_property_install_range(&psde->property_info, feature_name,
  3138. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3139. }
  3140. }
  3141. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3142. u32 master_plane_id, struct sde_kms_info *info,
  3143. struct sde_mdss_cfg *catalog)
  3144. {
  3145. bool is_master = !psde->is_virtual;
  3146. const struct sde_format_extended *format_list;
  3147. u32 index;
  3148. int pipe_id;
  3149. if (is_master) {
  3150. format_list = psde->pipe_sblk->format_list;
  3151. } else {
  3152. format_list = psde->pipe_sblk->virt_format_list;
  3153. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3154. master_plane_id);
  3155. }
  3156. if (format_list) {
  3157. sde_kms_info_start(info, "pixel_formats");
  3158. while (format_list->fourcc_format) {
  3159. sde_kms_info_append_format(info,
  3160. format_list->fourcc_format,
  3161. format_list->modifier);
  3162. ++format_list;
  3163. }
  3164. sde_kms_info_stop(info);
  3165. }
  3166. if (psde->pipe_hw && catalog->qseed_hw_rev)
  3167. sde_kms_info_add_keyint(info, "scaler_step_ver", catalog->qseed_hw_rev);
  3168. sde_kms_info_add_keyint(info, "max_linewidth",
  3169. psde->pipe_sblk->maxlinewidth);
  3170. sde_kms_info_add_keyint(info, "max_upscale",
  3171. psde->pipe_sblk->maxupscale);
  3172. sde_kms_info_add_keyint(info, "max_downscale",
  3173. psde->pipe_sblk->maxdwnscale);
  3174. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3175. psde->pipe_sblk->maxhdeciexp);
  3176. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3177. psde->pipe_sblk->maxvdeciexp);
  3178. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3179. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3180. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3181. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3182. if (SDE_SSPP_VALID_VIG(psde->pipe))
  3183. pipe_id = psde->pipe - SSPP_VIG0;
  3184. else if (SDE_SSPP_VALID_DMA(psde->pipe))
  3185. pipe_id = psde->pipe - SSPP_DMA0;
  3186. else
  3187. pipe_id = -1;
  3188. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3189. index = (master_plane_id == 0) ? 0 : 1;
  3190. if (test_bit(SDE_FEATURE_DEMURA, catalog->features) &&
  3191. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3192. sde_kms_info_add_keyint(info, "demura_block", index);
  3193. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3194. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3195. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3196. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3197. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3198. const struct sde_format_extended *inline_rot_fmt_list;
  3199. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3200. catalog->true_inline_rot_rev);
  3201. sde_kms_info_add_keyint(info,
  3202. "true_inline_dwnscale_rt",
  3203. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3204. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3205. sde_kms_info_add_keyint(info,
  3206. "true_inline_dwnscale_rt_numerator",
  3207. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3208. sde_kms_info_add_keyint(info,
  3209. "true_inline_dwnscale_rt_denominator",
  3210. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3211. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3212. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3213. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3214. psde->pipe_sblk->in_rot_maxheight);
  3215. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3216. if (inline_rot_fmt_list) {
  3217. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3218. while (inline_rot_fmt_list->fourcc_format) {
  3219. sde_kms_info_append_format(info,
  3220. inline_rot_fmt_list->fourcc_format,
  3221. inline_rot_fmt_list->modifier);
  3222. ++inline_rot_fmt_list;
  3223. }
  3224. sde_kms_info_stop(info);
  3225. }
  3226. }
  3227. }
  3228. /* helper to install properties which are common to planes and crtcs */
  3229. static void _sde_plane_install_properties(struct drm_plane *plane,
  3230. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3231. {
  3232. static const struct drm_prop_enum_list e_blend_op[] = {
  3233. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3234. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3235. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3236. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3237. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3238. };
  3239. static const struct drm_prop_enum_list e_src_config[] = {
  3240. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3241. };
  3242. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3243. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3244. {SDE_DRM_FB_SEC, "sec"},
  3245. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3246. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3247. };
  3248. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3249. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3250. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3251. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3252. };
  3253. struct sde_kms_info *info;
  3254. struct sde_plane *psde = to_sde_plane(plane);
  3255. bool is_master;
  3256. int zpos_max = 255;
  3257. int zpos_def = 0;
  3258. if (!plane || !psde) {
  3259. SDE_ERROR("invalid plane\n");
  3260. return;
  3261. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3262. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3263. !psde->pipe_hw, !psde->pipe_sblk);
  3264. return;
  3265. } else if (!catalog) {
  3266. SDE_ERROR("invalid catalog\n");
  3267. return;
  3268. }
  3269. psde->catalog = catalog;
  3270. is_master = !psde->is_virtual;
  3271. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3272. if (!info) {
  3273. SDE_ERROR("failed to allocate info memory\n");
  3274. return;
  3275. }
  3276. if (sde_is_custom_client()) {
  3277. if (catalog->mixer_count &&
  3278. catalog->mixer[0].sblk->maxblendstages) {
  3279. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3280. if (test_bit(SDE_FEATURE_BASE_LAYER, catalog->features) &&
  3281. (zpos_max > SDE_STAGE_MAX - 1))
  3282. zpos_max = SDE_STAGE_MAX - 1;
  3283. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3284. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3285. }
  3286. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3287. /* reserve zpos == 0 for primary planes */
  3288. zpos_def = drm_plane_index(plane) + 1;
  3289. }
  3290. msm_property_install_range(&psde->property_info, "zpos",
  3291. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3292. msm_property_install_range(&psde->property_info, "alpha",
  3293. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3294. /* linux default file descriptor range on each process */
  3295. msm_property_install_range(&psde->property_info, "input_fence",
  3296. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3297. if (is_master)
  3298. _sde_plane_install_master_only_properties(psde);
  3299. else
  3300. msm_property_install_enum(&psde->property_info,
  3301. "multirect_mode", 0x0, 0, e_multirect_mode,
  3302. ARRAY_SIZE(e_multirect_mode), 0,
  3303. PLANE_PROP_MULTIRECT_MODE);
  3304. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3305. msm_property_install_volatile_range(&psde->property_info,
  3306. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3307. sde_plane_rot_install_properties(plane, catalog);
  3308. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3309. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3310. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3311. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3312. PLANE_PROP_SRC_CONFIG);
  3313. if (psde->pipe_hw->ops.setup_solidfill)
  3314. msm_property_install_range(&psde->property_info, "color_fill",
  3315. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3316. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3317. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3318. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3319. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3320. msm_property_install_blob(&psde->property_info, "capabilities",
  3321. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3322. sde_kms_info_reset(info);
  3323. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3324. catalog);
  3325. _sde_plane_install_colorproc_properties(psde, info);
  3326. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3327. info->data, SDE_KMS_INFO_DATALEN(info),
  3328. PLANE_PROP_INFO);
  3329. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3330. 0x0, 0, e_fb_translation_mode,
  3331. ARRAY_SIZE(e_fb_translation_mode), 0,
  3332. PLANE_PROP_FB_TRANSLATION_MODE);
  3333. if (psde->pipe_hw->ops.set_ubwc_stats_roi)
  3334. msm_property_install_range(&psde->property_info, "ubwc_stats_roi",
  3335. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_UBWC_STATS_ROI);
  3336. kfree(info);
  3337. }
  3338. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3339. void __user *usr_ptr)
  3340. {
  3341. struct sde_drm_csc_v1 csc_v1;
  3342. int i;
  3343. if (!psde) {
  3344. SDE_ERROR("invalid plane\n");
  3345. return;
  3346. }
  3347. psde->csc_usr_ptr = NULL;
  3348. if (!usr_ptr) {
  3349. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3350. return;
  3351. }
  3352. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3353. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3354. return;
  3355. }
  3356. /* populate from user space */
  3357. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3358. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3359. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3360. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3361. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3362. }
  3363. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3364. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3365. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3366. }
  3367. psde->csc_usr_ptr = &psde->csc_cfg;
  3368. }
  3369. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3370. struct sde_plane_state *pstate, void __user *usr)
  3371. {
  3372. struct sde_drm_scaler_v1 scale_v1;
  3373. struct sde_hw_pixel_ext *pe;
  3374. int i;
  3375. if (!psde || !pstate) {
  3376. SDE_ERROR("invalid argument(s)\n");
  3377. return;
  3378. }
  3379. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3380. if (!usr) {
  3381. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3382. return;
  3383. }
  3384. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3385. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3386. return;
  3387. }
  3388. /* force property to be dirty, even if the pointer didn't change */
  3389. msm_property_set_dirty(&psde->property_info,
  3390. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3391. /* populate from user space */
  3392. pe = &pstate->pixel_ext;
  3393. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3394. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3395. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3396. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3397. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3398. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3399. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3400. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3401. }
  3402. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3403. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3404. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3405. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3406. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3407. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3408. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3409. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3410. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3411. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3412. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3413. }
  3414. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3415. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3416. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3417. }
  3418. static void _sde_plane_clear_predownscale_settings(
  3419. struct sde_plane_state *pstate)
  3420. {
  3421. pstate->pre_down.pre_downscale_x_0 = 0;
  3422. pstate->pre_down.pre_downscale_x_1 = 0;
  3423. pstate->pre_down.pre_downscale_y_0 = 0;
  3424. pstate->pre_down.pre_downscale_y_1 = 0;
  3425. }
  3426. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3427. struct sde_plane_state *pstate, void __user *usr)
  3428. {
  3429. struct sde_drm_scaler_v2 scale_v2;
  3430. struct sde_hw_pixel_ext *pe;
  3431. int i;
  3432. struct sde_hw_scaler3_cfg *cfg;
  3433. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3434. if (!psde || !pstate) {
  3435. SDE_ERROR("invalid argument(s)\n");
  3436. return;
  3437. }
  3438. cfg = &pstate->scaler3_cfg;
  3439. pd_cfg = &pstate->pre_down;
  3440. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3441. if (!usr) {
  3442. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3443. cfg->enable = 0;
  3444. _sde_plane_clear_predownscale_settings(pstate);
  3445. goto end;
  3446. }
  3447. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3448. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3449. return;
  3450. }
  3451. /* detach/ignore user data if 'disabled' */
  3452. if (!scale_v2.enable) {
  3453. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3454. cfg->enable = 0;
  3455. _sde_plane_clear_predownscale_settings(pstate);
  3456. goto end;
  3457. }
  3458. /* populate from user space */
  3459. sde_set_scaler_v2(cfg, &scale_v2);
  3460. if (_sde_plane_has_pre_downscale(psde)) {
  3461. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3462. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3463. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3464. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3465. }
  3466. pe = &pstate->pixel_ext;
  3467. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3468. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3469. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3470. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3471. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3472. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3473. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3474. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3475. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3476. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3477. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3478. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3479. }
  3480. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3481. end:
  3482. /* force property to be dirty, even if the pointer didn't change */
  3483. msm_property_set_dirty(&psde->property_info,
  3484. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3485. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3486. cfg->src_width[0], cfg->src_height[0],
  3487. cfg->dst_width, cfg->dst_height);
  3488. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3489. }
  3490. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3491. struct sde_plane_state *pstate, void __user *usr_ptr)
  3492. {
  3493. struct drm_clip_rect excl_rect_v1;
  3494. if (!psde || !pstate) {
  3495. SDE_ERROR("invalid argument(s)\n");
  3496. return;
  3497. }
  3498. if (!usr_ptr) {
  3499. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3500. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3501. return;
  3502. }
  3503. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3504. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3505. return;
  3506. }
  3507. /* populate from user space */
  3508. pstate->excl_rect.x = excl_rect_v1.x1;
  3509. pstate->excl_rect.y = excl_rect_v1.y1;
  3510. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3511. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3512. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3513. pstate->excl_rect.x, pstate->excl_rect.y,
  3514. pstate->excl_rect.w, pstate->excl_rect.h);
  3515. }
  3516. static void _sde_plane_set_ubwc_stats_roi(struct sde_plane *psde,
  3517. struct sde_plane_state *pstate, uint64_t roi)
  3518. {
  3519. uint16_t y0, y1;
  3520. if (!psde || !pstate) {
  3521. SDE_ERROR("invalid argument(s)\n");
  3522. return;
  3523. }
  3524. y0 = roi & 0xFFFF;
  3525. y1 = (roi >> 0x10) & 0xFFFF;
  3526. if (y0 > psde->pipe_cfg.src_rect.h || y1 > psde->pipe_cfg.src_rect.h) {
  3527. SDE_ERROR_PLANE(psde, "invalid ubwc roi y0 0x%x, y1 0x%x, src height 0x%x",
  3528. y0, y1, psde->pipe_cfg.src_rect.h);
  3529. y0 = 0;
  3530. y1 = 0;
  3531. }
  3532. pstate->ubwc_stats_roi.y_coord0 = y0;
  3533. pstate->ubwc_stats_roi.y_coord1 = y1;
  3534. }
  3535. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3536. struct drm_plane_state *state, struct drm_property *property,
  3537. uint64_t val)
  3538. {
  3539. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3540. struct sde_plane_state *pstate;
  3541. int idx, ret = -EINVAL;
  3542. SDE_DEBUG_PLANE(psde, "\n");
  3543. if (!plane) {
  3544. SDE_ERROR("invalid plane\n");
  3545. } else if (!state) {
  3546. SDE_ERROR_PLANE(psde, "invalid state\n");
  3547. } else {
  3548. pstate = to_sde_plane_state(state);
  3549. ret = msm_property_atomic_set(&psde->property_info,
  3550. &pstate->property_state, property, val);
  3551. if (!ret) {
  3552. idx = msm_property_index(&psde->property_info,
  3553. property);
  3554. switch (idx) {
  3555. case PLANE_PROP_INPUT_FENCE:
  3556. _sde_plane_set_input_fence(psde, pstate, val);
  3557. break;
  3558. case PLANE_PROP_CSC_V1:
  3559. case PLANE_PROP_CSC_DMA_V1:
  3560. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3561. break;
  3562. case PLANE_PROP_SCALER_V1:
  3563. _sde_plane_set_scaler_v1(psde, pstate,
  3564. (void *)(uintptr_t)val);
  3565. break;
  3566. case PLANE_PROP_SCALER_V2:
  3567. _sde_plane_set_scaler_v2(psde, pstate,
  3568. (void *)(uintptr_t)val);
  3569. break;
  3570. case PLANE_PROP_EXCL_RECT_V1:
  3571. _sde_plane_set_excl_rect_v1(psde, pstate,
  3572. (void *)(uintptr_t)val);
  3573. break;
  3574. case PLANE_PROP_UBWC_STATS_ROI:
  3575. _sde_plane_set_ubwc_stats_roi(psde, pstate, val);
  3576. break;
  3577. default:
  3578. /* nothing to do */
  3579. break;
  3580. }
  3581. }
  3582. }
  3583. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3584. property->name, property->base.id, val, ret);
  3585. return ret;
  3586. }
  3587. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3588. const struct drm_plane_state *state,
  3589. struct drm_property *property, uint64_t *val)
  3590. {
  3591. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3592. struct sde_plane_state *pstate;
  3593. int ret = -EINVAL;
  3594. if (!plane) {
  3595. SDE_ERROR("invalid plane\n");
  3596. } else if (!state) {
  3597. SDE_ERROR("invalid state\n");
  3598. } else {
  3599. SDE_DEBUG_PLANE(psde, "\n");
  3600. pstate = to_sde_plane_state(state);
  3601. ret = msm_property_atomic_get(&psde->property_info,
  3602. &pstate->property_state, property, val);
  3603. }
  3604. return ret;
  3605. }
  3606. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3607. struct drm_plane_state *plane_state)
  3608. {
  3609. struct sde_plane *psde;
  3610. struct sde_plane_state *pstate;
  3611. struct drm_property *drm_prop;
  3612. enum msm_mdp_plane_property prop_idx;
  3613. if (!plane || !plane_state) {
  3614. SDE_ERROR("invalid params\n");
  3615. return -EINVAL;
  3616. }
  3617. psde = to_sde_plane(plane);
  3618. pstate = to_sde_plane_state(plane_state);
  3619. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3620. uint64_t val = pstate->property_values[prop_idx].value;
  3621. uint64_t def;
  3622. int ret;
  3623. drm_prop = msm_property_index_to_drm_property(
  3624. &psde->property_info, prop_idx);
  3625. if (!drm_prop) {
  3626. /* not all props will be installed, based on caps */
  3627. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3628. prop_idx);
  3629. continue;
  3630. }
  3631. def = msm_property_get_default(&psde->property_info, prop_idx);
  3632. if (val == def)
  3633. continue;
  3634. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3635. drm_prop->name, prop_idx, val, def);
  3636. ret = sde_plane_atomic_set_property(plane, plane_state,
  3637. drm_prop, def);
  3638. if (ret) {
  3639. SDE_ERROR_PLANE(psde,
  3640. "set property failed, idx %d ret %d\n",
  3641. prop_idx, ret);
  3642. continue;
  3643. }
  3644. }
  3645. return 0;
  3646. }
  3647. static void sde_plane_destroy(struct drm_plane *plane)
  3648. {
  3649. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3650. SDE_DEBUG_PLANE(psde, "\n");
  3651. if (psde) {
  3652. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3653. if (psde->blob_info)
  3654. drm_property_blob_put(psde->blob_info);
  3655. msm_property_destroy(&psde->property_info);
  3656. mutex_destroy(&psde->lock);
  3657. /* this will destroy the states as well */
  3658. drm_plane_cleanup(plane);
  3659. if (psde->pipe_hw)
  3660. sde_hw_sspp_destroy(psde->pipe_hw);
  3661. kfree(psde);
  3662. }
  3663. }
  3664. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3665. {
  3666. struct sde_plane_state *pstate;
  3667. if (!state) {
  3668. SDE_ERROR("invalid arg state %d\n", !state);
  3669. return;
  3670. }
  3671. pstate = to_sde_plane_state(state);
  3672. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3673. SDE_DRM_FB_SEC) {
  3674. /* remove ref count for frame buffers */
  3675. if (state->fb) {
  3676. drm_framebuffer_put(state->fb);
  3677. state->fb = NULL;
  3678. }
  3679. }
  3680. }
  3681. static void sde_plane_destroy_state(struct drm_plane *plane,
  3682. struct drm_plane_state *state)
  3683. {
  3684. struct sde_plane *psde;
  3685. struct sde_plane_state *pstate;
  3686. if (!plane || !state) {
  3687. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3688. !plane, !state);
  3689. return;
  3690. }
  3691. psde = to_sde_plane(plane);
  3692. pstate = to_sde_plane_state(state);
  3693. SDE_DEBUG_PLANE(psde, "\n");
  3694. /* remove ref count for frame buffers */
  3695. if (state->fb)
  3696. drm_framebuffer_put(state->fb);
  3697. /* remove ref count for fence */
  3698. if (pstate->input_fence)
  3699. sde_sync_put(pstate->input_fence);
  3700. pstate->input_fence = 0;
  3701. /* destroy value helper */
  3702. msm_property_destroy_state(&psde->property_info, pstate,
  3703. &pstate->property_state);
  3704. }
  3705. static struct drm_plane_state *
  3706. sde_plane_duplicate_state(struct drm_plane *plane)
  3707. {
  3708. struct sde_plane *psde;
  3709. struct sde_plane_state *pstate;
  3710. struct sde_plane_state *old_state;
  3711. struct drm_property *drm_prop;
  3712. uint64_t input_fence_default;
  3713. if (!plane) {
  3714. SDE_ERROR("invalid plane\n");
  3715. return NULL;
  3716. } else if (!plane->state) {
  3717. SDE_ERROR("invalid plane state\n");
  3718. return NULL;
  3719. }
  3720. old_state = to_sde_plane_state(plane->state);
  3721. psde = to_sde_plane(plane);
  3722. if (old_state->cont_splash_populated) {
  3723. plane->state->crtc = NULL;
  3724. old_state->cont_splash_populated = false;
  3725. }
  3726. pstate = msm_property_alloc_state(&psde->property_info);
  3727. if (!pstate) {
  3728. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3729. return NULL;
  3730. }
  3731. SDE_DEBUG_PLANE(psde, "\n");
  3732. /* duplicate value helper */
  3733. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3734. &pstate->property_state, pstate->property_values);
  3735. /* clear out any input fence */
  3736. pstate->input_fence = 0;
  3737. input_fence_default = msm_property_get_default(
  3738. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3739. drm_prop = msm_property_index_to_drm_property(
  3740. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3741. if (msm_property_atomic_set(&psde->property_info,
  3742. &pstate->property_state, drm_prop,
  3743. input_fence_default))
  3744. SDE_DEBUG_PLANE(psde,
  3745. "error clearing duplicated input fence\n");
  3746. pstate->dirty = 0x0;
  3747. pstate->pending = false;
  3748. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3749. /* reset layout offset */
  3750. if (pstate->layout_offset) {
  3751. if (pstate->layout_offset > 0)
  3752. pstate->base.crtc_x += pstate->layout_offset;
  3753. pstate->layout = SDE_LAYOUT_NONE;
  3754. pstate->layout_offset = 0;
  3755. }
  3756. return &pstate->base;
  3757. }
  3758. static void sde_plane_reset(struct drm_plane *plane)
  3759. {
  3760. struct sde_plane *psde;
  3761. struct sde_plane_state *pstate;
  3762. if (!plane) {
  3763. SDE_ERROR("invalid plane\n");
  3764. return;
  3765. }
  3766. psde = to_sde_plane(plane);
  3767. SDE_DEBUG_PLANE(psde, "\n");
  3768. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3769. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3770. return;
  3771. }
  3772. /* remove previous state, if present */
  3773. if (plane->state) {
  3774. sde_plane_destroy_state(plane, plane->state);
  3775. plane->state = 0;
  3776. }
  3777. pstate = msm_property_alloc_state(&psde->property_info);
  3778. if (!pstate) {
  3779. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3780. return;
  3781. }
  3782. /* reset value helper */
  3783. msm_property_reset_state(&psde->property_info, pstate,
  3784. &pstate->property_state,
  3785. pstate->property_values);
  3786. pstate->base.plane = plane;
  3787. plane->state = &pstate->base;
  3788. }
  3789. void sde_plane_get_frame_data(struct drm_plane *plane,
  3790. struct sde_drm_plane_frame_data *data)
  3791. {
  3792. struct sde_plane *psde;
  3793. struct sde_plane_state *pstate;
  3794. struct sde_drm_ubwc_stats_data *ubwc_stats;
  3795. if (!plane) {
  3796. SDE_ERROR("invalid plane\n");
  3797. return;
  3798. }
  3799. psde = to_sde_plane(plane);
  3800. pstate = to_sde_plane_state(plane->state);
  3801. ubwc_stats = &data->ubwc_stats;
  3802. data->plane_id = DRMID(plane);
  3803. if (psde->pipe_hw->ops.get_ubwc_stats_data) {
  3804. memcpy(&ubwc_stats->roi, &pstate->ubwc_stats_roi,
  3805. sizeof(struct sde_drm_ubwc_stats_roi));
  3806. psde->pipe_hw->ops.get_ubwc_stats_data(psde->pipe_hw,
  3807. pstate->multirect_index, ubwc_stats);
  3808. }
  3809. if (psde->pipe_hw->ops.get_ubwc_error)
  3810. ubwc_stats->error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  3811. pstate->multirect_index);
  3812. if (psde->pipe_hw->ops.clear_ubwc_error && ubwc_stats->error)
  3813. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  3814. if (psde->pipe_hw->ops.get_meta_error)
  3815. ubwc_stats->meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  3816. pstate->multirect_index);
  3817. if (psde->pipe_hw->ops.clear_meta_error && ubwc_stats->meta_error)
  3818. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  3819. if (ubwc_stats->error || ubwc_stats->meta_error) {
  3820. SDE_EVT32(DRMID(plane), ubwc_stats->error, ubwc_stats->meta_error,
  3821. SDE_EVTLOG_ERROR);
  3822. SDE_DEBUG_PLANE(psde, "plane%d ubwc_error %d meta_error %d\n",
  3823. ubwc_stats->error, ubwc_stats->meta_error);
  3824. }
  3825. }
  3826. #ifdef CONFIG_DEBUG_FS
  3827. static ssize_t _sde_plane_danger_read(struct file *file,
  3828. char __user *buff, size_t count, loff_t *ppos)
  3829. {
  3830. struct sde_kms *kms = file->private_data;
  3831. struct sde_mdss_cfg *cfg = kms->catalog;
  3832. int len = 0;
  3833. char buf[40] = {'\0'};
  3834. if (!cfg)
  3835. return -ENODEV;
  3836. if (*ppos)
  3837. return 0; /* the end */
  3838. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3839. if (len < 0 || len >= sizeof(buf))
  3840. return 0;
  3841. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3842. return -EFAULT;
  3843. *ppos += len; /* increase offset */
  3844. return len;
  3845. }
  3846. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3847. {
  3848. struct drm_plane *plane;
  3849. drm_for_each_plane(plane, kms->dev) {
  3850. if (plane->fb && plane->state) {
  3851. sde_plane_danger_signal_ctrl(plane, enable);
  3852. SDE_DEBUG("plane:%d img:%dx%d ",
  3853. plane->base.id, plane->fb->width,
  3854. plane->fb->height);
  3855. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3856. plane->state->src_x >> 16,
  3857. plane->state->src_y >> 16,
  3858. plane->state->src_w >> 16,
  3859. plane->state->src_h >> 16,
  3860. plane->state->crtc_x, plane->state->crtc_y,
  3861. plane->state->crtc_w, plane->state->crtc_h);
  3862. } else {
  3863. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3864. }
  3865. }
  3866. }
  3867. static ssize_t _sde_plane_danger_write(struct file *file,
  3868. const char __user *user_buf, size_t count, loff_t *ppos)
  3869. {
  3870. struct sde_kms *kms = file->private_data;
  3871. struct sde_mdss_cfg *cfg = kms->catalog;
  3872. int disable_panic;
  3873. char buf[10];
  3874. if (!cfg)
  3875. return -EFAULT;
  3876. if (count >= sizeof(buf))
  3877. return -EFAULT;
  3878. if (copy_from_user(buf, user_buf, count))
  3879. return -EFAULT;
  3880. buf[count] = 0; /* end of string */
  3881. if (kstrtoint(buf, 0, &disable_panic))
  3882. return -EFAULT;
  3883. if (disable_panic) {
  3884. /* Disable panic signal for all active pipes */
  3885. SDE_DEBUG("Disabling danger:\n");
  3886. _sde_plane_set_danger_state(kms, false);
  3887. kms->has_danger_ctrl = false;
  3888. } else {
  3889. /* Enable panic signal for all active pipes */
  3890. SDE_DEBUG("Enabling danger:\n");
  3891. kms->has_danger_ctrl = true;
  3892. _sde_plane_set_danger_state(kms, true);
  3893. }
  3894. return count;
  3895. }
  3896. static const struct file_operations sde_plane_danger_enable = {
  3897. .open = simple_open,
  3898. .read = _sde_plane_danger_read,
  3899. .write = _sde_plane_danger_write,
  3900. };
  3901. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3902. {
  3903. struct sde_plane *psde;
  3904. struct sde_kms *kms;
  3905. struct msm_drm_private *priv;
  3906. const struct sde_sspp_sub_blks *sblk = 0;
  3907. const struct sde_sspp_cfg *cfg = 0;
  3908. if (!plane || !plane->dev) {
  3909. SDE_ERROR("invalid arguments\n");
  3910. return -EINVAL;
  3911. }
  3912. priv = plane->dev->dev_private;
  3913. if (!priv || !priv->kms) {
  3914. SDE_ERROR("invalid KMS reference\n");
  3915. return -EINVAL;
  3916. }
  3917. kms = to_sde_kms(priv->kms);
  3918. psde = to_sde_plane(plane);
  3919. if (psde && psde->pipe_hw)
  3920. cfg = psde->pipe_hw->cap;
  3921. if (cfg)
  3922. sblk = cfg->sblk;
  3923. if (!sblk)
  3924. return 0;
  3925. /* create overall sub-directory for the pipe */
  3926. psde->debugfs_root =
  3927. debugfs_create_dir(psde->pipe_name,
  3928. plane->dev->primary->debugfs_root);
  3929. if (!psde->debugfs_root)
  3930. return -ENOMEM;
  3931. /* don't error check these */
  3932. debugfs_create_x64("features", 0400,
  3933. psde->debugfs_root, &psde->features);
  3934. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3935. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3936. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3937. debugfs_create_bool("default_scaling",
  3938. 0600,
  3939. psde->debugfs_root,
  3940. &psde->debugfs_default_scale);
  3941. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3942. debugfs_create_u32("in_rot_max_downscale_rt_num",
  3943. 0600,
  3944. psde->debugfs_root,
  3945. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3946. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  3947. 0600,
  3948. psde->debugfs_root,
  3949. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3950. debugfs_create_u32("in_rot_max_downscale_nrt",
  3951. 0600,
  3952. psde->debugfs_root,
  3953. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3954. debugfs_create_u32("in_rot_max_height",
  3955. 0600,
  3956. psde->debugfs_root,
  3957. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  3958. }
  3959. debugfs_create_u32("xin_id",
  3960. 0400,
  3961. psde->debugfs_root,
  3962. (u32 *) &cfg->xin_id);
  3963. debugfs_create_x32("creq_vblank",
  3964. 0600,
  3965. psde->debugfs_root,
  3966. (u32 *) &sblk->creq_vblank);
  3967. debugfs_create_x32("danger_vblank",
  3968. 0600,
  3969. psde->debugfs_root,
  3970. (u32 *) &sblk->danger_vblank);
  3971. debugfs_create_file("disable_danger",
  3972. 0600,
  3973. psde->debugfs_root,
  3974. kms, &sde_plane_danger_enable);
  3975. return 0;
  3976. }
  3977. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3978. {
  3979. struct sde_plane *psde;
  3980. if (!plane)
  3981. return;
  3982. psde = to_sde_plane(plane);
  3983. debugfs_remove_recursive(psde->debugfs_root);
  3984. }
  3985. #else
  3986. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3987. {
  3988. return 0;
  3989. }
  3990. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3991. {
  3992. }
  3993. #endif
  3994. static int sde_plane_late_register(struct drm_plane *plane)
  3995. {
  3996. return _sde_plane_init_debugfs(plane);
  3997. }
  3998. static void sde_plane_early_unregister(struct drm_plane *plane)
  3999. {
  4000. _sde_plane_destroy_debugfs(plane);
  4001. }
  4002. static const struct drm_plane_funcs sde_plane_funcs = {
  4003. .update_plane = drm_atomic_helper_update_plane,
  4004. .disable_plane = drm_atomic_helper_disable_plane,
  4005. .destroy = sde_plane_destroy,
  4006. .atomic_set_property = sde_plane_atomic_set_property,
  4007. .atomic_get_property = sde_plane_atomic_get_property,
  4008. .reset = sde_plane_reset,
  4009. .atomic_duplicate_state = sde_plane_duplicate_state,
  4010. .atomic_destroy_state = sde_plane_destroy_state,
  4011. .late_register = sde_plane_late_register,
  4012. .early_unregister = sde_plane_early_unregister,
  4013. };
  4014. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  4015. .prepare_fb = sde_plane_prepare_fb,
  4016. .cleanup_fb = sde_plane_cleanup_fb,
  4017. .atomic_check = sde_plane_atomic_check,
  4018. .atomic_update = sde_plane_atomic_update,
  4019. };
  4020. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  4021. {
  4022. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  4023. }
  4024. bool is_sde_plane_virtual(struct drm_plane *plane)
  4025. {
  4026. return plane ? to_sde_plane(plane)->is_virtual : false;
  4027. }
  4028. /* initialize plane */
  4029. struct drm_plane *sde_plane_init(struct drm_device *dev,
  4030. uint32_t pipe, bool primary_plane,
  4031. unsigned long possible_crtcs, u32 master_plane_id)
  4032. {
  4033. struct drm_plane *plane = NULL, *master_plane = NULL;
  4034. const struct sde_format_extended *format_list;
  4035. struct sde_plane *psde;
  4036. struct msm_drm_private *priv;
  4037. struct sde_kms *kms;
  4038. enum drm_plane_type type;
  4039. struct sde_vbif_clk_client clk_client;
  4040. int ret = -EINVAL;
  4041. if (!dev) {
  4042. SDE_ERROR("[%u]device is NULL\n", pipe);
  4043. goto exit;
  4044. }
  4045. priv = dev->dev_private;
  4046. if (!priv) {
  4047. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4048. goto exit;
  4049. }
  4050. if (!priv->kms) {
  4051. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4052. goto exit;
  4053. }
  4054. kms = to_sde_kms(priv->kms);
  4055. if (!kms->catalog) {
  4056. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4057. goto exit;
  4058. }
  4059. /* create and zero local structure */
  4060. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4061. if (!psde) {
  4062. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4063. ret = -ENOMEM;
  4064. goto exit;
  4065. }
  4066. /* cache local stuff for later */
  4067. plane = &psde->base;
  4068. psde->pipe = pipe;
  4069. psde->is_virtual = (master_plane_id != 0);
  4070. INIT_LIST_HEAD(&psde->mplane_list);
  4071. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4072. if (master_plane) {
  4073. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4074. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4075. }
  4076. /* initialize underlying h/w driver */
  4077. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog, psde->is_virtual,
  4078. &clk_client);
  4079. if (IS_ERR(psde->pipe_hw)) {
  4080. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4081. ret = PTR_ERR(psde->pipe_hw);
  4082. goto clean_plane;
  4083. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4084. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4085. goto clean_sspp;
  4086. }
  4087. if (test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, kms->catalog->features)) {
  4088. ret = sde_vbif_clk_register(kms, &clk_client);
  4089. if (ret) {
  4090. SDE_ERROR("failed to register vbif client %d\n",
  4091. clk_client.clk_ctrl);
  4092. goto clean_sspp;
  4093. }
  4094. }
  4095. /* cache features mask for later */
  4096. psde->features = psde->pipe_hw->cap->features_ext;
  4097. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4098. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4099. if (!psde->pipe_sblk) {
  4100. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4101. goto clean_sspp;
  4102. }
  4103. if (psde->is_virtual)
  4104. format_list = psde->pipe_sblk->virt_format_list;
  4105. else
  4106. format_list = psde->pipe_sblk->format_list;
  4107. psde->nformats = sde_populate_formats(format_list,
  4108. psde->formats,
  4109. 0,
  4110. ARRAY_SIZE(psde->formats));
  4111. if (!psde->nformats) {
  4112. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4113. goto clean_sspp;
  4114. }
  4115. if (primary_plane)
  4116. type = DRM_PLANE_TYPE_PRIMARY;
  4117. else
  4118. type = DRM_PLANE_TYPE_OVERLAY;
  4119. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4120. psde->formats, psde->nformats,
  4121. NULL, type, NULL);
  4122. if (ret)
  4123. goto clean_sspp;
  4124. /* Populate static array of plane property flags */
  4125. _sde_plane_map_prop_to_dirty_bits();
  4126. /* success! finalize initialization */
  4127. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4128. msm_property_init(&psde->property_info, &plane->base, dev,
  4129. priv->plane_property, psde->property_data,
  4130. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4131. sizeof(struct sde_plane_state));
  4132. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4133. /* save user friendly pipe name for later */
  4134. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4135. mutex_init(&psde->lock);
  4136. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4137. pipe, plane->base.id, master_plane_id);
  4138. return plane;
  4139. clean_sspp:
  4140. if (psde && psde->pipe_hw)
  4141. sde_hw_sspp_destroy(psde->pipe_hw);
  4142. clean_plane:
  4143. kfree(psde);
  4144. exit:
  4145. return ERR_PTR(ret);
  4146. }
  4147. void sde_plane_add_data_to_minidump_va(struct drm_plane *plane)
  4148. {
  4149. struct sde_plane *sde_plane;
  4150. struct sde_plane_state *pstate;
  4151. sde_plane = to_sde_plane(plane);
  4152. pstate = to_sde_plane_state(plane->state);
  4153. sde_mini_dump_add_va_region("sde_plane", sizeof(*sde_plane), sde_plane);
  4154. sde_mini_dump_add_va_region("plane_state", sizeof(*pstate), pstate);
  4155. }