dp_tx.c 108 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #define DP_TX_QUEUE_MASK 0x3
  33. /* TODO Add support in TSO */
  34. #define DP_DESC_NUM_FRAG(x) 0
  35. /* disable TQM_BYPASS */
  36. #define TQM_BYPASS_WAR 0
  37. /* invalid peer id for reinject*/
  38. #define DP_INVALID_PEER 0XFFFE
  39. /*mapping between hal encrypt type and cdp_sec_type*/
  40. #define MAX_CDP_SEC_TYPE 12
  41. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  42. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  43. HAL_TX_ENCRYPT_TYPE_WEP_128,
  44. HAL_TX_ENCRYPT_TYPE_WEP_104,
  45. HAL_TX_ENCRYPT_TYPE_WEP_40,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  47. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  48. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  49. HAL_TX_ENCRYPT_TYPE_WAPI,
  50. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  52. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  53. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  54. /**
  55. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  56. * @vdev: DP Virtual device handle
  57. * @nbuf: Buffer pointer
  58. * @queue: queue ids container for nbuf
  59. *
  60. * TX packet queue has 2 instances, software descriptors id and dma ring id
  61. * Based on tx feature and hardware configuration queue id combination could be
  62. * different.
  63. * For example -
  64. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  65. * With no XPS,lock based resource protection, Descriptor pool ids are different
  66. * for each vdev, dma ring id will be same as single pdev id
  67. *
  68. * Return: None
  69. */
  70. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  71. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  72. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  73. {
  74. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  75. queue->desc_pool_id = queue_offset;
  76. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  77. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  78. "%s, pool_id:%d ring_id: %d",
  79. __func__, queue->desc_pool_id, queue->ring_id);
  80. return;
  81. }
  82. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #endif
  95. #if defined(FEATURE_TSO)
  96. /**
  97. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  98. *
  99. * @soc - core txrx main context
  100. * @seg_desc - tso segment descriptor
  101. * @num_seg_desc - tso number segment descriptor
  102. */
  103. static void dp_tx_tso_unmap_segment(
  104. struct dp_soc *soc,
  105. struct qdf_tso_seg_elem_t *seg_desc,
  106. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  107. {
  108. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  109. if (qdf_unlikely(!seg_desc)) {
  110. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  111. __func__, __LINE__);
  112. qdf_assert(0);
  113. } else if (qdf_unlikely(!num_seg_desc)) {
  114. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  115. __func__, __LINE__);
  116. qdf_assert(0);
  117. } else {
  118. bool is_last_seg;
  119. /* no tso segment left to do dma unmap */
  120. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  121. return;
  122. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  123. true : false;
  124. qdf_nbuf_unmap_tso_segment(soc->osdev,
  125. seg_desc, is_last_seg);
  126. num_seg_desc->num_seg.tso_cmn_num_seg--;
  127. }
  128. }
  129. /**
  130. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  131. * back to the freelist
  132. *
  133. * @soc - soc device handle
  134. * @tx_desc - Tx software descriptor
  135. */
  136. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  137. struct dp_tx_desc_s *tx_desc)
  138. {
  139. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  140. if (qdf_unlikely(!tx_desc->tso_desc)) {
  141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  142. "%s %d TSO desc is NULL!",
  143. __func__, __LINE__);
  144. qdf_assert(0);
  145. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  147. "%s %d TSO num desc is NULL!",
  148. __func__, __LINE__);
  149. qdf_assert(0);
  150. } else {
  151. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  152. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  153. /* Add the tso num segment into the free list */
  154. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  155. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  156. tx_desc->tso_num_desc);
  157. tx_desc->tso_num_desc = NULL;
  158. }
  159. /* Add the tso segment into the free list*/
  160. dp_tx_tso_desc_free(soc,
  161. tx_desc->pool_id, tx_desc->tso_desc);
  162. tx_desc->tso_desc = NULL;
  163. }
  164. }
  165. #else
  166. static void dp_tx_tso_unmap_segment(
  167. struct dp_soc *soc,
  168. struct qdf_tso_seg_elem_t *seg_desc,
  169. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  170. {
  171. }
  172. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  173. struct dp_tx_desc_s *tx_desc)
  174. {
  175. }
  176. #endif
  177. /**
  178. * dp_tx_desc_release() - Release Tx Descriptor
  179. * @tx_desc : Tx Descriptor
  180. * @desc_pool_id: Descriptor Pool ID
  181. *
  182. * Deallocate all resources attached to Tx descriptor and free the Tx
  183. * descriptor.
  184. *
  185. * Return:
  186. */
  187. static void
  188. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  189. {
  190. struct dp_pdev *pdev = tx_desc->pdev;
  191. struct dp_soc *soc;
  192. uint8_t comp_status = 0;
  193. qdf_assert(pdev);
  194. soc = pdev->soc;
  195. if (tx_desc->frm_type == dp_tx_frm_tso)
  196. dp_tx_tso_desc_release(soc, tx_desc);
  197. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  198. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  199. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  200. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  201. qdf_atomic_dec(&pdev->num_tx_outstanding);
  202. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  203. qdf_atomic_dec(&pdev->num_tx_exception);
  204. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  205. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  206. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  207. soc->hal_soc);
  208. else
  209. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  210. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  211. "Tx Completion Release desc %d status %d outstanding %d",
  212. tx_desc->id, comp_status,
  213. qdf_atomic_read(&pdev->num_tx_outstanding));
  214. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  215. return;
  216. }
  217. /**
  218. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  219. * @vdev: DP vdev Handle
  220. * @nbuf: skb
  221. *
  222. * Prepares and fills HTT metadata in the frame pre-header for special frames
  223. * that should be transmitted using varying transmit parameters.
  224. * There are 2 VDEV modes that currently needs this special metadata -
  225. * 1) Mesh Mode
  226. * 2) DSRC Mode
  227. *
  228. * Return: HTT metadata size
  229. *
  230. */
  231. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  232. uint32_t *meta_data)
  233. {
  234. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  235. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  236. uint8_t htt_desc_size;
  237. /* Size rounded of multiple of 8 bytes */
  238. uint8_t htt_desc_size_aligned;
  239. uint8_t *hdr = NULL;
  240. /*
  241. * Metadata - HTT MSDU Extension header
  242. */
  243. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  244. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  245. if (vdev->mesh_vdev) {
  246. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  247. htt_desc_size_aligned)) {
  248. DP_STATS_INC(vdev,
  249. tx_i.dropped.headroom_insufficient, 1);
  250. return 0;
  251. }
  252. /* Fill and add HTT metaheader */
  253. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  254. if (hdr == NULL) {
  255. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  256. "Error in filling HTT metadata");
  257. return 0;
  258. }
  259. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  260. } else if (vdev->opmode == wlan_op_mode_ocb) {
  261. /* Todo - Add support for DSRC */
  262. }
  263. return htt_desc_size_aligned;
  264. }
  265. /**
  266. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  267. * @tso_seg: TSO segment to process
  268. * @ext_desc: Pointer to MSDU extension descriptor
  269. *
  270. * Return: void
  271. */
  272. #if defined(FEATURE_TSO)
  273. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  274. void *ext_desc)
  275. {
  276. uint8_t num_frag;
  277. uint32_t tso_flags;
  278. /*
  279. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  280. * tcp_flag_mask
  281. *
  282. * Checksum enable flags are set in TCL descriptor and not in Extension
  283. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  284. */
  285. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  286. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  287. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  288. tso_seg->tso_flags.ip_len);
  289. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  290. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  291. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  292. uint32_t lo = 0;
  293. uint32_t hi = 0;
  294. qdf_dmaaddr_to_32s(
  295. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  296. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  297. tso_seg->tso_frags[num_frag].length);
  298. }
  299. return;
  300. }
  301. #else
  302. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  303. void *ext_desc)
  304. {
  305. return;
  306. }
  307. #endif
  308. #if defined(FEATURE_TSO)
  309. /**
  310. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  311. * allocated and free them
  312. *
  313. * @soc: soc handle
  314. * @free_seg: list of tso segments
  315. * @msdu_info: msdu descriptor
  316. *
  317. * Return - void
  318. */
  319. static void dp_tx_free_tso_seg_list(
  320. struct dp_soc *soc,
  321. struct qdf_tso_seg_elem_t *free_seg,
  322. struct dp_tx_msdu_info_s *msdu_info)
  323. {
  324. struct qdf_tso_seg_elem_t *next_seg;
  325. while (free_seg) {
  326. next_seg = free_seg->next;
  327. dp_tx_tso_desc_free(soc,
  328. msdu_info->tx_queue.desc_pool_id,
  329. free_seg);
  330. free_seg = next_seg;
  331. }
  332. }
  333. /**
  334. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  335. * allocated and free them
  336. *
  337. * @soc: soc handle
  338. * @free_num_seg: list of tso number segments
  339. * @msdu_info: msdu descriptor
  340. * Return - void
  341. */
  342. static void dp_tx_free_tso_num_seg_list(
  343. struct dp_soc *soc,
  344. struct qdf_tso_num_seg_elem_t *free_num_seg,
  345. struct dp_tx_msdu_info_s *msdu_info)
  346. {
  347. struct qdf_tso_num_seg_elem_t *next_num_seg;
  348. while (free_num_seg) {
  349. next_num_seg = free_num_seg->next;
  350. dp_tso_num_seg_free(soc,
  351. msdu_info->tx_queue.desc_pool_id,
  352. free_num_seg);
  353. free_num_seg = next_num_seg;
  354. }
  355. }
  356. /**
  357. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  358. * do dma unmap for each segment
  359. *
  360. * @soc: soc handle
  361. * @free_seg: list of tso segments
  362. * @num_seg_desc: tso number segment descriptor
  363. *
  364. * Return - void
  365. */
  366. static void dp_tx_unmap_tso_seg_list(
  367. struct dp_soc *soc,
  368. struct qdf_tso_seg_elem_t *free_seg,
  369. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  370. {
  371. struct qdf_tso_seg_elem_t *next_seg;
  372. if (qdf_unlikely(!num_seg_desc)) {
  373. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  374. return;
  375. }
  376. while (free_seg) {
  377. next_seg = free_seg->next;
  378. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  379. free_seg = next_seg;
  380. }
  381. }
  382. /**
  383. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  384. * free the tso segments descriptor and
  385. * tso num segments descriptor
  386. *
  387. * @soc: soc handle
  388. * @msdu_info: msdu descriptor
  389. * @tso_seg_unmap: flag to show if dma unmap is necessary
  390. *
  391. * Return - void
  392. */
  393. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  394. struct dp_tx_msdu_info_s *msdu_info,
  395. bool tso_seg_unmap)
  396. {
  397. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  398. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  399. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  400. tso_info->tso_num_seg_list;
  401. /* do dma unmap for each segment */
  402. if (tso_seg_unmap)
  403. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  404. /* free all tso number segment descriptor though looks only have 1 */
  405. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  406. /* free all tso segment descriptor */
  407. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  408. }
  409. /**
  410. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  411. * @vdev: virtual device handle
  412. * @msdu: network buffer
  413. * @msdu_info: meta data associated with the msdu
  414. *
  415. * Return: QDF_STATUS_SUCCESS success
  416. */
  417. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  418. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  419. {
  420. struct qdf_tso_seg_elem_t *tso_seg;
  421. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  422. struct dp_soc *soc = vdev->pdev->soc;
  423. struct qdf_tso_info_t *tso_info;
  424. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  425. tso_info = &msdu_info->u.tso_info;
  426. tso_info->curr_seg = NULL;
  427. tso_info->tso_seg_list = NULL;
  428. tso_info->num_segs = num_seg;
  429. msdu_info->frm_type = dp_tx_frm_tso;
  430. tso_info->tso_num_seg_list = NULL;
  431. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  432. while (num_seg) {
  433. tso_seg = dp_tx_tso_desc_alloc(
  434. soc, msdu_info->tx_queue.desc_pool_id);
  435. if (tso_seg) {
  436. tso_seg->next = tso_info->tso_seg_list;
  437. tso_info->tso_seg_list = tso_seg;
  438. num_seg--;
  439. } else {
  440. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  441. __func__);
  442. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  443. return QDF_STATUS_E_NOMEM;
  444. }
  445. }
  446. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  447. tso_num_seg = dp_tso_num_seg_alloc(soc,
  448. msdu_info->tx_queue.desc_pool_id);
  449. if (tso_num_seg) {
  450. tso_num_seg->next = tso_info->tso_num_seg_list;
  451. tso_info->tso_num_seg_list = tso_num_seg;
  452. } else {
  453. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  454. __func__);
  455. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  456. return QDF_STATUS_E_NOMEM;
  457. }
  458. msdu_info->num_seg =
  459. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  460. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  461. msdu_info->num_seg);
  462. if (!(msdu_info->num_seg)) {
  463. /*
  464. * Free allocated TSO seg desc and number seg desc,
  465. * do unmap for segments if dma map has done.
  466. */
  467. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  468. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  469. return QDF_STATUS_E_INVAL;
  470. }
  471. tso_info->curr_seg = tso_info->tso_seg_list;
  472. return QDF_STATUS_SUCCESS;
  473. }
  474. #else
  475. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  476. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  477. {
  478. return QDF_STATUS_E_NOMEM;
  479. }
  480. #endif
  481. /**
  482. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  483. * @vdev: DP Vdev handle
  484. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  485. * @desc_pool_id: Descriptor Pool ID
  486. *
  487. * Return:
  488. */
  489. static
  490. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  491. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  492. {
  493. uint8_t i;
  494. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  495. struct dp_tx_seg_info_s *seg_info;
  496. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  497. struct dp_soc *soc = vdev->pdev->soc;
  498. /* Allocate an extension descriptor */
  499. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  500. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  501. if (!msdu_ext_desc) {
  502. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  503. return NULL;
  504. }
  505. if (msdu_info->exception_fw &&
  506. qdf_unlikely(vdev->mesh_vdev)) {
  507. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  508. &msdu_info->meta_data[0],
  509. sizeof(struct htt_tx_msdu_desc_ext2_t));
  510. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  511. }
  512. switch (msdu_info->frm_type) {
  513. case dp_tx_frm_sg:
  514. case dp_tx_frm_me:
  515. case dp_tx_frm_raw:
  516. seg_info = msdu_info->u.sg_info.curr_seg;
  517. /* Update the buffer pointers in MSDU Extension Descriptor */
  518. for (i = 0; i < seg_info->frag_cnt; i++) {
  519. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  520. seg_info->frags[i].paddr_lo,
  521. seg_info->frags[i].paddr_hi,
  522. seg_info->frags[i].len);
  523. }
  524. break;
  525. case dp_tx_frm_tso:
  526. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  527. &cached_ext_desc[0]);
  528. break;
  529. default:
  530. break;
  531. }
  532. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  533. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  534. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  535. msdu_ext_desc->vaddr);
  536. return msdu_ext_desc;
  537. }
  538. /**
  539. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  540. *
  541. * @skb: skb to be traced
  542. * @msdu_id: msdu_id of the packet
  543. * @vdev_id: vdev_id of the packet
  544. *
  545. * Return: None
  546. */
  547. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  548. uint8_t vdev_id)
  549. {
  550. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  551. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  552. DPTRACE(qdf_dp_trace_ptr(skb,
  553. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  554. QDF_TRACE_DEFAULT_PDEV_ID,
  555. qdf_nbuf_data_addr(skb),
  556. sizeof(qdf_nbuf_data(skb)),
  557. msdu_id, vdev_id));
  558. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  559. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  560. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  561. msdu_id, QDF_TX));
  562. }
  563. /**
  564. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  565. * @vdev: DP vdev handle
  566. * @nbuf: skb
  567. * @desc_pool_id: Descriptor pool ID
  568. * @meta_data: Metadata to the fw
  569. * @tx_exc_metadata: Handle that holds exception path metadata
  570. * Allocate and prepare Tx descriptor with msdu information.
  571. *
  572. * Return: Pointer to Tx Descriptor on success,
  573. * NULL on failure
  574. */
  575. static
  576. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  577. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  578. struct dp_tx_msdu_info_s *msdu_info,
  579. struct cdp_tx_exception_metadata *tx_exc_metadata)
  580. {
  581. uint8_t align_pad;
  582. uint8_t is_exception = 0;
  583. uint8_t htt_hdr_size;
  584. struct ether_header *eh;
  585. struct dp_tx_desc_s *tx_desc;
  586. struct dp_pdev *pdev = vdev->pdev;
  587. struct dp_soc *soc = pdev->soc;
  588. /* Allocate software Tx descriptor */
  589. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  590. if (qdf_unlikely(!tx_desc)) {
  591. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  592. return NULL;
  593. }
  594. /* Flow control/Congestion Control counters */
  595. qdf_atomic_inc(&pdev->num_tx_outstanding);
  596. /* Initialize the SW tx descriptor */
  597. tx_desc->nbuf = nbuf;
  598. tx_desc->frm_type = dp_tx_frm_std;
  599. tx_desc->tx_encap_type = (tx_exc_metadata ?
  600. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  601. tx_desc->vdev = vdev;
  602. tx_desc->pdev = pdev;
  603. tx_desc->msdu_ext_desc = NULL;
  604. tx_desc->pkt_offset = 0;
  605. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  606. /*
  607. * For special modes (vdev_type == ocb or mesh), data frames should be
  608. * transmitted using varying transmit parameters (tx spec) which include
  609. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  610. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  611. * These frames are sent as exception packets to firmware.
  612. *
  613. * HW requirement is that metadata should always point to a
  614. * 8-byte aligned address. So we add alignment pad to start of buffer.
  615. * HTT Metadata should be ensured to be multiple of 8-bytes,
  616. * to get 8-byte aligned start address along with align_pad added
  617. *
  618. * |-----------------------------|
  619. * | |
  620. * |-----------------------------| <-----Buffer Pointer Address given
  621. * | | ^ in HW descriptor (aligned)
  622. * | HTT Metadata | |
  623. * | | |
  624. * | | | Packet Offset given in descriptor
  625. * | | |
  626. * |-----------------------------| |
  627. * | Alignment Pad | v
  628. * |-----------------------------| <----- Actual buffer start address
  629. * | SKB Data | (Unaligned)
  630. * | |
  631. * | |
  632. * | |
  633. * | |
  634. * | |
  635. * |-----------------------------|
  636. */
  637. if (qdf_unlikely((msdu_info->exception_fw)) ||
  638. (vdev->opmode == wlan_op_mode_ocb)) {
  639. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  640. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  641. DP_STATS_INC(vdev,
  642. tx_i.dropped.headroom_insufficient, 1);
  643. goto failure;
  644. }
  645. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  646. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  647. "qdf_nbuf_push_head failed");
  648. goto failure;
  649. }
  650. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  651. msdu_info->meta_data);
  652. if (htt_hdr_size == 0)
  653. goto failure;
  654. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  655. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  656. is_exception = 1;
  657. }
  658. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  659. qdf_nbuf_map(soc->osdev, nbuf,
  660. QDF_DMA_TO_DEVICE))) {
  661. /* Handle failure */
  662. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  663. "qdf_nbuf_map failed");
  664. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  665. goto failure;
  666. }
  667. if (qdf_unlikely(vdev->nawds_enabled)) {
  668. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  669. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  670. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  671. is_exception = 1;
  672. }
  673. }
  674. #if !TQM_BYPASS_WAR
  675. if (is_exception || tx_exc_metadata)
  676. #endif
  677. {
  678. /* Temporary WAR due to TQM VP issues */
  679. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  680. qdf_atomic_inc(&pdev->num_tx_exception);
  681. }
  682. return tx_desc;
  683. failure:
  684. dp_tx_desc_release(tx_desc, desc_pool_id);
  685. return NULL;
  686. }
  687. /**
  688. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  689. * @vdev: DP vdev handle
  690. * @nbuf: skb
  691. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  692. * @desc_pool_id : Descriptor Pool ID
  693. *
  694. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  695. * information. For frames wth fragments, allocate and prepare
  696. * an MSDU extension descriptor
  697. *
  698. * Return: Pointer to Tx Descriptor on success,
  699. * NULL on failure
  700. */
  701. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  702. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  703. uint8_t desc_pool_id)
  704. {
  705. struct dp_tx_desc_s *tx_desc;
  706. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  707. struct dp_pdev *pdev = vdev->pdev;
  708. struct dp_soc *soc = pdev->soc;
  709. /* Allocate software Tx descriptor */
  710. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  711. if (!tx_desc) {
  712. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  713. return NULL;
  714. }
  715. /* Flow control/Congestion Control counters */
  716. qdf_atomic_inc(&pdev->num_tx_outstanding);
  717. /* Initialize the SW tx descriptor */
  718. tx_desc->nbuf = nbuf;
  719. tx_desc->frm_type = msdu_info->frm_type;
  720. tx_desc->tx_encap_type = vdev->tx_encap_type;
  721. tx_desc->vdev = vdev;
  722. tx_desc->pdev = pdev;
  723. tx_desc->pkt_offset = 0;
  724. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  725. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  726. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  727. /* Handle scattered frames - TSO/SG/ME */
  728. /* Allocate and prepare an extension descriptor for scattered frames */
  729. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  730. if (!msdu_ext_desc) {
  731. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  732. "%s Tx Extension Descriptor Alloc Fail",
  733. __func__);
  734. goto failure;
  735. }
  736. #if TQM_BYPASS_WAR
  737. /* Temporary WAR due to TQM VP issues */
  738. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  739. qdf_atomic_inc(&pdev->num_tx_exception);
  740. #endif
  741. if (qdf_unlikely(msdu_info->exception_fw))
  742. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  743. tx_desc->msdu_ext_desc = msdu_ext_desc;
  744. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  745. return tx_desc;
  746. failure:
  747. dp_tx_desc_release(tx_desc, desc_pool_id);
  748. return NULL;
  749. }
  750. /**
  751. * dp_tx_prepare_raw() - Prepare RAW packet TX
  752. * @vdev: DP vdev handle
  753. * @nbuf: buffer pointer
  754. * @seg_info: Pointer to Segment info Descriptor to be prepared
  755. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  756. * descriptor
  757. *
  758. * Return:
  759. */
  760. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  761. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  762. {
  763. qdf_nbuf_t curr_nbuf = NULL;
  764. uint16_t total_len = 0;
  765. qdf_dma_addr_t paddr;
  766. int32_t i;
  767. int32_t mapped_buf_num = 0;
  768. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  769. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  770. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  771. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  772. if (vdev->raw_mode_war &&
  773. (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS))
  774. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  775. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  776. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  777. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  778. QDF_DMA_TO_DEVICE)) {
  779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  780. "%s dma map error ", __func__);
  781. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  782. mapped_buf_num = i;
  783. goto error;
  784. }
  785. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  786. seg_info->frags[i].paddr_lo = paddr;
  787. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  788. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  789. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  790. total_len += qdf_nbuf_len(curr_nbuf);
  791. }
  792. seg_info->frag_cnt = i;
  793. seg_info->total_len = total_len;
  794. seg_info->next = NULL;
  795. sg_info->curr_seg = seg_info;
  796. msdu_info->frm_type = dp_tx_frm_raw;
  797. msdu_info->num_seg = 1;
  798. return nbuf;
  799. error:
  800. i = 0;
  801. while (nbuf) {
  802. curr_nbuf = nbuf;
  803. if (i < mapped_buf_num) {
  804. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  805. i++;
  806. }
  807. nbuf = qdf_nbuf_next(nbuf);
  808. qdf_nbuf_free(curr_nbuf);
  809. }
  810. return NULL;
  811. }
  812. /**
  813. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  814. * @soc: DP Soc Handle
  815. * @vdev: DP vdev handle
  816. * @tx_desc: Tx Descriptor Handle
  817. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  818. * @fw_metadata: Metadata to send to Target Firmware along with frame
  819. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  820. * @tx_exc_metadata: Handle that holds exception path meta data
  821. *
  822. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  823. * from software Tx descriptor
  824. *
  825. * Return:
  826. */
  827. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  828. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  829. uint16_t fw_metadata, uint8_t ring_id,
  830. struct cdp_tx_exception_metadata
  831. *tx_exc_metadata)
  832. {
  833. uint8_t type;
  834. uint16_t length;
  835. void *hal_tx_desc, *hal_tx_desc_cached;
  836. qdf_dma_addr_t dma_addr;
  837. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  838. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  839. tx_exc_metadata->sec_type : vdev->sec_type);
  840. /* Return Buffer Manager ID */
  841. uint8_t bm_id = ring_id;
  842. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  843. hal_tx_desc_cached = (void *) cached_desc;
  844. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  845. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  846. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  847. type = HAL_TX_BUF_TYPE_EXT_DESC;
  848. dma_addr = tx_desc->msdu_ext_desc->paddr;
  849. } else {
  850. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  851. type = HAL_TX_BUF_TYPE_BUFFER;
  852. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  853. }
  854. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  855. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  856. dma_addr, bm_id, tx_desc->id,
  857. type, soc->hal_soc);
  858. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  859. return QDF_STATUS_E_RESOURCES;
  860. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  861. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  862. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  863. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  864. vdev->pdev->lmac_id);
  865. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  866. vdev->search_type);
  867. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  868. vdev->bss_ast_hash);
  869. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  870. vdev->dscp_tid_map_id);
  871. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  872. sec_type_map[sec_type]);
  873. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  874. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  875. __func__, length, type, (uint64_t)dma_addr,
  876. tx_desc->pkt_offset, tx_desc->id);
  877. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  878. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  879. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  880. vdev->hal_desc_addr_search_flags);
  881. /* verify checksum offload configuration*/
  882. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  883. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  884. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  885. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  886. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  887. }
  888. if (tid != HTT_TX_EXT_TID_INVALID)
  889. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  890. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  891. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  892. /* Sync cached descriptor with HW */
  893. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  894. if (!hal_tx_desc) {
  895. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  896. "%s TCL ring full ring_id:%d", __func__, ring_id);
  897. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  898. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  899. return QDF_STATUS_E_RESOURCES;
  900. }
  901. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  902. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  903. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  904. return QDF_STATUS_SUCCESS;
  905. }
  906. /**
  907. * dp_cce_classify() - Classify the frame based on CCE rules
  908. * @vdev: DP vdev handle
  909. * @nbuf: skb
  910. *
  911. * Classify frames based on CCE rules
  912. * Return: bool( true if classified,
  913. * else false)
  914. */
  915. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  916. {
  917. struct ether_header *eh = NULL;
  918. uint16_t ether_type;
  919. qdf_llc_t *llcHdr;
  920. qdf_nbuf_t nbuf_clone = NULL;
  921. qdf_dot3_qosframe_t *qos_wh = NULL;
  922. /* for mesh packets don't do any classification */
  923. if (qdf_unlikely(vdev->mesh_vdev))
  924. return false;
  925. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  926. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  927. ether_type = eh->ether_type;
  928. llcHdr = (qdf_llc_t *)(nbuf->data +
  929. sizeof(struct ether_header));
  930. } else {
  931. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  932. /* For encrypted packets don't do any classification */
  933. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  934. return false;
  935. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  936. if (qdf_unlikely(
  937. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  938. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  939. ether_type = *(uint16_t *)(nbuf->data
  940. + QDF_IEEE80211_4ADDR_HDR_LEN
  941. + sizeof(qdf_llc_t)
  942. - sizeof(ether_type));
  943. llcHdr = (qdf_llc_t *)(nbuf->data +
  944. QDF_IEEE80211_4ADDR_HDR_LEN);
  945. } else {
  946. ether_type = *(uint16_t *)(nbuf->data
  947. + QDF_IEEE80211_3ADDR_HDR_LEN
  948. + sizeof(qdf_llc_t)
  949. - sizeof(ether_type));
  950. llcHdr = (qdf_llc_t *)(nbuf->data +
  951. QDF_IEEE80211_3ADDR_HDR_LEN);
  952. }
  953. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  954. && (ether_type ==
  955. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  956. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  957. return true;
  958. }
  959. }
  960. return false;
  961. }
  962. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  963. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  964. sizeof(*llcHdr));
  965. nbuf_clone = qdf_nbuf_clone(nbuf);
  966. if (qdf_unlikely(nbuf_clone)) {
  967. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  968. if (ether_type == htons(ETHERTYPE_8021Q)) {
  969. qdf_nbuf_pull_head(nbuf_clone,
  970. sizeof(qdf_net_vlanhdr_t));
  971. }
  972. }
  973. } else {
  974. if (ether_type == htons(ETHERTYPE_8021Q)) {
  975. nbuf_clone = qdf_nbuf_clone(nbuf);
  976. if (qdf_unlikely(nbuf_clone)) {
  977. qdf_nbuf_pull_head(nbuf_clone,
  978. sizeof(qdf_net_vlanhdr_t));
  979. }
  980. }
  981. }
  982. if (qdf_unlikely(nbuf_clone))
  983. nbuf = nbuf_clone;
  984. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  985. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  986. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  987. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  988. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  989. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  990. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  991. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  992. if (qdf_unlikely(nbuf_clone != NULL))
  993. qdf_nbuf_free(nbuf_clone);
  994. return true;
  995. }
  996. if (qdf_unlikely(nbuf_clone != NULL))
  997. qdf_nbuf_free(nbuf_clone);
  998. return false;
  999. }
  1000. /**
  1001. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1002. * @vdev: DP vdev handle
  1003. * @nbuf: skb
  1004. *
  1005. * Extract the DSCP or PCP information from frame and map into TID value.
  1006. * Software based TID classification is required when more than 2 DSCP-TID
  1007. * mapping tables are needed.
  1008. * Hardware supports 2 DSCP-TID mapping tables
  1009. *
  1010. * Return: void
  1011. */
  1012. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1013. struct dp_tx_msdu_info_s *msdu_info)
  1014. {
  1015. uint8_t tos = 0, dscp_tid_override = 0;
  1016. uint8_t *hdr_ptr, *L3datap;
  1017. uint8_t is_mcast = 0;
  1018. struct ether_header *eh = NULL;
  1019. qdf_ethervlan_header_t *evh = NULL;
  1020. uint16_t ether_type;
  1021. qdf_llc_t *llcHdr;
  1022. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1023. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1024. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1025. return;
  1026. /* for mesh packets don't do any classification */
  1027. if (qdf_unlikely(vdev->mesh_vdev))
  1028. return;
  1029. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1030. eh = (struct ether_header *) nbuf->data;
  1031. hdr_ptr = eh->ether_dhost;
  1032. L3datap = hdr_ptr + sizeof(struct ether_header);
  1033. } else {
  1034. qdf_dot3_qosframe_t *qos_wh =
  1035. (qdf_dot3_qosframe_t *) nbuf->data;
  1036. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1037. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1038. return;
  1039. }
  1040. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1041. ether_type = eh->ether_type;
  1042. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  1043. /*
  1044. * Check if packet is dot3 or eth2 type.
  1045. */
  1046. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1047. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  1048. sizeof(*llcHdr));
  1049. if (ether_type == htons(ETHERTYPE_8021Q)) {
  1050. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1051. sizeof(*llcHdr);
  1052. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  1053. + sizeof(*llcHdr) +
  1054. sizeof(qdf_net_vlanhdr_t));
  1055. } else {
  1056. L3datap = hdr_ptr + sizeof(struct ether_header) +
  1057. sizeof(*llcHdr);
  1058. }
  1059. } else {
  1060. if (ether_type == htons(ETHERTYPE_8021Q)) {
  1061. evh = (qdf_ethervlan_header_t *) eh;
  1062. ether_type = evh->ether_type;
  1063. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1064. }
  1065. }
  1066. /*
  1067. * Find priority from IP TOS DSCP field
  1068. */
  1069. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1070. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1071. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1072. /* Only for unicast frames */
  1073. if (!is_mcast) {
  1074. /* send it on VO queue */
  1075. msdu_info->tid = DP_VO_TID;
  1076. }
  1077. } else {
  1078. /*
  1079. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1080. * from TOS byte.
  1081. */
  1082. tos = ip->ip_tos;
  1083. dscp_tid_override = 1;
  1084. }
  1085. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1086. /* TODO
  1087. * use flowlabel
  1088. *igmpmld cases to be handled in phase 2
  1089. */
  1090. unsigned long ver_pri_flowlabel;
  1091. unsigned long pri;
  1092. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1093. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1094. DP_IPV6_PRIORITY_SHIFT;
  1095. tos = pri;
  1096. dscp_tid_override = 1;
  1097. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1098. msdu_info->tid = DP_VO_TID;
  1099. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1100. /* Only for unicast frames */
  1101. if (!is_mcast) {
  1102. /* send ucast arp on VO queue */
  1103. msdu_info->tid = DP_VO_TID;
  1104. }
  1105. }
  1106. /*
  1107. * Assign all MCAST packets to BE
  1108. */
  1109. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1110. if (is_mcast) {
  1111. tos = 0;
  1112. dscp_tid_override = 1;
  1113. }
  1114. }
  1115. if (dscp_tid_override == 1) {
  1116. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1117. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1118. }
  1119. return;
  1120. }
  1121. #ifdef FEATURE_WLAN_TDLS
  1122. /**
  1123. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1124. * @tx_desc: TX descriptor
  1125. *
  1126. * Return: None
  1127. */
  1128. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1129. {
  1130. if (tx_desc->vdev) {
  1131. if (tx_desc->vdev->is_tdls_frame) {
  1132. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1133. tx_desc->vdev->is_tdls_frame = false;
  1134. }
  1135. }
  1136. }
  1137. /**
  1138. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1139. * @tx_desc: TX descriptor
  1140. * @vdev: datapath vdev handle
  1141. *
  1142. * Return: None
  1143. */
  1144. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1145. struct dp_vdev *vdev)
  1146. {
  1147. struct hal_tx_completion_status ts = {0};
  1148. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1149. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1150. if (vdev->tx_non_std_data_callback.func) {
  1151. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1152. vdev->tx_non_std_data_callback.func(
  1153. vdev->tx_non_std_data_callback.ctxt,
  1154. nbuf, ts.status);
  1155. return;
  1156. }
  1157. }
  1158. #else
  1159. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1160. {
  1161. }
  1162. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1163. struct dp_vdev *vdev)
  1164. {
  1165. }
  1166. #endif
  1167. /**
  1168. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1169. * @vdev: DP vdev handle
  1170. * @nbuf: skb
  1171. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1172. * @meta_data: Metadata to the fw
  1173. * @tx_q: Tx queue to be used for this Tx frame
  1174. * @peer_id: peer_id of the peer in case of NAWDS frames
  1175. * @tx_exc_metadata: Handle that holds exception path metadata
  1176. *
  1177. * Return: NULL on success,
  1178. * nbuf when it fails to send
  1179. */
  1180. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1181. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1182. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1183. {
  1184. struct dp_pdev *pdev = vdev->pdev;
  1185. struct dp_soc *soc = pdev->soc;
  1186. struct dp_tx_desc_s *tx_desc;
  1187. QDF_STATUS status;
  1188. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1189. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1190. uint16_t htt_tcl_metadata = 0;
  1191. uint8_t tid = msdu_info->tid;
  1192. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1193. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1194. msdu_info, tx_exc_metadata);
  1195. if (!tx_desc) {
  1196. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1197. "%s Tx_desc prepare Fail vdev %pK queue %d",
  1198. __func__, vdev, tx_q->desc_pool_id);
  1199. return nbuf;
  1200. }
  1201. if (qdf_unlikely(soc->cce_disable)) {
  1202. if (dp_cce_classify(vdev, nbuf) == true) {
  1203. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1204. tid = DP_VO_TID;
  1205. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1206. }
  1207. }
  1208. dp_tx_update_tdls_flags(tx_desc);
  1209. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1210. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1211. "%s %d : HAL RING Access Failed -- %pK",
  1212. __func__, __LINE__, hal_srng);
  1213. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1214. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1215. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1216. goto fail_return;
  1217. }
  1218. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1219. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1220. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1221. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1222. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1223. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1224. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1225. peer_id);
  1226. } else
  1227. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1228. if (msdu_info->exception_fw) {
  1229. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1230. }
  1231. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1232. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1233. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1234. if (status != QDF_STATUS_SUCCESS) {
  1235. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1236. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1237. __func__, tx_desc, tx_q->ring_id);
  1238. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1239. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1240. goto fail_return;
  1241. }
  1242. nbuf = NULL;
  1243. fail_return:
  1244. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1245. hal_srng_access_end(soc->hal_soc, hal_srng);
  1246. hif_pm_runtime_put(soc->hif_handle);
  1247. } else {
  1248. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1249. }
  1250. return nbuf;
  1251. }
  1252. /**
  1253. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1254. * @vdev: DP vdev handle
  1255. * @nbuf: skb
  1256. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1257. *
  1258. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1259. *
  1260. * Return: NULL on success,
  1261. * nbuf when it fails to send
  1262. */
  1263. #if QDF_LOCK_STATS
  1264. static noinline
  1265. #else
  1266. static
  1267. #endif
  1268. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1269. struct dp_tx_msdu_info_s *msdu_info)
  1270. {
  1271. uint8_t i;
  1272. struct dp_pdev *pdev = vdev->pdev;
  1273. struct dp_soc *soc = pdev->soc;
  1274. struct dp_tx_desc_s *tx_desc;
  1275. bool is_cce_classified = false;
  1276. QDF_STATUS status;
  1277. uint16_t htt_tcl_metadata = 0;
  1278. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1279. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1280. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1281. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1282. "%s %d : HAL RING Access Failed -- %pK",
  1283. __func__, __LINE__, hal_srng);
  1284. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1285. return nbuf;
  1286. }
  1287. if (qdf_unlikely(soc->cce_disable)) {
  1288. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1289. if (is_cce_classified) {
  1290. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1291. msdu_info->tid = DP_VO_TID;
  1292. }
  1293. }
  1294. if (msdu_info->frm_type == dp_tx_frm_me)
  1295. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1296. i = 0;
  1297. /* Print statement to track i and num_seg */
  1298. /*
  1299. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1300. * descriptors using information in msdu_info
  1301. */
  1302. while (i < msdu_info->num_seg) {
  1303. /*
  1304. * Setup Tx descriptor for an MSDU, and MSDU extension
  1305. * descriptor
  1306. */
  1307. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1308. tx_q->desc_pool_id);
  1309. if (!tx_desc) {
  1310. if (msdu_info->frm_type == dp_tx_frm_me) {
  1311. dp_tx_me_free_buf(pdev,
  1312. (void *)(msdu_info->u.sg_info
  1313. .curr_seg->frags[0].vaddr));
  1314. }
  1315. goto done;
  1316. }
  1317. if (msdu_info->frm_type == dp_tx_frm_me) {
  1318. tx_desc->me_buffer =
  1319. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1320. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1321. }
  1322. if (is_cce_classified)
  1323. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1324. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1325. if (msdu_info->exception_fw) {
  1326. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1327. }
  1328. /*
  1329. * Enqueue the Tx MSDU descriptor to HW for transmit
  1330. */
  1331. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1332. htt_tcl_metadata, tx_q->ring_id, NULL);
  1333. if (status != QDF_STATUS_SUCCESS) {
  1334. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1335. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1336. __func__, tx_desc, tx_q->ring_id);
  1337. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1338. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1339. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1340. goto done;
  1341. }
  1342. /*
  1343. * TODO
  1344. * if tso_info structure can be modified to have curr_seg
  1345. * as first element, following 2 blocks of code (for TSO and SG)
  1346. * can be combined into 1
  1347. */
  1348. /*
  1349. * For frames with multiple segments (TSO, ME), jump to next
  1350. * segment.
  1351. */
  1352. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1353. if (msdu_info->u.tso_info.curr_seg->next) {
  1354. msdu_info->u.tso_info.curr_seg =
  1355. msdu_info->u.tso_info.curr_seg->next;
  1356. /*
  1357. * If this is a jumbo nbuf, then increment the number of
  1358. * nbuf users for each additional segment of the msdu.
  1359. * This will ensure that the skb is freed only after
  1360. * receiving tx completion for all segments of an nbuf
  1361. */
  1362. qdf_nbuf_inc_users(nbuf);
  1363. /* Check with MCL if this is needed */
  1364. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1365. }
  1366. }
  1367. /*
  1368. * For Multicast-Unicast converted packets,
  1369. * each converted frame (for a client) is represented as
  1370. * 1 segment
  1371. */
  1372. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1373. (msdu_info->frm_type == dp_tx_frm_me)) {
  1374. if (msdu_info->u.sg_info.curr_seg->next) {
  1375. msdu_info->u.sg_info.curr_seg =
  1376. msdu_info->u.sg_info.curr_seg->next;
  1377. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1378. }
  1379. }
  1380. i++;
  1381. }
  1382. nbuf = NULL;
  1383. done:
  1384. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1385. hal_srng_access_end(soc->hal_soc, hal_srng);
  1386. hif_pm_runtime_put(soc->hif_handle);
  1387. } else {
  1388. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1389. }
  1390. return nbuf;
  1391. }
  1392. /**
  1393. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1394. * for SG frames
  1395. * @vdev: DP vdev handle
  1396. * @nbuf: skb
  1397. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1398. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1399. *
  1400. * Return: NULL on success,
  1401. * nbuf when it fails to send
  1402. */
  1403. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1404. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1405. {
  1406. uint32_t cur_frag, nr_frags;
  1407. qdf_dma_addr_t paddr;
  1408. struct dp_tx_sg_info_s *sg_info;
  1409. sg_info = &msdu_info->u.sg_info;
  1410. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1411. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1412. QDF_DMA_TO_DEVICE)) {
  1413. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1414. "dma map error");
  1415. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1416. qdf_nbuf_free(nbuf);
  1417. return NULL;
  1418. }
  1419. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1420. seg_info->frags[0].paddr_lo = paddr;
  1421. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1422. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1423. seg_info->frags[0].vaddr = (void *) nbuf;
  1424. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1425. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1426. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1427. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1428. "frag dma map error");
  1429. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1430. qdf_nbuf_free(nbuf);
  1431. return NULL;
  1432. }
  1433. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1434. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1435. seg_info->frags[cur_frag + 1].paddr_hi =
  1436. ((uint64_t) paddr) >> 32;
  1437. seg_info->frags[cur_frag + 1].len =
  1438. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1439. }
  1440. seg_info->frag_cnt = (cur_frag + 1);
  1441. seg_info->total_len = qdf_nbuf_len(nbuf);
  1442. seg_info->next = NULL;
  1443. sg_info->curr_seg = seg_info;
  1444. msdu_info->frm_type = dp_tx_frm_sg;
  1445. msdu_info->num_seg = 1;
  1446. return nbuf;
  1447. }
  1448. #ifdef MESH_MODE_SUPPORT
  1449. /**
  1450. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1451. and prepare msdu_info for mesh frames.
  1452. * @vdev: DP vdev handle
  1453. * @nbuf: skb
  1454. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1455. *
  1456. * Return: NULL on failure,
  1457. * nbuf when extracted successfully
  1458. */
  1459. static
  1460. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1461. struct dp_tx_msdu_info_s *msdu_info)
  1462. {
  1463. struct meta_hdr_s *mhdr;
  1464. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1465. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1466. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1467. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1468. msdu_info->exception_fw = 0;
  1469. goto remove_meta_hdr;
  1470. }
  1471. msdu_info->exception_fw = 1;
  1472. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1473. meta_data->host_tx_desc_pool = 1;
  1474. meta_data->update_peer_cache = 1;
  1475. meta_data->learning_frame = 1;
  1476. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1477. meta_data->power = mhdr->power;
  1478. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1479. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1480. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1481. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1482. meta_data->dyn_bw = 1;
  1483. meta_data->valid_pwr = 1;
  1484. meta_data->valid_mcs_mask = 1;
  1485. meta_data->valid_nss_mask = 1;
  1486. meta_data->valid_preamble_type = 1;
  1487. meta_data->valid_retries = 1;
  1488. meta_data->valid_bw_info = 1;
  1489. }
  1490. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1491. meta_data->encrypt_type = 0;
  1492. meta_data->valid_encrypt_type = 1;
  1493. meta_data->learning_frame = 0;
  1494. }
  1495. meta_data->valid_key_flags = 1;
  1496. meta_data->key_flags = (mhdr->keyix & 0x3);
  1497. remove_meta_hdr:
  1498. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1499. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1500. "qdf_nbuf_pull_head failed");
  1501. qdf_nbuf_free(nbuf);
  1502. return NULL;
  1503. }
  1504. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1505. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1506. else
  1507. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1508. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1509. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1510. " tid %d to_fw %d",
  1511. __func__, msdu_info->meta_data[0],
  1512. msdu_info->meta_data[1],
  1513. msdu_info->meta_data[2],
  1514. msdu_info->meta_data[3],
  1515. msdu_info->meta_data[4],
  1516. msdu_info->meta_data[5],
  1517. msdu_info->tid, msdu_info->exception_fw);
  1518. return nbuf;
  1519. }
  1520. #else
  1521. static
  1522. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1523. struct dp_tx_msdu_info_s *msdu_info)
  1524. {
  1525. return nbuf;
  1526. }
  1527. #endif
  1528. #ifdef DP_FEATURE_NAWDS_TX
  1529. /**
  1530. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1531. * @vdev: dp_vdev handle
  1532. * @nbuf: skb
  1533. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1534. * @tx_q: Tx queue to be used for this Tx frame
  1535. * @meta_data: Meta date for mesh
  1536. * @peer_id: peer_id of the peer in case of NAWDS frames
  1537. *
  1538. * return: NULL on success nbuf on failure
  1539. */
  1540. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1541. struct dp_tx_msdu_info_s *msdu_info)
  1542. {
  1543. struct dp_peer *peer = NULL;
  1544. struct dp_soc *soc = vdev->pdev->soc;
  1545. struct dp_ast_entry *ast_entry = NULL;
  1546. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1547. uint16_t peer_id = HTT_INVALID_PEER;
  1548. struct dp_peer *sa_peer = NULL;
  1549. qdf_nbuf_t nbuf_copy;
  1550. qdf_spin_lock_bh(&(soc->ast_lock));
  1551. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1552. (soc,
  1553. (uint8_t *)(eh->ether_shost),
  1554. vdev->pdev->pdev_id);
  1555. if (ast_entry)
  1556. sa_peer = ast_entry->peer;
  1557. qdf_spin_unlock_bh(&(soc->ast_lock));
  1558. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1559. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1560. (peer->nawds_enabled)) {
  1561. if (sa_peer == peer) {
  1562. QDF_TRACE(QDF_MODULE_ID_DP,
  1563. QDF_TRACE_LEVEL_DEBUG,
  1564. " %s: broadcast multicast packet",
  1565. __func__);
  1566. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1567. continue;
  1568. }
  1569. nbuf_copy = qdf_nbuf_copy(nbuf);
  1570. if (!nbuf_copy) {
  1571. QDF_TRACE(QDF_MODULE_ID_DP,
  1572. QDF_TRACE_LEVEL_ERROR,
  1573. "nbuf copy failed");
  1574. }
  1575. peer_id = peer->peer_ids[0];
  1576. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1577. msdu_info, peer_id, NULL);
  1578. if (nbuf_copy != NULL) {
  1579. qdf_nbuf_free(nbuf_copy);
  1580. continue;
  1581. }
  1582. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1583. 1, qdf_nbuf_len(nbuf));
  1584. }
  1585. }
  1586. if (peer_id == HTT_INVALID_PEER)
  1587. return nbuf;
  1588. return NULL;
  1589. }
  1590. #endif
  1591. /**
  1592. * dp_check_exc_metadata() - Checks if parameters are valid
  1593. * @tx_exc - holds all exception path parameters
  1594. *
  1595. * Returns true when all the parameters are valid else false
  1596. *
  1597. */
  1598. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1599. {
  1600. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1601. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1602. tx_exc->sec_type > cdp_num_sec_types) {
  1603. return false;
  1604. }
  1605. return true;
  1606. }
  1607. /**
  1608. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1609. * @vap_dev: DP vdev handle
  1610. * @nbuf: skb
  1611. * @tx_exc_metadata: Handle that holds exception path meta data
  1612. *
  1613. * Entry point for Core Tx layer (DP_TX) invoked from
  1614. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1615. *
  1616. * Return: NULL on success,
  1617. * nbuf when it fails to send
  1618. */
  1619. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1620. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1621. {
  1622. struct ether_header *eh = NULL;
  1623. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1624. struct dp_tx_msdu_info_s msdu_info;
  1625. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1626. msdu_info.tid = tx_exc_metadata->tid;
  1627. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1628. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1629. "%s , skb %pM",
  1630. __func__, nbuf->data);
  1631. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1632. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1633. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1634. "Invalid parameters in exception path");
  1635. goto fail;
  1636. }
  1637. /* Basic sanity checks for unsupported packets */
  1638. /* MESH mode */
  1639. if (qdf_unlikely(vdev->mesh_vdev)) {
  1640. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1641. "Mesh mode is not supported in exception path");
  1642. goto fail;
  1643. }
  1644. /* TSO or SG */
  1645. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1646. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1647. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1648. "TSO and SG are not supported in exception path");
  1649. goto fail;
  1650. }
  1651. /* RAW */
  1652. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1653. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1654. "Raw frame is not supported in exception path");
  1655. goto fail;
  1656. }
  1657. /* Mcast enhancement*/
  1658. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1659. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1660. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1661. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1662. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1663. }
  1664. }
  1665. /*
  1666. * Get HW Queue to use for this frame.
  1667. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1668. * dedicated for data and 1 for command.
  1669. * "queue_id" maps to one hardware ring.
  1670. * With each ring, we also associate a unique Tx descriptor pool
  1671. * to minimize lock contention for these resources.
  1672. */
  1673. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1674. /* Single linear frame */
  1675. /*
  1676. * If nbuf is a simple linear frame, use send_single function to
  1677. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1678. * SRNG. There is no need to setup a MSDU extension descriptor.
  1679. */
  1680. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1681. tx_exc_metadata->peer_id, tx_exc_metadata);
  1682. return nbuf;
  1683. fail:
  1684. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1685. "pkt send failed");
  1686. return nbuf;
  1687. }
  1688. /**
  1689. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1690. * @vap_dev: DP vdev handle
  1691. * @nbuf: skb
  1692. *
  1693. * Entry point for Core Tx layer (DP_TX) invoked from
  1694. * hard_start_xmit in OSIF/HDD
  1695. *
  1696. * Return: NULL on success,
  1697. * nbuf when it fails to send
  1698. */
  1699. #ifdef MESH_MODE_SUPPORT
  1700. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1701. {
  1702. struct meta_hdr_s *mhdr;
  1703. qdf_nbuf_t nbuf_mesh = NULL;
  1704. qdf_nbuf_t nbuf_clone = NULL;
  1705. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1706. uint8_t no_enc_frame = 0;
  1707. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1708. if (nbuf_mesh == NULL) {
  1709. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1710. "qdf_nbuf_unshare failed");
  1711. return nbuf;
  1712. }
  1713. nbuf = nbuf_mesh;
  1714. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1715. if ((vdev->sec_type != cdp_sec_type_none) &&
  1716. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1717. no_enc_frame = 1;
  1718. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1719. !no_enc_frame) {
  1720. nbuf_clone = qdf_nbuf_clone(nbuf);
  1721. if (nbuf_clone == NULL) {
  1722. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1723. "qdf_nbuf_clone failed");
  1724. return nbuf;
  1725. }
  1726. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1727. }
  1728. if (nbuf_clone) {
  1729. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1730. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1731. } else {
  1732. qdf_nbuf_free(nbuf_clone);
  1733. }
  1734. }
  1735. if (no_enc_frame)
  1736. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1737. else
  1738. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1739. nbuf = dp_tx_send(vap_dev, nbuf);
  1740. if ((nbuf == NULL) && no_enc_frame) {
  1741. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1742. }
  1743. return nbuf;
  1744. }
  1745. #else
  1746. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1747. {
  1748. return dp_tx_send(vap_dev, nbuf);
  1749. }
  1750. #endif
  1751. /**
  1752. * dp_tx_send() - Transmit a frame on a given VAP
  1753. * @vap_dev: DP vdev handle
  1754. * @nbuf: skb
  1755. *
  1756. * Entry point for Core Tx layer (DP_TX) invoked from
  1757. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1758. * cases
  1759. *
  1760. * Return: NULL on success,
  1761. * nbuf when it fails to send
  1762. */
  1763. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1764. {
  1765. struct ether_header *eh = NULL;
  1766. struct dp_tx_msdu_info_s msdu_info;
  1767. struct dp_tx_seg_info_s seg_info;
  1768. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1769. uint16_t peer_id = HTT_INVALID_PEER;
  1770. qdf_nbuf_t nbuf_mesh = NULL;
  1771. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1772. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1773. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1774. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1775. "%s , skb %pM",
  1776. __func__, nbuf->data);
  1777. /*
  1778. * Set Default Host TID value to invalid TID
  1779. * (TID override disabled)
  1780. */
  1781. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1782. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1783. if (qdf_unlikely(vdev->mesh_vdev)) {
  1784. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1785. &msdu_info);
  1786. if (nbuf_mesh == NULL) {
  1787. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1788. "Extracting mesh metadata failed");
  1789. return nbuf;
  1790. }
  1791. nbuf = nbuf_mesh;
  1792. }
  1793. /*
  1794. * Get HW Queue to use for this frame.
  1795. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1796. * dedicated for data and 1 for command.
  1797. * "queue_id" maps to one hardware ring.
  1798. * With each ring, we also associate a unique Tx descriptor pool
  1799. * to minimize lock contention for these resources.
  1800. */
  1801. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1802. /*
  1803. * TCL H/W supports 2 DSCP-TID mapping tables.
  1804. * Table 1 - Default DSCP-TID mapping table
  1805. * Table 2 - 1 DSCP-TID override table
  1806. *
  1807. * If we need a different DSCP-TID mapping for this vap,
  1808. * call tid_classify to extract DSCP/ToS from frame and
  1809. * map to a TID and store in msdu_info. This is later used
  1810. * to fill in TCL Input descriptor (per-packet TID override).
  1811. */
  1812. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1813. /*
  1814. * Classify the frame and call corresponding
  1815. * "prepare" function which extracts the segment (TSO)
  1816. * and fragmentation information (for TSO , SG, ME, or Raw)
  1817. * into MSDU_INFO structure which is later used to fill
  1818. * SW and HW descriptors.
  1819. */
  1820. if (qdf_nbuf_is_tso(nbuf)) {
  1821. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1822. "%s TSO frame %pK", __func__, vdev);
  1823. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1824. qdf_nbuf_len(nbuf));
  1825. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1826. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1827. qdf_nbuf_len(nbuf));
  1828. return nbuf;
  1829. }
  1830. goto send_multiple;
  1831. }
  1832. /* SG */
  1833. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1834. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1835. if (!nbuf)
  1836. return NULL;
  1837. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1838. "%s non-TSO SG frame %pK", __func__, vdev);
  1839. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1840. qdf_nbuf_len(nbuf));
  1841. goto send_multiple;
  1842. }
  1843. #ifdef ATH_SUPPORT_IQUE
  1844. /* Mcast to Ucast Conversion*/
  1845. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1846. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1847. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1848. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1849. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1850. "%s Mcast frm for ME %pK", __func__, vdev);
  1851. DP_STATS_INC_PKT(vdev,
  1852. tx_i.mcast_en.mcast_pkt, 1,
  1853. qdf_nbuf_len(nbuf));
  1854. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1855. QDF_STATUS_SUCCESS) {
  1856. return NULL;
  1857. }
  1858. }
  1859. }
  1860. #endif
  1861. /* RAW */
  1862. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1863. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1864. if (nbuf == NULL)
  1865. return NULL;
  1866. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1867. "%s Raw frame %pK", __func__, vdev);
  1868. goto send_multiple;
  1869. }
  1870. /* Single linear frame */
  1871. /*
  1872. * If nbuf is a simple linear frame, use send_single function to
  1873. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1874. * SRNG. There is no need to setup a MSDU extension descriptor.
  1875. */
  1876. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1877. return nbuf;
  1878. send_multiple:
  1879. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1880. return nbuf;
  1881. }
  1882. /**
  1883. * dp_tx_reinject_handler() - Tx Reinject Handler
  1884. * @tx_desc: software descriptor head pointer
  1885. * @status : Tx completion status from HTT descriptor
  1886. *
  1887. * This function reinjects frames back to Target.
  1888. * Todo - Host queue needs to be added
  1889. *
  1890. * Return: none
  1891. */
  1892. static
  1893. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1894. {
  1895. struct dp_vdev *vdev;
  1896. struct dp_peer *peer = NULL;
  1897. uint32_t peer_id = HTT_INVALID_PEER;
  1898. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1899. qdf_nbuf_t nbuf_copy = NULL;
  1900. struct dp_tx_msdu_info_s msdu_info;
  1901. struct dp_peer *sa_peer = NULL;
  1902. struct dp_ast_entry *ast_entry = NULL;
  1903. struct dp_soc *soc = NULL;
  1904. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1905. #ifdef WDS_VENDOR_EXTENSION
  1906. int is_mcast = 0, is_ucast = 0;
  1907. int num_peers_3addr = 0;
  1908. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1909. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1910. #endif
  1911. vdev = tx_desc->vdev;
  1912. soc = vdev->pdev->soc;
  1913. qdf_assert(vdev);
  1914. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1915. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1916. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1917. "%s Tx reinject path", __func__);
  1918. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1919. qdf_nbuf_len(tx_desc->nbuf));
  1920. qdf_spin_lock_bh(&(soc->ast_lock));
  1921. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1922. (soc,
  1923. (uint8_t *)(eh->ether_shost),
  1924. vdev->pdev->pdev_id);
  1925. if (ast_entry)
  1926. sa_peer = ast_entry->peer;
  1927. qdf_spin_unlock_bh(&(soc->ast_lock));
  1928. #ifdef WDS_VENDOR_EXTENSION
  1929. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1930. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1931. } else {
  1932. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1933. }
  1934. is_ucast = !is_mcast;
  1935. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1936. if (peer->bss_peer)
  1937. continue;
  1938. /* Detect wds peers that use 3-addr framing for mcast.
  1939. * if there are any, the bss_peer is used to send the
  1940. * the mcast frame using 3-addr format. all wds enabled
  1941. * peers that use 4-addr framing for mcast frames will
  1942. * be duplicated and sent as 4-addr frames below.
  1943. */
  1944. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1945. num_peers_3addr = 1;
  1946. break;
  1947. }
  1948. }
  1949. #endif
  1950. if (qdf_unlikely(vdev->mesh_vdev)) {
  1951. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1952. } else {
  1953. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1954. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1955. #ifdef WDS_VENDOR_EXTENSION
  1956. /*
  1957. * . if 3-addr STA, then send on BSS Peer
  1958. * . if Peer WDS enabled and accept 4-addr mcast,
  1959. * send mcast on that peer only
  1960. * . if Peer WDS enabled and accept 4-addr ucast,
  1961. * send ucast on that peer only
  1962. */
  1963. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1964. (peer->wds_enabled &&
  1965. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1966. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1967. #else
  1968. ((peer->bss_peer &&
  1969. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1970. peer->nawds_enabled)) {
  1971. #endif
  1972. peer_id = DP_INVALID_PEER;
  1973. if (peer->nawds_enabled) {
  1974. peer_id = peer->peer_ids[0];
  1975. if (sa_peer == peer) {
  1976. QDF_TRACE(
  1977. QDF_MODULE_ID_DP,
  1978. QDF_TRACE_LEVEL_DEBUG,
  1979. " %s: multicast packet",
  1980. __func__);
  1981. DP_STATS_INC(peer,
  1982. tx.nawds_mcast_drop, 1);
  1983. continue;
  1984. }
  1985. }
  1986. nbuf_copy = qdf_nbuf_copy(nbuf);
  1987. if (!nbuf_copy) {
  1988. QDF_TRACE(QDF_MODULE_ID_DP,
  1989. QDF_TRACE_LEVEL_DEBUG,
  1990. FL("nbuf copy failed"));
  1991. break;
  1992. }
  1993. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1994. nbuf_copy,
  1995. &msdu_info,
  1996. peer_id,
  1997. NULL);
  1998. if (nbuf_copy) {
  1999. QDF_TRACE(QDF_MODULE_ID_DP,
  2000. QDF_TRACE_LEVEL_DEBUG,
  2001. FL("pkt send failed"));
  2002. qdf_nbuf_free(nbuf_copy);
  2003. } else {
  2004. if (peer_id != DP_INVALID_PEER)
  2005. DP_STATS_INC_PKT(peer,
  2006. tx.nawds_mcast,
  2007. 1, qdf_nbuf_len(nbuf));
  2008. }
  2009. }
  2010. }
  2011. }
  2012. if (vdev->nawds_enabled) {
  2013. peer_id = DP_INVALID_PEER;
  2014. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2015. 1, qdf_nbuf_len(nbuf));
  2016. nbuf = dp_tx_send_msdu_single(vdev,
  2017. nbuf,
  2018. &msdu_info,
  2019. peer_id, NULL);
  2020. if (nbuf) {
  2021. QDF_TRACE(QDF_MODULE_ID_DP,
  2022. QDF_TRACE_LEVEL_DEBUG,
  2023. FL("pkt send failed"));
  2024. qdf_nbuf_free(nbuf);
  2025. }
  2026. } else
  2027. qdf_nbuf_free(nbuf);
  2028. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2029. }
  2030. /**
  2031. * dp_tx_inspect_handler() - Tx Inspect Handler
  2032. * @tx_desc: software descriptor head pointer
  2033. * @status : Tx completion status from HTT descriptor
  2034. *
  2035. * Handles Tx frames sent back to Host for inspection
  2036. * (ProxyARP)
  2037. *
  2038. * Return: none
  2039. */
  2040. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2041. {
  2042. struct dp_soc *soc;
  2043. struct dp_pdev *pdev = tx_desc->pdev;
  2044. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2045. "%s Tx inspect path",
  2046. __func__);
  2047. qdf_assert(pdev);
  2048. soc = pdev->soc;
  2049. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2050. qdf_nbuf_len(tx_desc->nbuf));
  2051. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2052. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2053. }
  2054. #ifdef FEATURE_PERPKT_INFO
  2055. /**
  2056. * dp_get_completion_indication_for_stack() - send completion to stack
  2057. * @soc : dp_soc handle
  2058. * @pdev: dp_pdev handle
  2059. * @peer: dp peer handle
  2060. * @ts: transmit completion status structure
  2061. * @netbuf: Buffer pointer for free
  2062. *
  2063. * This function is used for indication whether buffer needs to be
  2064. * sent to stack for freeing or not
  2065. */
  2066. QDF_STATUS
  2067. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2068. struct dp_pdev *pdev,
  2069. struct dp_peer *peer,
  2070. struct hal_tx_completion_status *ts,
  2071. qdf_nbuf_t netbuf)
  2072. {
  2073. struct tx_capture_hdr *ppdu_hdr;
  2074. uint16_t peer_id = ts->peer_id;
  2075. uint32_t ppdu_id = ts->ppdu_id;
  2076. uint8_t first_msdu = ts->first_msdu;
  2077. uint8_t last_msdu = ts->last_msdu;
  2078. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  2079. return QDF_STATUS_E_NOSUPPORT;
  2080. if (!peer) {
  2081. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2082. FL("Peer Invalid"));
  2083. return QDF_STATUS_E_INVAL;
  2084. }
  2085. if (pdev->mcopy_mode) {
  2086. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2087. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2088. return QDF_STATUS_E_INVAL;
  2089. }
  2090. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2091. pdev->m_copy_id.tx_peer_id = peer_id;
  2092. }
  2093. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2094. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2095. FL("No headroom"));
  2096. return QDF_STATUS_E_NOMEM;
  2097. }
  2098. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2099. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2100. IEEE80211_ADDR_LEN);
  2101. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2102. IEEE80211_ADDR_LEN);
  2103. ppdu_hdr->ppdu_id = ppdu_id;
  2104. ppdu_hdr->peer_id = peer_id;
  2105. ppdu_hdr->first_msdu = first_msdu;
  2106. ppdu_hdr->last_msdu = last_msdu;
  2107. return QDF_STATUS_SUCCESS;
  2108. }
  2109. /**
  2110. * dp_send_completion_to_stack() - send completion to stack
  2111. * @soc : dp_soc handle
  2112. * @pdev: dp_pdev handle
  2113. * @peer_id: peer_id of the peer for which completion came
  2114. * @ppdu_id: ppdu_id
  2115. * @netbuf: Buffer pointer for free
  2116. *
  2117. * This function is used to send completion to stack
  2118. * to free buffer
  2119. */
  2120. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2121. uint16_t peer_id, uint32_t ppdu_id,
  2122. qdf_nbuf_t netbuf)
  2123. {
  2124. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2125. netbuf, peer_id,
  2126. WDI_NO_VAL, pdev->pdev_id);
  2127. }
  2128. #else
  2129. static QDF_STATUS
  2130. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2131. struct dp_pdev *pdev,
  2132. struct dp_peer *peer,
  2133. struct hal_tx_completion_status *ts,
  2134. qdf_nbuf_t netbuf)
  2135. {
  2136. return QDF_STATUS_E_NOSUPPORT;
  2137. }
  2138. static void
  2139. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2140. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2141. {
  2142. }
  2143. #endif
  2144. /**
  2145. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2146. * @soc: Soc handle
  2147. * @desc: software Tx descriptor to be processed
  2148. *
  2149. * Return: none
  2150. */
  2151. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2152. struct dp_tx_desc_s *desc)
  2153. {
  2154. struct dp_vdev *vdev = desc->vdev;
  2155. qdf_nbuf_t nbuf = desc->nbuf;
  2156. /* If it is TDLS mgmt, don't unmap or free the frame */
  2157. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2158. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2159. /* 0 : MSDU buffer, 1 : MLE */
  2160. if (desc->msdu_ext_desc) {
  2161. /* TSO free */
  2162. if (hal_tx_ext_desc_get_tso_enable(
  2163. desc->msdu_ext_desc->vaddr)) {
  2164. /* unmap eash TSO seg before free the nbuf */
  2165. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2166. desc->tso_num_desc);
  2167. qdf_nbuf_free(nbuf);
  2168. return;
  2169. }
  2170. }
  2171. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2172. if (qdf_likely(!vdev->mesh_vdev))
  2173. qdf_nbuf_free(nbuf);
  2174. else {
  2175. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2176. qdf_nbuf_free(nbuf);
  2177. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2178. } else
  2179. vdev->osif_tx_free_ext((nbuf));
  2180. }
  2181. }
  2182. /**
  2183. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2184. * @vdev: pointer to dp dev handler
  2185. * @status : Tx completion status from HTT descriptor
  2186. *
  2187. * Handles MEC notify event sent from fw to Host
  2188. *
  2189. * Return: none
  2190. */
  2191. #ifdef FEATURE_WDS
  2192. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2193. {
  2194. struct dp_soc *soc;
  2195. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2196. struct dp_peer *peer;
  2197. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2198. if (!vdev->mec_enabled)
  2199. return;
  2200. /* MEC required only in STA mode */
  2201. if (vdev->opmode != wlan_op_mode_sta)
  2202. return;
  2203. soc = vdev->pdev->soc;
  2204. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2205. peer = TAILQ_FIRST(&vdev->peer_list);
  2206. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2207. if (!peer) {
  2208. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2209. FL("peer is NULL"));
  2210. return;
  2211. }
  2212. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2213. "%s Tx MEC Handler",
  2214. __func__);
  2215. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2216. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2217. status[(DP_MAC_ADDR_LEN - 2) + i];
  2218. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2219. dp_peer_add_ast(soc,
  2220. peer,
  2221. mac_addr,
  2222. CDP_TXRX_AST_TYPE_MEC,
  2223. flags);
  2224. }
  2225. #endif
  2226. #ifdef MESH_MODE_SUPPORT
  2227. /**
  2228. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2229. * in mesh meta header
  2230. * @tx_desc: software descriptor head pointer
  2231. * @ts: pointer to tx completion stats
  2232. * Return: none
  2233. */
  2234. static
  2235. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2236. struct hal_tx_completion_status *ts)
  2237. {
  2238. struct meta_hdr_s *mhdr;
  2239. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2240. if (!tx_desc->msdu_ext_desc) {
  2241. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2242. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2243. "netbuf %pK offset %d",
  2244. netbuf, tx_desc->pkt_offset);
  2245. return;
  2246. }
  2247. }
  2248. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2249. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2250. "netbuf %pK offset %d", netbuf,
  2251. sizeof(struct meta_hdr_s));
  2252. return;
  2253. }
  2254. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2255. mhdr->rssi = ts->ack_frame_rssi;
  2256. mhdr->channel = tx_desc->pdev->operating_channel;
  2257. }
  2258. #else
  2259. static
  2260. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2261. struct hal_tx_completion_status *ts)
  2262. {
  2263. }
  2264. #endif
  2265. /**
  2266. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2267. * @peer: Handle to DP peer
  2268. * @ts: pointer to HAL Tx completion stats
  2269. *
  2270. * Return: None
  2271. */
  2272. static inline void
  2273. dp_tx_update_peer_stats(struct dp_peer *peer,
  2274. struct hal_tx_completion_status *ts, uint32_t length)
  2275. {
  2276. struct dp_pdev *pdev = peer->vdev->pdev;
  2277. struct dp_soc *soc = NULL;
  2278. uint8_t mcs, pkt_type;
  2279. if (!pdev)
  2280. return;
  2281. soc = pdev->soc;
  2282. mcs = ts->mcs;
  2283. pkt_type = ts->pkt_type;
  2284. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2285. dp_err("Release source is not from TQM");
  2286. return;
  2287. }
  2288. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2289. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2290. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2291. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2292. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2293. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2294. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2295. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2296. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2297. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2298. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2299. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2300. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2301. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2302. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2303. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2304. return;
  2305. }
  2306. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2307. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2308. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2309. /*
  2310. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2311. * Return from here if HTT PPDU events are enabled.
  2312. */
  2313. if (!(soc->process_tx_status))
  2314. return;
  2315. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2316. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2317. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2318. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2319. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2320. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2321. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2322. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2323. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2324. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2325. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2326. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2327. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2328. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2329. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2330. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2331. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2332. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2333. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2334. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2335. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2336. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2337. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2338. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2339. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2340. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2341. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2342. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2343. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2344. &peer->stats, ts->peer_id,
  2345. UPDATE_PEER_STATS, pdev->pdev_id);
  2346. #endif
  2347. }
  2348. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2349. /**
  2350. * dp_tx_flow_pool_lock() - take flow pool lock
  2351. * @soc: core txrx main context
  2352. * @tx_desc: tx desc
  2353. *
  2354. * Return: None
  2355. */
  2356. static inline
  2357. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2358. struct dp_tx_desc_s *tx_desc)
  2359. {
  2360. struct dp_tx_desc_pool_s *pool;
  2361. uint8_t desc_pool_id;
  2362. desc_pool_id = tx_desc->pool_id;
  2363. pool = &soc->tx_desc[desc_pool_id];
  2364. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2365. }
  2366. /**
  2367. * dp_tx_flow_pool_unlock() - release flow pool lock
  2368. * @soc: core txrx main context
  2369. * @tx_desc: tx desc
  2370. *
  2371. * Return: None
  2372. */
  2373. static inline
  2374. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2375. struct dp_tx_desc_s *tx_desc)
  2376. {
  2377. struct dp_tx_desc_pool_s *pool;
  2378. uint8_t desc_pool_id;
  2379. desc_pool_id = tx_desc->pool_id;
  2380. pool = &soc->tx_desc[desc_pool_id];
  2381. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2382. }
  2383. #else
  2384. static inline
  2385. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2386. {
  2387. }
  2388. static inline
  2389. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2390. {
  2391. }
  2392. #endif
  2393. /**
  2394. * dp_tx_notify_completion() - Notify tx completion for this desc
  2395. * @soc: core txrx main context
  2396. * @tx_desc: tx desc
  2397. * @netbuf: buffer
  2398. *
  2399. * Return: none
  2400. */
  2401. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2402. struct dp_tx_desc_s *tx_desc,
  2403. qdf_nbuf_t netbuf)
  2404. {
  2405. void *osif_dev;
  2406. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2407. qdf_assert(tx_desc);
  2408. dp_tx_flow_pool_lock(soc, tx_desc);
  2409. if (!tx_desc->vdev ||
  2410. !tx_desc->vdev->osif_vdev) {
  2411. dp_tx_flow_pool_unlock(soc, tx_desc);
  2412. return;
  2413. }
  2414. osif_dev = tx_desc->vdev->osif_vdev;
  2415. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2416. dp_tx_flow_pool_unlock(soc, tx_desc);
  2417. if (tx_compl_cbk)
  2418. tx_compl_cbk(netbuf, osif_dev);
  2419. }
  2420. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2421. * @pdev: pdev handle
  2422. * @tid: tid value
  2423. * @txdesc_ts: timestamp from txdesc
  2424. * @ppdu_id: ppdu id
  2425. *
  2426. * Return: none
  2427. */
  2428. #ifdef FEATURE_PERPKT_INFO
  2429. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2430. uint8_t tid,
  2431. uint64_t txdesc_ts,
  2432. uint32_t ppdu_id)
  2433. {
  2434. uint64_t delta_ms;
  2435. struct cdp_tx_sojourn_stats *sojourn_stats;
  2436. if (pdev->enhanced_stats_en == 0)
  2437. return;
  2438. if (pdev->sojourn_stats.ppdu_seq_id == 0)
  2439. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2440. if (ppdu_id != pdev->sojourn_stats.ppdu_seq_id) {
  2441. if (!pdev->sojourn_buf)
  2442. return;
  2443. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2444. qdf_nbuf_data(pdev->sojourn_buf);
  2445. qdf_mem_copy(sojourn_stats, &pdev->sojourn_stats,
  2446. sizeof(struct cdp_tx_sojourn_stats));
  2447. qdf_mem_zero(&pdev->sojourn_stats,
  2448. sizeof(struct cdp_tx_sojourn_stats));
  2449. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2450. pdev->sojourn_buf, HTT_INVALID_PEER,
  2451. WDI_NO_VAL, pdev->pdev_id);
  2452. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2453. }
  2454. if (tid == HTT_INVALID_TID)
  2455. return;
  2456. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2457. txdesc_ts;
  2458. qdf_ewma_tx_lag_add(&pdev->sojourn_stats.avg_sojourn_msdu[tid],
  2459. delta_ms);
  2460. pdev->sojourn_stats.sum_sojourn_msdu[tid] += delta_ms;
  2461. pdev->sojourn_stats.num_msdus[tid]++;
  2462. }
  2463. #else
  2464. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2465. uint8_t tid,
  2466. uint64_t txdesc_ts,
  2467. uint32_t ppdu_id)
  2468. {
  2469. }
  2470. #endif
  2471. /**
  2472. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2473. * @soc: DP Soc handle
  2474. * @tx_desc: software Tx descriptor
  2475. * @ts : Tx completion status from HAL/HTT descriptor
  2476. *
  2477. * Return: none
  2478. */
  2479. static inline void
  2480. dp_tx_comp_process_desc(struct dp_soc *soc,
  2481. struct dp_tx_desc_s *desc,
  2482. struct hal_tx_completion_status *ts,
  2483. struct dp_peer *peer)
  2484. {
  2485. /*
  2486. * m_copy/tx_capture modes are not supported for
  2487. * scatter gather packets
  2488. */
  2489. if (!(desc->msdu_ext_desc) &&
  2490. (dp_get_completion_indication_for_stack(soc, desc->pdev,
  2491. peer, ts, desc->nbuf)
  2492. == QDF_STATUS_SUCCESS)) {
  2493. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2494. QDF_DMA_TO_DEVICE);
  2495. dp_send_completion_to_stack(soc, desc->pdev, ts->peer_id,
  2496. ts->ppdu_id, desc->nbuf);
  2497. } else {
  2498. dp_tx_comp_free_buf(soc, desc);
  2499. }
  2500. }
  2501. /**
  2502. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2503. * @tx_desc: software descriptor head pointer
  2504. * @ts: Tx completion status
  2505. * @peer: peer handle
  2506. *
  2507. * Return: none
  2508. */
  2509. static inline
  2510. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2511. struct hal_tx_completion_status *ts,
  2512. struct dp_peer *peer)
  2513. {
  2514. uint32_t length;
  2515. struct dp_soc *soc = NULL;
  2516. struct dp_vdev *vdev = tx_desc->vdev;
  2517. struct ether_header *eh =
  2518. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2519. if (!vdev) {
  2520. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2521. "invalid vdev");
  2522. goto out;
  2523. }
  2524. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2525. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2526. QDF_TRACE_DEFAULT_PDEV_ID,
  2527. qdf_nbuf_data_addr(tx_desc->nbuf),
  2528. sizeof(qdf_nbuf_data(tx_desc->nbuf)),
  2529. tx_desc->id,
  2530. ts->status));
  2531. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2532. "-------------------- \n"
  2533. "Tx Completion Stats: \n"
  2534. "-------------------- \n"
  2535. "ack_frame_rssi = %d \n"
  2536. "first_msdu = %d \n"
  2537. "last_msdu = %d \n"
  2538. "msdu_part_of_amsdu = %d \n"
  2539. "rate_stats valid = %d \n"
  2540. "bw = %d \n"
  2541. "pkt_type = %d \n"
  2542. "stbc = %d \n"
  2543. "ldpc = %d \n"
  2544. "sgi = %d \n"
  2545. "mcs = %d \n"
  2546. "ofdma = %d \n"
  2547. "tones_in_ru = %d \n"
  2548. "tsf = %d \n"
  2549. "ppdu_id = %d \n"
  2550. "transmit_cnt = %d \n"
  2551. "tid = %d \n"
  2552. "peer_id = %d\n",
  2553. ts->ack_frame_rssi, ts->first_msdu,
  2554. ts->last_msdu, ts->msdu_part_of_amsdu,
  2555. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2556. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2557. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2558. ts->transmit_cnt, ts->tid, ts->peer_id);
  2559. soc = vdev->pdev->soc;
  2560. /* Update SoC level stats */
  2561. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2562. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2563. /* Update per-packet stats for mesh mode */
  2564. if (qdf_unlikely(vdev->mesh_vdev) &&
  2565. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2566. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2567. length = qdf_nbuf_len(tx_desc->nbuf);
  2568. /* Update peer level stats */
  2569. if (!peer) {
  2570. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2571. "peer is null or deletion in progress");
  2572. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2573. goto out;
  2574. }
  2575. if (qdf_likely(!peer->bss_peer)) {
  2576. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2577. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2578. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2579. } else {
  2580. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2581. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2582. if ((peer->vdev->tx_encap_type ==
  2583. htt_cmn_pkt_type_ethernet) &&
  2584. IEEE80211_IS_BROADCAST(eh->ether_dhost)) {
  2585. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2586. }
  2587. }
  2588. }
  2589. dp_tx_update_peer_stats(peer, ts, length);
  2590. out:
  2591. return;
  2592. }
  2593. /**
  2594. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2595. * @soc: core txrx main context
  2596. * @comp_head: software descriptor head pointer
  2597. *
  2598. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2599. * and release the software descriptors after processing is complete
  2600. *
  2601. * Return: none
  2602. */
  2603. static void
  2604. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2605. struct dp_tx_desc_s *comp_head)
  2606. {
  2607. struct dp_tx_desc_s *desc;
  2608. struct dp_tx_desc_s *next;
  2609. struct hal_tx_completion_status ts = {0};
  2610. struct dp_peer *peer;
  2611. DP_HIST_INIT();
  2612. desc = comp_head;
  2613. while (desc) {
  2614. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2615. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2616. dp_tx_comp_process_tx_status(desc, &ts, peer);
  2617. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2618. if (peer)
  2619. dp_peer_unref_del_find_by_id(peer);
  2620. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2621. next = desc->next;
  2622. dp_tx_desc_release(desc, desc->pool_id);
  2623. desc = next;
  2624. }
  2625. DP_TX_HIST_STATS_PER_PDEV();
  2626. }
  2627. /**
  2628. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2629. * @tx_desc: software descriptor head pointer
  2630. * @status : Tx completion status from HTT descriptor
  2631. *
  2632. * This function will process HTT Tx indication messages from Target
  2633. *
  2634. * Return: none
  2635. */
  2636. static
  2637. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2638. {
  2639. uint8_t tx_status;
  2640. struct dp_pdev *pdev;
  2641. struct dp_vdev *vdev;
  2642. struct dp_soc *soc;
  2643. struct hal_tx_completion_status ts = {0};
  2644. uint32_t *htt_desc = (uint32_t *)status;
  2645. struct dp_peer *peer;
  2646. qdf_assert(tx_desc->pdev);
  2647. pdev = tx_desc->pdev;
  2648. vdev = tx_desc->vdev;
  2649. soc = pdev->soc;
  2650. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2651. switch (tx_status) {
  2652. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2653. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2654. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2655. {
  2656. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2657. ts.peer_id =
  2658. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2659. htt_desc[2]);
  2660. ts.tid =
  2661. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2662. htt_desc[2]);
  2663. } else {
  2664. ts.peer_id = HTT_INVALID_PEER;
  2665. ts.tid = HTT_INVALID_TID;
  2666. }
  2667. ts.ppdu_id =
  2668. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2669. htt_desc[1]);
  2670. ts.ack_frame_rssi =
  2671. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2672. htt_desc[1]);
  2673. ts.first_msdu = 1;
  2674. ts.last_msdu = 1;
  2675. if (tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)
  2676. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2677. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2678. if (qdf_likely(peer))
  2679. dp_peer_unref_del_find_by_id(peer);
  2680. dp_tx_comp_process_tx_status(tx_desc, &ts, peer);
  2681. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2682. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2683. break;
  2684. }
  2685. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2686. {
  2687. dp_tx_reinject_handler(tx_desc, status);
  2688. break;
  2689. }
  2690. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2691. {
  2692. dp_tx_inspect_handler(tx_desc, status);
  2693. break;
  2694. }
  2695. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2696. {
  2697. dp_tx_mec_handler(vdev, status);
  2698. break;
  2699. }
  2700. default:
  2701. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2702. "%s Invalid HTT tx_status %d\n",
  2703. __func__, tx_status);
  2704. break;
  2705. }
  2706. }
  2707. /**
  2708. * dp_tx_comp_handler() - Tx completion handler
  2709. * @soc: core txrx main context
  2710. * @ring_id: completion ring id
  2711. * @quota: No. of packets/descriptors that can be serviced in one loop
  2712. *
  2713. * This function will collect hardware release ring element contents and
  2714. * handle descriptor contents. Based on contents, free packet or handle error
  2715. * conditions
  2716. *
  2717. * Return: none
  2718. */
  2719. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2720. {
  2721. void *tx_comp_hal_desc;
  2722. uint8_t buffer_src;
  2723. uint8_t pool_id;
  2724. uint32_t tx_desc_id;
  2725. struct dp_tx_desc_s *tx_desc = NULL;
  2726. struct dp_tx_desc_s *head_desc = NULL;
  2727. struct dp_tx_desc_s *tail_desc = NULL;
  2728. uint32_t num_processed;
  2729. uint32_t count;
  2730. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2731. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2732. "%s %d : HAL RING Access Failed -- %pK",
  2733. __func__, __LINE__, hal_srng);
  2734. return 0;
  2735. }
  2736. num_processed = 0;
  2737. count = 0;
  2738. /* Find head descriptor from completion ring */
  2739. while (qdf_likely(tx_comp_hal_desc =
  2740. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2741. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2742. /* If this buffer was not released by TQM or FW, then it is not
  2743. * Tx completion indication, assert */
  2744. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2745. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2746. QDF_TRACE(QDF_MODULE_ID_DP,
  2747. QDF_TRACE_LEVEL_FATAL,
  2748. "Tx comp release_src != TQM | FW");
  2749. qdf_assert_always(0);
  2750. }
  2751. /* Get descriptor id */
  2752. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2753. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2754. DP_TX_DESC_ID_POOL_OS;
  2755. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2756. continue;
  2757. /* Find Tx descriptor */
  2758. tx_desc = dp_tx_desc_find(soc, pool_id,
  2759. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2760. DP_TX_DESC_ID_PAGE_OS,
  2761. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2762. DP_TX_DESC_ID_OFFSET_OS);
  2763. /*
  2764. * If the descriptor is already freed in vdev_detach,
  2765. * continue to next descriptor
  2766. */
  2767. if (!tx_desc->vdev) {
  2768. QDF_TRACE(QDF_MODULE_ID_DP,
  2769. QDF_TRACE_LEVEL_INFO,
  2770. "Descriptor freed in vdev_detach %d",
  2771. tx_desc_id);
  2772. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2773. count++;
  2774. continue;
  2775. }
  2776. /*
  2777. * If the release source is FW, process the HTT status
  2778. */
  2779. if (qdf_unlikely(buffer_src ==
  2780. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2781. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2782. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2783. htt_tx_status);
  2784. dp_tx_process_htt_completion(tx_desc,
  2785. htt_tx_status);
  2786. } else {
  2787. /* Pool id is not matching. Error */
  2788. if (tx_desc->pool_id != pool_id) {
  2789. QDF_TRACE(QDF_MODULE_ID_DP,
  2790. QDF_TRACE_LEVEL_FATAL,
  2791. "Tx Comp pool id %d not matched %d",
  2792. pool_id, tx_desc->pool_id);
  2793. qdf_assert_always(0);
  2794. }
  2795. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2796. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2797. QDF_TRACE(QDF_MODULE_ID_DP,
  2798. QDF_TRACE_LEVEL_FATAL,
  2799. "Txdesc invalid, flgs = %x,id = %d",
  2800. tx_desc->flags, tx_desc_id);
  2801. qdf_assert_always(0);
  2802. }
  2803. /* First ring descriptor on the cycle */
  2804. if (!head_desc) {
  2805. head_desc = tx_desc;
  2806. tail_desc = tx_desc;
  2807. }
  2808. tail_desc->next = tx_desc;
  2809. tx_desc->next = NULL;
  2810. tail_desc = tx_desc;
  2811. /* Collect hw completion contents */
  2812. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2813. &tx_desc->comp, 1);
  2814. }
  2815. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2816. /*
  2817. * Processed packet count is more than given quota
  2818. * stop to processing
  2819. */
  2820. if ((num_processed >= quota))
  2821. break;
  2822. count++;
  2823. }
  2824. hal_srng_access_end(soc->hal_soc, hal_srng);
  2825. /* Process the reaped descriptors */
  2826. if (head_desc)
  2827. dp_tx_comp_process_desc_list(soc, head_desc);
  2828. return num_processed;
  2829. }
  2830. #ifdef FEATURE_WLAN_TDLS
  2831. /**
  2832. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2833. *
  2834. * @data_vdev - which vdev should transmit the tx data frames
  2835. * @tx_spec - what non-standard handling to apply to the tx data frames
  2836. * @msdu_list - NULL-terminated list of tx MSDUs
  2837. *
  2838. * Return: NULL on success,
  2839. * nbuf when it fails to send
  2840. */
  2841. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2842. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2843. {
  2844. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2845. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2846. vdev->is_tdls_frame = true;
  2847. return dp_tx_send(vdev_handle, msdu_list);
  2848. }
  2849. #endif
  2850. /**
  2851. * dp_tx_vdev_attach() - attach vdev to dp tx
  2852. * @vdev: virtual device instance
  2853. *
  2854. * Return: QDF_STATUS_SUCCESS: success
  2855. * QDF_STATUS_E_RESOURCES: Error return
  2856. */
  2857. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2858. {
  2859. /*
  2860. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2861. */
  2862. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2863. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2864. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2865. vdev->vdev_id);
  2866. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2867. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2868. /*
  2869. * Set HTT Extension Valid bit to 0 by default
  2870. */
  2871. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2872. dp_tx_vdev_update_search_flags(vdev);
  2873. return QDF_STATUS_SUCCESS;
  2874. }
  2875. #ifdef FEATURE_WDS
  2876. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  2877. {
  2878. struct dp_soc *soc = vdev->pdev->soc;
  2879. /*
  2880. * If AST index override support is available (HKv2 etc),
  2881. * DA search flag be enabled always
  2882. *
  2883. * If AST index override support is not available (HKv1),
  2884. * DA search flag should be used for all modes except QWRAP
  2885. */
  2886. if (soc->ast_override_support || !vdev->proxysta_vdev)
  2887. return true;
  2888. return false;
  2889. }
  2890. #else
  2891. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  2892. {
  2893. return false;
  2894. }
  2895. #endif
  2896. /**
  2897. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2898. * @vdev: virtual device instance
  2899. *
  2900. * Return: void
  2901. *
  2902. */
  2903. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2904. {
  2905. struct dp_soc *soc = vdev->pdev->soc;
  2906. /*
  2907. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2908. * for TDLS link
  2909. *
  2910. * Enable AddrY (SA based search) only for non-WDS STA and
  2911. * ProxySTA VAP (in HKv1) modes.
  2912. *
  2913. * In all other VAP modes, only DA based search should be
  2914. * enabled
  2915. */
  2916. if (vdev->opmode == wlan_op_mode_sta &&
  2917. vdev->tdls_link_connected)
  2918. vdev->hal_desc_addr_search_flags =
  2919. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2920. else if ((vdev->opmode == wlan_op_mode_sta) &&
  2921. !dp_tx_da_search_override(vdev))
  2922. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2923. else
  2924. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2925. /* Set search type only when peer map v2 messaging is enabled
  2926. * as we will have the search index (AST hash) only when v2 is
  2927. * enabled
  2928. */
  2929. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  2930. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  2931. else
  2932. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  2933. }
  2934. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2935. /* dp_tx_desc_flush() - release resources associated
  2936. * to tx_desc
  2937. * @vdev: virtual device instance
  2938. *
  2939. * This function will free all outstanding Tx buffers,
  2940. * including ME buffer for which either free during
  2941. * completion didn't happened or completion is not
  2942. * received.
  2943. */
  2944. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2945. {
  2946. uint8_t i;
  2947. uint32_t j;
  2948. uint32_t num_desc, page_id, offset;
  2949. uint16_t num_desc_per_page;
  2950. struct dp_soc *soc = vdev->pdev->soc;
  2951. struct dp_tx_desc_s *tx_desc = NULL;
  2952. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2953. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  2954. tx_desc_pool = &soc->tx_desc[i];
  2955. if (!(tx_desc_pool->pool_size) ||
  2956. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  2957. !(tx_desc_pool->desc_pages.cacheable_pages))
  2958. continue;
  2959. num_desc = tx_desc_pool->pool_size;
  2960. num_desc_per_page =
  2961. tx_desc_pool->desc_pages.num_element_per_page;
  2962. for (j = 0; j < num_desc; j++) {
  2963. page_id = j / num_desc_per_page;
  2964. offset = j % num_desc_per_page;
  2965. if (qdf_unlikely(!(tx_desc_pool->
  2966. desc_pages.cacheable_pages)))
  2967. break;
  2968. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  2969. if (tx_desc && (tx_desc->vdev == vdev) &&
  2970. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2971. dp_tx_comp_free_buf(soc, tx_desc);
  2972. dp_tx_desc_release(tx_desc, i);
  2973. }
  2974. }
  2975. }
  2976. }
  2977. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2978. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2979. {
  2980. uint8_t i, num_pool;
  2981. uint32_t j;
  2982. uint32_t num_desc, page_id, offset;
  2983. uint16_t num_desc_per_page;
  2984. struct dp_soc *soc = vdev->pdev->soc;
  2985. struct dp_tx_desc_s *tx_desc = NULL;
  2986. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2987. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2988. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2989. for (i = 0; i < num_pool; i++) {
  2990. tx_desc_pool = &soc->tx_desc[i];
  2991. if (!tx_desc_pool->desc_pages.cacheable_pages)
  2992. continue;
  2993. num_desc_per_page =
  2994. tx_desc_pool->desc_pages.num_element_per_page;
  2995. for (j = 0; j < num_desc; j++) {
  2996. page_id = j / num_desc_per_page;
  2997. offset = j % num_desc_per_page;
  2998. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  2999. if (tx_desc && (tx_desc->vdev == vdev) &&
  3000. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  3001. dp_tx_comp_free_buf(soc, tx_desc);
  3002. dp_tx_desc_release(tx_desc, i);
  3003. }
  3004. }
  3005. }
  3006. }
  3007. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3008. /**
  3009. * dp_tx_vdev_detach() - detach vdev from dp tx
  3010. * @vdev: virtual device instance
  3011. *
  3012. * Return: QDF_STATUS_SUCCESS: success
  3013. * QDF_STATUS_E_RESOURCES: Error return
  3014. */
  3015. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3016. {
  3017. dp_tx_desc_flush(vdev);
  3018. return QDF_STATUS_SUCCESS;
  3019. }
  3020. /**
  3021. * dp_tx_pdev_attach() - attach pdev to dp tx
  3022. * @pdev: physical device instance
  3023. *
  3024. * Return: QDF_STATUS_SUCCESS: success
  3025. * QDF_STATUS_E_RESOURCES: Error return
  3026. */
  3027. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3028. {
  3029. struct dp_soc *soc = pdev->soc;
  3030. /* Initialize Flow control counters */
  3031. qdf_atomic_init(&pdev->num_tx_exception);
  3032. qdf_atomic_init(&pdev->num_tx_outstanding);
  3033. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3034. /* Initialize descriptors in TCL Ring */
  3035. hal_tx_init_data_ring(soc->hal_soc,
  3036. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3037. }
  3038. return QDF_STATUS_SUCCESS;
  3039. }
  3040. /**
  3041. * dp_tx_pdev_detach() - detach pdev from dp tx
  3042. * @pdev: physical device instance
  3043. *
  3044. * Return: QDF_STATUS_SUCCESS: success
  3045. * QDF_STATUS_E_RESOURCES: Error return
  3046. */
  3047. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3048. {
  3049. dp_tx_me_exit(pdev);
  3050. return QDF_STATUS_SUCCESS;
  3051. }
  3052. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3053. /* Pools will be allocated dynamically */
  3054. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3055. int num_desc)
  3056. {
  3057. uint8_t i;
  3058. for (i = 0; i < num_pool; i++) {
  3059. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3060. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3061. }
  3062. return 0;
  3063. }
  3064. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3065. {
  3066. uint8_t i;
  3067. for (i = 0; i < num_pool; i++)
  3068. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3069. }
  3070. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3071. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3072. int num_desc)
  3073. {
  3074. uint8_t i;
  3075. /* Allocate software Tx descriptor pools */
  3076. for (i = 0; i < num_pool; i++) {
  3077. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3078. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3079. "%s Tx Desc Pool alloc %d failed %pK",
  3080. __func__, i, soc);
  3081. return ENOMEM;
  3082. }
  3083. }
  3084. return 0;
  3085. }
  3086. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3087. {
  3088. uint8_t i;
  3089. for (i = 0; i < num_pool; i++) {
  3090. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3091. if (dp_tx_desc_pool_free(soc, i)) {
  3092. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3093. "%s Tx Desc Pool Free failed", __func__);
  3094. }
  3095. }
  3096. }
  3097. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3098. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3099. /**
  3100. * dp_tso_attach_wifi3() - TSO attach handler
  3101. * @txrx_soc: Opaque Dp handle
  3102. *
  3103. * Reserve TSO descriptor buffers
  3104. *
  3105. * Return: QDF_STATUS_E_FAILURE on failure or
  3106. * QDF_STATUS_SUCCESS on success
  3107. */
  3108. static
  3109. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3110. {
  3111. return dp_tso_soc_attach(txrx_soc);
  3112. }
  3113. /**
  3114. * dp_tso_detach_wifi3() - TSO Detach handler
  3115. * @txrx_soc: Opaque Dp handle
  3116. *
  3117. * Deallocate TSO descriptor buffers
  3118. *
  3119. * Return: QDF_STATUS_E_FAILURE on failure or
  3120. * QDF_STATUS_SUCCESS on success
  3121. */
  3122. static
  3123. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3124. {
  3125. return dp_tso_soc_detach(txrx_soc);
  3126. }
  3127. #else
  3128. static
  3129. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3130. {
  3131. return QDF_STATUS_SUCCESS;
  3132. }
  3133. static
  3134. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3135. {
  3136. return QDF_STATUS_SUCCESS;
  3137. }
  3138. #endif
  3139. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3140. {
  3141. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3142. uint8_t i;
  3143. uint8_t num_pool;
  3144. uint32_t num_desc;
  3145. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3146. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3147. for (i = 0; i < num_pool; i++)
  3148. dp_tx_tso_desc_pool_free(soc, i);
  3149. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3150. __func__, num_pool, num_desc);
  3151. for (i = 0; i < num_pool; i++)
  3152. dp_tx_tso_num_seg_pool_free(soc, i);
  3153. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3154. __func__, num_pool, num_desc);
  3155. return QDF_STATUS_SUCCESS;
  3156. }
  3157. /**
  3158. * dp_tso_attach() - TSO attach handler
  3159. * @txrx_soc: Opaque Dp handle
  3160. *
  3161. * Reserve TSO descriptor buffers
  3162. *
  3163. * Return: QDF_STATUS_E_FAILURE on failure or
  3164. * QDF_STATUS_SUCCESS on success
  3165. */
  3166. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3167. {
  3168. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3169. uint8_t i;
  3170. uint8_t num_pool;
  3171. uint32_t num_desc;
  3172. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3173. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3174. for (i = 0; i < num_pool; i++) {
  3175. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3176. dp_err("TSO Desc Pool alloc %d failed %pK",
  3177. i, soc);
  3178. return QDF_STATUS_E_FAILURE;
  3179. }
  3180. }
  3181. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3182. __func__, num_pool, num_desc);
  3183. for (i = 0; i < num_pool; i++) {
  3184. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3185. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3186. i, soc);
  3187. return QDF_STATUS_E_FAILURE;
  3188. }
  3189. }
  3190. return QDF_STATUS_SUCCESS;
  3191. }
  3192. /**
  3193. * dp_tx_soc_detach() - detach soc from dp tx
  3194. * @soc: core txrx main context
  3195. *
  3196. * This function will detach dp tx into main device context
  3197. * will free dp tx resource and initialize resources
  3198. *
  3199. * Return: QDF_STATUS_SUCCESS: success
  3200. * QDF_STATUS_E_RESOURCES: Error return
  3201. */
  3202. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3203. {
  3204. uint8_t num_pool;
  3205. uint16_t num_desc;
  3206. uint16_t num_ext_desc;
  3207. uint8_t i;
  3208. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3209. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3210. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3211. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3212. dp_tx_flow_control_deinit(soc);
  3213. dp_tx_delete_static_pools(soc, num_pool);
  3214. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3215. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3216. __func__, num_pool, num_desc);
  3217. for (i = 0; i < num_pool; i++) {
  3218. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3219. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3220. "%s Tx Ext Desc Pool Free failed",
  3221. __func__);
  3222. return QDF_STATUS_E_RESOURCES;
  3223. }
  3224. }
  3225. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3226. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3227. __func__, num_pool, num_ext_desc);
  3228. status = dp_tso_detach_wifi3(soc);
  3229. if (status != QDF_STATUS_SUCCESS)
  3230. return status;
  3231. return QDF_STATUS_SUCCESS;
  3232. }
  3233. /**
  3234. * dp_tx_soc_attach() - attach soc to dp tx
  3235. * @soc: core txrx main context
  3236. *
  3237. * This function will attach dp tx into main device context
  3238. * will allocate dp tx resource and initialize resources
  3239. *
  3240. * Return: QDF_STATUS_SUCCESS: success
  3241. * QDF_STATUS_E_RESOURCES: Error return
  3242. */
  3243. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3244. {
  3245. uint8_t i;
  3246. uint8_t num_pool;
  3247. uint32_t num_desc;
  3248. uint32_t num_ext_desc;
  3249. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3250. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3251. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3252. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3253. if (num_pool > MAX_TXDESC_POOLS)
  3254. goto fail;
  3255. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3256. goto fail;
  3257. dp_tx_flow_control_init(soc);
  3258. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3259. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3260. __func__, num_pool, num_desc);
  3261. /* Allocate extension tx descriptor pools */
  3262. for (i = 0; i < num_pool; i++) {
  3263. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3264. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3265. "MSDU Ext Desc Pool alloc %d failed %pK",
  3266. i, soc);
  3267. goto fail;
  3268. }
  3269. }
  3270. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3271. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3272. __func__, num_pool, num_ext_desc);
  3273. status = dp_tso_attach_wifi3((void *)soc);
  3274. if (status != QDF_STATUS_SUCCESS)
  3275. goto fail;
  3276. /* Initialize descriptors in TCL Rings */
  3277. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3278. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3279. hal_tx_init_data_ring(soc->hal_soc,
  3280. soc->tcl_data_ring[i].hal_srng);
  3281. }
  3282. }
  3283. /*
  3284. * todo - Add a runtime config option to enable this.
  3285. */
  3286. /*
  3287. * Due to multiple issues on NPR EMU, enable it selectively
  3288. * only for NPR EMU, should be removed, once NPR platforms
  3289. * are stable.
  3290. */
  3291. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3292. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3293. "%s HAL Tx init Success", __func__);
  3294. return QDF_STATUS_SUCCESS;
  3295. fail:
  3296. /* Detach will take care of freeing only allocated resources */
  3297. dp_tx_soc_detach(soc);
  3298. return QDF_STATUS_E_RESOURCES;
  3299. }
  3300. /*
  3301. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3302. * pdev: pointer to DP PDEV structure
  3303. * seg_info_head: Pointer to the head of list
  3304. *
  3305. * return: void
  3306. */
  3307. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3308. struct dp_tx_seg_info_s *seg_info_head)
  3309. {
  3310. struct dp_tx_me_buf_t *mc_uc_buf;
  3311. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3312. qdf_nbuf_t nbuf = NULL;
  3313. uint64_t phy_addr;
  3314. while (seg_info_head) {
  3315. nbuf = seg_info_head->nbuf;
  3316. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3317. seg_info_head->frags[0].vaddr;
  3318. phy_addr = seg_info_head->frags[0].paddr_hi;
  3319. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3320. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3321. phy_addr,
  3322. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  3323. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3324. qdf_nbuf_free(nbuf);
  3325. seg_info_new = seg_info_head;
  3326. seg_info_head = seg_info_head->next;
  3327. qdf_mem_free(seg_info_new);
  3328. }
  3329. }
  3330. /**
  3331. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3332. * @vdev: DP VDEV handle
  3333. * @nbuf: Multicast nbuf
  3334. * @newmac: Table of the clients to which packets have to be sent
  3335. * @new_mac_cnt: No of clients
  3336. *
  3337. * return: no of converted packets
  3338. */
  3339. uint16_t
  3340. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3341. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  3342. {
  3343. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3344. struct dp_pdev *pdev = vdev->pdev;
  3345. struct ether_header *eh;
  3346. uint8_t *data;
  3347. uint16_t len;
  3348. /* reference to frame dst addr */
  3349. uint8_t *dstmac;
  3350. /* copy of original frame src addr */
  3351. uint8_t srcmac[DP_MAC_ADDR_LEN];
  3352. /* local index into newmac */
  3353. uint8_t new_mac_idx = 0;
  3354. struct dp_tx_me_buf_t *mc_uc_buf;
  3355. qdf_nbuf_t nbuf_clone;
  3356. struct dp_tx_msdu_info_s msdu_info;
  3357. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3358. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3359. struct dp_tx_seg_info_s *seg_info_new;
  3360. struct dp_tx_frag_info_s data_frag;
  3361. qdf_dma_addr_t paddr_data;
  3362. qdf_dma_addr_t paddr_mcbuf = 0;
  3363. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  3364. QDF_STATUS status;
  3365. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  3366. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3367. eh = (struct ether_header *) nbuf;
  3368. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  3369. len = qdf_nbuf_len(nbuf);
  3370. data = qdf_nbuf_data(nbuf);
  3371. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3372. QDF_DMA_TO_DEVICE);
  3373. if (status) {
  3374. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3375. "Mapping failure Error:%d", status);
  3376. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3377. qdf_nbuf_free(nbuf);
  3378. return 1;
  3379. }
  3380. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3381. /*preparing data fragment*/
  3382. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3383. data_frag.paddr_lo = (uint32_t)paddr_data;
  3384. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3385. data_frag.len = len - DP_MAC_ADDR_LEN;
  3386. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3387. dstmac = newmac[new_mac_idx];
  3388. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3389. "added mac addr (%pM)", dstmac);
  3390. /* Check for NULL Mac Address */
  3391. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3392. continue;
  3393. /* frame to self mac. skip */
  3394. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3395. continue;
  3396. /*
  3397. * TODO: optimize to avoid malloc in per-packet path
  3398. * For eg. seg_pool can be made part of vdev structure
  3399. */
  3400. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3401. if (!seg_info_new) {
  3402. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3403. "alloc failed");
  3404. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3405. goto fail_seg_alloc;
  3406. }
  3407. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3408. if (mc_uc_buf == NULL)
  3409. goto fail_buf_alloc;
  3410. /*
  3411. * TODO: Check if we need to clone the nbuf
  3412. * Or can we just use the reference for all cases
  3413. */
  3414. if (new_mac_idx < (new_mac_cnt - 1)) {
  3415. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3416. if (nbuf_clone == NULL) {
  3417. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3418. goto fail_clone;
  3419. }
  3420. } else {
  3421. /*
  3422. * Update the ref
  3423. * to account for frame sent without cloning
  3424. */
  3425. qdf_nbuf_ref(nbuf);
  3426. nbuf_clone = nbuf;
  3427. }
  3428. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3429. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3430. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3431. &paddr_mcbuf);
  3432. if (status) {
  3433. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3434. "Mapping failure Error:%d", status);
  3435. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3436. goto fail_map;
  3437. }
  3438. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3439. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3440. seg_info_new->frags[0].paddr_hi =
  3441. ((uint64_t) paddr_mcbuf >> 32);
  3442. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3443. seg_info_new->frags[1] = data_frag;
  3444. seg_info_new->nbuf = nbuf_clone;
  3445. seg_info_new->frag_cnt = 2;
  3446. seg_info_new->total_len = len;
  3447. seg_info_new->next = NULL;
  3448. if (seg_info_head == NULL)
  3449. seg_info_head = seg_info_new;
  3450. else
  3451. seg_info_tail->next = seg_info_new;
  3452. seg_info_tail = seg_info_new;
  3453. }
  3454. if (!seg_info_head) {
  3455. goto free_return;
  3456. }
  3457. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3458. msdu_info.num_seg = new_mac_cnt;
  3459. msdu_info.frm_type = dp_tx_frm_me;
  3460. if (qdf_unlikely(vdev->mcast_enhancement_en > 0) &&
  3461. qdf_unlikely(pdev->hmmc_tid_override_en))
  3462. msdu_info.tid = pdev->hmmc_tid;
  3463. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3464. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3465. while (seg_info_head->next) {
  3466. seg_info_new = seg_info_head;
  3467. seg_info_head = seg_info_head->next;
  3468. qdf_mem_free(seg_info_new);
  3469. }
  3470. qdf_mem_free(seg_info_head);
  3471. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3472. qdf_nbuf_free(nbuf);
  3473. return new_mac_cnt;
  3474. fail_map:
  3475. qdf_nbuf_free(nbuf_clone);
  3476. fail_clone:
  3477. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3478. fail_buf_alloc:
  3479. qdf_mem_free(seg_info_new);
  3480. fail_seg_alloc:
  3481. dp_tx_me_mem_free(pdev, seg_info_head);
  3482. free_return:
  3483. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3484. qdf_nbuf_free(nbuf);
  3485. return 1;
  3486. }