dp_tx.c 102 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #define DP_TX_QUEUE_MASK 0x3
  33. /* TODO Add support in TSO */
  34. #define DP_DESC_NUM_FRAG(x) 0
  35. /* disable TQM_BYPASS */
  36. #define TQM_BYPASS_WAR 0
  37. /* invalid peer id for reinject*/
  38. #define DP_INVALID_PEER 0XFFFE
  39. /*mapping between hal encrypt type and cdp_sec_type*/
  40. #define MAX_CDP_SEC_TYPE 12
  41. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  42. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  43. HAL_TX_ENCRYPT_TYPE_WEP_128,
  44. HAL_TX_ENCRYPT_TYPE_WEP_104,
  45. HAL_TX_ENCRYPT_TYPE_WEP_40,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  47. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  48. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  49. HAL_TX_ENCRYPT_TYPE_WAPI,
  50. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  52. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  53. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  54. /**
  55. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  56. * @vdev: DP Virtual device handle
  57. * @nbuf: Buffer pointer
  58. * @queue: queue ids container for nbuf
  59. *
  60. * TX packet queue has 2 instances, software descriptors id and dma ring id
  61. * Based on tx feature and hardware configuration queue id combination could be
  62. * different.
  63. * For example -
  64. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  65. * With no XPS,lock based resource protection, Descriptor pool ids are different
  66. * for each vdev, dma ring id will be same as single pdev id
  67. *
  68. * Return: None
  69. */
  70. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  71. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  72. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  73. {
  74. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  75. queue->desc_pool_id = queue_offset;
  76. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  77. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  78. "%s, pool_id:%d ring_id: %d",
  79. __func__, queue->desc_pool_id, queue->ring_id);
  80. return;
  81. }
  82. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #endif
  95. #if defined(FEATURE_TSO)
  96. /**
  97. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  98. *
  99. * @soc - core txrx main context
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  106. if (qdf_unlikely(!tx_desc->tso_desc)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO num desc is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. bool is_last_seg;
  118. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  119. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  120. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1)
  121. is_last_seg = false;
  122. else
  123. is_last_seg = true;
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_nbuf_unmap_tso_segment(soc->osdev,
  126. tx_desc->tso_desc, is_last_seg);
  127. }
  128. }
  129. /**
  130. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  131. * back to the freelist
  132. *
  133. * @soc - soc device handle
  134. * @tx_desc - Tx software descriptor
  135. */
  136. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  137. struct dp_tx_desc_s *tx_desc)
  138. {
  139. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  140. if (qdf_unlikely(!tx_desc->tso_desc)) {
  141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  142. "%s %d TSO desc is NULL!",
  143. __func__, __LINE__);
  144. qdf_assert(0);
  145. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  147. "%s %d TSO num desc is NULL!",
  148. __func__, __LINE__);
  149. qdf_assert(0);
  150. } else {
  151. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  152. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  153. /* Add the tso num segment into the free list */
  154. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  155. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  156. tx_desc->tso_num_desc);
  157. tx_desc->tso_num_desc = NULL;
  158. }
  159. /* Add the tso segment into the free list*/
  160. dp_tx_tso_desc_free(soc,
  161. tx_desc->pool_id, tx_desc->tso_desc);
  162. tx_desc->tso_desc = NULL;
  163. }
  164. }
  165. #else
  166. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  167. struct dp_tx_desc_s *tx_desc)
  168. {
  169. }
  170. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  171. struct dp_tx_desc_s *tx_desc)
  172. {
  173. }
  174. #endif
  175. /**
  176. * dp_tx_desc_release() - Release Tx Descriptor
  177. * @tx_desc : Tx Descriptor
  178. * @desc_pool_id: Descriptor Pool ID
  179. *
  180. * Deallocate all resources attached to Tx descriptor and free the Tx
  181. * descriptor.
  182. *
  183. * Return:
  184. */
  185. static void
  186. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  187. {
  188. struct dp_pdev *pdev = tx_desc->pdev;
  189. struct dp_soc *soc;
  190. uint8_t comp_status = 0;
  191. qdf_assert(pdev);
  192. soc = pdev->soc;
  193. if (tx_desc->frm_type == dp_tx_frm_tso)
  194. dp_tx_tso_desc_release(soc, tx_desc);
  195. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  196. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  197. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  198. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  199. qdf_atomic_dec(&pdev->num_tx_outstanding);
  200. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  201. qdf_atomic_dec(&pdev->num_tx_exception);
  202. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  203. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  204. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  205. soc->hal_soc);
  206. else
  207. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  208. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  209. "Tx Completion Release desc %d status %d outstanding %d",
  210. tx_desc->id, comp_status,
  211. qdf_atomic_read(&pdev->num_tx_outstanding));
  212. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  213. return;
  214. }
  215. /**
  216. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  217. * @vdev: DP vdev Handle
  218. * @nbuf: skb
  219. *
  220. * Prepares and fills HTT metadata in the frame pre-header for special frames
  221. * that should be transmitted using varying transmit parameters.
  222. * There are 2 VDEV modes that currently needs this special metadata -
  223. * 1) Mesh Mode
  224. * 2) DSRC Mode
  225. *
  226. * Return: HTT metadata size
  227. *
  228. */
  229. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  230. uint32_t *meta_data)
  231. {
  232. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  233. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  234. uint8_t htt_desc_size;
  235. /* Size rounded of multiple of 8 bytes */
  236. uint8_t htt_desc_size_aligned;
  237. uint8_t *hdr = NULL;
  238. /*
  239. * Metadata - HTT MSDU Extension header
  240. */
  241. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  242. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  243. if (vdev->mesh_vdev) {
  244. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  245. htt_desc_size_aligned)) {
  246. DP_STATS_INC(vdev,
  247. tx_i.dropped.headroom_insufficient, 1);
  248. return 0;
  249. }
  250. /* Fill and add HTT metaheader */
  251. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  252. if (hdr == NULL) {
  253. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  254. "Error in filling HTT metadata");
  255. return 0;
  256. }
  257. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  258. } else if (vdev->opmode == wlan_op_mode_ocb) {
  259. /* Todo - Add support for DSRC */
  260. }
  261. return htt_desc_size_aligned;
  262. }
  263. /**
  264. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  265. * @tso_seg: TSO segment to process
  266. * @ext_desc: Pointer to MSDU extension descriptor
  267. *
  268. * Return: void
  269. */
  270. #if defined(FEATURE_TSO)
  271. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  272. void *ext_desc)
  273. {
  274. uint8_t num_frag;
  275. uint32_t tso_flags;
  276. /*
  277. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  278. * tcp_flag_mask
  279. *
  280. * Checksum enable flags are set in TCL descriptor and not in Extension
  281. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  282. */
  283. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  284. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  285. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  286. tso_seg->tso_flags.ip_len);
  287. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  288. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  289. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  290. uint32_t lo = 0;
  291. uint32_t hi = 0;
  292. qdf_dmaaddr_to_32s(
  293. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  294. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  295. tso_seg->tso_frags[num_frag].length);
  296. }
  297. return;
  298. }
  299. #else
  300. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  301. void *ext_desc)
  302. {
  303. return;
  304. }
  305. #endif
  306. #if defined(FEATURE_TSO)
  307. /**
  308. * dp_tx_free_tso_seg() - Loop through the tso segments
  309. * allocated and free them
  310. *
  311. * @soc: soc handle
  312. * @free_seg: list of tso segments
  313. * @msdu_info: msdu descriptor
  314. *
  315. * Return - void
  316. */
  317. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  318. struct qdf_tso_seg_elem_t *free_seg,
  319. struct dp_tx_msdu_info_s *msdu_info)
  320. {
  321. struct qdf_tso_seg_elem_t *next_seg;
  322. while (free_seg) {
  323. next_seg = free_seg->next;
  324. dp_tx_tso_desc_free(soc,
  325. msdu_info->tx_queue.desc_pool_id,
  326. free_seg);
  327. free_seg = next_seg;
  328. }
  329. }
  330. /**
  331. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  332. * allocated and free them
  333. *
  334. * @soc: soc handle
  335. * @free_seg: list of tso segments
  336. * @msdu_info: msdu descriptor
  337. * Return - void
  338. */
  339. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  340. struct qdf_tso_num_seg_elem_t *free_seg,
  341. struct dp_tx_msdu_info_s *msdu_info)
  342. {
  343. struct qdf_tso_num_seg_elem_t *next_seg;
  344. while (free_seg) {
  345. next_seg = free_seg->next;
  346. dp_tso_num_seg_free(soc,
  347. msdu_info->tx_queue.desc_pool_id,
  348. free_seg);
  349. free_seg = next_seg;
  350. }
  351. }
  352. /**
  353. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  354. * @vdev: virtual device handle
  355. * @msdu: network buffer
  356. * @msdu_info: meta data associated with the msdu
  357. *
  358. * Return: QDF_STATUS_SUCCESS success
  359. */
  360. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  361. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  362. {
  363. struct qdf_tso_seg_elem_t *tso_seg;
  364. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  365. struct dp_soc *soc = vdev->pdev->soc;
  366. struct qdf_tso_info_t *tso_info;
  367. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  368. tso_info = &msdu_info->u.tso_info;
  369. tso_info->curr_seg = NULL;
  370. tso_info->tso_seg_list = NULL;
  371. tso_info->num_segs = num_seg;
  372. msdu_info->frm_type = dp_tx_frm_tso;
  373. tso_info->tso_num_seg_list = NULL;
  374. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  375. while (num_seg) {
  376. tso_seg = dp_tx_tso_desc_alloc(
  377. soc, msdu_info->tx_queue.desc_pool_id);
  378. if (tso_seg) {
  379. tso_seg->next = tso_info->tso_seg_list;
  380. tso_info->tso_seg_list = tso_seg;
  381. num_seg--;
  382. } else {
  383. struct qdf_tso_seg_elem_t *free_seg =
  384. tso_info->tso_seg_list;
  385. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  386. return QDF_STATUS_E_NOMEM;
  387. }
  388. }
  389. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  390. tso_num_seg = dp_tso_num_seg_alloc(soc,
  391. msdu_info->tx_queue.desc_pool_id);
  392. if (tso_num_seg) {
  393. tso_num_seg->next = tso_info->tso_num_seg_list;
  394. tso_info->tso_num_seg_list = tso_num_seg;
  395. } else {
  396. /* Bug: free tso_num_seg and tso_seg */
  397. /* Free the already allocated num of segments */
  398. struct qdf_tso_seg_elem_t *free_seg =
  399. tso_info->tso_seg_list;
  400. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  401. __func__);
  402. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  403. return QDF_STATUS_E_NOMEM;
  404. }
  405. msdu_info->num_seg =
  406. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  407. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  408. msdu_info->num_seg);
  409. if (!(msdu_info->num_seg)) {
  410. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  411. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  412. msdu_info);
  413. return QDF_STATUS_E_INVAL;
  414. }
  415. tso_info->curr_seg = tso_info->tso_seg_list;
  416. return QDF_STATUS_SUCCESS;
  417. }
  418. #else
  419. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  420. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  421. {
  422. return QDF_STATUS_E_NOMEM;
  423. }
  424. #endif
  425. /**
  426. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  427. * @vdev: DP Vdev handle
  428. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  429. * @desc_pool_id: Descriptor Pool ID
  430. *
  431. * Return:
  432. */
  433. static
  434. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  435. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  436. {
  437. uint8_t i;
  438. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  439. struct dp_tx_seg_info_s *seg_info;
  440. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  441. struct dp_soc *soc = vdev->pdev->soc;
  442. /* Allocate an extension descriptor */
  443. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  444. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  445. if (!msdu_ext_desc) {
  446. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  447. return NULL;
  448. }
  449. if (msdu_info->exception_fw &&
  450. qdf_unlikely(vdev->mesh_vdev)) {
  451. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  452. &msdu_info->meta_data[0],
  453. sizeof(struct htt_tx_msdu_desc_ext2_t));
  454. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  455. }
  456. switch (msdu_info->frm_type) {
  457. case dp_tx_frm_sg:
  458. case dp_tx_frm_me:
  459. case dp_tx_frm_raw:
  460. seg_info = msdu_info->u.sg_info.curr_seg;
  461. /* Update the buffer pointers in MSDU Extension Descriptor */
  462. for (i = 0; i < seg_info->frag_cnt; i++) {
  463. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  464. seg_info->frags[i].paddr_lo,
  465. seg_info->frags[i].paddr_hi,
  466. seg_info->frags[i].len);
  467. }
  468. break;
  469. case dp_tx_frm_tso:
  470. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  471. &cached_ext_desc[0]);
  472. break;
  473. default:
  474. break;
  475. }
  476. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  477. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  478. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  479. msdu_ext_desc->vaddr);
  480. return msdu_ext_desc;
  481. }
  482. /**
  483. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  484. *
  485. * @skb: skb to be traced
  486. * @msdu_id: msdu_id of the packet
  487. * @vdev_id: vdev_id of the packet
  488. *
  489. * Return: None
  490. */
  491. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  492. uint8_t vdev_id)
  493. {
  494. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  495. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  496. DPTRACE(qdf_dp_trace_ptr(skb,
  497. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  498. QDF_TRACE_DEFAULT_PDEV_ID,
  499. qdf_nbuf_data_addr(skb),
  500. sizeof(qdf_nbuf_data(skb)),
  501. msdu_id, vdev_id));
  502. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  503. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  504. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  505. msdu_id, QDF_TX));
  506. }
  507. /**
  508. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  509. * @vdev: DP vdev handle
  510. * @nbuf: skb
  511. * @desc_pool_id: Descriptor pool ID
  512. * @meta_data: Metadata to the fw
  513. * @tx_exc_metadata: Handle that holds exception path metadata
  514. * Allocate and prepare Tx descriptor with msdu information.
  515. *
  516. * Return: Pointer to Tx Descriptor on success,
  517. * NULL on failure
  518. */
  519. static
  520. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  521. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  522. struct dp_tx_msdu_info_s *msdu_info,
  523. struct cdp_tx_exception_metadata *tx_exc_metadata)
  524. {
  525. uint8_t align_pad;
  526. uint8_t is_exception = 0;
  527. uint8_t htt_hdr_size;
  528. struct ether_header *eh;
  529. struct dp_tx_desc_s *tx_desc;
  530. struct dp_pdev *pdev = vdev->pdev;
  531. struct dp_soc *soc = pdev->soc;
  532. /* Allocate software Tx descriptor */
  533. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  534. if (qdf_unlikely(!tx_desc)) {
  535. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  536. return NULL;
  537. }
  538. /* Flow control/Congestion Control counters */
  539. qdf_atomic_inc(&pdev->num_tx_outstanding);
  540. /* Initialize the SW tx descriptor */
  541. tx_desc->nbuf = nbuf;
  542. tx_desc->frm_type = dp_tx_frm_std;
  543. tx_desc->tx_encap_type = (tx_exc_metadata ?
  544. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  545. tx_desc->vdev = vdev;
  546. tx_desc->pdev = pdev;
  547. tx_desc->msdu_ext_desc = NULL;
  548. tx_desc->pkt_offset = 0;
  549. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  550. /* Reset the control block */
  551. qdf_nbuf_reset_ctxt(nbuf);
  552. /*
  553. * For special modes (vdev_type == ocb or mesh), data frames should be
  554. * transmitted using varying transmit parameters (tx spec) which include
  555. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  556. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  557. * These frames are sent as exception packets to firmware.
  558. *
  559. * HW requirement is that metadata should always point to a
  560. * 8-byte aligned address. So we add alignment pad to start of buffer.
  561. * HTT Metadata should be ensured to be multiple of 8-bytes,
  562. * to get 8-byte aligned start address along with align_pad added
  563. *
  564. * |-----------------------------|
  565. * | |
  566. * |-----------------------------| <-----Buffer Pointer Address given
  567. * | | ^ in HW descriptor (aligned)
  568. * | HTT Metadata | |
  569. * | | |
  570. * | | | Packet Offset given in descriptor
  571. * | | |
  572. * |-----------------------------| |
  573. * | Alignment Pad | v
  574. * |-----------------------------| <----- Actual buffer start address
  575. * | SKB Data | (Unaligned)
  576. * | |
  577. * | |
  578. * | |
  579. * | |
  580. * | |
  581. * |-----------------------------|
  582. */
  583. if (qdf_unlikely((msdu_info->exception_fw)) ||
  584. (vdev->opmode == wlan_op_mode_ocb)) {
  585. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  586. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  587. DP_STATS_INC(vdev,
  588. tx_i.dropped.headroom_insufficient, 1);
  589. goto failure;
  590. }
  591. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  592. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  593. "qdf_nbuf_push_head failed");
  594. goto failure;
  595. }
  596. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  597. msdu_info->meta_data);
  598. if (htt_hdr_size == 0)
  599. goto failure;
  600. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  601. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  602. is_exception = 1;
  603. }
  604. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  605. qdf_nbuf_map(soc->osdev, nbuf,
  606. QDF_DMA_TO_DEVICE))) {
  607. /* Handle failure */
  608. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  609. "qdf_nbuf_map failed");
  610. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  611. goto failure;
  612. }
  613. if (qdf_unlikely(vdev->nawds_enabled)) {
  614. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  615. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  616. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  617. is_exception = 1;
  618. }
  619. }
  620. #if !TQM_BYPASS_WAR
  621. if (is_exception || tx_exc_metadata)
  622. #endif
  623. {
  624. /* Temporary WAR due to TQM VP issues */
  625. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  626. qdf_atomic_inc(&pdev->num_tx_exception);
  627. }
  628. return tx_desc;
  629. failure:
  630. dp_tx_desc_release(tx_desc, desc_pool_id);
  631. return NULL;
  632. }
  633. /**
  634. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  635. * @vdev: DP vdev handle
  636. * @nbuf: skb
  637. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  638. * @desc_pool_id : Descriptor Pool ID
  639. *
  640. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  641. * information. For frames wth fragments, allocate and prepare
  642. * an MSDU extension descriptor
  643. *
  644. * Return: Pointer to Tx Descriptor on success,
  645. * NULL on failure
  646. */
  647. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  648. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  649. uint8_t desc_pool_id)
  650. {
  651. struct dp_tx_desc_s *tx_desc;
  652. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  653. struct dp_pdev *pdev = vdev->pdev;
  654. struct dp_soc *soc = pdev->soc;
  655. /* Allocate software Tx descriptor */
  656. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  657. if (!tx_desc) {
  658. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  659. return NULL;
  660. }
  661. /* Flow control/Congestion Control counters */
  662. qdf_atomic_inc(&pdev->num_tx_outstanding);
  663. /* Initialize the SW tx descriptor */
  664. tx_desc->nbuf = nbuf;
  665. tx_desc->frm_type = msdu_info->frm_type;
  666. tx_desc->tx_encap_type = vdev->tx_encap_type;
  667. tx_desc->vdev = vdev;
  668. tx_desc->pdev = pdev;
  669. tx_desc->pkt_offset = 0;
  670. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  671. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  672. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  673. /* Reset the control block */
  674. qdf_nbuf_reset_ctxt(nbuf);
  675. /* Handle scattered frames - TSO/SG/ME */
  676. /* Allocate and prepare an extension descriptor for scattered frames */
  677. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  678. if (!msdu_ext_desc) {
  679. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  680. "%s Tx Extension Descriptor Alloc Fail",
  681. __func__);
  682. goto failure;
  683. }
  684. #if TQM_BYPASS_WAR
  685. /* Temporary WAR due to TQM VP issues */
  686. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  687. qdf_atomic_inc(&pdev->num_tx_exception);
  688. #endif
  689. if (qdf_unlikely(msdu_info->exception_fw))
  690. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  691. tx_desc->msdu_ext_desc = msdu_ext_desc;
  692. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  693. return tx_desc;
  694. failure:
  695. dp_tx_desc_release(tx_desc, desc_pool_id);
  696. return NULL;
  697. }
  698. /**
  699. * dp_tx_prepare_raw() - Prepare RAW packet TX
  700. * @vdev: DP vdev handle
  701. * @nbuf: buffer pointer
  702. * @seg_info: Pointer to Segment info Descriptor to be prepared
  703. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  704. * descriptor
  705. *
  706. * Return:
  707. */
  708. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  709. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  710. {
  711. qdf_nbuf_t curr_nbuf = NULL;
  712. uint16_t total_len = 0;
  713. qdf_dma_addr_t paddr;
  714. int32_t i;
  715. int32_t mapped_buf_num = 0;
  716. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  717. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  718. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  719. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  720. if (vdev->raw_mode_war &&
  721. (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS))
  722. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  723. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  724. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  725. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  726. QDF_DMA_TO_DEVICE)) {
  727. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  728. "%s dma map error ", __func__);
  729. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  730. mapped_buf_num = i;
  731. goto error;
  732. }
  733. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  734. seg_info->frags[i].paddr_lo = paddr;
  735. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  736. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  737. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  738. total_len += qdf_nbuf_len(curr_nbuf);
  739. }
  740. seg_info->frag_cnt = i;
  741. seg_info->total_len = total_len;
  742. seg_info->next = NULL;
  743. sg_info->curr_seg = seg_info;
  744. msdu_info->frm_type = dp_tx_frm_raw;
  745. msdu_info->num_seg = 1;
  746. return nbuf;
  747. error:
  748. i = 0;
  749. while (nbuf) {
  750. curr_nbuf = nbuf;
  751. if (i < mapped_buf_num) {
  752. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  753. i++;
  754. }
  755. nbuf = qdf_nbuf_next(nbuf);
  756. qdf_nbuf_free(curr_nbuf);
  757. }
  758. return NULL;
  759. }
  760. /**
  761. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  762. * @soc: DP Soc Handle
  763. * @vdev: DP vdev handle
  764. * @tx_desc: Tx Descriptor Handle
  765. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  766. * @fw_metadata: Metadata to send to Target Firmware along with frame
  767. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  768. * @tx_exc_metadata: Handle that holds exception path meta data
  769. *
  770. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  771. * from software Tx descriptor
  772. *
  773. * Return:
  774. */
  775. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  776. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  777. uint16_t fw_metadata, uint8_t ring_id,
  778. struct cdp_tx_exception_metadata
  779. *tx_exc_metadata)
  780. {
  781. uint8_t type;
  782. uint16_t length;
  783. void *hal_tx_desc, *hal_tx_desc_cached;
  784. qdf_dma_addr_t dma_addr;
  785. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  786. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  787. tx_exc_metadata->sec_type : vdev->sec_type);
  788. /* Return Buffer Manager ID */
  789. uint8_t bm_id = ring_id;
  790. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  791. hal_tx_desc_cached = (void *) cached_desc;
  792. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  793. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  794. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  795. type = HAL_TX_BUF_TYPE_EXT_DESC;
  796. dma_addr = tx_desc->msdu_ext_desc->paddr;
  797. } else {
  798. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  799. type = HAL_TX_BUF_TYPE_BUFFER;
  800. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  801. }
  802. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  803. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  804. dma_addr, bm_id, tx_desc->id,
  805. type, soc->hal_soc);
  806. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  807. return QDF_STATUS_E_RESOURCES;
  808. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  809. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  810. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  811. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  812. vdev->pdev->lmac_id);
  813. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  814. vdev->search_type);
  815. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  816. vdev->bss_ast_hash);
  817. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  818. vdev->dscp_tid_map_id);
  819. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  820. sec_type_map[sec_type]);
  821. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  822. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  823. __func__, length, type, (uint64_t)dma_addr,
  824. tx_desc->pkt_offset, tx_desc->id);
  825. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  826. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  827. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  828. vdev->hal_desc_addr_search_flags);
  829. /* verify checksum offload configuration*/
  830. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  831. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  832. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  833. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  834. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  835. }
  836. if (tid != HTT_TX_EXT_TID_INVALID)
  837. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  838. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  839. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  840. /* Sync cached descriptor with HW */
  841. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  842. if (!hal_tx_desc) {
  843. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  844. "%s TCL ring full ring_id:%d", __func__, ring_id);
  845. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  846. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  847. return QDF_STATUS_E_RESOURCES;
  848. }
  849. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  850. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  851. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  852. return QDF_STATUS_SUCCESS;
  853. }
  854. /**
  855. * dp_cce_classify() - Classify the frame based on CCE rules
  856. * @vdev: DP vdev handle
  857. * @nbuf: skb
  858. *
  859. * Classify frames based on CCE rules
  860. * Return: bool( true if classified,
  861. * else false)
  862. */
  863. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  864. {
  865. struct ether_header *eh = NULL;
  866. uint16_t ether_type;
  867. qdf_llc_t *llcHdr;
  868. qdf_nbuf_t nbuf_clone = NULL;
  869. qdf_dot3_qosframe_t *qos_wh = NULL;
  870. /* for mesh packets don't do any classification */
  871. if (qdf_unlikely(vdev->mesh_vdev))
  872. return false;
  873. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  874. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  875. ether_type = eh->ether_type;
  876. llcHdr = (qdf_llc_t *)(nbuf->data +
  877. sizeof(struct ether_header));
  878. } else {
  879. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  880. /* For encrypted packets don't do any classification */
  881. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  882. return false;
  883. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  884. if (qdf_unlikely(
  885. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  886. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  887. ether_type = *(uint16_t *)(nbuf->data
  888. + QDF_IEEE80211_4ADDR_HDR_LEN
  889. + sizeof(qdf_llc_t)
  890. - sizeof(ether_type));
  891. llcHdr = (qdf_llc_t *)(nbuf->data +
  892. QDF_IEEE80211_4ADDR_HDR_LEN);
  893. } else {
  894. ether_type = *(uint16_t *)(nbuf->data
  895. + QDF_IEEE80211_3ADDR_HDR_LEN
  896. + sizeof(qdf_llc_t)
  897. - sizeof(ether_type));
  898. llcHdr = (qdf_llc_t *)(nbuf->data +
  899. QDF_IEEE80211_3ADDR_HDR_LEN);
  900. }
  901. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  902. && (ether_type ==
  903. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  904. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  905. return true;
  906. }
  907. }
  908. return false;
  909. }
  910. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  911. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  912. sizeof(*llcHdr));
  913. nbuf_clone = qdf_nbuf_clone(nbuf);
  914. if (qdf_unlikely(nbuf_clone)) {
  915. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  916. if (ether_type == htons(ETHERTYPE_8021Q)) {
  917. qdf_nbuf_pull_head(nbuf_clone,
  918. sizeof(qdf_net_vlanhdr_t));
  919. }
  920. }
  921. } else {
  922. if (ether_type == htons(ETHERTYPE_8021Q)) {
  923. nbuf_clone = qdf_nbuf_clone(nbuf);
  924. if (qdf_unlikely(nbuf_clone)) {
  925. qdf_nbuf_pull_head(nbuf_clone,
  926. sizeof(qdf_net_vlanhdr_t));
  927. }
  928. }
  929. }
  930. if (qdf_unlikely(nbuf_clone))
  931. nbuf = nbuf_clone;
  932. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  933. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  934. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  935. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  936. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  937. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  938. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  939. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  940. if (qdf_unlikely(nbuf_clone != NULL))
  941. qdf_nbuf_free(nbuf_clone);
  942. return true;
  943. }
  944. if (qdf_unlikely(nbuf_clone != NULL))
  945. qdf_nbuf_free(nbuf_clone);
  946. return false;
  947. }
  948. /**
  949. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  950. * @vdev: DP vdev handle
  951. * @nbuf: skb
  952. *
  953. * Extract the DSCP or PCP information from frame and map into TID value.
  954. * Software based TID classification is required when more than 2 DSCP-TID
  955. * mapping tables are needed.
  956. * Hardware supports 2 DSCP-TID mapping tables
  957. *
  958. * Return: void
  959. */
  960. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  961. struct dp_tx_msdu_info_s *msdu_info)
  962. {
  963. uint8_t tos = 0, dscp_tid_override = 0;
  964. uint8_t *hdr_ptr, *L3datap;
  965. uint8_t is_mcast = 0;
  966. struct ether_header *eh = NULL;
  967. qdf_ethervlan_header_t *evh = NULL;
  968. uint16_t ether_type;
  969. qdf_llc_t *llcHdr;
  970. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  971. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  972. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  973. return;
  974. /* for mesh packets don't do any classification */
  975. if (qdf_unlikely(vdev->mesh_vdev))
  976. return;
  977. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  978. eh = (struct ether_header *) nbuf->data;
  979. hdr_ptr = eh->ether_dhost;
  980. L3datap = hdr_ptr + sizeof(struct ether_header);
  981. } else {
  982. qdf_dot3_qosframe_t *qos_wh =
  983. (qdf_dot3_qosframe_t *) nbuf->data;
  984. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  985. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  986. return;
  987. }
  988. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  989. ether_type = eh->ether_type;
  990. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  991. /*
  992. * Check if packet is dot3 or eth2 type.
  993. */
  994. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  995. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  996. sizeof(*llcHdr));
  997. if (ether_type == htons(ETHERTYPE_8021Q)) {
  998. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  999. sizeof(*llcHdr);
  1000. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  1001. + sizeof(*llcHdr) +
  1002. sizeof(qdf_net_vlanhdr_t));
  1003. } else {
  1004. L3datap = hdr_ptr + sizeof(struct ether_header) +
  1005. sizeof(*llcHdr);
  1006. }
  1007. } else {
  1008. if (ether_type == htons(ETHERTYPE_8021Q)) {
  1009. evh = (qdf_ethervlan_header_t *) eh;
  1010. ether_type = evh->ether_type;
  1011. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1012. }
  1013. }
  1014. /*
  1015. * Find priority from IP TOS DSCP field
  1016. */
  1017. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1018. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1019. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1020. /* Only for unicast frames */
  1021. if (!is_mcast) {
  1022. /* send it on VO queue */
  1023. msdu_info->tid = DP_VO_TID;
  1024. }
  1025. } else {
  1026. /*
  1027. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1028. * from TOS byte.
  1029. */
  1030. tos = ip->ip_tos;
  1031. dscp_tid_override = 1;
  1032. }
  1033. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1034. /* TODO
  1035. * use flowlabel
  1036. *igmpmld cases to be handled in phase 2
  1037. */
  1038. unsigned long ver_pri_flowlabel;
  1039. unsigned long pri;
  1040. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1041. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1042. DP_IPV6_PRIORITY_SHIFT;
  1043. tos = pri;
  1044. dscp_tid_override = 1;
  1045. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1046. msdu_info->tid = DP_VO_TID;
  1047. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1048. /* Only for unicast frames */
  1049. if (!is_mcast) {
  1050. /* send ucast arp on VO queue */
  1051. msdu_info->tid = DP_VO_TID;
  1052. }
  1053. }
  1054. /*
  1055. * Assign all MCAST packets to BE
  1056. */
  1057. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1058. if (is_mcast) {
  1059. tos = 0;
  1060. dscp_tid_override = 1;
  1061. }
  1062. }
  1063. if (dscp_tid_override == 1) {
  1064. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1065. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1066. }
  1067. return;
  1068. }
  1069. #ifdef CONVERGED_TDLS_ENABLE
  1070. /**
  1071. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1072. * @tx_desc: TX descriptor
  1073. *
  1074. * Return: None
  1075. */
  1076. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1077. {
  1078. if (tx_desc->vdev) {
  1079. if (tx_desc->vdev->is_tdls_frame)
  1080. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1081. tx_desc->vdev->is_tdls_frame = false;
  1082. }
  1083. }
  1084. /**
  1085. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1086. * @tx_desc: TX descriptor
  1087. * @vdev: datapath vdev handle
  1088. *
  1089. * Return: None
  1090. */
  1091. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1092. struct dp_vdev *vdev)
  1093. {
  1094. struct hal_tx_completion_status ts = {0};
  1095. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1096. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1097. if (vdev->tx_non_std_data_callback.func) {
  1098. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1099. vdev->tx_non_std_data_callback.func(
  1100. vdev->tx_non_std_data_callback.ctxt,
  1101. nbuf, ts.status);
  1102. return;
  1103. }
  1104. }
  1105. #endif
  1106. /**
  1107. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1108. * @vdev: DP vdev handle
  1109. * @nbuf: skb
  1110. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1111. * @meta_data: Metadata to the fw
  1112. * @tx_q: Tx queue to be used for this Tx frame
  1113. * @peer_id: peer_id of the peer in case of NAWDS frames
  1114. * @tx_exc_metadata: Handle that holds exception path metadata
  1115. *
  1116. * Return: NULL on success,
  1117. * nbuf when it fails to send
  1118. */
  1119. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1120. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1121. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1122. {
  1123. struct dp_pdev *pdev = vdev->pdev;
  1124. struct dp_soc *soc = pdev->soc;
  1125. struct dp_tx_desc_s *tx_desc;
  1126. QDF_STATUS status;
  1127. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1128. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1129. uint16_t htt_tcl_metadata = 0;
  1130. uint8_t tid = msdu_info->tid;
  1131. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1132. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1133. msdu_info, tx_exc_metadata);
  1134. if (!tx_desc) {
  1135. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1136. "%s Tx_desc prepare Fail vdev %pK queue %d",
  1137. __func__, vdev, tx_q->desc_pool_id);
  1138. return nbuf;
  1139. }
  1140. if (qdf_unlikely(soc->cce_disable)) {
  1141. if (dp_cce_classify(vdev, nbuf) == true) {
  1142. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1143. tid = DP_VO_TID;
  1144. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1145. }
  1146. }
  1147. dp_tx_update_tdls_flags(tx_desc);
  1148. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1149. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1150. "%s %d : HAL RING Access Failed -- %pK",
  1151. __func__, __LINE__, hal_srng);
  1152. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1153. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1154. goto fail_return;
  1155. }
  1156. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1157. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1158. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1159. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1160. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1161. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1162. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1163. peer_id);
  1164. } else
  1165. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1166. if (msdu_info->exception_fw) {
  1167. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1168. }
  1169. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1170. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1171. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1172. if (status != QDF_STATUS_SUCCESS) {
  1173. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1174. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1175. __func__, tx_desc, tx_q->ring_id);
  1176. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1177. goto fail_return;
  1178. }
  1179. nbuf = NULL;
  1180. fail_return:
  1181. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1182. hal_srng_access_end(soc->hal_soc, hal_srng);
  1183. hif_pm_runtime_put(soc->hif_handle);
  1184. } else {
  1185. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1186. }
  1187. return nbuf;
  1188. }
  1189. /**
  1190. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1191. * @vdev: DP vdev handle
  1192. * @nbuf: skb
  1193. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1194. *
  1195. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1196. *
  1197. * Return: NULL on success,
  1198. * nbuf when it fails to send
  1199. */
  1200. #if QDF_LOCK_STATS
  1201. static noinline
  1202. #else
  1203. static
  1204. #endif
  1205. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1206. struct dp_tx_msdu_info_s *msdu_info)
  1207. {
  1208. uint8_t i;
  1209. struct dp_pdev *pdev = vdev->pdev;
  1210. struct dp_soc *soc = pdev->soc;
  1211. struct dp_tx_desc_s *tx_desc;
  1212. bool is_cce_classified = false;
  1213. QDF_STATUS status;
  1214. uint16_t htt_tcl_metadata = 0;
  1215. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1216. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1217. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1218. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1219. "%s %d : HAL RING Access Failed -- %pK",
  1220. __func__, __LINE__, hal_srng);
  1221. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1222. return nbuf;
  1223. }
  1224. if (qdf_unlikely(soc->cce_disable)) {
  1225. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1226. if (is_cce_classified) {
  1227. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1228. msdu_info->tid = DP_VO_TID;
  1229. }
  1230. }
  1231. if (msdu_info->frm_type == dp_tx_frm_me)
  1232. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1233. i = 0;
  1234. /* Print statement to track i and num_seg */
  1235. /*
  1236. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1237. * descriptors using information in msdu_info
  1238. */
  1239. while (i < msdu_info->num_seg) {
  1240. /*
  1241. * Setup Tx descriptor for an MSDU, and MSDU extension
  1242. * descriptor
  1243. */
  1244. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1245. tx_q->desc_pool_id);
  1246. if (!tx_desc) {
  1247. if (msdu_info->frm_type == dp_tx_frm_me) {
  1248. dp_tx_me_free_buf(pdev,
  1249. (void *)(msdu_info->u.sg_info
  1250. .curr_seg->frags[0].vaddr));
  1251. }
  1252. goto done;
  1253. }
  1254. if (msdu_info->frm_type == dp_tx_frm_me) {
  1255. tx_desc->me_buffer =
  1256. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1257. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1258. }
  1259. if (is_cce_classified)
  1260. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1261. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1262. if (msdu_info->exception_fw) {
  1263. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1264. }
  1265. /*
  1266. * Enqueue the Tx MSDU descriptor to HW for transmit
  1267. */
  1268. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1269. htt_tcl_metadata, tx_q->ring_id, NULL);
  1270. if (status != QDF_STATUS_SUCCESS) {
  1271. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1272. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1273. __func__, tx_desc, tx_q->ring_id);
  1274. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1275. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1276. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1277. goto done;
  1278. }
  1279. /*
  1280. * TODO
  1281. * if tso_info structure can be modified to have curr_seg
  1282. * as first element, following 2 blocks of code (for TSO and SG)
  1283. * can be combined into 1
  1284. */
  1285. /*
  1286. * For frames with multiple segments (TSO, ME), jump to next
  1287. * segment.
  1288. */
  1289. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1290. if (msdu_info->u.tso_info.curr_seg->next) {
  1291. msdu_info->u.tso_info.curr_seg =
  1292. msdu_info->u.tso_info.curr_seg->next;
  1293. /*
  1294. * If this is a jumbo nbuf, then increment the number of
  1295. * nbuf users for each additional segment of the msdu.
  1296. * This will ensure that the skb is freed only after
  1297. * receiving tx completion for all segments of an nbuf
  1298. */
  1299. qdf_nbuf_inc_users(nbuf);
  1300. /* Check with MCL if this is needed */
  1301. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1302. }
  1303. }
  1304. /*
  1305. * For Multicast-Unicast converted packets,
  1306. * each converted frame (for a client) is represented as
  1307. * 1 segment
  1308. */
  1309. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1310. (msdu_info->frm_type == dp_tx_frm_me)) {
  1311. if (msdu_info->u.sg_info.curr_seg->next) {
  1312. msdu_info->u.sg_info.curr_seg =
  1313. msdu_info->u.sg_info.curr_seg->next;
  1314. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1315. }
  1316. }
  1317. i++;
  1318. }
  1319. nbuf = NULL;
  1320. done:
  1321. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1322. hal_srng_access_end(soc->hal_soc, hal_srng);
  1323. hif_pm_runtime_put(soc->hif_handle);
  1324. } else {
  1325. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1326. }
  1327. return nbuf;
  1328. }
  1329. /**
  1330. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1331. * for SG frames
  1332. * @vdev: DP vdev handle
  1333. * @nbuf: skb
  1334. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1335. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1336. *
  1337. * Return: NULL on success,
  1338. * nbuf when it fails to send
  1339. */
  1340. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1341. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1342. {
  1343. uint32_t cur_frag, nr_frags;
  1344. qdf_dma_addr_t paddr;
  1345. struct dp_tx_sg_info_s *sg_info;
  1346. sg_info = &msdu_info->u.sg_info;
  1347. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1348. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1349. QDF_DMA_TO_DEVICE)) {
  1350. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1351. "dma map error");
  1352. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1353. qdf_nbuf_free(nbuf);
  1354. return NULL;
  1355. }
  1356. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1357. seg_info->frags[0].paddr_lo = paddr;
  1358. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1359. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1360. seg_info->frags[0].vaddr = (void *) nbuf;
  1361. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1362. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1363. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1364. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1365. "frag dma map error");
  1366. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1367. qdf_nbuf_free(nbuf);
  1368. return NULL;
  1369. }
  1370. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1371. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1372. seg_info->frags[cur_frag + 1].paddr_hi =
  1373. ((uint64_t) paddr) >> 32;
  1374. seg_info->frags[cur_frag + 1].len =
  1375. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1376. }
  1377. seg_info->frag_cnt = (cur_frag + 1);
  1378. seg_info->total_len = qdf_nbuf_len(nbuf);
  1379. seg_info->next = NULL;
  1380. sg_info->curr_seg = seg_info;
  1381. msdu_info->frm_type = dp_tx_frm_sg;
  1382. msdu_info->num_seg = 1;
  1383. return nbuf;
  1384. }
  1385. #ifdef MESH_MODE_SUPPORT
  1386. /**
  1387. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1388. and prepare msdu_info for mesh frames.
  1389. * @vdev: DP vdev handle
  1390. * @nbuf: skb
  1391. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1392. *
  1393. * Return: NULL on failure,
  1394. * nbuf when extracted successfully
  1395. */
  1396. static
  1397. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1398. struct dp_tx_msdu_info_s *msdu_info)
  1399. {
  1400. struct meta_hdr_s *mhdr;
  1401. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1402. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1403. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1404. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1405. msdu_info->exception_fw = 0;
  1406. goto remove_meta_hdr;
  1407. }
  1408. msdu_info->exception_fw = 1;
  1409. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1410. meta_data->host_tx_desc_pool = 1;
  1411. meta_data->update_peer_cache = 1;
  1412. meta_data->learning_frame = 1;
  1413. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1414. meta_data->power = mhdr->power;
  1415. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1416. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1417. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1418. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1419. meta_data->dyn_bw = 1;
  1420. meta_data->valid_pwr = 1;
  1421. meta_data->valid_mcs_mask = 1;
  1422. meta_data->valid_nss_mask = 1;
  1423. meta_data->valid_preamble_type = 1;
  1424. meta_data->valid_retries = 1;
  1425. meta_data->valid_bw_info = 1;
  1426. }
  1427. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1428. meta_data->encrypt_type = 0;
  1429. meta_data->valid_encrypt_type = 1;
  1430. meta_data->learning_frame = 0;
  1431. }
  1432. meta_data->valid_key_flags = 1;
  1433. meta_data->key_flags = (mhdr->keyix & 0x3);
  1434. remove_meta_hdr:
  1435. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1436. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1437. "qdf_nbuf_pull_head failed");
  1438. qdf_nbuf_free(nbuf);
  1439. return NULL;
  1440. }
  1441. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1442. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1443. else
  1444. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1445. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1446. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1447. " tid %d to_fw %d",
  1448. __func__, msdu_info->meta_data[0],
  1449. msdu_info->meta_data[1],
  1450. msdu_info->meta_data[2],
  1451. msdu_info->meta_data[3],
  1452. msdu_info->meta_data[4],
  1453. msdu_info->meta_data[5],
  1454. msdu_info->tid, msdu_info->exception_fw);
  1455. return nbuf;
  1456. }
  1457. #else
  1458. static
  1459. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1460. struct dp_tx_msdu_info_s *msdu_info)
  1461. {
  1462. return nbuf;
  1463. }
  1464. #endif
  1465. #ifdef DP_FEATURE_NAWDS_TX
  1466. /**
  1467. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1468. * @vdev: dp_vdev handle
  1469. * @nbuf: skb
  1470. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1471. * @tx_q: Tx queue to be used for this Tx frame
  1472. * @meta_data: Meta date for mesh
  1473. * @peer_id: peer_id of the peer in case of NAWDS frames
  1474. *
  1475. * return: NULL on success nbuf on failure
  1476. */
  1477. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1478. struct dp_tx_msdu_info_s *msdu_info)
  1479. {
  1480. struct dp_peer *peer = NULL;
  1481. struct dp_soc *soc = vdev->pdev->soc;
  1482. struct dp_ast_entry *ast_entry = NULL;
  1483. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1484. uint16_t peer_id = HTT_INVALID_PEER;
  1485. struct dp_peer *sa_peer = NULL;
  1486. qdf_nbuf_t nbuf_copy;
  1487. qdf_spin_lock_bh(&(soc->ast_lock));
  1488. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1489. (soc,
  1490. (uint8_t *)(eh->ether_shost),
  1491. vdev->pdev->pdev_id);
  1492. if (ast_entry)
  1493. sa_peer = ast_entry->peer;
  1494. qdf_spin_unlock_bh(&(soc->ast_lock));
  1495. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1496. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1497. (peer->nawds_enabled)) {
  1498. if (sa_peer == peer) {
  1499. QDF_TRACE(QDF_MODULE_ID_DP,
  1500. QDF_TRACE_LEVEL_DEBUG,
  1501. " %s: broadcast multicast packet",
  1502. __func__);
  1503. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1504. continue;
  1505. }
  1506. nbuf_copy = qdf_nbuf_copy(nbuf);
  1507. if (!nbuf_copy) {
  1508. QDF_TRACE(QDF_MODULE_ID_DP,
  1509. QDF_TRACE_LEVEL_ERROR,
  1510. "nbuf copy failed");
  1511. }
  1512. peer_id = peer->peer_ids[0];
  1513. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1514. msdu_info, peer_id, NULL);
  1515. if (nbuf_copy != NULL) {
  1516. qdf_nbuf_free(nbuf_copy);
  1517. continue;
  1518. }
  1519. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1520. 1, qdf_nbuf_len(nbuf));
  1521. }
  1522. }
  1523. if (peer_id == HTT_INVALID_PEER)
  1524. return nbuf;
  1525. return NULL;
  1526. }
  1527. #endif
  1528. /**
  1529. * dp_check_exc_metadata() - Checks if parameters are valid
  1530. * @tx_exc - holds all exception path parameters
  1531. *
  1532. * Returns true when all the parameters are valid else false
  1533. *
  1534. */
  1535. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1536. {
  1537. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1538. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1539. tx_exc->sec_type > cdp_num_sec_types) {
  1540. return false;
  1541. }
  1542. return true;
  1543. }
  1544. /**
  1545. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1546. * @vap_dev: DP vdev handle
  1547. * @nbuf: skb
  1548. * @tx_exc_metadata: Handle that holds exception path meta data
  1549. *
  1550. * Entry point for Core Tx layer (DP_TX) invoked from
  1551. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1552. *
  1553. * Return: NULL on success,
  1554. * nbuf when it fails to send
  1555. */
  1556. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1557. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1558. {
  1559. struct ether_header *eh = NULL;
  1560. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1561. struct dp_tx_msdu_info_s msdu_info;
  1562. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1563. msdu_info.tid = tx_exc_metadata->tid;
  1564. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1565. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1566. "%s , skb %pM",
  1567. __func__, nbuf->data);
  1568. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1569. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1570. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1571. "Invalid parameters in exception path");
  1572. goto fail;
  1573. }
  1574. /* Basic sanity checks for unsupported packets */
  1575. /* MESH mode */
  1576. if (qdf_unlikely(vdev->mesh_vdev)) {
  1577. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1578. "Mesh mode is not supported in exception path");
  1579. goto fail;
  1580. }
  1581. /* TSO or SG */
  1582. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1583. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1584. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1585. "TSO and SG are not supported in exception path");
  1586. goto fail;
  1587. }
  1588. /* RAW */
  1589. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1590. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1591. "Raw frame is not supported in exception path");
  1592. goto fail;
  1593. }
  1594. /* Mcast enhancement*/
  1595. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1596. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1597. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1598. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1599. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1600. }
  1601. }
  1602. /*
  1603. * Get HW Queue to use for this frame.
  1604. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1605. * dedicated for data and 1 for command.
  1606. * "queue_id" maps to one hardware ring.
  1607. * With each ring, we also associate a unique Tx descriptor pool
  1608. * to minimize lock contention for these resources.
  1609. */
  1610. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1611. /* Single linear frame */
  1612. /*
  1613. * If nbuf is a simple linear frame, use send_single function to
  1614. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1615. * SRNG. There is no need to setup a MSDU extension descriptor.
  1616. */
  1617. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1618. tx_exc_metadata->peer_id, tx_exc_metadata);
  1619. return nbuf;
  1620. fail:
  1621. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1622. "pkt send failed");
  1623. return nbuf;
  1624. }
  1625. /**
  1626. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1627. * @vap_dev: DP vdev handle
  1628. * @nbuf: skb
  1629. *
  1630. * Entry point for Core Tx layer (DP_TX) invoked from
  1631. * hard_start_xmit in OSIF/HDD
  1632. *
  1633. * Return: NULL on success,
  1634. * nbuf when it fails to send
  1635. */
  1636. #ifdef MESH_MODE_SUPPORT
  1637. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1638. {
  1639. struct meta_hdr_s *mhdr;
  1640. qdf_nbuf_t nbuf_mesh = NULL;
  1641. qdf_nbuf_t nbuf_clone = NULL;
  1642. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1643. uint8_t no_enc_frame = 0;
  1644. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1645. if (nbuf_mesh == NULL) {
  1646. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1647. "qdf_nbuf_unshare failed");
  1648. return nbuf;
  1649. }
  1650. nbuf = nbuf_mesh;
  1651. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1652. if ((vdev->sec_type != cdp_sec_type_none) &&
  1653. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1654. no_enc_frame = 1;
  1655. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1656. !no_enc_frame) {
  1657. nbuf_clone = qdf_nbuf_clone(nbuf);
  1658. if (nbuf_clone == NULL) {
  1659. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1660. "qdf_nbuf_clone failed");
  1661. return nbuf;
  1662. }
  1663. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1664. }
  1665. if (nbuf_clone) {
  1666. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1667. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1668. } else {
  1669. qdf_nbuf_free(nbuf_clone);
  1670. }
  1671. }
  1672. if (no_enc_frame)
  1673. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1674. else
  1675. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1676. nbuf = dp_tx_send(vap_dev, nbuf);
  1677. if ((nbuf == NULL) && no_enc_frame) {
  1678. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1679. }
  1680. return nbuf;
  1681. }
  1682. #else
  1683. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1684. {
  1685. return dp_tx_send(vap_dev, nbuf);
  1686. }
  1687. #endif
  1688. /**
  1689. * dp_tx_send() - Transmit a frame on a given VAP
  1690. * @vap_dev: DP vdev handle
  1691. * @nbuf: skb
  1692. *
  1693. * Entry point for Core Tx layer (DP_TX) invoked from
  1694. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1695. * cases
  1696. *
  1697. * Return: NULL on success,
  1698. * nbuf when it fails to send
  1699. */
  1700. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1701. {
  1702. struct ether_header *eh = NULL;
  1703. struct dp_tx_msdu_info_s msdu_info;
  1704. struct dp_tx_seg_info_s seg_info;
  1705. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1706. uint16_t peer_id = HTT_INVALID_PEER;
  1707. qdf_nbuf_t nbuf_mesh = NULL;
  1708. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1709. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1710. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1711. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1712. "%s , skb %pM",
  1713. __func__, nbuf->data);
  1714. /*
  1715. * Set Default Host TID value to invalid TID
  1716. * (TID override disabled)
  1717. */
  1718. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1719. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1720. if (qdf_unlikely(vdev->mesh_vdev)) {
  1721. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1722. &msdu_info);
  1723. if (nbuf_mesh == NULL) {
  1724. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1725. "Extracting mesh metadata failed");
  1726. return nbuf;
  1727. }
  1728. nbuf = nbuf_mesh;
  1729. }
  1730. /*
  1731. * Get HW Queue to use for this frame.
  1732. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1733. * dedicated for data and 1 for command.
  1734. * "queue_id" maps to one hardware ring.
  1735. * With each ring, we also associate a unique Tx descriptor pool
  1736. * to minimize lock contention for these resources.
  1737. */
  1738. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1739. /*
  1740. * TCL H/W supports 2 DSCP-TID mapping tables.
  1741. * Table 1 - Default DSCP-TID mapping table
  1742. * Table 2 - 1 DSCP-TID override table
  1743. *
  1744. * If we need a different DSCP-TID mapping for this vap,
  1745. * call tid_classify to extract DSCP/ToS from frame and
  1746. * map to a TID and store in msdu_info. This is later used
  1747. * to fill in TCL Input descriptor (per-packet TID override).
  1748. */
  1749. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1750. /*
  1751. * Classify the frame and call corresponding
  1752. * "prepare" function which extracts the segment (TSO)
  1753. * and fragmentation information (for TSO , SG, ME, or Raw)
  1754. * into MSDU_INFO structure which is later used to fill
  1755. * SW and HW descriptors.
  1756. */
  1757. if (qdf_nbuf_is_tso(nbuf)) {
  1758. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1759. "%s TSO frame %pK", __func__, vdev);
  1760. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1761. qdf_nbuf_len(nbuf));
  1762. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1763. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1764. qdf_nbuf_len(nbuf));
  1765. return nbuf;
  1766. }
  1767. goto send_multiple;
  1768. }
  1769. /* SG */
  1770. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1771. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1772. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1773. "%s non-TSO SG frame %pK", __func__, vdev);
  1774. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1775. qdf_nbuf_len(nbuf));
  1776. goto send_multiple;
  1777. }
  1778. #ifdef ATH_SUPPORT_IQUE
  1779. /* Mcast to Ucast Conversion*/
  1780. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1781. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1782. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1783. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1784. "%s Mcast frm for ME %pK", __func__, vdev);
  1785. DP_STATS_INC_PKT(vdev,
  1786. tx_i.mcast_en.mcast_pkt, 1,
  1787. qdf_nbuf_len(nbuf));
  1788. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1789. QDF_STATUS_SUCCESS) {
  1790. return NULL;
  1791. }
  1792. }
  1793. }
  1794. #endif
  1795. /* RAW */
  1796. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1797. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1798. if (nbuf == NULL)
  1799. return NULL;
  1800. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1801. "%s Raw frame %pK", __func__, vdev);
  1802. goto send_multiple;
  1803. }
  1804. /* Single linear frame */
  1805. /*
  1806. * If nbuf is a simple linear frame, use send_single function to
  1807. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1808. * SRNG. There is no need to setup a MSDU extension descriptor.
  1809. */
  1810. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1811. return nbuf;
  1812. send_multiple:
  1813. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1814. return nbuf;
  1815. }
  1816. /**
  1817. * dp_tx_reinject_handler() - Tx Reinject Handler
  1818. * @tx_desc: software descriptor head pointer
  1819. * @status : Tx completion status from HTT descriptor
  1820. *
  1821. * This function reinjects frames back to Target.
  1822. * Todo - Host queue needs to be added
  1823. *
  1824. * Return: none
  1825. */
  1826. static
  1827. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1828. {
  1829. struct dp_vdev *vdev;
  1830. struct dp_peer *peer = NULL;
  1831. uint32_t peer_id = HTT_INVALID_PEER;
  1832. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1833. qdf_nbuf_t nbuf_copy = NULL;
  1834. struct dp_tx_msdu_info_s msdu_info;
  1835. struct dp_peer *sa_peer = NULL;
  1836. struct dp_ast_entry *ast_entry = NULL;
  1837. struct dp_soc *soc = NULL;
  1838. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1839. #ifdef WDS_VENDOR_EXTENSION
  1840. int is_mcast = 0, is_ucast = 0;
  1841. int num_peers_3addr = 0;
  1842. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1843. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1844. #endif
  1845. vdev = tx_desc->vdev;
  1846. soc = vdev->pdev->soc;
  1847. qdf_assert(vdev);
  1848. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1849. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1850. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1851. "%s Tx reinject path", __func__);
  1852. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1853. qdf_nbuf_len(tx_desc->nbuf));
  1854. qdf_spin_lock_bh(&(soc->ast_lock));
  1855. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1856. (soc,
  1857. (uint8_t *)(eh->ether_shost),
  1858. vdev->pdev->pdev_id);
  1859. if (ast_entry)
  1860. sa_peer = ast_entry->peer;
  1861. qdf_spin_unlock_bh(&(soc->ast_lock));
  1862. #ifdef WDS_VENDOR_EXTENSION
  1863. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1864. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1865. } else {
  1866. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1867. }
  1868. is_ucast = !is_mcast;
  1869. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1870. if (peer->bss_peer)
  1871. continue;
  1872. /* Detect wds peers that use 3-addr framing for mcast.
  1873. * if there are any, the bss_peer is used to send the
  1874. * the mcast frame using 3-addr format. all wds enabled
  1875. * peers that use 4-addr framing for mcast frames will
  1876. * be duplicated and sent as 4-addr frames below.
  1877. */
  1878. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1879. num_peers_3addr = 1;
  1880. break;
  1881. }
  1882. }
  1883. #endif
  1884. if (qdf_unlikely(vdev->mesh_vdev)) {
  1885. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1886. } else {
  1887. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1888. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1889. #ifdef WDS_VENDOR_EXTENSION
  1890. /*
  1891. * . if 3-addr STA, then send on BSS Peer
  1892. * . if Peer WDS enabled and accept 4-addr mcast,
  1893. * send mcast on that peer only
  1894. * . if Peer WDS enabled and accept 4-addr ucast,
  1895. * send ucast on that peer only
  1896. */
  1897. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1898. (peer->wds_enabled &&
  1899. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1900. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1901. #else
  1902. ((peer->bss_peer &&
  1903. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1904. peer->nawds_enabled)) {
  1905. #endif
  1906. peer_id = DP_INVALID_PEER;
  1907. if (peer->nawds_enabled) {
  1908. peer_id = peer->peer_ids[0];
  1909. if (sa_peer == peer) {
  1910. QDF_TRACE(
  1911. QDF_MODULE_ID_DP,
  1912. QDF_TRACE_LEVEL_DEBUG,
  1913. " %s: multicast packet",
  1914. __func__);
  1915. DP_STATS_INC(peer,
  1916. tx.nawds_mcast_drop, 1);
  1917. continue;
  1918. }
  1919. }
  1920. nbuf_copy = qdf_nbuf_copy(nbuf);
  1921. if (!nbuf_copy) {
  1922. QDF_TRACE(QDF_MODULE_ID_DP,
  1923. QDF_TRACE_LEVEL_DEBUG,
  1924. FL("nbuf copy failed"));
  1925. break;
  1926. }
  1927. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1928. nbuf_copy,
  1929. &msdu_info,
  1930. peer_id,
  1931. NULL);
  1932. if (nbuf_copy) {
  1933. QDF_TRACE(QDF_MODULE_ID_DP,
  1934. QDF_TRACE_LEVEL_DEBUG,
  1935. FL("pkt send failed"));
  1936. qdf_nbuf_free(nbuf_copy);
  1937. } else {
  1938. if (peer_id != DP_INVALID_PEER)
  1939. DP_STATS_INC_PKT(peer,
  1940. tx.nawds_mcast,
  1941. 1, qdf_nbuf_len(nbuf));
  1942. }
  1943. }
  1944. }
  1945. }
  1946. if (vdev->nawds_enabled) {
  1947. peer_id = DP_INVALID_PEER;
  1948. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1949. 1, qdf_nbuf_len(nbuf));
  1950. nbuf = dp_tx_send_msdu_single(vdev,
  1951. nbuf,
  1952. &msdu_info,
  1953. peer_id, NULL);
  1954. if (nbuf) {
  1955. QDF_TRACE(QDF_MODULE_ID_DP,
  1956. QDF_TRACE_LEVEL_DEBUG,
  1957. FL("pkt send failed"));
  1958. qdf_nbuf_free(nbuf);
  1959. }
  1960. } else
  1961. qdf_nbuf_free(nbuf);
  1962. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1963. }
  1964. /**
  1965. * dp_tx_inspect_handler() - Tx Inspect Handler
  1966. * @tx_desc: software descriptor head pointer
  1967. * @status : Tx completion status from HTT descriptor
  1968. *
  1969. * Handles Tx frames sent back to Host for inspection
  1970. * (ProxyARP)
  1971. *
  1972. * Return: none
  1973. */
  1974. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1975. {
  1976. struct dp_soc *soc;
  1977. struct dp_pdev *pdev = tx_desc->pdev;
  1978. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1979. "%s Tx inspect path",
  1980. __func__);
  1981. qdf_assert(pdev);
  1982. soc = pdev->soc;
  1983. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1984. qdf_nbuf_len(tx_desc->nbuf));
  1985. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1986. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1987. }
  1988. #ifdef FEATURE_PERPKT_INFO
  1989. /**
  1990. * dp_get_completion_indication_for_stack() - send completion to stack
  1991. * @soc : dp_soc handle
  1992. * @pdev: dp_pdev handle
  1993. * @peer: dp peer handle
  1994. * @ts: transmit completion status structure
  1995. * @netbuf: Buffer pointer for free
  1996. *
  1997. * This function is used for indication whether buffer needs to be
  1998. * sent to stack for freeing or not
  1999. */
  2000. QDF_STATUS
  2001. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2002. struct dp_pdev *pdev,
  2003. struct dp_peer *peer,
  2004. struct hal_tx_completion_status *ts,
  2005. qdf_nbuf_t netbuf)
  2006. {
  2007. struct tx_capture_hdr *ppdu_hdr;
  2008. uint16_t peer_id = ts->peer_id;
  2009. uint32_t ppdu_id = ts->ppdu_id;
  2010. uint8_t first_msdu = ts->first_msdu;
  2011. uint8_t last_msdu = ts->last_msdu;
  2012. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  2013. return QDF_STATUS_E_NOSUPPORT;
  2014. if (!peer) {
  2015. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2016. FL("Peer Invalid"));
  2017. return QDF_STATUS_E_INVAL;
  2018. }
  2019. if (pdev->mcopy_mode) {
  2020. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2021. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2022. return QDF_STATUS_E_INVAL;
  2023. }
  2024. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2025. pdev->m_copy_id.tx_peer_id = peer_id;
  2026. }
  2027. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2028. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2029. FL("No headroom"));
  2030. return QDF_STATUS_E_NOMEM;
  2031. }
  2032. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2033. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2034. IEEE80211_ADDR_LEN);
  2035. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2036. IEEE80211_ADDR_LEN);
  2037. ppdu_hdr->ppdu_id = ppdu_id;
  2038. ppdu_hdr->peer_id = peer_id;
  2039. ppdu_hdr->first_msdu = first_msdu;
  2040. ppdu_hdr->last_msdu = last_msdu;
  2041. return QDF_STATUS_SUCCESS;
  2042. }
  2043. /**
  2044. * dp_send_completion_to_stack() - send completion to stack
  2045. * @soc : dp_soc handle
  2046. * @pdev: dp_pdev handle
  2047. * @peer_id: peer_id of the peer for which completion came
  2048. * @ppdu_id: ppdu_id
  2049. * @netbuf: Buffer pointer for free
  2050. *
  2051. * This function is used to send completion to stack
  2052. * to free buffer
  2053. */
  2054. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2055. uint16_t peer_id, uint32_t ppdu_id,
  2056. qdf_nbuf_t netbuf)
  2057. {
  2058. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2059. netbuf, peer_id,
  2060. WDI_NO_VAL, pdev->pdev_id);
  2061. }
  2062. #else
  2063. static QDF_STATUS
  2064. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2065. struct dp_pdev *pdev,
  2066. struct dp_peer *peer,
  2067. struct hal_tx_completion_status *ts,
  2068. qdf_nbuf_t netbuf)
  2069. {
  2070. return QDF_STATUS_E_NOSUPPORT;
  2071. }
  2072. static void
  2073. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2074. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2075. {
  2076. }
  2077. #endif
  2078. /**
  2079. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2080. * @soc: Soc handle
  2081. * @desc: software Tx descriptor to be processed
  2082. *
  2083. * Return: none
  2084. */
  2085. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2086. struct dp_tx_desc_s *desc)
  2087. {
  2088. struct dp_vdev *vdev = desc->vdev;
  2089. qdf_nbuf_t nbuf = desc->nbuf;
  2090. /* If it is TDLS mgmt, don't unmap or free the frame */
  2091. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2092. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2093. /* 0 : MSDU buffer, 1 : MLE */
  2094. if (desc->msdu_ext_desc) {
  2095. /* TSO free */
  2096. if (hal_tx_ext_desc_get_tso_enable(
  2097. desc->msdu_ext_desc->vaddr)) {
  2098. /* unmap eash TSO seg before free the nbuf */
  2099. dp_tx_tso_unmap_segment(soc, desc);
  2100. qdf_nbuf_free(nbuf);
  2101. return;
  2102. }
  2103. }
  2104. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2105. if (qdf_likely(!vdev->mesh_vdev))
  2106. qdf_nbuf_free(nbuf);
  2107. else {
  2108. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2109. qdf_nbuf_free(nbuf);
  2110. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2111. } else
  2112. vdev->osif_tx_free_ext((nbuf));
  2113. }
  2114. }
  2115. /**
  2116. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2117. * @vdev: pointer to dp dev handler
  2118. * @status : Tx completion status from HTT descriptor
  2119. *
  2120. * Handles MEC notify event sent from fw to Host
  2121. *
  2122. * Return: none
  2123. */
  2124. #ifdef FEATURE_WDS
  2125. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2126. {
  2127. struct dp_soc *soc;
  2128. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2129. struct dp_peer *peer;
  2130. if (!vdev->wds_enabled)
  2131. return;
  2132. /* MEC required only in STA mode */
  2133. if (vdev->opmode != wlan_op_mode_sta)
  2134. return;
  2135. soc = vdev->pdev->soc;
  2136. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2137. peer = TAILQ_FIRST(&vdev->peer_list);
  2138. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2139. if (!peer) {
  2140. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2141. FL("peer is NULL"));
  2142. return;
  2143. }
  2144. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2145. "%s Tx MEC Handler",
  2146. __func__);
  2147. /* note: mac address is in (status + sizeof(uint32_t)) */
  2148. if (qdf_mem_cmp((status + sizeof(uint32_t)),
  2149. vdev->mac_addr.raw,
  2150. DP_MAC_ADDR_LEN))
  2151. dp_peer_add_ast(soc,
  2152. peer,
  2153. (status + sizeof(uint32_t)),
  2154. CDP_TXRX_AST_TYPE_MEC,
  2155. flags);
  2156. }
  2157. #endif
  2158. #ifdef MESH_MODE_SUPPORT
  2159. /**
  2160. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2161. * in mesh meta header
  2162. * @tx_desc: software descriptor head pointer
  2163. * @ts: pointer to tx completion stats
  2164. * Return: none
  2165. */
  2166. static
  2167. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2168. struct hal_tx_completion_status *ts)
  2169. {
  2170. struct meta_hdr_s *mhdr;
  2171. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2172. if (!tx_desc->msdu_ext_desc) {
  2173. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2174. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2175. "netbuf %pK offset %d",
  2176. netbuf, tx_desc->pkt_offset);
  2177. return;
  2178. }
  2179. }
  2180. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2181. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2182. "netbuf %pK offset %d", netbuf,
  2183. sizeof(struct meta_hdr_s));
  2184. return;
  2185. }
  2186. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2187. mhdr->rssi = ts->ack_frame_rssi;
  2188. mhdr->channel = tx_desc->pdev->operating_channel;
  2189. }
  2190. #else
  2191. static
  2192. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2193. struct hal_tx_completion_status *ts)
  2194. {
  2195. }
  2196. #endif
  2197. /**
  2198. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2199. * @peer: Handle to DP peer
  2200. * @ts: pointer to HAL Tx completion stats
  2201. *
  2202. * Return: None
  2203. */
  2204. static inline void
  2205. dp_tx_update_peer_stats(struct dp_peer *peer,
  2206. struct hal_tx_completion_status *ts)
  2207. {
  2208. struct dp_pdev *pdev = peer->vdev->pdev;
  2209. struct dp_soc *soc = pdev->soc;
  2210. uint8_t mcs, pkt_type;
  2211. mcs = ts->mcs;
  2212. pkt_type = ts->pkt_type;
  2213. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2214. dp_err("Release source is not from TQM");
  2215. return;
  2216. }
  2217. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2218. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2219. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2220. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2221. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2222. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2223. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2224. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2225. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2226. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2227. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2228. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2229. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2230. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2231. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2232. dp_err("Tx completion has no valid acknowledgment");
  2233. return;
  2234. }
  2235. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2236. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2237. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2238. /*
  2239. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2240. * Return from here if HTT PPDU events are enabled.
  2241. */
  2242. if (!(soc->process_tx_status))
  2243. return;
  2244. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2245. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2246. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2247. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2248. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2249. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2250. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2251. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2252. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2253. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2254. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2255. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2256. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2257. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2258. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2259. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2260. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2261. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2262. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2263. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2264. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2265. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2266. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2267. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2268. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2269. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2270. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2271. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2272. soc->cdp_soc.ol_ops->update_dp_stats(pdev->ctrl_pdev,
  2273. &peer->stats, ts->peer_id,
  2274. UPDATE_PEER_STATS);
  2275. }
  2276. }
  2277. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2278. /**
  2279. * dp_tx_flow_pool_lock() - take flow pool lock
  2280. * @soc: core txrx main context
  2281. * @tx_desc: tx desc
  2282. *
  2283. * Return: None
  2284. */
  2285. static inline
  2286. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2287. struct dp_tx_desc_s *tx_desc)
  2288. {
  2289. struct dp_tx_desc_pool_s *pool;
  2290. uint8_t desc_pool_id;
  2291. desc_pool_id = tx_desc->pool_id;
  2292. pool = &soc->tx_desc[desc_pool_id];
  2293. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2294. }
  2295. /**
  2296. * dp_tx_flow_pool_unlock() - release flow pool lock
  2297. * @soc: core txrx main context
  2298. * @tx_desc: tx desc
  2299. *
  2300. * Return: None
  2301. */
  2302. static inline
  2303. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2304. struct dp_tx_desc_s *tx_desc)
  2305. {
  2306. struct dp_tx_desc_pool_s *pool;
  2307. uint8_t desc_pool_id;
  2308. desc_pool_id = tx_desc->pool_id;
  2309. pool = &soc->tx_desc[desc_pool_id];
  2310. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2311. }
  2312. #else
  2313. static inline
  2314. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2315. {
  2316. }
  2317. static inline
  2318. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2319. {
  2320. }
  2321. #endif
  2322. /**
  2323. * dp_tx_notify_completion() - Notify tx completion for this desc
  2324. * @soc: core txrx main context
  2325. * @tx_desc: tx desc
  2326. * @netbuf: buffer
  2327. *
  2328. * Return: none
  2329. */
  2330. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2331. struct dp_tx_desc_s *tx_desc,
  2332. qdf_nbuf_t netbuf)
  2333. {
  2334. void *osif_dev;
  2335. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2336. qdf_assert(tx_desc);
  2337. dp_tx_flow_pool_lock(soc, tx_desc);
  2338. if (!tx_desc->vdev ||
  2339. !tx_desc->vdev->osif_vdev) {
  2340. dp_tx_flow_pool_unlock(soc, tx_desc);
  2341. return;
  2342. }
  2343. osif_dev = tx_desc->vdev->osif_vdev;
  2344. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2345. dp_tx_flow_pool_unlock(soc, tx_desc);
  2346. if (tx_compl_cbk)
  2347. tx_compl_cbk(netbuf, osif_dev);
  2348. }
  2349. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2350. * @pdev: pdev handle
  2351. * @tid: tid value
  2352. * @txdesc_ts: timestamp from txdesc
  2353. * @ppdu_id: ppdu id
  2354. *
  2355. * Return: none
  2356. */
  2357. #ifdef FEATURE_PERPKT_INFO
  2358. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2359. uint8_t tid,
  2360. uint64_t txdesc_ts,
  2361. uint32_t ppdu_id)
  2362. {
  2363. uint64_t delta_ms;
  2364. struct cdp_tx_sojourn_stats *sojourn_stats;
  2365. if (pdev->enhanced_stats_en == 0)
  2366. return;
  2367. if (pdev->sojourn_stats.ppdu_seq_id == 0)
  2368. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2369. if (ppdu_id != pdev->sojourn_stats.ppdu_seq_id) {
  2370. if (!pdev->sojourn_buf)
  2371. return;
  2372. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2373. qdf_nbuf_data(pdev->sojourn_buf);
  2374. qdf_mem_copy(sojourn_stats, &pdev->sojourn_stats,
  2375. sizeof(struct cdp_tx_sojourn_stats));
  2376. qdf_mem_zero(&pdev->sojourn_stats,
  2377. sizeof(struct cdp_tx_sojourn_stats));
  2378. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2379. pdev->sojourn_buf, HTT_INVALID_PEER,
  2380. WDI_NO_VAL, pdev->pdev_id);
  2381. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2382. }
  2383. if (tid == HTT_INVALID_TID)
  2384. return;
  2385. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2386. txdesc_ts;
  2387. qdf_ewma_tx_lag_add(&pdev->sojourn_stats.avg_sojourn_msdu[tid],
  2388. delta_ms);
  2389. pdev->sojourn_stats.sum_sojourn_msdu[tid] += delta_ms;
  2390. pdev->sojourn_stats.num_msdus[tid]++;
  2391. }
  2392. #else
  2393. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2394. uint8_t tid,
  2395. uint64_t txdesc_ts,
  2396. uint32_t ppdu_id)
  2397. {
  2398. }
  2399. #endif
  2400. /**
  2401. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2402. * @soc: DP Soc handle
  2403. * @tx_desc: software Tx descriptor
  2404. * @ts : Tx completion status from HAL/HTT descriptor
  2405. *
  2406. * Return: none
  2407. */
  2408. static inline void
  2409. dp_tx_comp_process_desc(struct dp_soc *soc,
  2410. struct dp_tx_desc_s *desc,
  2411. struct hal_tx_completion_status *ts,
  2412. struct dp_peer *peer)
  2413. {
  2414. /*
  2415. * m_copy/tx_capture modes are not supported for
  2416. * scatter gather packets
  2417. */
  2418. if (!(desc->msdu_ext_desc) &&
  2419. (dp_get_completion_indication_for_stack(soc, desc->pdev,
  2420. peer, ts, desc->nbuf)
  2421. == QDF_STATUS_SUCCESS)) {
  2422. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2423. QDF_DMA_TO_DEVICE);
  2424. dp_send_completion_to_stack(soc, desc->pdev, ts->peer_id,
  2425. ts->ppdu_id, desc->nbuf);
  2426. } else {
  2427. dp_tx_comp_free_buf(soc, desc);
  2428. }
  2429. }
  2430. /**
  2431. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2432. * @tx_desc: software descriptor head pointer
  2433. * @ts: Tx completion status
  2434. * @peer: peer handle
  2435. *
  2436. * Return: none
  2437. */
  2438. static inline
  2439. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2440. struct hal_tx_completion_status *ts,
  2441. struct dp_peer *peer)
  2442. {
  2443. uint32_t length;
  2444. struct dp_soc *soc = NULL;
  2445. struct dp_vdev *vdev = tx_desc->vdev;
  2446. struct ether_header *eh =
  2447. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2448. if (!vdev) {
  2449. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2450. "invalid vdev");
  2451. goto out;
  2452. }
  2453. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2454. "-------------------- \n"
  2455. "Tx Completion Stats: \n"
  2456. "-------------------- \n"
  2457. "ack_frame_rssi = %d \n"
  2458. "first_msdu = %d \n"
  2459. "last_msdu = %d \n"
  2460. "msdu_part_of_amsdu = %d \n"
  2461. "rate_stats valid = %d \n"
  2462. "bw = %d \n"
  2463. "pkt_type = %d \n"
  2464. "stbc = %d \n"
  2465. "ldpc = %d \n"
  2466. "sgi = %d \n"
  2467. "mcs = %d \n"
  2468. "ofdma = %d \n"
  2469. "tones_in_ru = %d \n"
  2470. "tsf = %d \n"
  2471. "ppdu_id = %d \n"
  2472. "transmit_cnt = %d \n"
  2473. "tid = %d \n"
  2474. "peer_id = %d\n",
  2475. ts->ack_frame_rssi, ts->first_msdu,
  2476. ts->last_msdu, ts->msdu_part_of_amsdu,
  2477. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2478. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2479. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2480. ts->transmit_cnt, ts->tid, ts->peer_id);
  2481. soc = vdev->pdev->soc;
  2482. /* Update SoC level stats */
  2483. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2484. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2485. /* Update per-packet stats for mesh mode */
  2486. if (qdf_unlikely(vdev->mesh_vdev) &&
  2487. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2488. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2489. length = qdf_nbuf_len(tx_desc->nbuf);
  2490. /* Update peer level stats */
  2491. if (!peer) {
  2492. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2493. "invalid peer");
  2494. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2495. goto out;
  2496. }
  2497. if (qdf_likely(!peer->bss_peer)) {
  2498. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2499. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2500. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2501. } else {
  2502. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2503. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2504. if ((peer->vdev->tx_encap_type ==
  2505. htt_cmn_pkt_type_ethernet) &&
  2506. IEEE80211_IS_BROADCAST(eh->ether_dhost)) {
  2507. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2508. }
  2509. }
  2510. }
  2511. dp_tx_update_peer_stats(peer, ts);
  2512. out:
  2513. return;
  2514. }
  2515. /**
  2516. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2517. * @soc: core txrx main context
  2518. * @comp_head: software descriptor head pointer
  2519. *
  2520. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2521. * and release the software descriptors after processing is complete
  2522. *
  2523. * Return: none
  2524. */
  2525. static void
  2526. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2527. struct dp_tx_desc_s *comp_head)
  2528. {
  2529. struct dp_tx_desc_s *desc;
  2530. struct dp_tx_desc_s *next;
  2531. struct hal_tx_completion_status ts = {0};
  2532. struct dp_peer *peer;
  2533. DP_HIST_INIT();
  2534. desc = comp_head;
  2535. while (desc) {
  2536. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2537. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2538. dp_tx_comp_process_tx_status(desc, &ts, peer);
  2539. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2540. if (peer)
  2541. dp_peer_unref_del_find_by_id(peer);
  2542. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2543. next = desc->next;
  2544. dp_tx_desc_release(desc, desc->pool_id);
  2545. desc = next;
  2546. }
  2547. DP_TX_HIST_STATS_PER_PDEV();
  2548. }
  2549. /**
  2550. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2551. * @tx_desc: software descriptor head pointer
  2552. * @status : Tx completion status from HTT descriptor
  2553. *
  2554. * This function will process HTT Tx indication messages from Target
  2555. *
  2556. * Return: none
  2557. */
  2558. static
  2559. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2560. {
  2561. uint8_t tx_status;
  2562. struct dp_pdev *pdev;
  2563. struct dp_vdev *vdev;
  2564. struct dp_soc *soc;
  2565. struct hal_tx_completion_status ts = {0};
  2566. uint32_t *htt_desc = (uint32_t *)status;
  2567. struct dp_peer *peer;
  2568. qdf_nbuf_t nbuf;
  2569. qdf_assert(tx_desc->pdev);
  2570. pdev = tx_desc->pdev;
  2571. vdev = tx_desc->vdev;
  2572. soc = pdev->soc;
  2573. nbuf = tx_desc->nbuf;
  2574. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2575. switch (tx_status) {
  2576. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2577. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2578. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2579. {
  2580. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2581. ts.peer_id =
  2582. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2583. htt_desc[2]);
  2584. ts.tid =
  2585. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2586. htt_desc[2]);
  2587. } else {
  2588. ts.peer_id = HTT_INVALID_PEER;
  2589. ts.tid = HTT_INVALID_TID;
  2590. }
  2591. ts.ppdu_id =
  2592. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2593. htt_desc[1]);
  2594. ts.ack_frame_rssi =
  2595. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2596. htt_desc[1]);
  2597. ts.first_msdu = 1;
  2598. ts.last_msdu = 1;
  2599. if (tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)
  2600. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2601. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2602. dp_tx_comp_process_tx_status(tx_desc, &ts, peer);
  2603. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2604. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2605. break;
  2606. }
  2607. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2608. {
  2609. dp_tx_reinject_handler(tx_desc, status);
  2610. break;
  2611. }
  2612. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2613. {
  2614. dp_tx_inspect_handler(tx_desc, status);
  2615. break;
  2616. }
  2617. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2618. {
  2619. qdf_mem_copy(((uint8_t *)&htt_desc[1]),
  2620. &nbuf->data[DP_MAC_ADDR_LEN],
  2621. DP_MAC_ADDR_LEN);
  2622. dp_tx_mec_handler(vdev, status);
  2623. break;
  2624. }
  2625. default:
  2626. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2627. "%s Invalid HTT tx_status %d\n",
  2628. __func__, tx_status);
  2629. break;
  2630. }
  2631. }
  2632. /**
  2633. * dp_tx_comp_handler() - Tx completion handler
  2634. * @soc: core txrx main context
  2635. * @ring_id: completion ring id
  2636. * @quota: No. of packets/descriptors that can be serviced in one loop
  2637. *
  2638. * This function will collect hardware release ring element contents and
  2639. * handle descriptor contents. Based on contents, free packet or handle error
  2640. * conditions
  2641. *
  2642. * Return: none
  2643. */
  2644. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2645. {
  2646. void *tx_comp_hal_desc;
  2647. uint8_t buffer_src;
  2648. uint8_t pool_id;
  2649. uint32_t tx_desc_id;
  2650. struct dp_tx_desc_s *tx_desc = NULL;
  2651. struct dp_tx_desc_s *head_desc = NULL;
  2652. struct dp_tx_desc_s *tail_desc = NULL;
  2653. uint32_t num_processed;
  2654. uint32_t count;
  2655. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2656. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2657. "%s %d : HAL RING Access Failed -- %pK",
  2658. __func__, __LINE__, hal_srng);
  2659. return 0;
  2660. }
  2661. num_processed = 0;
  2662. count = 0;
  2663. /* Find head descriptor from completion ring */
  2664. while (qdf_likely(tx_comp_hal_desc =
  2665. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2666. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2667. /* If this buffer was not released by TQM or FW, then it is not
  2668. * Tx completion indication, assert */
  2669. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2670. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2671. QDF_TRACE(QDF_MODULE_ID_DP,
  2672. QDF_TRACE_LEVEL_FATAL,
  2673. "Tx comp release_src != TQM | FW");
  2674. qdf_assert_always(0);
  2675. }
  2676. /* Get descriptor id */
  2677. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2678. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2679. DP_TX_DESC_ID_POOL_OS;
  2680. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2681. continue;
  2682. /* Find Tx descriptor */
  2683. tx_desc = dp_tx_desc_find(soc, pool_id,
  2684. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2685. DP_TX_DESC_ID_PAGE_OS,
  2686. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2687. DP_TX_DESC_ID_OFFSET_OS);
  2688. /*
  2689. * If the release source is FW, process the HTT status
  2690. */
  2691. if (qdf_unlikely(buffer_src ==
  2692. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2693. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2694. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2695. htt_tx_status);
  2696. dp_tx_process_htt_completion(tx_desc,
  2697. htt_tx_status);
  2698. } else {
  2699. /* Pool id is not matching. Error */
  2700. if (tx_desc->pool_id != pool_id) {
  2701. QDF_TRACE(QDF_MODULE_ID_DP,
  2702. QDF_TRACE_LEVEL_FATAL,
  2703. "Tx Comp pool id %d not matched %d",
  2704. pool_id, tx_desc->pool_id);
  2705. qdf_assert_always(0);
  2706. }
  2707. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2708. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2709. QDF_TRACE(QDF_MODULE_ID_DP,
  2710. QDF_TRACE_LEVEL_FATAL,
  2711. "Txdesc invalid, flgs = %x,id = %d",
  2712. tx_desc->flags, tx_desc_id);
  2713. qdf_assert_always(0);
  2714. }
  2715. /* First ring descriptor on the cycle */
  2716. if (!head_desc) {
  2717. head_desc = tx_desc;
  2718. tail_desc = tx_desc;
  2719. }
  2720. tail_desc->next = tx_desc;
  2721. tx_desc->next = NULL;
  2722. tail_desc = tx_desc;
  2723. /* Collect hw completion contents */
  2724. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2725. &tx_desc->comp, 1);
  2726. }
  2727. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2728. /*
  2729. * Processed packet count is more than given quota
  2730. * stop to processing
  2731. */
  2732. if ((num_processed >= quota))
  2733. break;
  2734. count++;
  2735. }
  2736. hal_srng_access_end(soc->hal_soc, hal_srng);
  2737. /* Process the reaped descriptors */
  2738. if (head_desc)
  2739. dp_tx_comp_process_desc_list(soc, head_desc);
  2740. return num_processed;
  2741. }
  2742. #ifdef CONVERGED_TDLS_ENABLE
  2743. /**
  2744. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2745. *
  2746. * @data_vdev - which vdev should transmit the tx data frames
  2747. * @tx_spec - what non-standard handling to apply to the tx data frames
  2748. * @msdu_list - NULL-terminated list of tx MSDUs
  2749. *
  2750. * Return: NULL on success,
  2751. * nbuf when it fails to send
  2752. */
  2753. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2754. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2755. {
  2756. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2757. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2758. vdev->is_tdls_frame = true;
  2759. return dp_tx_send(vdev_handle, msdu_list);
  2760. }
  2761. #endif
  2762. /**
  2763. * dp_tx_vdev_attach() - attach vdev to dp tx
  2764. * @vdev: virtual device instance
  2765. *
  2766. * Return: QDF_STATUS_SUCCESS: success
  2767. * QDF_STATUS_E_RESOURCES: Error return
  2768. */
  2769. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2770. {
  2771. /*
  2772. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2773. */
  2774. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2775. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2776. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2777. vdev->vdev_id);
  2778. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2779. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2780. /*
  2781. * Set HTT Extension Valid bit to 0 by default
  2782. */
  2783. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2784. dp_tx_vdev_update_search_flags(vdev);
  2785. return QDF_STATUS_SUCCESS;
  2786. }
  2787. /**
  2788. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2789. * @vdev: virtual device instance
  2790. *
  2791. * Return: void
  2792. *
  2793. */
  2794. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2795. {
  2796. struct dp_soc *soc = vdev->pdev->soc;
  2797. /*
  2798. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2799. * for TDLS link
  2800. *
  2801. * Enable AddrY (SA based search) only for non-WDS STA and
  2802. * ProxySTA VAP modes.
  2803. *
  2804. * In all other VAP modes, only DA based search should be
  2805. * enabled
  2806. */
  2807. if (vdev->opmode == wlan_op_mode_sta &&
  2808. vdev->tdls_link_connected)
  2809. vdev->hal_desc_addr_search_flags =
  2810. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2811. else if ((vdev->opmode == wlan_op_mode_sta &&
  2812. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2813. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2814. else
  2815. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2816. /* Set search type only when peer map v2 messaging is enabled
  2817. * as we will have the search index (AST hash) only when v2 is
  2818. * enabled
  2819. */
  2820. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  2821. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  2822. else
  2823. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  2824. }
  2825. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2826. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2827. {
  2828. }
  2829. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2830. /* dp_tx_desc_flush() - release resources associated
  2831. * to tx_desc
  2832. * @vdev: virtual device instance
  2833. *
  2834. * This function will free all outstanding Tx buffers,
  2835. * including ME buffer for which either free during
  2836. * completion didn't happened or completion is not
  2837. * received.
  2838. */
  2839. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2840. {
  2841. uint8_t i, num_pool;
  2842. uint32_t j;
  2843. uint32_t num_desc;
  2844. struct dp_soc *soc = vdev->pdev->soc;
  2845. struct dp_tx_desc_s *tx_desc = NULL;
  2846. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2847. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2848. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2849. for (i = 0; i < num_pool; i++) {
  2850. for (j = 0; j < num_desc; j++) {
  2851. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2852. if (tx_desc_pool &&
  2853. tx_desc_pool->desc_pages.cacheable_pages) {
  2854. tx_desc = dp_tx_desc_find(soc, i,
  2855. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2856. DP_TX_DESC_ID_PAGE_OS,
  2857. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2858. DP_TX_DESC_ID_OFFSET_OS);
  2859. if (tx_desc && (tx_desc->vdev == vdev) &&
  2860. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2861. dp_tx_comp_free_buf(soc, tx_desc);
  2862. dp_tx_desc_release(tx_desc, i);
  2863. }
  2864. }
  2865. }
  2866. }
  2867. }
  2868. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2869. /**
  2870. * dp_tx_vdev_detach() - detach vdev from dp tx
  2871. * @vdev: virtual device instance
  2872. *
  2873. * Return: QDF_STATUS_SUCCESS: success
  2874. * QDF_STATUS_E_RESOURCES: Error return
  2875. */
  2876. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2877. {
  2878. dp_tx_desc_flush(vdev);
  2879. return QDF_STATUS_SUCCESS;
  2880. }
  2881. /**
  2882. * dp_tx_pdev_attach() - attach pdev to dp tx
  2883. * @pdev: physical device instance
  2884. *
  2885. * Return: QDF_STATUS_SUCCESS: success
  2886. * QDF_STATUS_E_RESOURCES: Error return
  2887. */
  2888. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2889. {
  2890. struct dp_soc *soc = pdev->soc;
  2891. /* Initialize Flow control counters */
  2892. qdf_atomic_init(&pdev->num_tx_exception);
  2893. qdf_atomic_init(&pdev->num_tx_outstanding);
  2894. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2895. /* Initialize descriptors in TCL Ring */
  2896. hal_tx_init_data_ring(soc->hal_soc,
  2897. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2898. }
  2899. return QDF_STATUS_SUCCESS;
  2900. }
  2901. /**
  2902. * dp_tx_pdev_detach() - detach pdev from dp tx
  2903. * @pdev: physical device instance
  2904. *
  2905. * Return: QDF_STATUS_SUCCESS: success
  2906. * QDF_STATUS_E_RESOURCES: Error return
  2907. */
  2908. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2909. {
  2910. dp_tx_me_exit(pdev);
  2911. return QDF_STATUS_SUCCESS;
  2912. }
  2913. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2914. /* Pools will be allocated dynamically */
  2915. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2916. int num_desc)
  2917. {
  2918. uint8_t i;
  2919. for (i = 0; i < num_pool; i++) {
  2920. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2921. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2922. }
  2923. return 0;
  2924. }
  2925. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2926. {
  2927. uint8_t i;
  2928. for (i = 0; i < num_pool; i++)
  2929. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2930. }
  2931. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2932. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2933. int num_desc)
  2934. {
  2935. uint8_t i;
  2936. /* Allocate software Tx descriptor pools */
  2937. for (i = 0; i < num_pool; i++) {
  2938. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2939. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2940. "%s Tx Desc Pool alloc %d failed %pK",
  2941. __func__, i, soc);
  2942. return ENOMEM;
  2943. }
  2944. }
  2945. return 0;
  2946. }
  2947. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2948. {
  2949. uint8_t i;
  2950. for (i = 0; i < num_pool; i++) {
  2951. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2952. if (dp_tx_desc_pool_free(soc, i)) {
  2953. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2954. "%s Tx Desc Pool Free failed", __func__);
  2955. }
  2956. }
  2957. }
  2958. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2959. /**
  2960. * dp_tx_soc_detach() - detach soc from dp tx
  2961. * @soc: core txrx main context
  2962. *
  2963. * This function will detach dp tx into main device context
  2964. * will free dp tx resource and initialize resources
  2965. *
  2966. * Return: QDF_STATUS_SUCCESS: success
  2967. * QDF_STATUS_E_RESOURCES: Error return
  2968. */
  2969. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2970. {
  2971. uint8_t num_pool;
  2972. uint16_t num_desc;
  2973. uint16_t num_ext_desc;
  2974. uint8_t i;
  2975. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2976. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2977. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2978. dp_tx_flow_control_deinit(soc);
  2979. dp_tx_delete_static_pools(soc, num_pool);
  2980. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2981. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  2982. __func__, num_pool, num_desc);
  2983. for (i = 0; i < num_pool; i++) {
  2984. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2985. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2986. "%s Tx Ext Desc Pool Free failed",
  2987. __func__);
  2988. return QDF_STATUS_E_RESOURCES;
  2989. }
  2990. }
  2991. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2992. "%s MSDU Ext Desc Pool %d Free descs = %d",
  2993. __func__, num_pool, num_ext_desc);
  2994. for (i = 0; i < num_pool; i++) {
  2995. dp_tx_tso_desc_pool_free(soc, i);
  2996. }
  2997. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2998. "%s TSO Desc Pool %d Free descs = %d",
  2999. __func__, num_pool, num_desc);
  3000. for (i = 0; i < num_pool; i++)
  3001. dp_tx_tso_num_seg_pool_free(soc, i);
  3002. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3003. "%s TSO Num of seg Desc Pool %d Free descs = %d",
  3004. __func__, num_pool, num_desc);
  3005. return QDF_STATUS_SUCCESS;
  3006. }
  3007. /**
  3008. * dp_tx_soc_attach() - attach soc to dp tx
  3009. * @soc: core txrx main context
  3010. *
  3011. * This function will attach dp tx into main device context
  3012. * will allocate dp tx resource and initialize resources
  3013. *
  3014. * Return: QDF_STATUS_SUCCESS: success
  3015. * QDF_STATUS_E_RESOURCES: Error return
  3016. */
  3017. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3018. {
  3019. uint8_t i;
  3020. uint8_t num_pool;
  3021. uint32_t num_desc;
  3022. uint32_t num_ext_desc;
  3023. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3024. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3025. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3026. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3027. goto fail;
  3028. dp_tx_flow_control_init(soc);
  3029. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3030. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3031. __func__, num_pool, num_desc);
  3032. /* Allocate extension tx descriptor pools */
  3033. for (i = 0; i < num_pool; i++) {
  3034. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3035. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3036. "MSDU Ext Desc Pool alloc %d failed %pK",
  3037. i, soc);
  3038. goto fail;
  3039. }
  3040. }
  3041. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3042. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3043. __func__, num_pool, num_ext_desc);
  3044. for (i = 0; i < num_pool; i++) {
  3045. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3046. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3047. "TSO Desc Pool alloc %d failed %pK",
  3048. i, soc);
  3049. goto fail;
  3050. }
  3051. }
  3052. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3053. "%s TSO Desc Alloc %d, descs = %d",
  3054. __func__, num_pool, num_desc);
  3055. for (i = 0; i < num_pool; i++) {
  3056. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3057. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3058. "TSO Num of seg Pool alloc %d failed %pK",
  3059. i, soc);
  3060. goto fail;
  3061. }
  3062. }
  3063. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3064. "%s TSO Num of seg pool Alloc %d, descs = %d",
  3065. __func__, num_pool, num_desc);
  3066. /* Initialize descriptors in TCL Rings */
  3067. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3068. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3069. hal_tx_init_data_ring(soc->hal_soc,
  3070. soc->tcl_data_ring[i].hal_srng);
  3071. }
  3072. }
  3073. /*
  3074. * todo - Add a runtime config option to enable this.
  3075. */
  3076. /*
  3077. * Due to multiple issues on NPR EMU, enable it selectively
  3078. * only for NPR EMU, should be removed, once NPR platforms
  3079. * are stable.
  3080. */
  3081. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3082. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3083. "%s HAL Tx init Success", __func__);
  3084. return QDF_STATUS_SUCCESS;
  3085. fail:
  3086. /* Detach will take care of freeing only allocated resources */
  3087. dp_tx_soc_detach(soc);
  3088. return QDF_STATUS_E_RESOURCES;
  3089. }
  3090. /*
  3091. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3092. * pdev: pointer to DP PDEV structure
  3093. * seg_info_head: Pointer to the head of list
  3094. *
  3095. * return: void
  3096. */
  3097. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3098. struct dp_tx_seg_info_s *seg_info_head)
  3099. {
  3100. struct dp_tx_me_buf_t *mc_uc_buf;
  3101. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3102. qdf_nbuf_t nbuf = NULL;
  3103. uint64_t phy_addr;
  3104. while (seg_info_head) {
  3105. nbuf = seg_info_head->nbuf;
  3106. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3107. seg_info_head->frags[0].vaddr;
  3108. phy_addr = seg_info_head->frags[0].paddr_hi;
  3109. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3110. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3111. phy_addr,
  3112. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  3113. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3114. qdf_nbuf_free(nbuf);
  3115. seg_info_new = seg_info_head;
  3116. seg_info_head = seg_info_head->next;
  3117. qdf_mem_free(seg_info_new);
  3118. }
  3119. }
  3120. /**
  3121. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3122. * @vdev: DP VDEV handle
  3123. * @nbuf: Multicast nbuf
  3124. * @newmac: Table of the clients to which packets have to be sent
  3125. * @new_mac_cnt: No of clients
  3126. *
  3127. * return: no of converted packets
  3128. */
  3129. uint16_t
  3130. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3131. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  3132. {
  3133. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3134. struct dp_pdev *pdev = vdev->pdev;
  3135. struct ether_header *eh;
  3136. uint8_t *data;
  3137. uint16_t len;
  3138. /* reference to frame dst addr */
  3139. uint8_t *dstmac;
  3140. /* copy of original frame src addr */
  3141. uint8_t srcmac[DP_MAC_ADDR_LEN];
  3142. /* local index into newmac */
  3143. uint8_t new_mac_idx = 0;
  3144. struct dp_tx_me_buf_t *mc_uc_buf;
  3145. qdf_nbuf_t nbuf_clone;
  3146. struct dp_tx_msdu_info_s msdu_info;
  3147. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3148. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3149. struct dp_tx_seg_info_s *seg_info_new;
  3150. struct dp_tx_frag_info_s data_frag;
  3151. qdf_dma_addr_t paddr_data;
  3152. qdf_dma_addr_t paddr_mcbuf = 0;
  3153. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  3154. QDF_STATUS status;
  3155. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  3156. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3157. eh = (struct ether_header *) nbuf;
  3158. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  3159. len = qdf_nbuf_len(nbuf);
  3160. data = qdf_nbuf_data(nbuf);
  3161. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3162. QDF_DMA_TO_DEVICE);
  3163. if (status) {
  3164. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3165. "Mapping failure Error:%d", status);
  3166. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3167. qdf_nbuf_free(nbuf);
  3168. return 1;
  3169. }
  3170. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3171. /*preparing data fragment*/
  3172. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3173. data_frag.paddr_lo = (uint32_t)paddr_data;
  3174. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3175. data_frag.len = len - DP_MAC_ADDR_LEN;
  3176. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3177. dstmac = newmac[new_mac_idx];
  3178. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3179. "added mac addr (%pM)", dstmac);
  3180. /* Check for NULL Mac Address */
  3181. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3182. continue;
  3183. /* frame to self mac. skip */
  3184. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3185. continue;
  3186. /*
  3187. * TODO: optimize to avoid malloc in per-packet path
  3188. * For eg. seg_pool can be made part of vdev structure
  3189. */
  3190. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3191. if (!seg_info_new) {
  3192. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3193. "alloc failed");
  3194. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3195. goto fail_seg_alloc;
  3196. }
  3197. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3198. if (mc_uc_buf == NULL)
  3199. goto fail_buf_alloc;
  3200. /*
  3201. * TODO: Check if we need to clone the nbuf
  3202. * Or can we just use the reference for all cases
  3203. */
  3204. if (new_mac_idx < (new_mac_cnt - 1)) {
  3205. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3206. if (nbuf_clone == NULL) {
  3207. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3208. goto fail_clone;
  3209. }
  3210. } else {
  3211. /*
  3212. * Update the ref
  3213. * to account for frame sent without cloning
  3214. */
  3215. qdf_nbuf_ref(nbuf);
  3216. nbuf_clone = nbuf;
  3217. }
  3218. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3219. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3220. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3221. &paddr_mcbuf);
  3222. if (status) {
  3223. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3224. "Mapping failure Error:%d", status);
  3225. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3226. goto fail_map;
  3227. }
  3228. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3229. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3230. seg_info_new->frags[0].paddr_hi =
  3231. ((uint64_t) paddr_mcbuf >> 32);
  3232. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3233. seg_info_new->frags[1] = data_frag;
  3234. seg_info_new->nbuf = nbuf_clone;
  3235. seg_info_new->frag_cnt = 2;
  3236. seg_info_new->total_len = len;
  3237. seg_info_new->next = NULL;
  3238. if (seg_info_head == NULL)
  3239. seg_info_head = seg_info_new;
  3240. else
  3241. seg_info_tail->next = seg_info_new;
  3242. seg_info_tail = seg_info_new;
  3243. }
  3244. if (!seg_info_head) {
  3245. goto free_return;
  3246. }
  3247. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3248. msdu_info.num_seg = new_mac_cnt;
  3249. msdu_info.frm_type = dp_tx_frm_me;
  3250. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3251. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3252. while (seg_info_head->next) {
  3253. seg_info_new = seg_info_head;
  3254. seg_info_head = seg_info_head->next;
  3255. qdf_mem_free(seg_info_new);
  3256. }
  3257. qdf_mem_free(seg_info_head);
  3258. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3259. qdf_nbuf_free(nbuf);
  3260. return new_mac_cnt;
  3261. fail_map:
  3262. qdf_nbuf_free(nbuf_clone);
  3263. fail_clone:
  3264. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3265. fail_buf_alloc:
  3266. qdf_mem_free(seg_info_new);
  3267. fail_seg_alloc:
  3268. dp_tx_me_mem_free(pdev, seg_info_head);
  3269. free_return:
  3270. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3271. qdf_nbuf_free(nbuf);
  3272. return 1;
  3273. }