sdm660-common.c 93 KB

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  1. /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/input.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/of_device.h>
  17. #include <sound/pcm_params.h>
  18. #include <dsp/q6afe-v2.h>
  19. #include "msm-pcm-routing-v2.h"
  20. #include "sdm660-common.h"
  21. #include "sdm660-internal.h"
  22. #include "sdm660-external.h"
  23. #include "codecs/msm-cdc-pinctrl.h"
  24. #include "codecs/sdm660_cdc/msm-analog-cdc.h"
  25. #include "codecs/wsa881x.h"
  26. #define DRV_NAME "sdm660-asoc-snd"
  27. #define MSM_INT_DIGITAL_CODEC "msm-dig-codec"
  28. #define PMIC_INT_ANALOG_CODEC "analog-codec"
  29. #define DEV_NAME_STR_LEN 32
  30. #define DEFAULT_MCLK_RATE 9600000
  31. struct dev_config {
  32. u32 sample_rate;
  33. u32 bit_format;
  34. u32 channels;
  35. };
  36. enum {
  37. DP_RX_IDX,
  38. EXT_DISP_RX_IDX_MAX,
  39. };
  40. bool codec_reg_done;
  41. /* TDM default config */
  42. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  43. { /* PRI TDM */
  44. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  45. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  46. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  47. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  48. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  49. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  50. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  51. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  52. },
  53. { /* SEC TDM */
  54. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  55. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  56. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  57. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  58. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  59. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  60. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  61. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  62. },
  63. { /* TERT TDM */
  64. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  65. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  66. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  67. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  68. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  69. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  70. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  71. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  72. },
  73. { /* QUAT TDM */
  74. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  75. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  76. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  77. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  78. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  79. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  80. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  81. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  82. },
  83. { /* QUIN TDM */
  84. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  85. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  86. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  87. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  88. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  89. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  90. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  91. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  92. }
  93. };
  94. /* TDM default config */
  95. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  96. { /* PRI TDM */
  97. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  98. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  99. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  100. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  101. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  102. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  103. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  104. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  105. },
  106. { /* SEC TDM */
  107. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  108. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  109. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  110. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  111. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  112. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  113. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  114. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  115. },
  116. { /* TERT TDM */
  117. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  118. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  119. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  120. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  121. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  122. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  123. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  124. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  125. },
  126. { /* QUAT TDM */
  127. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  128. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  129. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  130. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  131. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  132. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  133. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  134. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  135. },
  136. { /* QUIN TDM */
  137. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  138. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  139. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  140. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  141. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  142. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  143. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  144. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  145. }
  146. };
  147. /* Default configuration of external display BE */
  148. static struct dev_config ext_disp_rx_cfg[] = {
  149. [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  150. };
  151. static struct dev_config usb_rx_cfg = {
  152. .sample_rate = SAMPLING_RATE_48KHZ,
  153. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  154. .channels = 2,
  155. };
  156. static struct dev_config usb_tx_cfg = {
  157. .sample_rate = SAMPLING_RATE_48KHZ,
  158. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  159. .channels = 1,
  160. };
  161. enum {
  162. PRIM_MI2S = 0,
  163. SEC_MI2S,
  164. TERT_MI2S,
  165. QUAT_MI2S,
  166. QUIN_MI2S,
  167. MI2S_MAX,
  168. };
  169. enum {
  170. PRIM_AUX_PCM = 0,
  171. SEC_AUX_PCM,
  172. TERT_AUX_PCM,
  173. QUAT_AUX_PCM,
  174. QUIN_AUX_PCM,
  175. AUX_PCM_MAX,
  176. };
  177. enum {
  178. PCM_I2S_SEL_PRIM = 0,
  179. PCM_I2S_SEL_SEC,
  180. PCM_I2S_SEL_TERT,
  181. PCM_I2S_SEL_QUAT,
  182. PCM_I2S_SEL_QUIN,
  183. PCM_I2S_SEL_MAX,
  184. };
  185. struct mi2s_conf {
  186. struct mutex lock;
  187. u32 ref_cnt;
  188. u32 msm_is_mi2s_master;
  189. u32 msm_is_ext_mclk;
  190. };
  191. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  192. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  193. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  194. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  195. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT
  196. };
  197. struct msm_wsa881x_dev_info {
  198. struct device_node *of_node;
  199. u32 index;
  200. };
  201. static struct snd_soc_aux_dev *msm_aux_dev;
  202. static struct snd_soc_codec_conf *msm_codec_conf;
  203. static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active);
  204. static struct wcd_mbhc_config mbhc_cfg = {
  205. .read_fw_bin = false,
  206. .calibration = NULL,
  207. .detect_extn_cable = true,
  208. .mono_stero_detection = false,
  209. .swap_gnd_mic = NULL,
  210. .hs_ext_micbias = true,
  211. .key_code[0] = KEY_MEDIA,
  212. .key_code[1] = KEY_VOICECOMMAND,
  213. .key_code[2] = KEY_VOLUMEUP,
  214. .key_code[3] = KEY_VOLUMEDOWN,
  215. .key_code[4] = 0,
  216. .key_code[5] = 0,
  217. .key_code[6] = 0,
  218. .key_code[7] = 0,
  219. .linein_th = 5000,
  220. .moisture_en = false,
  221. .mbhc_micbias = 0,
  222. .anc_micbias = 0,
  223. .enable_anc_mic_detect = false,
  224. };
  225. static struct dev_config proxy_rx_cfg = {
  226. .sample_rate = SAMPLING_RATE_48KHZ,
  227. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  228. .channels = 2,
  229. };
  230. /* Default configuration of MI2S channels */
  231. static struct dev_config mi2s_rx_cfg[] = {
  232. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  233. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  234. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  235. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  236. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  237. };
  238. static struct dev_config mi2s_tx_cfg[] = {
  239. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  240. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  241. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  242. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  243. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  244. };
  245. static struct dev_config aux_pcm_rx_cfg[] = {
  246. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  247. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  248. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  249. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  250. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  251. };
  252. static struct dev_config aux_pcm_tx_cfg[] = {
  253. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  254. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  255. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  256. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  257. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  258. };
  259. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  260. "Six", "Seven", "Eight"};
  261. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  262. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_16",
  263. "KHZ_32", "KHZ_44P1", "KHZ_48",
  264. "KHZ_96", "KHZ_192"};
  265. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  266. "Five", "Six", "Seven",
  267. "Eight"};
  268. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  269. "S32_LE"};
  270. static char const *mi2s_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  271. "S32_LE"};
  272. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  273. "Five", "Six", "Seven", "Eight"};
  274. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  275. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  276. "KHZ_44P1", "KHZ_48", "KHZ_96",
  277. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  278. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  279. "Five", "Six", "Seven",
  280. "Eight"};
  281. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  282. "KHZ_16", "KHZ_22P05",
  283. "KHZ_32", "KHZ_44P1", "KHZ_48",
  284. "KHZ_96", "KHZ_192", "KHZ_384"};
  285. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE"};
  286. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  287. "KHZ_192"};
  288. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  289. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  290. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  291. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  292. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  293. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  294. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  295. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  296. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  297. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  298. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  299. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  300. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  301. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  302. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  303. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  304. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  305. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  306. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  307. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  308. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  309. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  310. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_format, mi2s_format_text);
  311. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_format, mi2s_format_text);
  312. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_format, mi2s_format_text);
  313. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_format, mi2s_format_text);
  314. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_format, mi2s_format_text);
  315. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_format, mi2s_format_text);
  316. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_format, mi2s_format_text);
  317. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_format, mi2s_format_text);
  318. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_format, mi2s_format_text);
  319. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_format, mi2s_format_text);
  320. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  321. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  322. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  323. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  324. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  325. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  326. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  327. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  328. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  329. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  330. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  331. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  332. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  333. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  334. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  335. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  336. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  337. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  338. ext_disp_sample_rate_text);
  339. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  340. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  341. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  342. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  343. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  344. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  345. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  346. {
  347. AFE_API_VERSION_I2S_CONFIG,
  348. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  349. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  350. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  351. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  352. 0,
  353. },
  354. {
  355. AFE_API_VERSION_I2S_CONFIG,
  356. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  357. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  358. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  359. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  360. 0,
  361. },
  362. {
  363. AFE_API_VERSION_I2S_CONFIG,
  364. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  365. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  366. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  367. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  368. 0,
  369. },
  370. {
  371. AFE_API_VERSION_I2S_CONFIG,
  372. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  373. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  374. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  375. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  376. 0,
  377. }
  378. };
  379. static struct afe_clk_set mi2s_mclk[MI2S_MAX] = {
  380. {
  381. AFE_API_VERSION_I2S_CONFIG,
  382. Q6AFE_LPASS_CLK_ID_MCLK_3,
  383. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  384. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  385. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  386. 0,
  387. },
  388. {
  389. AFE_API_VERSION_I2S_CONFIG,
  390. Q6AFE_LPASS_CLK_ID_MCLK_4,
  391. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  392. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  393. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  394. 0,
  395. },
  396. {
  397. AFE_API_VERSION_I2S_CONFIG,
  398. Q6AFE_LPASS_CLK_ID_MCLK_1,
  399. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  400. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  401. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  402. 0,
  403. },
  404. {
  405. AFE_API_VERSION_I2S_CONFIG,
  406. Q6AFE_LPASS_CLK_ID_MCLK_2,
  407. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  408. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  409. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  410. 0,
  411. }
  412. };
  413. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  414. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  415. struct snd_ctl_elem_value *ucontrol)
  416. {
  417. pr_debug("%s: proxy_rx channels = %d\n",
  418. __func__, proxy_rx_cfg.channels);
  419. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  420. return 0;
  421. }
  422. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  423. struct snd_ctl_elem_value *ucontrol)
  424. {
  425. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  426. pr_debug("%s: proxy_rx channels = %d\n",
  427. __func__, proxy_rx_cfg.channels);
  428. return 1;
  429. }
  430. static int tdm_get_sample_rate(int value)
  431. {
  432. int sample_rate = 0;
  433. switch (value) {
  434. case 0:
  435. sample_rate = SAMPLING_RATE_8KHZ;
  436. break;
  437. case 1:
  438. sample_rate = SAMPLING_RATE_16KHZ;
  439. break;
  440. case 2:
  441. sample_rate = SAMPLING_RATE_32KHZ;
  442. break;
  443. case 3:
  444. sample_rate = SAMPLING_RATE_44P1KHZ;
  445. break;
  446. case 4:
  447. sample_rate = SAMPLING_RATE_48KHZ;
  448. break;
  449. case 5:
  450. sample_rate = SAMPLING_RATE_96KHZ;
  451. break;
  452. case 6:
  453. sample_rate = SAMPLING_RATE_192KHZ;
  454. break;
  455. case 7:
  456. sample_rate = SAMPLING_RATE_352P8KHZ;
  457. break;
  458. case 8:
  459. sample_rate = SAMPLING_RATE_384KHZ;
  460. break;
  461. default:
  462. sample_rate = SAMPLING_RATE_48KHZ;
  463. break;
  464. }
  465. return sample_rate;
  466. }
  467. static int tdm_get_sample_rate_val(int sample_rate)
  468. {
  469. int sample_rate_val = 0;
  470. switch (sample_rate) {
  471. case SAMPLING_RATE_8KHZ:
  472. sample_rate_val = 0;
  473. break;
  474. case SAMPLING_RATE_16KHZ:
  475. sample_rate_val = 1;
  476. break;
  477. case SAMPLING_RATE_32KHZ:
  478. sample_rate_val = 2;
  479. break;
  480. case SAMPLING_RATE_44P1KHZ:
  481. sample_rate_val = 3;
  482. break;
  483. case SAMPLING_RATE_48KHZ:
  484. sample_rate_val = 4;
  485. break;
  486. case SAMPLING_RATE_96KHZ:
  487. sample_rate_val = 5;
  488. break;
  489. case SAMPLING_RATE_192KHZ:
  490. sample_rate_val = 6;
  491. break;
  492. case SAMPLING_RATE_352P8KHZ:
  493. sample_rate_val = 7;
  494. break;
  495. case SAMPLING_RATE_384KHZ:
  496. sample_rate_val = 8;
  497. break;
  498. default:
  499. sample_rate_val = 4;
  500. break;
  501. }
  502. return sample_rate_val;
  503. }
  504. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  505. struct tdm_port *port)
  506. {
  507. if (port) {
  508. if (strnstr(kcontrol->id.name, "PRI",
  509. sizeof(kcontrol->id.name))) {
  510. port->mode = TDM_PRI;
  511. } else if (strnstr(kcontrol->id.name, "SEC",
  512. sizeof(kcontrol->id.name))) {
  513. port->mode = TDM_SEC;
  514. } else if (strnstr(kcontrol->id.name, "TERT",
  515. sizeof(kcontrol->id.name))) {
  516. port->mode = TDM_TERT;
  517. } else if (strnstr(kcontrol->id.name, "QUAT",
  518. sizeof(kcontrol->id.name))) {
  519. port->mode = TDM_QUAT;
  520. } else if (strnstr(kcontrol->id.name, "QUIN",
  521. sizeof(kcontrol->id.name))) {
  522. port->mode = TDM_QUIN;
  523. } else {
  524. pr_err("%s: unsupported mode in: %s",
  525. __func__, kcontrol->id.name);
  526. return -EINVAL;
  527. }
  528. if (strnstr(kcontrol->id.name, "RX_0",
  529. sizeof(kcontrol->id.name)) ||
  530. strnstr(kcontrol->id.name, "TX_0",
  531. sizeof(kcontrol->id.name))) {
  532. port->channel = TDM_0;
  533. } else if (strnstr(kcontrol->id.name, "RX_1",
  534. sizeof(kcontrol->id.name)) ||
  535. strnstr(kcontrol->id.name, "TX_1",
  536. sizeof(kcontrol->id.name))) {
  537. port->channel = TDM_1;
  538. } else if (strnstr(kcontrol->id.name, "RX_2",
  539. sizeof(kcontrol->id.name)) ||
  540. strnstr(kcontrol->id.name, "TX_2",
  541. sizeof(kcontrol->id.name))) {
  542. port->channel = TDM_2;
  543. } else if (strnstr(kcontrol->id.name, "RX_3",
  544. sizeof(kcontrol->id.name)) ||
  545. strnstr(kcontrol->id.name, "TX_3",
  546. sizeof(kcontrol->id.name))) {
  547. port->channel = TDM_3;
  548. } else if (strnstr(kcontrol->id.name, "RX_4",
  549. sizeof(kcontrol->id.name)) ||
  550. strnstr(kcontrol->id.name, "TX_4",
  551. sizeof(kcontrol->id.name))) {
  552. port->channel = TDM_4;
  553. } else if (strnstr(kcontrol->id.name, "RX_5",
  554. sizeof(kcontrol->id.name)) ||
  555. strnstr(kcontrol->id.name, "TX_5",
  556. sizeof(kcontrol->id.name))) {
  557. port->channel = TDM_5;
  558. } else if (strnstr(kcontrol->id.name, "RX_6",
  559. sizeof(kcontrol->id.name)) ||
  560. strnstr(kcontrol->id.name, "TX_6",
  561. sizeof(kcontrol->id.name))) {
  562. port->channel = TDM_6;
  563. } else if (strnstr(kcontrol->id.name, "RX_7",
  564. sizeof(kcontrol->id.name)) ||
  565. strnstr(kcontrol->id.name, "TX_7",
  566. sizeof(kcontrol->id.name))) {
  567. port->channel = TDM_7;
  568. } else {
  569. pr_err("%s: unsupported channel in: %s",
  570. __func__, kcontrol->id.name);
  571. return -EINVAL;
  572. }
  573. } else
  574. return -EINVAL;
  575. return 0;
  576. }
  577. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  578. struct snd_ctl_elem_value *ucontrol)
  579. {
  580. struct tdm_port port;
  581. int ret = tdm_get_port_idx(kcontrol, &port);
  582. if (ret) {
  583. pr_err("%s: unsupported control: %s",
  584. __func__, kcontrol->id.name);
  585. } else {
  586. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  587. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  588. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  589. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  590. ucontrol->value.enumerated.item[0]);
  591. }
  592. return ret;
  593. }
  594. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  595. struct snd_ctl_elem_value *ucontrol)
  596. {
  597. struct tdm_port port;
  598. int ret = tdm_get_port_idx(kcontrol, &port);
  599. if (ret) {
  600. pr_err("%s: unsupported control: %s",
  601. __func__, kcontrol->id.name);
  602. } else {
  603. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  604. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  605. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  606. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  607. ucontrol->value.enumerated.item[0]);
  608. }
  609. return ret;
  610. }
  611. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  612. struct snd_ctl_elem_value *ucontrol)
  613. {
  614. struct tdm_port port;
  615. int ret = tdm_get_port_idx(kcontrol, &port);
  616. if (ret) {
  617. pr_err("%s: unsupported control: %s",
  618. __func__, kcontrol->id.name);
  619. } else {
  620. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  621. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  622. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  623. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  624. ucontrol->value.enumerated.item[0]);
  625. }
  626. return ret;
  627. }
  628. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  629. struct snd_ctl_elem_value *ucontrol)
  630. {
  631. struct tdm_port port;
  632. int ret = tdm_get_port_idx(kcontrol, &port);
  633. if (ret) {
  634. pr_err("%s: unsupported control: %s",
  635. __func__, kcontrol->id.name);
  636. } else {
  637. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  638. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  639. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  640. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  641. ucontrol->value.enumerated.item[0]);
  642. }
  643. return ret;
  644. }
  645. static int tdm_get_format(int value)
  646. {
  647. int format = 0;
  648. switch (value) {
  649. case 0:
  650. format = SNDRV_PCM_FORMAT_S16_LE;
  651. break;
  652. case 1:
  653. format = SNDRV_PCM_FORMAT_S24_LE;
  654. break;
  655. case 2:
  656. format = SNDRV_PCM_FORMAT_S32_LE;
  657. break;
  658. default:
  659. format = SNDRV_PCM_FORMAT_S16_LE;
  660. break;
  661. }
  662. return format;
  663. }
  664. static int tdm_get_format_val(int format)
  665. {
  666. int value = 0;
  667. switch (format) {
  668. case SNDRV_PCM_FORMAT_S16_LE:
  669. value = 0;
  670. break;
  671. case SNDRV_PCM_FORMAT_S24_LE:
  672. value = 1;
  673. break;
  674. case SNDRV_PCM_FORMAT_S32_LE:
  675. value = 2;
  676. break;
  677. default:
  678. value = 0;
  679. break;
  680. }
  681. return value;
  682. }
  683. static int mi2s_get_format(int value)
  684. {
  685. int format = 0;
  686. switch (value) {
  687. case 0:
  688. format = SNDRV_PCM_FORMAT_S16_LE;
  689. break;
  690. case 1:
  691. format = SNDRV_PCM_FORMAT_S24_LE;
  692. break;
  693. case 2:
  694. format = SNDRV_PCM_FORMAT_S24_3LE;
  695. break;
  696. case 3:
  697. format = SNDRV_PCM_FORMAT_S32_LE;
  698. break;
  699. default:
  700. format = SNDRV_PCM_FORMAT_S16_LE;
  701. break;
  702. }
  703. return format;
  704. }
  705. static int mi2s_get_format_value(int format)
  706. {
  707. int value = 0;
  708. switch (format) {
  709. case SNDRV_PCM_FORMAT_S16_LE:
  710. value = 0;
  711. break;
  712. case SNDRV_PCM_FORMAT_S24_LE:
  713. value = 1;
  714. break;
  715. case SNDRV_PCM_FORMAT_S24_3LE:
  716. value = 2;
  717. break;
  718. case SNDRV_PCM_FORMAT_S32_LE:
  719. value = 3;
  720. break;
  721. default:
  722. value = 0;
  723. break;
  724. }
  725. return value;
  726. }
  727. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  728. struct snd_ctl_elem_value *ucontrol)
  729. {
  730. struct tdm_port port;
  731. int ret = tdm_get_port_idx(kcontrol, &port);
  732. if (ret) {
  733. pr_err("%s: unsupported control: %s",
  734. __func__, kcontrol->id.name);
  735. } else {
  736. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  737. tdm_rx_cfg[port.mode][port.channel].bit_format);
  738. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  739. tdm_rx_cfg[port.mode][port.channel].bit_format,
  740. ucontrol->value.enumerated.item[0]);
  741. }
  742. return ret;
  743. }
  744. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  745. struct snd_ctl_elem_value *ucontrol)
  746. {
  747. struct tdm_port port;
  748. int ret = tdm_get_port_idx(kcontrol, &port);
  749. if (ret) {
  750. pr_err("%s: unsupported control: %s",
  751. __func__, kcontrol->id.name);
  752. } else {
  753. tdm_rx_cfg[port.mode][port.channel].bit_format =
  754. tdm_get_format(ucontrol->value.enumerated.item[0]);
  755. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  756. tdm_rx_cfg[port.mode][port.channel].bit_format,
  757. ucontrol->value.enumerated.item[0]);
  758. }
  759. return ret;
  760. }
  761. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  762. struct snd_ctl_elem_value *ucontrol)
  763. {
  764. struct tdm_port port;
  765. int ret = tdm_get_port_idx(kcontrol, &port);
  766. if (ret) {
  767. pr_err("%s: unsupported control: %s",
  768. __func__, kcontrol->id.name);
  769. } else {
  770. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  771. tdm_tx_cfg[port.mode][port.channel].bit_format);
  772. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  773. tdm_tx_cfg[port.mode][port.channel].bit_format,
  774. ucontrol->value.enumerated.item[0]);
  775. }
  776. return ret;
  777. }
  778. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  779. struct snd_ctl_elem_value *ucontrol)
  780. {
  781. struct tdm_port port;
  782. int ret = tdm_get_port_idx(kcontrol, &port);
  783. if (ret) {
  784. pr_err("%s: unsupported control: %s",
  785. __func__, kcontrol->id.name);
  786. } else {
  787. tdm_tx_cfg[port.mode][port.channel].bit_format =
  788. tdm_get_format(ucontrol->value.enumerated.item[0]);
  789. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  790. tdm_tx_cfg[port.mode][port.channel].bit_format,
  791. ucontrol->value.enumerated.item[0]);
  792. }
  793. return ret;
  794. }
  795. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  796. struct snd_ctl_elem_value *ucontrol)
  797. {
  798. struct tdm_port port;
  799. int ret = tdm_get_port_idx(kcontrol, &port);
  800. if (ret) {
  801. pr_err("%s: unsupported control: %s",
  802. __func__, kcontrol->id.name);
  803. } else {
  804. ucontrol->value.enumerated.item[0] =
  805. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  806. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  807. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  808. ucontrol->value.enumerated.item[0]);
  809. }
  810. return ret;
  811. }
  812. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  813. struct snd_ctl_elem_value *ucontrol)
  814. {
  815. struct tdm_port port;
  816. int ret = tdm_get_port_idx(kcontrol, &port);
  817. if (ret) {
  818. pr_err("%s: unsupported control: %s",
  819. __func__, kcontrol->id.name);
  820. } else {
  821. tdm_rx_cfg[port.mode][port.channel].channels =
  822. ucontrol->value.enumerated.item[0] + 1;
  823. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  824. tdm_rx_cfg[port.mode][port.channel].channels,
  825. ucontrol->value.enumerated.item[0] + 1);
  826. }
  827. return ret;
  828. }
  829. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  830. struct snd_ctl_elem_value *ucontrol)
  831. {
  832. struct tdm_port port;
  833. int ret = tdm_get_port_idx(kcontrol, &port);
  834. if (ret) {
  835. pr_err("%s: unsupported control: %s",
  836. __func__, kcontrol->id.name);
  837. } else {
  838. ucontrol->value.enumerated.item[0] =
  839. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  840. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  841. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  842. ucontrol->value.enumerated.item[0]);
  843. }
  844. return ret;
  845. }
  846. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  847. struct snd_ctl_elem_value *ucontrol)
  848. {
  849. struct tdm_port port;
  850. int ret = tdm_get_port_idx(kcontrol, &port);
  851. if (ret) {
  852. pr_err("%s: unsupported control: %s",
  853. __func__, kcontrol->id.name);
  854. } else {
  855. tdm_tx_cfg[port.mode][port.channel].channels =
  856. ucontrol->value.enumerated.item[0] + 1;
  857. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  858. tdm_tx_cfg[port.mode][port.channel].channels,
  859. ucontrol->value.enumerated.item[0] + 1);
  860. }
  861. return ret;
  862. }
  863. static int aux_pcm_get_sample_rate(int value)
  864. {
  865. int sample_rate;
  866. switch (value) {
  867. case 1:
  868. sample_rate = SAMPLING_RATE_16KHZ;
  869. break;
  870. case 0:
  871. default:
  872. sample_rate = SAMPLING_RATE_8KHZ;
  873. break;
  874. }
  875. return sample_rate;
  876. }
  877. static int aux_pcm_get_sample_rate_val(int sample_rate)
  878. {
  879. int sample_rate_val;
  880. switch (sample_rate) {
  881. case SAMPLING_RATE_16KHZ:
  882. sample_rate_val = 1;
  883. break;
  884. case SAMPLING_RATE_8KHZ:
  885. default:
  886. sample_rate_val = 0;
  887. break;
  888. }
  889. return sample_rate_val;
  890. }
  891. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  892. {
  893. int idx;
  894. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  895. sizeof("PRIM_AUX_PCM")))
  896. idx = PRIM_AUX_PCM;
  897. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  898. sizeof("SEC_AUX_PCM")))
  899. idx = SEC_AUX_PCM;
  900. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  901. sizeof("TERT_AUX_PCM")))
  902. idx = TERT_AUX_PCM;
  903. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  904. sizeof("QUAT_AUX_PCM")))
  905. idx = QUAT_AUX_PCM;
  906. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  907. sizeof("QUIN_AUX_PCM")))
  908. idx = QUIN_AUX_PCM;
  909. else {
  910. pr_err("%s: unsupported port: %s",
  911. __func__, kcontrol->id.name);
  912. idx = -EINVAL;
  913. }
  914. return idx;
  915. }
  916. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  917. struct snd_ctl_elem_value *ucontrol)
  918. {
  919. int idx = aux_pcm_get_port_idx(kcontrol);
  920. if (idx < 0)
  921. return idx;
  922. aux_pcm_rx_cfg[idx].sample_rate =
  923. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  924. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  925. idx, aux_pcm_rx_cfg[idx].sample_rate,
  926. ucontrol->value.enumerated.item[0]);
  927. return 0;
  928. }
  929. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  930. struct snd_ctl_elem_value *ucontrol)
  931. {
  932. int idx = aux_pcm_get_port_idx(kcontrol);
  933. if (idx < 0)
  934. return idx;
  935. ucontrol->value.enumerated.item[0] =
  936. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  937. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  938. idx, aux_pcm_rx_cfg[idx].sample_rate,
  939. ucontrol->value.enumerated.item[0]);
  940. return 0;
  941. }
  942. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  943. struct snd_ctl_elem_value *ucontrol)
  944. {
  945. int idx = aux_pcm_get_port_idx(kcontrol);
  946. if (idx < 0)
  947. return idx;
  948. aux_pcm_tx_cfg[idx].sample_rate =
  949. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  950. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  951. idx, aux_pcm_tx_cfg[idx].sample_rate,
  952. ucontrol->value.enumerated.item[0]);
  953. return 0;
  954. }
  955. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  956. struct snd_ctl_elem_value *ucontrol)
  957. {
  958. int idx = aux_pcm_get_port_idx(kcontrol);
  959. if (idx < 0)
  960. return idx;
  961. ucontrol->value.enumerated.item[0] =
  962. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  963. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  964. idx, aux_pcm_tx_cfg[idx].sample_rate,
  965. ucontrol->value.enumerated.item[0]);
  966. return 0;
  967. }
  968. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  969. {
  970. int idx;
  971. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  972. sizeof("PRIM_MI2S_RX")))
  973. idx = PRIM_MI2S;
  974. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  975. sizeof("SEC_MI2S_RX")))
  976. idx = SEC_MI2S;
  977. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  978. sizeof("TERT_MI2S_RX")))
  979. idx = TERT_MI2S;
  980. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  981. sizeof("QUAT_MI2S_RX")))
  982. idx = QUAT_MI2S;
  983. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  984. sizeof("QUIN_MI2S_RX")))
  985. idx = QUIN_MI2S;
  986. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  987. sizeof("PRIM_MI2S_TX")))
  988. idx = PRIM_MI2S;
  989. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  990. sizeof("SEC_MI2S_TX")))
  991. idx = SEC_MI2S;
  992. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  993. sizeof("TERT_MI2S_TX")))
  994. idx = TERT_MI2S;
  995. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  996. sizeof("QUAT_MI2S_TX")))
  997. idx = QUAT_MI2S;
  998. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  999. sizeof("QUIN_MI2S_TX")))
  1000. idx = QUIN_MI2S;
  1001. else {
  1002. pr_err("%s: unsupported channel: %s",
  1003. __func__, kcontrol->id.name);
  1004. idx = -EINVAL;
  1005. }
  1006. return idx;
  1007. }
  1008. static int mi2s_get_sample_rate_val(int sample_rate)
  1009. {
  1010. int sample_rate_val;
  1011. switch (sample_rate) {
  1012. case SAMPLING_RATE_8KHZ:
  1013. sample_rate_val = 0;
  1014. break;
  1015. case SAMPLING_RATE_16KHZ:
  1016. sample_rate_val = 1;
  1017. break;
  1018. case SAMPLING_RATE_32KHZ:
  1019. sample_rate_val = 2;
  1020. break;
  1021. case SAMPLING_RATE_44P1KHZ:
  1022. sample_rate_val = 3;
  1023. break;
  1024. case SAMPLING_RATE_48KHZ:
  1025. sample_rate_val = 4;
  1026. break;
  1027. case SAMPLING_RATE_96KHZ:
  1028. sample_rate_val = 5;
  1029. break;
  1030. case SAMPLING_RATE_192KHZ:
  1031. sample_rate_val = 6;
  1032. break;
  1033. default:
  1034. sample_rate_val = 4;
  1035. break;
  1036. }
  1037. return sample_rate_val;
  1038. }
  1039. static int mi2s_get_sample_rate(int value)
  1040. {
  1041. int sample_rate;
  1042. switch (value) {
  1043. case 0:
  1044. sample_rate = SAMPLING_RATE_8KHZ;
  1045. break;
  1046. case 1:
  1047. sample_rate = SAMPLING_RATE_16KHZ;
  1048. break;
  1049. case 2:
  1050. sample_rate = SAMPLING_RATE_32KHZ;
  1051. break;
  1052. case 3:
  1053. sample_rate = SAMPLING_RATE_44P1KHZ;
  1054. break;
  1055. case 4:
  1056. sample_rate = SAMPLING_RATE_48KHZ;
  1057. break;
  1058. case 5:
  1059. sample_rate = SAMPLING_RATE_96KHZ;
  1060. break;
  1061. case 6:
  1062. sample_rate = SAMPLING_RATE_192KHZ;
  1063. break;
  1064. default:
  1065. sample_rate = SAMPLING_RATE_48KHZ;
  1066. break;
  1067. }
  1068. return sample_rate;
  1069. }
  1070. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1071. struct snd_ctl_elem_value *ucontrol)
  1072. {
  1073. int idx = mi2s_get_port_idx(kcontrol);
  1074. if (idx < 0)
  1075. return idx;
  1076. mi2s_rx_cfg[idx].sample_rate =
  1077. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1078. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1079. idx, mi2s_rx_cfg[idx].sample_rate,
  1080. ucontrol->value.enumerated.item[0]);
  1081. return 0;
  1082. }
  1083. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1084. struct snd_ctl_elem_value *ucontrol)
  1085. {
  1086. int idx = mi2s_get_port_idx(kcontrol);
  1087. if (idx < 0)
  1088. return idx;
  1089. ucontrol->value.enumerated.item[0] =
  1090. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1091. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1092. idx, mi2s_rx_cfg[idx].sample_rate,
  1093. ucontrol->value.enumerated.item[0]);
  1094. return 0;
  1095. }
  1096. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1097. struct snd_ctl_elem_value *ucontrol)
  1098. {
  1099. int idx = mi2s_get_port_idx(kcontrol);
  1100. if (idx < 0)
  1101. return idx;
  1102. mi2s_tx_cfg[idx].sample_rate =
  1103. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1104. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1105. idx, mi2s_tx_cfg[idx].sample_rate,
  1106. ucontrol->value.enumerated.item[0]);
  1107. return 0;
  1108. }
  1109. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1110. struct snd_ctl_elem_value *ucontrol)
  1111. {
  1112. int idx = mi2s_get_port_idx(kcontrol);
  1113. if (idx < 0)
  1114. return idx;
  1115. ucontrol->value.enumerated.item[0] =
  1116. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1117. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1118. idx, mi2s_tx_cfg[idx].sample_rate,
  1119. ucontrol->value.enumerated.item[0]);
  1120. return 0;
  1121. }
  1122. static int mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1123. struct snd_ctl_elem_value *ucontrol)
  1124. {
  1125. int idx = mi2s_get_port_idx(kcontrol);
  1126. if (idx < 0)
  1127. return idx;
  1128. mi2s_tx_cfg[idx].bit_format =
  1129. mi2s_get_format(ucontrol->value.enumerated.item[0]);
  1130. pr_debug("%s: idx[%d] _tx_format = %d, item = %d\n", __func__,
  1131. idx, mi2s_tx_cfg[idx].bit_format,
  1132. ucontrol->value.enumerated.item[0]);
  1133. return 0;
  1134. }
  1135. static int mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1136. struct snd_ctl_elem_value *ucontrol)
  1137. {
  1138. int idx = mi2s_get_port_idx(kcontrol);
  1139. if (idx < 0)
  1140. return idx;
  1141. ucontrol->value.enumerated.item[0] =
  1142. mi2s_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1143. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1144. idx, mi2s_tx_cfg[idx].bit_format,
  1145. ucontrol->value.enumerated.item[0]);
  1146. return 0;
  1147. }
  1148. static int mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1149. struct snd_ctl_elem_value *ucontrol)
  1150. {
  1151. int idx = mi2s_get_port_idx(kcontrol);
  1152. if (idx < 0)
  1153. return idx;
  1154. mi2s_rx_cfg[idx].bit_format =
  1155. mi2s_get_format(ucontrol->value.enumerated.item[0]);
  1156. pr_debug("%s: idx[%d] _rx_format = %d, item = %d\n", __func__,
  1157. idx, mi2s_rx_cfg[idx].bit_format,
  1158. ucontrol->value.enumerated.item[0]);
  1159. return 0;
  1160. }
  1161. static int mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1162. struct snd_ctl_elem_value *ucontrol)
  1163. {
  1164. int idx = mi2s_get_port_idx(kcontrol);
  1165. if (idx < 0)
  1166. return idx;
  1167. ucontrol->value.enumerated.item[0] =
  1168. mi2s_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1169. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1170. idx, mi2s_rx_cfg[idx].bit_format,
  1171. ucontrol->value.enumerated.item[0]);
  1172. return 0;
  1173. }
  1174. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1175. struct snd_ctl_elem_value *ucontrol)
  1176. {
  1177. int idx = mi2s_get_port_idx(kcontrol);
  1178. if (idx < 0)
  1179. return idx;
  1180. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1181. idx, mi2s_rx_cfg[idx].channels);
  1182. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1183. return 0;
  1184. }
  1185. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1186. struct snd_ctl_elem_value *ucontrol)
  1187. {
  1188. int idx = mi2s_get_port_idx(kcontrol);
  1189. if (idx < 0)
  1190. return idx;
  1191. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1192. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1193. idx, mi2s_rx_cfg[idx].channels);
  1194. return 1;
  1195. }
  1196. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  1197. struct snd_ctl_elem_value *ucontrol)
  1198. {
  1199. int idx = mi2s_get_port_idx(kcontrol);
  1200. if (idx < 0)
  1201. return idx;
  1202. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1203. idx, mi2s_tx_cfg[idx].channels);
  1204. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  1205. return 0;
  1206. }
  1207. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  1208. struct snd_ctl_elem_value *ucontrol)
  1209. {
  1210. int idx = mi2s_get_port_idx(kcontrol);
  1211. if (idx < 0)
  1212. return idx;
  1213. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1214. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1215. idx, mi2s_tx_cfg[idx].channels);
  1216. return 1;
  1217. }
  1218. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1219. struct snd_ctl_elem_value *ucontrol)
  1220. {
  1221. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1222. usb_rx_cfg.channels);
  1223. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1224. return 0;
  1225. }
  1226. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1227. struct snd_ctl_elem_value *ucontrol)
  1228. {
  1229. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1230. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1231. return 1;
  1232. }
  1233. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1234. struct snd_ctl_elem_value *ucontrol)
  1235. {
  1236. int sample_rate_val;
  1237. switch (usb_rx_cfg.sample_rate) {
  1238. case SAMPLING_RATE_384KHZ:
  1239. sample_rate_val = 9;
  1240. break;
  1241. case SAMPLING_RATE_192KHZ:
  1242. sample_rate_val = 8;
  1243. break;
  1244. case SAMPLING_RATE_96KHZ:
  1245. sample_rate_val = 7;
  1246. break;
  1247. case SAMPLING_RATE_48KHZ:
  1248. sample_rate_val = 6;
  1249. break;
  1250. case SAMPLING_RATE_44P1KHZ:
  1251. sample_rate_val = 5;
  1252. break;
  1253. case SAMPLING_RATE_32KHZ:
  1254. sample_rate_val = 4;
  1255. break;
  1256. case SAMPLING_RATE_22P05KHZ:
  1257. sample_rate_val = 3;
  1258. break;
  1259. case SAMPLING_RATE_16KHZ:
  1260. sample_rate_val = 2;
  1261. break;
  1262. case SAMPLING_RATE_11P025KHZ:
  1263. sample_rate_val = 1;
  1264. break;
  1265. case SAMPLING_RATE_8KHZ:
  1266. default:
  1267. sample_rate_val = 0;
  1268. break;
  1269. }
  1270. ucontrol->value.integer.value[0] = sample_rate_val;
  1271. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1272. usb_rx_cfg.sample_rate);
  1273. return 0;
  1274. }
  1275. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1276. struct snd_ctl_elem_value *ucontrol)
  1277. {
  1278. switch (ucontrol->value.integer.value[0]) {
  1279. case 9:
  1280. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1281. break;
  1282. case 8:
  1283. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1284. break;
  1285. case 7:
  1286. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1287. break;
  1288. case 6:
  1289. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1290. break;
  1291. case 5:
  1292. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1293. break;
  1294. case 4:
  1295. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1296. break;
  1297. case 3:
  1298. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1299. break;
  1300. case 2:
  1301. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1302. break;
  1303. case 1:
  1304. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1305. break;
  1306. case 0:
  1307. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1308. break;
  1309. default:
  1310. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1311. break;
  1312. }
  1313. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1314. __func__, ucontrol->value.integer.value[0],
  1315. usb_rx_cfg.sample_rate);
  1316. return 0;
  1317. }
  1318. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1319. struct snd_ctl_elem_value *ucontrol)
  1320. {
  1321. switch (usb_rx_cfg.bit_format) {
  1322. case SNDRV_PCM_FORMAT_S32_LE:
  1323. ucontrol->value.integer.value[0] = 3;
  1324. break;
  1325. case SNDRV_PCM_FORMAT_S24_3LE:
  1326. ucontrol->value.integer.value[0] = 2;
  1327. break;
  1328. case SNDRV_PCM_FORMAT_S24_LE:
  1329. ucontrol->value.integer.value[0] = 1;
  1330. break;
  1331. case SNDRV_PCM_FORMAT_S16_LE:
  1332. default:
  1333. ucontrol->value.integer.value[0] = 0;
  1334. break;
  1335. }
  1336. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1337. __func__, usb_rx_cfg.bit_format,
  1338. ucontrol->value.integer.value[0]);
  1339. return 0;
  1340. }
  1341. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1342. struct snd_ctl_elem_value *ucontrol)
  1343. {
  1344. int rc = 0;
  1345. switch (ucontrol->value.integer.value[0]) {
  1346. case 3:
  1347. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1348. break;
  1349. case 2:
  1350. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1351. break;
  1352. case 1:
  1353. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1354. break;
  1355. case 0:
  1356. default:
  1357. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1358. break;
  1359. }
  1360. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1361. __func__, usb_rx_cfg.bit_format,
  1362. ucontrol->value.integer.value[0]);
  1363. return rc;
  1364. }
  1365. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1366. struct snd_ctl_elem_value *ucontrol)
  1367. {
  1368. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1369. usb_tx_cfg.channels);
  1370. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1371. return 0;
  1372. }
  1373. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1374. struct snd_ctl_elem_value *ucontrol)
  1375. {
  1376. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1377. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1378. return 1;
  1379. }
  1380. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1381. struct snd_ctl_elem_value *ucontrol)
  1382. {
  1383. int sample_rate_val;
  1384. switch (usb_tx_cfg.sample_rate) {
  1385. case SAMPLING_RATE_384KHZ:
  1386. sample_rate_val = 9;
  1387. break;
  1388. case SAMPLING_RATE_192KHZ:
  1389. sample_rate_val = 8;
  1390. break;
  1391. case SAMPLING_RATE_96KHZ:
  1392. sample_rate_val = 7;
  1393. break;
  1394. case SAMPLING_RATE_48KHZ:
  1395. sample_rate_val = 6;
  1396. break;
  1397. case SAMPLING_RATE_44P1KHZ:
  1398. sample_rate_val = 5;
  1399. break;
  1400. case SAMPLING_RATE_32KHZ:
  1401. sample_rate_val = 4;
  1402. break;
  1403. case SAMPLING_RATE_22P05KHZ:
  1404. sample_rate_val = 3;
  1405. break;
  1406. case SAMPLING_RATE_16KHZ:
  1407. sample_rate_val = 2;
  1408. break;
  1409. case SAMPLING_RATE_11P025KHZ:
  1410. sample_rate_val = 1;
  1411. break;
  1412. case SAMPLING_RATE_8KHZ:
  1413. sample_rate_val = 0;
  1414. break;
  1415. default:
  1416. sample_rate_val = 6;
  1417. break;
  1418. }
  1419. ucontrol->value.integer.value[0] = sample_rate_val;
  1420. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1421. usb_tx_cfg.sample_rate);
  1422. return 0;
  1423. }
  1424. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1425. struct snd_ctl_elem_value *ucontrol)
  1426. {
  1427. switch (ucontrol->value.integer.value[0]) {
  1428. case 9:
  1429. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1430. break;
  1431. case 8:
  1432. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1433. break;
  1434. case 7:
  1435. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1436. break;
  1437. case 6:
  1438. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1439. break;
  1440. case 5:
  1441. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1442. break;
  1443. case 4:
  1444. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1445. break;
  1446. case 3:
  1447. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1448. break;
  1449. case 2:
  1450. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1451. break;
  1452. case 1:
  1453. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1454. break;
  1455. case 0:
  1456. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1457. break;
  1458. default:
  1459. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1460. break;
  1461. }
  1462. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1463. __func__, ucontrol->value.integer.value[0],
  1464. usb_tx_cfg.sample_rate);
  1465. return 0;
  1466. }
  1467. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1468. struct snd_ctl_elem_value *ucontrol)
  1469. {
  1470. switch (usb_tx_cfg.bit_format) {
  1471. case SNDRV_PCM_FORMAT_S32_LE:
  1472. ucontrol->value.integer.value[0] = 3;
  1473. break;
  1474. case SNDRV_PCM_FORMAT_S24_3LE:
  1475. ucontrol->value.integer.value[0] = 2;
  1476. break;
  1477. case SNDRV_PCM_FORMAT_S24_LE:
  1478. ucontrol->value.integer.value[0] = 1;
  1479. break;
  1480. case SNDRV_PCM_FORMAT_S16_LE:
  1481. default:
  1482. ucontrol->value.integer.value[0] = 0;
  1483. break;
  1484. }
  1485. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1486. __func__, usb_tx_cfg.bit_format,
  1487. ucontrol->value.integer.value[0]);
  1488. return 0;
  1489. }
  1490. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1491. struct snd_ctl_elem_value *ucontrol)
  1492. {
  1493. int rc = 0;
  1494. switch (ucontrol->value.integer.value[0]) {
  1495. case 3:
  1496. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1497. break;
  1498. case 2:
  1499. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1500. break;
  1501. case 1:
  1502. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1503. break;
  1504. case 0:
  1505. default:
  1506. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1507. break;
  1508. }
  1509. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1510. __func__, usb_tx_cfg.bit_format,
  1511. ucontrol->value.integer.value[0]);
  1512. return rc;
  1513. }
  1514. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1515. {
  1516. int idx;
  1517. if (strnstr(kcontrol->id.name, "Display Port RX",
  1518. sizeof("Display Port RX")))
  1519. idx = DP_RX_IDX;
  1520. else {
  1521. pr_err("%s: unsupported BE: %s",
  1522. __func__, kcontrol->id.name);
  1523. idx = -EINVAL;
  1524. }
  1525. return idx;
  1526. }
  1527. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1528. struct snd_ctl_elem_value *ucontrol)
  1529. {
  1530. int idx = ext_disp_get_port_idx(kcontrol);
  1531. if (idx < 0)
  1532. return idx;
  1533. switch (ext_disp_rx_cfg[idx].bit_format) {
  1534. case SNDRV_PCM_FORMAT_S24_LE:
  1535. ucontrol->value.integer.value[0] = 1;
  1536. break;
  1537. case SNDRV_PCM_FORMAT_S16_LE:
  1538. default:
  1539. ucontrol->value.integer.value[0] = 0;
  1540. break;
  1541. }
  1542. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1543. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1544. ucontrol->value.integer.value[0]);
  1545. return 0;
  1546. }
  1547. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1548. struct snd_ctl_elem_value *ucontrol)
  1549. {
  1550. int idx = ext_disp_get_port_idx(kcontrol);
  1551. if (idx < 0)
  1552. return idx;
  1553. switch (ucontrol->value.integer.value[0]) {
  1554. case 1:
  1555. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1556. break;
  1557. case 0:
  1558. default:
  1559. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1560. break;
  1561. }
  1562. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1563. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1564. ucontrol->value.integer.value[0]);
  1565. return 0;
  1566. }
  1567. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1568. struct snd_ctl_elem_value *ucontrol)
  1569. {
  1570. int idx = ext_disp_get_port_idx(kcontrol);
  1571. if (idx < 0)
  1572. return idx;
  1573. ucontrol->value.integer.value[0] =
  1574. ext_disp_rx_cfg[idx].channels - 2;
  1575. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1576. idx, ext_disp_rx_cfg[idx].channels);
  1577. return 0;
  1578. }
  1579. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1580. struct snd_ctl_elem_value *ucontrol)
  1581. {
  1582. int idx = ext_disp_get_port_idx(kcontrol);
  1583. if (idx < 0)
  1584. return idx;
  1585. ext_disp_rx_cfg[idx].channels =
  1586. ucontrol->value.integer.value[0] + 2;
  1587. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1588. idx, ext_disp_rx_cfg[idx].channels);
  1589. return 1;
  1590. }
  1591. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1592. struct snd_ctl_elem_value *ucontrol)
  1593. {
  1594. int sample_rate_val;
  1595. int idx = ext_disp_get_port_idx(kcontrol);
  1596. if (idx < 0)
  1597. return idx;
  1598. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1599. case SAMPLING_RATE_192KHZ:
  1600. sample_rate_val = 2;
  1601. break;
  1602. case SAMPLING_RATE_96KHZ:
  1603. sample_rate_val = 1;
  1604. break;
  1605. case SAMPLING_RATE_48KHZ:
  1606. default:
  1607. sample_rate_val = 0;
  1608. break;
  1609. }
  1610. ucontrol->value.integer.value[0] = sample_rate_val;
  1611. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1612. idx, ext_disp_rx_cfg[idx].sample_rate);
  1613. return 0;
  1614. }
  1615. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1616. struct snd_ctl_elem_value *ucontrol)
  1617. {
  1618. int idx = ext_disp_get_port_idx(kcontrol);
  1619. if (idx < 0)
  1620. return idx;
  1621. switch (ucontrol->value.integer.value[0]) {
  1622. case 2:
  1623. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1624. break;
  1625. case 1:
  1626. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1627. break;
  1628. case 0:
  1629. default:
  1630. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1631. break;
  1632. }
  1633. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1634. __func__, ucontrol->value.integer.value[0], idx,
  1635. ext_disp_rx_cfg[idx].sample_rate);
  1636. return 0;
  1637. }
  1638. const struct snd_kcontrol_new msm_common_snd_controls[] = {
  1639. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  1640. proxy_rx_ch_get, proxy_rx_ch_put),
  1641. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  1642. aux_pcm_rx_sample_rate_get,
  1643. aux_pcm_rx_sample_rate_put),
  1644. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  1645. aux_pcm_rx_sample_rate_get,
  1646. aux_pcm_rx_sample_rate_put),
  1647. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  1648. aux_pcm_rx_sample_rate_get,
  1649. aux_pcm_rx_sample_rate_put),
  1650. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  1651. aux_pcm_rx_sample_rate_get,
  1652. aux_pcm_rx_sample_rate_put),
  1653. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  1654. aux_pcm_rx_sample_rate_get,
  1655. aux_pcm_rx_sample_rate_put),
  1656. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  1657. aux_pcm_tx_sample_rate_get,
  1658. aux_pcm_tx_sample_rate_put),
  1659. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  1660. aux_pcm_tx_sample_rate_get,
  1661. aux_pcm_tx_sample_rate_put),
  1662. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  1663. aux_pcm_tx_sample_rate_get,
  1664. aux_pcm_tx_sample_rate_put),
  1665. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  1666. aux_pcm_tx_sample_rate_get,
  1667. aux_pcm_tx_sample_rate_put),
  1668. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  1669. aux_pcm_tx_sample_rate_get,
  1670. aux_pcm_tx_sample_rate_put),
  1671. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  1672. mi2s_rx_sample_rate_get,
  1673. mi2s_rx_sample_rate_put),
  1674. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  1675. mi2s_rx_sample_rate_get,
  1676. mi2s_rx_sample_rate_put),
  1677. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  1678. mi2s_rx_sample_rate_get,
  1679. mi2s_rx_sample_rate_put),
  1680. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  1681. mi2s_rx_sample_rate_get,
  1682. mi2s_rx_sample_rate_put),
  1683. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  1684. mi2s_rx_sample_rate_get,
  1685. mi2s_rx_sample_rate_put),
  1686. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  1687. mi2s_tx_sample_rate_get,
  1688. mi2s_tx_sample_rate_put),
  1689. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  1690. mi2s_tx_sample_rate_get,
  1691. mi2s_tx_sample_rate_put),
  1692. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  1693. mi2s_tx_sample_rate_get,
  1694. mi2s_tx_sample_rate_put),
  1695. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  1696. mi2s_tx_sample_rate_get,
  1697. mi2s_tx_sample_rate_put),
  1698. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  1699. mi2s_tx_sample_rate_get,
  1700. mi2s_tx_sample_rate_put),
  1701. SOC_ENUM_EXT("PRIM_MI2S_RX Format", prim_mi2s_rx_format,
  1702. mi2s_rx_format_get,
  1703. mi2s_rx_format_put),
  1704. SOC_ENUM_EXT("SEC_MI2S_RX Format", sec_mi2s_rx_format,
  1705. mi2s_rx_format_get,
  1706. mi2s_rx_format_put),
  1707. SOC_ENUM_EXT("TERT_MI2S_RX Format", tert_mi2s_rx_format,
  1708. mi2s_rx_format_get,
  1709. mi2s_rx_format_put),
  1710. SOC_ENUM_EXT("QUAT_MI2S_RX Format", quat_mi2s_rx_format,
  1711. mi2s_rx_format_get,
  1712. mi2s_rx_format_put),
  1713. SOC_ENUM_EXT("QUIN_MI2S_RX Format", quin_mi2s_rx_format,
  1714. mi2s_rx_format_get,
  1715. mi2s_rx_format_put),
  1716. SOC_ENUM_EXT("PRIM_MI2S_TX Format", prim_mi2s_tx_format,
  1717. mi2s_tx_format_get,
  1718. mi2s_tx_format_put),
  1719. SOC_ENUM_EXT("SEC_MI2S_TX Format", sec_mi2s_tx_format,
  1720. mi2s_tx_format_get,
  1721. mi2s_tx_format_put),
  1722. SOC_ENUM_EXT("TERT_MI2S_TX Format", tert_mi2s_tx_format,
  1723. mi2s_tx_format_get,
  1724. mi2s_tx_format_put),
  1725. SOC_ENUM_EXT("QUAT_MI2S_TX Format", quat_mi2s_tx_format,
  1726. mi2s_tx_format_get,
  1727. mi2s_tx_format_put),
  1728. SOC_ENUM_EXT("QUIN_MI2S_TX Format", quin_mi2s_tx_format,
  1729. mi2s_tx_format_get,
  1730. mi2s_tx_format_put),
  1731. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  1732. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1733. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  1734. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1735. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  1736. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1737. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  1738. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1739. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  1740. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1741. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  1742. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1743. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  1744. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1745. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  1746. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1747. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  1748. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1749. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  1750. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1751. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  1752. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  1753. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  1754. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  1755. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  1756. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  1757. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  1758. usb_audio_rx_format_get, usb_audio_rx_format_put),
  1759. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  1760. usb_audio_tx_format_get, usb_audio_tx_format_put),
  1761. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  1762. ext_disp_rx_format_get, ext_disp_rx_format_put),
  1763. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  1764. usb_audio_rx_sample_rate_get,
  1765. usb_audio_rx_sample_rate_put),
  1766. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  1767. usb_audio_tx_sample_rate_get,
  1768. usb_audio_tx_sample_rate_put),
  1769. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  1770. ext_disp_rx_sample_rate_get,
  1771. ext_disp_rx_sample_rate_put),
  1772. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1773. tdm_rx_sample_rate_get,
  1774. tdm_rx_sample_rate_put),
  1775. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1776. tdm_tx_sample_rate_get,
  1777. tdm_tx_sample_rate_put),
  1778. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  1779. tdm_rx_format_get,
  1780. tdm_rx_format_put),
  1781. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  1782. tdm_tx_format_get,
  1783. tdm_tx_format_put),
  1784. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  1785. tdm_rx_ch_get,
  1786. tdm_rx_ch_put),
  1787. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  1788. tdm_tx_ch_get,
  1789. tdm_tx_ch_put),
  1790. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1791. tdm_rx_sample_rate_get,
  1792. tdm_rx_sample_rate_put),
  1793. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1794. tdm_tx_sample_rate_get,
  1795. tdm_tx_sample_rate_put),
  1796. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  1797. tdm_rx_format_get,
  1798. tdm_rx_format_put),
  1799. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  1800. tdm_tx_format_get,
  1801. tdm_tx_format_put),
  1802. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  1803. tdm_rx_ch_get,
  1804. tdm_rx_ch_put),
  1805. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  1806. tdm_tx_ch_get,
  1807. tdm_tx_ch_put),
  1808. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1809. tdm_rx_sample_rate_get,
  1810. tdm_rx_sample_rate_put),
  1811. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1812. tdm_tx_sample_rate_get,
  1813. tdm_tx_sample_rate_put),
  1814. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  1815. tdm_rx_format_get,
  1816. tdm_rx_format_put),
  1817. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  1818. tdm_tx_format_get,
  1819. tdm_tx_format_put),
  1820. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  1821. tdm_rx_ch_get,
  1822. tdm_rx_ch_put),
  1823. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  1824. tdm_tx_ch_get,
  1825. tdm_tx_ch_put),
  1826. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1827. tdm_rx_sample_rate_get,
  1828. tdm_rx_sample_rate_put),
  1829. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1830. tdm_tx_sample_rate_get,
  1831. tdm_tx_sample_rate_put),
  1832. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  1833. tdm_rx_format_get,
  1834. tdm_rx_format_put),
  1835. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  1836. tdm_tx_format_get,
  1837. tdm_tx_format_put),
  1838. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  1839. tdm_rx_ch_get,
  1840. tdm_rx_ch_put),
  1841. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  1842. tdm_tx_ch_get,
  1843. tdm_tx_ch_put),
  1844. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1845. tdm_rx_sample_rate_get,
  1846. tdm_rx_sample_rate_put),
  1847. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1848. tdm_tx_sample_rate_get,
  1849. tdm_tx_sample_rate_put),
  1850. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  1851. tdm_rx_format_get,
  1852. tdm_rx_format_put),
  1853. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  1854. tdm_tx_format_get,
  1855. tdm_tx_format_put),
  1856. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  1857. tdm_rx_ch_get,
  1858. tdm_rx_ch_put),
  1859. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  1860. tdm_tx_ch_get,
  1861. tdm_tx_ch_put),
  1862. };
  1863. /**
  1864. * msm_common_snd_controls_size - to return controls size
  1865. *
  1866. * Return: returns size of common controls array
  1867. */
  1868. int msm_common_snd_controls_size(void)
  1869. {
  1870. return ARRAY_SIZE(msm_common_snd_controls);
  1871. }
  1872. EXPORT_SYMBOL(msm_common_snd_controls_size);
  1873. void msm_set_codec_reg_done(bool done)
  1874. {
  1875. codec_reg_done = done;
  1876. }
  1877. EXPORT_SYMBOL(msm_set_codec_reg_done);
  1878. static inline int param_is_mask(int p)
  1879. {
  1880. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  1881. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  1882. }
  1883. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  1884. int n)
  1885. {
  1886. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  1887. }
  1888. static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned int bit)
  1889. {
  1890. if (bit >= SNDRV_MASK_MAX)
  1891. return;
  1892. if (param_is_mask(n)) {
  1893. struct snd_mask *m = param_to_mask(p, n);
  1894. m->bits[0] = 0;
  1895. m->bits[1] = 0;
  1896. m->bits[bit >> 5] |= (1 << (bit & 31));
  1897. }
  1898. }
  1899. static int msm_ext_disp_get_idx_from_beid(int32_t id)
  1900. {
  1901. int idx;
  1902. switch (id) {
  1903. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  1904. idx = DP_RX_IDX;
  1905. break;
  1906. default:
  1907. pr_err("%s: Incorrect ext_disp id %d\n", __func__, id);
  1908. idx = -EINVAL;
  1909. break;
  1910. }
  1911. return idx;
  1912. }
  1913. /**
  1914. * msm_common_be_hw_params_fixup - updates settings of ALSA BE hw params.
  1915. *
  1916. * @rtd: runtime dailink instance
  1917. * @params: HW params of associated backend dailink.
  1918. *
  1919. * Returns 0.
  1920. */
  1921. int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  1922. struct snd_pcm_hw_params *params)
  1923. {
  1924. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  1925. struct snd_interval *rate = hw_param_interval(params,
  1926. SNDRV_PCM_HW_PARAM_RATE);
  1927. struct snd_interval *channels = hw_param_interval(params,
  1928. SNDRV_PCM_HW_PARAM_CHANNELS);
  1929. int rc = 0;
  1930. int idx;
  1931. pr_debug("%s: format = %d, rate = %d\n",
  1932. __func__, params_format(params), params_rate(params));
  1933. switch (dai_link->id) {
  1934. case MSM_BACKEND_DAI_USB_RX:
  1935. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1936. usb_rx_cfg.bit_format);
  1937. rate->min = rate->max = usb_rx_cfg.sample_rate;
  1938. channels->min = channels->max = usb_rx_cfg.channels;
  1939. break;
  1940. case MSM_BACKEND_DAI_USB_TX:
  1941. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1942. usb_tx_cfg.bit_format);
  1943. rate->min = rate->max = usb_tx_cfg.sample_rate;
  1944. channels->min = channels->max = usb_tx_cfg.channels;
  1945. break;
  1946. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  1947. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  1948. if (idx < 0) {
  1949. pr_err("%s: Incorrect ext disp idx %d\n",
  1950. __func__, idx);
  1951. rc = idx;
  1952. break;
  1953. }
  1954. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1955. ext_disp_rx_cfg[idx].bit_format);
  1956. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  1957. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  1958. break;
  1959. case MSM_BACKEND_DAI_AFE_PCM_RX:
  1960. channels->min = channels->max = proxy_rx_cfg.channels;
  1961. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  1962. break;
  1963. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  1964. channels->min = channels->max =
  1965. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  1966. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1967. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  1968. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  1969. break;
  1970. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  1971. channels->min = channels->max =
  1972. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  1973. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1974. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  1975. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  1976. break;
  1977. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  1978. channels->min = channels->max =
  1979. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  1980. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1981. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  1982. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  1983. break;
  1984. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  1985. channels->min = channels->max =
  1986. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  1987. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1988. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  1989. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  1990. break;
  1991. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  1992. channels->min = channels->max =
  1993. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  1994. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1995. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  1996. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  1997. break;
  1998. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  1999. channels->min = channels->max =
  2000. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  2001. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2002. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  2003. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  2004. break;
  2005. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  2006. channels->min = channels->max =
  2007. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  2008. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2009. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  2010. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2011. break;
  2012. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  2013. channels->min = channels->max =
  2014. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  2015. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2016. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  2017. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2018. break;
  2019. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  2020. channels->min = channels->max =
  2021. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  2022. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2023. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  2024. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  2025. break;
  2026. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  2027. channels->min = channels->max =
  2028. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  2029. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2030. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  2031. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  2032. break;
  2033. case MSM_BACKEND_DAI_AUXPCM_RX:
  2034. rate->min = rate->max =
  2035. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  2036. channels->min = channels->max =
  2037. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  2038. break;
  2039. case MSM_BACKEND_DAI_AUXPCM_TX:
  2040. rate->min = rate->max =
  2041. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  2042. channels->min = channels->max =
  2043. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  2044. break;
  2045. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  2046. rate->min = rate->max =
  2047. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  2048. channels->min = channels->max =
  2049. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  2050. break;
  2051. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  2052. rate->min = rate->max =
  2053. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  2054. channels->min = channels->max =
  2055. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  2056. break;
  2057. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  2058. rate->min = rate->max =
  2059. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  2060. channels->min = channels->max =
  2061. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  2062. break;
  2063. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  2064. rate->min = rate->max =
  2065. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  2066. channels->min = channels->max =
  2067. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  2068. break;
  2069. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  2070. rate->min = rate->max =
  2071. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  2072. channels->min = channels->max =
  2073. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  2074. break;
  2075. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  2076. rate->min = rate->max =
  2077. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  2078. channels->min = channels->max =
  2079. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  2080. break;
  2081. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  2082. rate->min = rate->max =
  2083. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  2084. channels->min = channels->max =
  2085. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  2086. break;
  2087. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  2088. rate->min = rate->max =
  2089. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  2090. channels->min = channels->max =
  2091. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  2092. break;
  2093. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2094. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  2095. channels->min = channels->max =
  2096. mi2s_rx_cfg[PRIM_MI2S].channels;
  2097. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2098. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  2099. break;
  2100. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2101. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  2102. channels->min = channels->max =
  2103. mi2s_tx_cfg[PRIM_MI2S].channels;
  2104. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2105. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  2106. break;
  2107. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2108. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  2109. channels->min = channels->max =
  2110. mi2s_rx_cfg[SEC_MI2S].channels;
  2111. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2112. mi2s_rx_cfg[SEC_MI2S].bit_format);
  2113. break;
  2114. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2115. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  2116. channels->min = channels->max =
  2117. mi2s_tx_cfg[SEC_MI2S].channels;
  2118. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2119. mi2s_tx_cfg[SEC_MI2S].bit_format);
  2120. break;
  2121. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2122. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  2123. channels->min = channels->max =
  2124. mi2s_rx_cfg[TERT_MI2S].channels;
  2125. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2126. mi2s_rx_cfg[TERT_MI2S].bit_format);
  2127. break;
  2128. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2129. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  2130. channels->min = channels->max =
  2131. mi2s_tx_cfg[TERT_MI2S].channels;
  2132. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2133. mi2s_tx_cfg[TERT_MI2S].bit_format);
  2134. break;
  2135. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2136. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  2137. channels->min = channels->max =
  2138. mi2s_rx_cfg[QUAT_MI2S].channels;
  2139. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2140. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  2141. break;
  2142. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2143. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  2144. channels->min = channels->max =
  2145. mi2s_tx_cfg[QUAT_MI2S].channels;
  2146. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2147. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  2148. break;
  2149. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2150. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  2151. channels->min = channels->max =
  2152. mi2s_rx_cfg[QUIN_MI2S].channels;
  2153. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2154. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  2155. break;
  2156. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2157. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  2158. channels->min = channels->max =
  2159. mi2s_tx_cfg[QUIN_MI2S].channels;
  2160. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2161. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  2162. break;
  2163. default:
  2164. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  2165. break;
  2166. }
  2167. return rc;
  2168. }
  2169. EXPORT_SYMBOL(msm_common_be_hw_params_fixup);
  2170. /**
  2171. * msm_aux_pcm_snd_startup - startup ops of auxpcm.
  2172. *
  2173. * @substream: PCM stream pointer of associated backend dailink
  2174. *
  2175. * Returns 0 on success or -EINVAL on error.
  2176. */
  2177. int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream)
  2178. {
  2179. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2180. dev_dbg(rtd->card->dev,
  2181. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2182. __func__, substream->name, substream->stream,
  2183. rtd->cpu_dai->name, rtd->cpu_dai->id);
  2184. return 0;
  2185. }
  2186. EXPORT_SYMBOL(msm_aux_pcm_snd_startup);
  2187. /**
  2188. * msm_aux_pcm_snd_shutdown - shutdown ops of auxpcm.
  2189. *
  2190. * @substream: PCM stream pointer of associated backend dailink
  2191. */
  2192. void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream)
  2193. {
  2194. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2195. dev_dbg(rtd->card->dev,
  2196. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2197. __func__,
  2198. substream->name, substream->stream,
  2199. rtd->cpu_dai->name, rtd->cpu_dai->id);
  2200. }
  2201. EXPORT_SYMBOL(msm_aux_pcm_snd_shutdown);
  2202. static int msm_get_port_id(int id)
  2203. {
  2204. int afe_port_id;
  2205. switch (id) {
  2206. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2207. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2208. break;
  2209. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2210. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2211. break;
  2212. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2213. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2214. break;
  2215. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2216. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2217. break;
  2218. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2219. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2220. break;
  2221. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2222. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2223. break;
  2224. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2225. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2226. break;
  2227. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2228. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2229. break;
  2230. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2231. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2232. break;
  2233. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2234. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2235. break;
  2236. default:
  2237. pr_err("%s: Invalid id: %d\n", __func__, id);
  2238. afe_port_id = -EINVAL;
  2239. }
  2240. return afe_port_id;
  2241. }
  2242. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2243. {
  2244. u32 bit_per_sample;
  2245. switch (bit_format) {
  2246. case SNDRV_PCM_FORMAT_S32_LE:
  2247. case SNDRV_PCM_FORMAT_S24_3LE:
  2248. case SNDRV_PCM_FORMAT_S24_LE:
  2249. bit_per_sample = 32;
  2250. break;
  2251. case SNDRV_PCM_FORMAT_S16_LE:
  2252. default:
  2253. bit_per_sample = 16;
  2254. break;
  2255. }
  2256. return bit_per_sample;
  2257. }
  2258. static void update_mi2s_clk_val(int dai_id, int stream)
  2259. {
  2260. u32 bit_per_sample;
  2261. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2262. bit_per_sample =
  2263. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2264. mi2s_clk[dai_id].clk_freq_in_hz =
  2265. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2266. } else {
  2267. bit_per_sample =
  2268. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2269. mi2s_clk[dai_id].clk_freq_in_hz =
  2270. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2271. }
  2272. }
  2273. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2274. {
  2275. int ret = 0;
  2276. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2277. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2278. int port_id = 0;
  2279. int index = cpu_dai->id;
  2280. port_id = msm_get_port_id(rtd->dai_link->id);
  2281. if (port_id < 0) {
  2282. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2283. ret = port_id;
  2284. goto done;
  2285. }
  2286. if (enable) {
  2287. update_mi2s_clk_val(index, substream->stream);
  2288. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2289. mi2s_clk[index].clk_freq_in_hz);
  2290. }
  2291. mi2s_clk[index].enable = enable;
  2292. ret = afe_set_lpass_clock_v2(port_id,
  2293. &mi2s_clk[index]);
  2294. if (ret < 0) {
  2295. dev_err(rtd->card->dev,
  2296. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2297. __func__, port_id, ret);
  2298. goto done;
  2299. }
  2300. done:
  2301. return ret;
  2302. }
  2303. /**
  2304. * msm_mi2s_snd_startup - startup ops of mi2s.
  2305. *
  2306. * @substream: PCM stream pointer of associated backend dailink
  2307. *
  2308. * Returns 0 on success or -EINVAL on error.
  2309. */
  2310. int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  2311. {
  2312. int ret = 0;
  2313. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2314. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2315. int port_id = msm_get_port_id(rtd->dai_link->id);
  2316. int index = cpu_dai->id;
  2317. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  2318. dev_dbg(rtd->card->dev,
  2319. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2320. __func__, substream->name, substream->stream,
  2321. cpu_dai->name, cpu_dai->id);
  2322. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  2323. ret = -EINVAL;
  2324. dev_err(rtd->card->dev,
  2325. "%s: CPU DAI id (%d) out of range\n",
  2326. __func__, cpu_dai->id);
  2327. goto done;
  2328. }
  2329. /*
  2330. * Muxtex protection in case the same MI2S
  2331. * interface using for both TX and RX so
  2332. * that the same clock won't be enable twice.
  2333. */
  2334. mutex_lock(&mi2s_intf_conf[index].lock);
  2335. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  2336. /* Check if msm needs to provide the clock to the interface */
  2337. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  2338. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  2339. fmt = SND_SOC_DAIFMT_CBM_CFM;
  2340. }
  2341. ret = msm_mi2s_set_sclk(substream, true);
  2342. if (ret < 0) {
  2343. dev_err(rtd->card->dev,
  2344. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  2345. __func__, ret);
  2346. goto clean_up;
  2347. }
  2348. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  2349. if (ret < 0) {
  2350. dev_err(rtd->card->dev,
  2351. "%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  2352. __func__, index, ret);
  2353. goto clk_off;
  2354. }
  2355. if (mi2s_intf_conf[index].msm_is_ext_mclk) {
  2356. mi2s_mclk[index].enable = 1;
  2357. pr_debug("%s: Enabling mclk, clk_freq_in_hz = %u\n",
  2358. __func__, mi2s_mclk[index].clk_freq_in_hz);
  2359. ret = afe_set_lpass_clock_v2(port_id,
  2360. &mi2s_mclk[index]);
  2361. if (ret < 0) {
  2362. pr_err("%s: afe lpass mclk failed, err:%d\n",
  2363. __func__, ret);
  2364. goto clk_off;
  2365. }
  2366. }
  2367. }
  2368. mutex_unlock(&mi2s_intf_conf[index].lock);
  2369. return 0;
  2370. clk_off:
  2371. if (ret < 0)
  2372. msm_mi2s_set_sclk(substream, false);
  2373. clean_up:
  2374. if (ret < 0)
  2375. mi2s_intf_conf[index].ref_cnt--;
  2376. mutex_unlock(&mi2s_intf_conf[index].lock);
  2377. done:
  2378. return ret;
  2379. }
  2380. EXPORT_SYMBOL(msm_mi2s_snd_startup);
  2381. /**
  2382. * msm_mi2s_snd_shutdown - shutdown ops of mi2s.
  2383. *
  2384. * @substream: PCM stream pointer of associated backend dailink
  2385. */
  2386. void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  2387. {
  2388. int ret;
  2389. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2390. int port_id = msm_get_port_id(rtd->dai_link->id);
  2391. int index = rtd->cpu_dai->id;
  2392. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  2393. substream->name, substream->stream);
  2394. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  2395. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  2396. return;
  2397. }
  2398. mutex_lock(&mi2s_intf_conf[index].lock);
  2399. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  2400. ret = msm_mi2s_set_sclk(substream, false);
  2401. if (ret < 0) {
  2402. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  2403. __func__, index, ret);
  2404. mi2s_intf_conf[index].ref_cnt++;
  2405. }
  2406. if (mi2s_intf_conf[index].msm_is_ext_mclk) {
  2407. mi2s_mclk[index].enable = 0;
  2408. pr_debug("%s: Disabling mclk, clk_freq_in_hz = %u\n",
  2409. __func__, mi2s_mclk[index].clk_freq_in_hz);
  2410. ret = afe_set_lpass_clock_v2(port_id,
  2411. &mi2s_mclk[index]);
  2412. if (ret < 0) {
  2413. pr_err("%s: mclk disable failed for MCLK (%d); ret=%d\n",
  2414. __func__, index, ret);
  2415. }
  2416. }
  2417. }
  2418. mutex_unlock(&mi2s_intf_conf[index].lock);
  2419. }
  2420. EXPORT_SYMBOL(msm_mi2s_snd_shutdown);
  2421. /* Validate whether US EU switch is present or not */
  2422. static int msm_prepare_us_euro(struct snd_soc_card *card)
  2423. {
  2424. struct msm_asoc_mach_data *pdata =
  2425. snd_soc_card_get_drvdata(card);
  2426. int ret = 0;
  2427. if (pdata->us_euro_gpio >= 0) {
  2428. dev_dbg(card->dev, "%s: us_euro gpio request %d", __func__,
  2429. pdata->us_euro_gpio);
  2430. ret = gpio_request(pdata->us_euro_gpio, "TASHA_CODEC_US_EURO");
  2431. if (ret) {
  2432. dev_err(card->dev,
  2433. "%s: Failed to request codec US/EURO gpio %d error %d\n",
  2434. __func__, pdata->us_euro_gpio, ret);
  2435. }
  2436. }
  2437. return ret;
  2438. }
  2439. static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active)
  2440. {
  2441. struct snd_soc_card *card = codec->component.card;
  2442. struct msm_asoc_mach_data *pdata =
  2443. snd_soc_card_get_drvdata(card);
  2444. int value = 0;
  2445. if (pdata->us_euro_gpio_p) {
  2446. value = msm_cdc_pinctrl_get_state(pdata->us_euro_gpio_p);
  2447. if (value)
  2448. msm_cdc_pinctrl_select_sleep_state(
  2449. pdata->us_euro_gpio_p);
  2450. else
  2451. msm_cdc_pinctrl_select_active_state(
  2452. pdata->us_euro_gpio_p);
  2453. } else if (pdata->us_euro_gpio >= 0) {
  2454. value = gpio_get_value_cansleep(pdata->us_euro_gpio);
  2455. gpio_set_value_cansleep(pdata->us_euro_gpio, !value);
  2456. }
  2457. pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value);
  2458. return true;
  2459. }
  2460. static int msm_populate_dai_link_component_of_node(
  2461. struct msm_asoc_mach_data *pdata,
  2462. struct snd_soc_card *card)
  2463. {
  2464. int i, index, ret = 0;
  2465. struct device *cdev = card->dev;
  2466. struct snd_soc_dai_link *dai_link = card->dai_link;
  2467. struct device_node *phandle;
  2468. if (!cdev) {
  2469. pr_err("%s: Sound card device memory NULL\n", __func__);
  2470. return -ENODEV;
  2471. }
  2472. for (i = 0; i < card->num_links; i++) {
  2473. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  2474. continue;
  2475. /* populate platform_of_node for snd card dai links */
  2476. if (dai_link[i].platform_name &&
  2477. !dai_link[i].platform_of_node) {
  2478. index = of_property_match_string(cdev->of_node,
  2479. "asoc-platform-names",
  2480. dai_link[i].platform_name);
  2481. if (index < 0) {
  2482. pr_err("%s: No match found for platform name: %s\n",
  2483. __func__, dai_link[i].platform_name);
  2484. ret = index;
  2485. goto cpu_dai;
  2486. }
  2487. phandle = of_parse_phandle(cdev->of_node,
  2488. "asoc-platform",
  2489. index);
  2490. if (!phandle) {
  2491. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  2492. __func__, dai_link[i].platform_name,
  2493. index);
  2494. ret = -ENODEV;
  2495. goto err;
  2496. }
  2497. dai_link[i].platform_of_node = phandle;
  2498. dai_link[i].platform_name = NULL;
  2499. }
  2500. cpu_dai:
  2501. /* populate cpu_of_node for snd card dai links */
  2502. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  2503. index = of_property_match_string(cdev->of_node,
  2504. "asoc-cpu-names",
  2505. dai_link[i].cpu_dai_name);
  2506. if (index < 0)
  2507. goto codec_dai;
  2508. phandle = of_parse_phandle(cdev->of_node, "asoc-cpu",
  2509. index);
  2510. if (!phandle) {
  2511. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  2512. __func__, dai_link[i].cpu_dai_name);
  2513. ret = -ENODEV;
  2514. goto err;
  2515. }
  2516. dai_link[i].cpu_of_node = phandle;
  2517. dai_link[i].cpu_dai_name = NULL;
  2518. }
  2519. codec_dai:
  2520. /* populate codec_of_node for snd card dai links */
  2521. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  2522. index = of_property_match_string(cdev->of_node,
  2523. "asoc-codec-names",
  2524. dai_link[i].codec_name);
  2525. if (index < 0)
  2526. continue;
  2527. phandle = of_parse_phandle(cdev->of_node, "asoc-codec",
  2528. index);
  2529. if (!phandle) {
  2530. pr_err("%s: retrieving phandle for codec dai %s failed\n",
  2531. __func__, dai_link[i].codec_name);
  2532. ret = -ENODEV;
  2533. goto err;
  2534. }
  2535. dai_link[i].codec_of_node = phandle;
  2536. dai_link[i].codec_name = NULL;
  2537. }
  2538. if (pdata->snd_card_val == INT_SND_CARD) {
  2539. if ((dai_link[i].id ==
  2540. MSM_BACKEND_DAI_INT0_MI2S_RX) ||
  2541. (dai_link[i].id ==
  2542. MSM_BACKEND_DAI_INT1_MI2S_RX) ||
  2543. (dai_link[i].id ==
  2544. MSM_BACKEND_DAI_INT2_MI2S_TX) ||
  2545. (dai_link[i].id ==
  2546. MSM_BACKEND_DAI_INT3_MI2S_TX)) {
  2547. index = of_property_match_string(cdev->of_node,
  2548. "asoc-codec-names",
  2549. MSM_INT_DIGITAL_CODEC);
  2550. phandle = of_parse_phandle(cdev->of_node,
  2551. "asoc-codec",
  2552. index);
  2553. dai_link[i].codecs[DIG_CDC].of_node = phandle;
  2554. index = of_property_match_string(cdev->of_node,
  2555. "asoc-codec-names",
  2556. PMIC_INT_ANALOG_CODEC);
  2557. phandle = of_parse_phandle(cdev->of_node,
  2558. "asoc-codec",
  2559. index);
  2560. dai_link[i].codecs[ANA_CDC].of_node = phandle;
  2561. }
  2562. }
  2563. }
  2564. err:
  2565. return ret;
  2566. }
  2567. static int msm_wsa881x_init(struct snd_soc_component *component)
  2568. {
  2569. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106};
  2570. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107};
  2571. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  2572. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  2573. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  2574. struct msm_asoc_mach_data *pdata;
  2575. struct snd_soc_dapm_context *dapm =
  2576. snd_soc_codec_get_dapm(codec);
  2577. if (!codec) {
  2578. pr_err("%s codec is NULL\n", __func__);
  2579. return -EINVAL;
  2580. }
  2581. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  2582. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  2583. __func__, codec->component.name);
  2584. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  2585. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  2586. &ch_rate[0]);
  2587. if (dapm->component) {
  2588. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  2589. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  2590. }
  2591. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  2592. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  2593. __func__, codec->component.name);
  2594. wsa881x_set_channel_map(codec, &spkright_ports[0],
  2595. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  2596. &ch_rate[0]);
  2597. if (dapm->component) {
  2598. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  2599. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  2600. }
  2601. } else {
  2602. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  2603. codec->component.name);
  2604. return -EINVAL;
  2605. }
  2606. pdata = snd_soc_card_get_drvdata(component->card);
  2607. if (pdata && pdata->codec_root)
  2608. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  2609. codec);
  2610. return 0;
  2611. }
  2612. static int msm_init_wsa_dev(struct platform_device *pdev,
  2613. struct snd_soc_card *card)
  2614. {
  2615. struct device_node *wsa_of_node;
  2616. u32 wsa_max_devs;
  2617. u32 wsa_dev_cnt;
  2618. char *dev_name_str = NULL;
  2619. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  2620. const char *wsa_auxdev_name_prefix[1];
  2621. int found = 0;
  2622. int i;
  2623. int ret;
  2624. /* Get maximum WSA device count for this platform */
  2625. ret = of_property_read_u32(pdev->dev.of_node,
  2626. "qcom,wsa-max-devs", &wsa_max_devs);
  2627. if (ret) {
  2628. dev_dbg(&pdev->dev,
  2629. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  2630. __func__, pdev->dev.of_node->full_name, ret);
  2631. goto err_dt;
  2632. }
  2633. if (wsa_max_devs == 0) {
  2634. dev_warn(&pdev->dev,
  2635. "%s: Max WSA devices is 0 for this target?\n",
  2636. __func__);
  2637. goto err_dt;
  2638. }
  2639. /* Get count of WSA device phandles for this platform */
  2640. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  2641. "qcom,wsa-devs", NULL);
  2642. if (wsa_dev_cnt == -ENOENT) {
  2643. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  2644. __func__);
  2645. goto err_dt;
  2646. } else if (wsa_dev_cnt <= 0) {
  2647. dev_err(&pdev->dev,
  2648. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  2649. __func__, wsa_dev_cnt);
  2650. ret = -EINVAL;
  2651. goto err_dt;
  2652. }
  2653. /*
  2654. * Expect total phandles count to be NOT less than maximum possible
  2655. * WSA count. However, if it is less, then assign same value to
  2656. * max count as well.
  2657. */
  2658. if (wsa_dev_cnt < wsa_max_devs) {
  2659. dev_dbg(&pdev->dev,
  2660. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  2661. __func__, wsa_max_devs, wsa_dev_cnt);
  2662. wsa_max_devs = wsa_dev_cnt;
  2663. }
  2664. /* Make sure prefix string passed for each WSA device */
  2665. ret = of_property_count_strings(pdev->dev.of_node,
  2666. "qcom,wsa-aux-dev-prefix");
  2667. if (ret != wsa_dev_cnt) {
  2668. dev_err(&pdev->dev,
  2669. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  2670. __func__, wsa_dev_cnt, ret);
  2671. ret = -EINVAL;
  2672. goto err_dt;
  2673. }
  2674. /*
  2675. * Alloc mem to store phandle and index info of WSA device, if already
  2676. * registered with ALSA core
  2677. */
  2678. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  2679. sizeof(struct msm_wsa881x_dev_info),
  2680. GFP_KERNEL);
  2681. if (!wsa881x_dev_info) {
  2682. ret = -ENOMEM;
  2683. goto err_mem;
  2684. }
  2685. /*
  2686. * search and check whether all WSA devices are already
  2687. * registered with ALSA core or not. If found a node, store
  2688. * the node and the index in a local array of struct for later
  2689. * use.
  2690. */
  2691. for (i = 0; i < wsa_dev_cnt; i++) {
  2692. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  2693. "qcom,wsa-devs", i);
  2694. if (unlikely(!wsa_of_node)) {
  2695. /* we should not be here */
  2696. dev_err(&pdev->dev,
  2697. "%s: wsa dev node is not present\n",
  2698. __func__);
  2699. ret = -EINVAL;
  2700. goto err_dev_node;
  2701. }
  2702. if (soc_find_component(wsa_of_node, NULL)) {
  2703. /* WSA device registered with ALSA core */
  2704. wsa881x_dev_info[found].of_node = wsa_of_node;
  2705. wsa881x_dev_info[found].index = i;
  2706. found++;
  2707. if (found == wsa_max_devs)
  2708. break;
  2709. }
  2710. }
  2711. if (found < wsa_max_devs) {
  2712. dev_dbg(&pdev->dev,
  2713. "%s: failed to find %d components. Found only %d\n",
  2714. __func__, wsa_max_devs, found);
  2715. return -EPROBE_DEFER;
  2716. }
  2717. dev_info(&pdev->dev,
  2718. "%s: found %d wsa881x devices registered with ALSA core\n",
  2719. __func__, found);
  2720. card->num_aux_devs = wsa_max_devs;
  2721. card->num_configs = wsa_max_devs;
  2722. /* Alloc array of AUX devs struct */
  2723. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  2724. sizeof(struct snd_soc_aux_dev),
  2725. GFP_KERNEL);
  2726. if (!msm_aux_dev) {
  2727. ret = -ENOMEM;
  2728. goto err_auxdev_mem;
  2729. }
  2730. /* Alloc array of codec conf struct */
  2731. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  2732. sizeof(struct snd_soc_codec_conf),
  2733. GFP_KERNEL);
  2734. if (!msm_codec_conf) {
  2735. ret = -ENOMEM;
  2736. goto err_codec_conf;
  2737. }
  2738. for (i = 0; i < card->num_aux_devs; i++) {
  2739. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  2740. GFP_KERNEL);
  2741. if (!dev_name_str) {
  2742. ret = -ENOMEM;
  2743. goto err_dev_str;
  2744. }
  2745. ret = of_property_read_string_index(pdev->dev.of_node,
  2746. "qcom,wsa-aux-dev-prefix",
  2747. wsa881x_dev_info[i].index,
  2748. wsa_auxdev_name_prefix);
  2749. if (ret) {
  2750. dev_err(&pdev->dev,
  2751. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  2752. __func__, ret);
  2753. ret = -EINVAL;
  2754. goto err_dt_prop;
  2755. }
  2756. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  2757. msm_aux_dev[i].name = dev_name_str;
  2758. msm_aux_dev[i].codec_name = NULL;
  2759. msm_aux_dev[i].codec_of_node =
  2760. wsa881x_dev_info[i].of_node;
  2761. msm_aux_dev[i].init = msm_wsa881x_init;
  2762. msm_codec_conf[i].dev_name = NULL;
  2763. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  2764. msm_codec_conf[i].of_node = wsa881x_dev_info[i].of_node;
  2765. }
  2766. card->codec_conf = msm_codec_conf;
  2767. card->aux_dev = msm_aux_dev;
  2768. return 0;
  2769. err_dt_prop:
  2770. devm_kfree(&pdev->dev, dev_name_str);
  2771. err_dev_str:
  2772. devm_kfree(&pdev->dev, msm_codec_conf);
  2773. err_codec_conf:
  2774. devm_kfree(&pdev->dev, msm_aux_dev);
  2775. err_auxdev_mem:
  2776. err_dev_node:
  2777. devm_kfree(&pdev->dev, wsa881x_dev_info);
  2778. err_mem:
  2779. err_dt:
  2780. return ret;
  2781. }
  2782. static void msm_free_auxdev_mem(struct platform_device *pdev)
  2783. {
  2784. struct snd_soc_card *card = platform_get_drvdata(pdev);
  2785. int i;
  2786. if (card->num_aux_devs > 0) {
  2787. for (i = 0; i < card->num_aux_devs; i++) {
  2788. kfree(msm_aux_dev[i].codec_name);
  2789. kfree(msm_codec_conf[i].dev_name);
  2790. kfree(msm_codec_conf[i].name_prefix);
  2791. }
  2792. }
  2793. }
  2794. static void i2s_auxpcm_init(struct platform_device *pdev)
  2795. {
  2796. int count;
  2797. u32 mi2s_master_slave[MI2S_MAX];
  2798. u32 mi2s_ext_mclk[MI2S_MAX];
  2799. int ret;
  2800. for (count = 0; count < MI2S_MAX; count++) {
  2801. mutex_init(&mi2s_intf_conf[count].lock);
  2802. mi2s_intf_conf[count].ref_cnt = 0;
  2803. }
  2804. ret = of_property_read_u32_array(pdev->dev.of_node,
  2805. "qcom,msm-mi2s-master",
  2806. mi2s_master_slave, MI2S_MAX);
  2807. if (ret) {
  2808. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  2809. __func__);
  2810. } else {
  2811. for (count = 0; count < MI2S_MAX; count++) {
  2812. mi2s_intf_conf[count].msm_is_mi2s_master =
  2813. mi2s_master_slave[count];
  2814. }
  2815. }
  2816. ret = of_property_read_u32_array(pdev->dev.of_node,
  2817. "qcom,msm-mi2s-ext-mclk",
  2818. mi2s_ext_mclk, MI2S_MAX);
  2819. if (ret) {
  2820. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-ext-mclk in DT node\n",
  2821. __func__);
  2822. } else {
  2823. for (count = 0; count < MI2S_MAX; count++)
  2824. mi2s_intf_conf[count].msm_is_ext_mclk =
  2825. mi2s_ext_mclk[count];
  2826. }
  2827. }
  2828. static const struct of_device_id sdm660_asoc_machine_of_match[] = {
  2829. { .compatible = "qcom,sdm660-asoc-snd",
  2830. .data = "internal_codec"},
  2831. { .compatible = "qcom,sdm660-asoc-snd-tasha",
  2832. .data = "tasha_codec"},
  2833. { .compatible = "qcom,sdm660-asoc-snd-tavil",
  2834. .data = "tavil_codec"},
  2835. { .compatible = "qcom,sdm670-asoc-snd",
  2836. .data = "internal_codec"},
  2837. { .compatible = "qcom,sdm670-asoc-snd-tasha",
  2838. .data = "tasha_codec"},
  2839. { .compatible = "qcom,sdm670-asoc-snd-tavil",
  2840. .data = "tavil_codec"},
  2841. {},
  2842. };
  2843. static int msm_asoc_machine_probe(struct platform_device *pdev)
  2844. {
  2845. struct snd_soc_card *card = NULL;
  2846. struct msm_asoc_mach_data *pdata = NULL;
  2847. const char *mclk = "qcom,msm-mclk-freq";
  2848. int ret = -EINVAL, id;
  2849. const struct of_device_id *match;
  2850. pdata = devm_kzalloc(&pdev->dev,
  2851. sizeof(struct msm_asoc_mach_data),
  2852. GFP_KERNEL);
  2853. if (!pdata)
  2854. return -ENOMEM;
  2855. msm_set_codec_reg_done(false);
  2856. match = of_match_node(sdm660_asoc_machine_of_match,
  2857. pdev->dev.of_node);
  2858. if (!match)
  2859. goto err;
  2860. ret = of_property_read_u32(pdev->dev.of_node, mclk, &id);
  2861. if (ret) {
  2862. dev_err(&pdev->dev,
  2863. "%s: missing %s in dt node\n", __func__, mclk);
  2864. id = DEFAULT_MCLK_RATE;
  2865. }
  2866. pdata->mclk_freq = id;
  2867. if (!strcmp(match->data, "tasha_codec") ||
  2868. !strcmp(match->data, "tavil_codec")) {
  2869. if (!strcmp(match->data, "tasha_codec"))
  2870. pdata->snd_card_val = EXT_SND_CARD_TASHA;
  2871. else
  2872. pdata->snd_card_val = EXT_SND_CARD_TAVIL;
  2873. ret = msm_ext_cdc_init(pdev, pdata, &card, &mbhc_cfg);
  2874. if (ret)
  2875. goto err;
  2876. } else if (!strcmp(match->data, "internal_codec")) {
  2877. pdata->snd_card_val = INT_SND_CARD;
  2878. ret = msm_int_cdc_init(pdev, pdata, &card, &mbhc_cfg);
  2879. if (ret)
  2880. goto err;
  2881. } else {
  2882. dev_err(&pdev->dev,
  2883. "%s: Not a matching DT sound node\n", __func__);
  2884. goto err;
  2885. }
  2886. if (!card)
  2887. goto err;
  2888. if (pdata->snd_card_val == INT_SND_CARD) {
  2889. /*reading the gpio configurations from dtsi file*/
  2890. pdata->pdm_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2891. "qcom,cdc-pdm-gpios", 0);
  2892. pdata->comp_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2893. "qcom,cdc-comp-gpios", 0);
  2894. pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2895. "qcom,cdc-dmic-gpios", 0);
  2896. pdata->ext_spk_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2897. "qcom,cdc-ext-spk-gpios", 0);
  2898. }
  2899. /*
  2900. * Parse US-Euro gpio info from DT. Report no error if us-euro
  2901. * entry is not found in DT file as some targets do not support
  2902. * US-Euro detection
  2903. */
  2904. pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node,
  2905. "qcom,us-euro-gpios", 0);
  2906. if (!gpio_is_valid(pdata->us_euro_gpio))
  2907. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2908. "qcom,us-euro-gpios", 0);
  2909. if (!gpio_is_valid(pdata->us_euro_gpio) && (!pdata->us_euro_gpio_p)) {
  2910. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  2911. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  2912. } else {
  2913. dev_dbg(&pdev->dev, "%s detected",
  2914. "qcom,us-euro-gpios");
  2915. mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  2916. }
  2917. ret = msm_prepare_us_euro(card);
  2918. if (ret)
  2919. dev_dbg(&pdev->dev, "msm_prepare_us_euro failed (%d)\n",
  2920. ret);
  2921. i2s_auxpcm_init(pdev);
  2922. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  2923. if (ret)
  2924. goto err;
  2925. ret = msm_populate_dai_link_component_of_node(pdata, card);
  2926. if (ret) {
  2927. ret = -EPROBE_DEFER;
  2928. goto err;
  2929. }
  2930. if (!of_property_read_bool(pdev->dev.of_node, "qcom,wsa-disable")) {
  2931. ret = msm_init_wsa_dev(pdev, card);
  2932. if (ret)
  2933. goto err;
  2934. }
  2935. ret = devm_snd_soc_register_card(&pdev->dev, card);
  2936. if (ret == -EPROBE_DEFER) {
  2937. if (codec_reg_done) {
  2938. /*
  2939. * return failure as EINVAL since other codec
  2940. * registered sound card successfully.
  2941. * This avoids any further probe calls.
  2942. */
  2943. ret = -EINVAL;
  2944. }
  2945. goto err;
  2946. } else if (ret) {
  2947. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  2948. ret);
  2949. goto err;
  2950. }
  2951. if (pdata->snd_card_val != INT_SND_CARD)
  2952. msm_ext_register_audio_notifier(pdev);
  2953. return 0;
  2954. err:
  2955. if (pdata->us_euro_gpio > 0) {
  2956. dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n",
  2957. __func__, pdata->us_euro_gpio);
  2958. pdata->us_euro_gpio = 0;
  2959. }
  2960. if (pdata->hph_en1_gpio > 0) {
  2961. dev_dbg(&pdev->dev, "%s free hph_en1_gpio %d\n",
  2962. __func__, pdata->hph_en1_gpio);
  2963. gpio_free(pdata->hph_en1_gpio);
  2964. pdata->hph_en1_gpio = 0;
  2965. }
  2966. if (pdata->hph_en0_gpio > 0) {
  2967. dev_dbg(&pdev->dev, "%s free hph_en0_gpio %d\n",
  2968. __func__, pdata->hph_en0_gpio);
  2969. gpio_free(pdata->hph_en0_gpio);
  2970. pdata->hph_en0_gpio = 0;
  2971. }
  2972. devm_kfree(&pdev->dev, pdata);
  2973. return ret;
  2974. }
  2975. static int msm_asoc_machine_remove(struct platform_device *pdev)
  2976. {
  2977. struct snd_soc_card *card = platform_get_drvdata(pdev);
  2978. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  2979. if (pdata->snd_card_val == INT_SND_CARD)
  2980. mutex_destroy(&pdata->cdc_int_mclk0_mutex);
  2981. msm_free_auxdev_mem(pdev);
  2982. gpio_free(pdata->us_euro_gpio);
  2983. gpio_free(pdata->hph_en1_gpio);
  2984. gpio_free(pdata->hph_en0_gpio);
  2985. snd_soc_unregister_card(card);
  2986. return 0;
  2987. }
  2988. static struct platform_driver sdm660_asoc_machine_driver = {
  2989. .driver = {
  2990. .name = DRV_NAME,
  2991. .owner = THIS_MODULE,
  2992. .pm = &snd_soc_pm_ops,
  2993. .of_match_table = sdm660_asoc_machine_of_match,
  2994. },
  2995. .probe = msm_asoc_machine_probe,
  2996. .remove = msm_asoc_machine_remove,
  2997. };
  2998. module_platform_driver(sdm660_asoc_machine_driver);
  2999. MODULE_DESCRIPTION("ALSA SoC msm");
  3000. MODULE_LICENSE("GPL v2");
  3001. MODULE_ALIAS("platform:" DRV_NAME);
  3002. MODULE_DEVICE_TABLE(of, sdm660_asoc_machine_of_match);