cvp_hfi.c 116 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <asm/memory.h>
  6. #include <linux/coresight-stm.h>
  7. #include <linux/delay.h>
  8. #include <linux/devfreq.h>
  9. #include <linux/hash.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/iommu.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/of.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/slab.h>
  18. #include <linux/workqueue.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/soc/qcom/llcc-qcom.h>
  21. #include <linux/qcom_scm.h>
  22. #include <linux/soc/qcom/smem.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/reset.h>
  25. #include "hfi_packetization.h"
  26. #include "msm_cvp_debug.h"
  27. #include "cvp_core_hfi.h"
  28. #include "cvp_hfi_helper.h"
  29. #include "cvp_hfi_io.h"
  30. #include "msm_cvp_dsp.h"
  31. #define FIRMWARE_SIZE 0X00A00000
  32. #define REG_ADDR_OFFSET_BITMASK 0x000FFFFF
  33. #define QDSS_IOVA_START 0x80001000
  34. #define MIN_PAYLOAD_SIZE 3
  35. const struct msm_cvp_hfi_defs cvp_hfi_defs[] = {
  36. {
  37. .size = HFI_DFS_CONFIG_CMD_SIZE,
  38. .type = HFI_CMD_SESSION_CVP_DFS_CONFIG,
  39. .buf_offset = 0,
  40. .buf_num = 0,
  41. .resp = HAL_SESSION_DFS_CONFIG_CMD_DONE,
  42. },
  43. {
  44. .size = HFI_DFS_FRAME_CMD_SIZE,
  45. .type = HFI_CMD_SESSION_CVP_DFS_FRAME,
  46. .buf_offset = HFI_DFS_FRAME_BUFFERS_OFFSET,
  47. .buf_num = HFI_DFS_BUF_NUM,
  48. .resp = HAL_NO_RESP,
  49. },
  50. {
  51. .size = HFI_DME_CONFIG_CMD_SIZE,
  52. .type = HFI_CMD_SESSION_CVP_DME_CONFIG,
  53. .buf_offset = 0,
  54. .buf_num = 0,
  55. .resp = HAL_SESSION_DME_CONFIG_CMD_DONE,
  56. },
  57. {
  58. .size = HFI_DME_BASIC_CONFIG_CMD_SIZE,
  59. .type = HFI_CMD_SESSION_CVP_DME_BASIC_CONFIG,
  60. .buf_offset = 0,
  61. .buf_num = 0,
  62. .resp = HAL_SESSION_DME_BASIC_CONFIG_CMD_DONE,
  63. },
  64. {
  65. .size = HFI_DME_FRAME_CMD_SIZE,
  66. .type = HFI_CMD_SESSION_CVP_DME_FRAME,
  67. .buf_offset = HFI_DME_FRAME_BUFFERS_OFFSET,
  68. .buf_num = HFI_DME_BUF_NUM,
  69. .resp = HAL_NO_RESP,
  70. },
  71. {
  72. .size = HFI_PERSIST_CMD_SIZE,
  73. .type = HFI_CMD_SESSION_CVP_SET_PERSIST_BUFFERS,
  74. .buf_offset = HFI_PERSIST_BUFFERS_OFFSET,
  75. .buf_num = HFI_PERSIST_BUF_NUM,
  76. .resp = HAL_SESSION_PERSIST_SET_DONE,
  77. },
  78. {
  79. .size = 0xffffffff,
  80. .type = HFI_CMD_SESSION_CVP_RELEASE_PERSIST_BUFFERS,
  81. .buf_offset = 0,
  82. .buf_num = 0,
  83. .resp = HAL_SESSION_PERSIST_REL_DONE,
  84. },
  85. {
  86. .size = HFI_DS_CMD_SIZE,
  87. .type = HFI_CMD_SESSION_CVP_DS,
  88. .buf_offset = HFI_DS_BUFFERS_OFFSET,
  89. .buf_num = HFI_DS_BUF_NUM,
  90. .resp = HAL_NO_RESP,
  91. },
  92. {
  93. .size = HFI_OF_CONFIG_CMD_SIZE,
  94. .type = HFI_CMD_SESSION_CVP_CV_TME_CONFIG,
  95. .buf_offset = 0,
  96. .buf_num = 0,
  97. .resp = HAL_SESSION_TME_CONFIG_CMD_DONE,
  98. },
  99. {
  100. .size = HFI_OF_FRAME_CMD_SIZE,
  101. .type = HFI_CMD_SESSION_CVP_CV_TME_FRAME,
  102. .buf_offset = HFI_OF_BUFFERS_OFFSET,
  103. .buf_num = HFI_OF_BUF_NUM,
  104. .resp = HAL_NO_RESP,
  105. },
  106. {
  107. .size = HFI_ODT_CONFIG_CMD_SIZE,
  108. .type = HFI_CMD_SESSION_CVP_CV_ODT_CONFIG,
  109. .buf_offset = 0,
  110. .buf_num = 0,
  111. .resp = HAL_SESSION_ODT_CONFIG_CMD_DONE,
  112. },
  113. {
  114. .size = HFI_ODT_FRAME_CMD_SIZE,
  115. .type = HFI_CMD_SESSION_CVP_CV_ODT_FRAME,
  116. .buf_offset = HFI_ODT_BUFFERS_OFFSET,
  117. .buf_num = HFI_ODT_BUF_NUM,
  118. .resp = HAL_NO_RESP,
  119. },
  120. {
  121. .size = HFI_OD_CONFIG_CMD_SIZE,
  122. .type = HFI_CMD_SESSION_CVP_CV_OD_CONFIG,
  123. .buf_offset = 0,
  124. .buf_num = 0,
  125. .resp = HAL_SESSION_OD_CONFIG_CMD_DONE,
  126. },
  127. {
  128. .size = HFI_OD_FRAME_CMD_SIZE,
  129. .type = HFI_CMD_SESSION_CVP_CV_OD_FRAME,
  130. .buf_offset = HFI_OD_BUFFERS_OFFSET,
  131. .buf_num = HFI_OD_BUF_NUM,
  132. .resp = HAL_NO_RESP,
  133. },
  134. {
  135. .size = HFI_NCC_CONFIG_CMD_SIZE,
  136. .type = HFI_CMD_SESSION_CVP_NCC_CONFIG,
  137. .buf_offset = 0,
  138. .buf_num = 0,
  139. .resp = HAL_SESSION_NCC_CONFIG_CMD_DONE,
  140. },
  141. {
  142. .size = HFI_NCC_FRAME_CMD_SIZE,
  143. .type = HFI_CMD_SESSION_CVP_NCC_FRAME,
  144. .buf_offset = HFI_NCC_BUFFERS_OFFSET,
  145. .buf_num = HFI_NCC_BUF_NUM,
  146. .resp = HAL_NO_RESP,
  147. },
  148. {
  149. .size = HFI_ICA_CONFIG_CMD_SIZE,
  150. .type = HFI_CMD_SESSION_CVP_ICA_CONFIG,
  151. .buf_offset = 0,
  152. .buf_num = 0,
  153. .resp = HAL_SESSION_ICA_CONFIG_CMD_DONE,
  154. },
  155. {
  156. .size = HFI_ICA_FRAME_CMD_SIZE,
  157. .type = HFI_CMD_SESSION_CVP_ICA_FRAME,
  158. .buf_offset = HFI_ICA_BUFFERS_OFFSET,
  159. .buf_num = HFI_ICA_BUF_NUM,
  160. .resp = HAL_NO_RESP,
  161. },
  162. {
  163. .size = HFI_HCD_CONFIG_CMD_SIZE,
  164. .type = HFI_CMD_SESSION_CVP_HCD_CONFIG,
  165. .buf_offset = 0,
  166. .buf_num = 0,
  167. .resp = HAL_SESSION_HCD_CONFIG_CMD_DONE,
  168. },
  169. {
  170. .size = HFI_HCD_FRAME_CMD_SIZE,
  171. .type = HFI_CMD_SESSION_CVP_HCD_FRAME,
  172. .buf_offset = HFI_HCD_BUFFERS_OFFSET,
  173. .buf_num = HFI_HCD_BUF_NUM,
  174. .resp = HAL_NO_RESP,
  175. },
  176. {
  177. .size = HFI_DCM_CONFIG_CMD_SIZE,
  178. .type = HFI_CMD_SESSION_CVP_DC_CONFIG,
  179. .buf_offset = 0,
  180. .buf_num = 0,
  181. .resp = HAL_SESSION_DC_CONFIG_CMD_DONE,
  182. },
  183. {
  184. .size = HFI_DCM_FRAME_CMD_SIZE,
  185. .type = HFI_CMD_SESSION_CVP_DC_FRAME,
  186. .buf_offset = HFI_DCM_BUFFERS_OFFSET,
  187. .buf_num = HFI_DCM_BUF_NUM,
  188. .resp = HAL_NO_RESP,
  189. },
  190. {
  191. .size = HFI_DCM_CONFIG_CMD_SIZE,
  192. .type = HFI_CMD_SESSION_CVP_DCM_CONFIG,
  193. .buf_offset = 0,
  194. .buf_num = 0,
  195. .resp = HAL_SESSION_DCM_CONFIG_CMD_DONE,
  196. },
  197. {
  198. .size = HFI_DCM_FRAME_CMD_SIZE,
  199. .type = HFI_CMD_SESSION_CVP_DCM_FRAME,
  200. .buf_offset = HFI_DCM_BUFFERS_OFFSET,
  201. .buf_num = HFI_DCM_BUF_NUM,
  202. .resp = HAL_NO_RESP,
  203. },
  204. {
  205. .size = HFI_PYS_HCD_CONFIG_CMD_SIZE,
  206. .type = HFI_CMD_SESSION_CVP_PYS_HCD_CONFIG,
  207. .buf_offset = 0,
  208. .buf_num = 0,
  209. .resp = HAL_SESSION_PYS_HCD_CONFIG_CMD_DONE,
  210. },
  211. {
  212. .size = HFI_PYS_HCD_FRAME_CMD_SIZE,
  213. .type = HFI_CMD_SESSION_CVP_PYS_HCD_FRAME,
  214. .buf_offset = HFI_PYS_HCD_BUFFERS_OFFSET,
  215. .buf_num = HFI_PYS_HCD_BUF_NUM,
  216. .resp = HAL_NO_RESP,
  217. },
  218. {
  219. .size = 0xFFFFFFFF,
  220. .type = HFI_CMD_SESSION_CVP_SET_MODEL_BUFFERS,
  221. .buf_offset = 0,
  222. .buf_num = 0,
  223. .resp = HAL_SESSION_MODEL_BUF_CMD_DONE,
  224. },
  225. {
  226. .size = 0xFFFFFFFF,
  227. .type = HFI_CMD_SESSION_CVP_FD_CONFIG,
  228. .buf_offset = 0,
  229. .buf_num = 0,
  230. .resp = HAL_SESSION_FD_CONFIG_CMD_DONE,
  231. },
  232. {
  233. .size = 0xFFFFFFFF,
  234. .type = HFI_CMD_SESSION_CVP_FD_FRAME,
  235. .buf_offset = 0,
  236. .buf_num = 0,
  237. .resp = HAL_NO_RESP,
  238. },
  239. };
  240. struct cvp_tzbsp_memprot {
  241. u32 cp_start;
  242. u32 cp_size;
  243. u32 cp_nonpixel_start;
  244. u32 cp_nonpixel_size;
  245. };
  246. #define TZBSP_PIL_SET_STATE 0xA
  247. #define TZBSP_CVP_PAS_ID 26
  248. /* Poll interval in uS */
  249. #define POLL_INTERVAL_US 50
  250. enum tzbsp_subsys_state {
  251. TZ_SUBSYS_STATE_SUSPEND = 0,
  252. TZ_SUBSYS_STATE_RESUME = 1,
  253. TZ_SUBSYS_STATE_RESTORE_THRESHOLD = 2,
  254. };
  255. const struct msm_cvp_gov_data CVP_DEFAULT_BUS_VOTE = {
  256. .data = NULL,
  257. .data_count = 0,
  258. };
  259. const int cvp_max_packets = 32;
  260. static void iris_hfi_pm_handler(struct work_struct *work);
  261. static DECLARE_DELAYED_WORK(iris_hfi_pm_work, iris_hfi_pm_handler);
  262. static inline int __resume(struct iris_hfi_device *device);
  263. static inline int __suspend(struct iris_hfi_device *device);
  264. static int __disable_regulators(struct iris_hfi_device *device);
  265. static int __enable_regulators(struct iris_hfi_device *device);
  266. static inline int __prepare_enable_clks(struct iris_hfi_device *device);
  267. static inline void __disable_unprepare_clks(struct iris_hfi_device *device);
  268. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet);
  269. static int __initialize_packetization(struct iris_hfi_device *device);
  270. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  271. u32 session_id);
  272. static bool __is_session_valid(struct iris_hfi_device *device,
  273. struct cvp_hal_session *session, const char *func);
  274. static int __set_clocks(struct iris_hfi_device *device, u32 freq);
  275. static int __iface_cmdq_write(struct iris_hfi_device *device,
  276. void *pkt);
  277. static int __load_fw(struct iris_hfi_device *device);
  278. static void __unload_fw(struct iris_hfi_device *device);
  279. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state);
  280. static int __enable_subcaches(struct iris_hfi_device *device);
  281. static int __set_subcaches(struct iris_hfi_device *device);
  282. static int __release_subcaches(struct iris_hfi_device *device);
  283. static int __disable_subcaches(struct iris_hfi_device *device);
  284. static int __power_collapse(struct iris_hfi_device *device, bool force);
  285. static int iris_hfi_noc_error_info(void *dev);
  286. static void interrupt_init_iris2(struct iris_hfi_device *device);
  287. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device);
  288. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device);
  289. static int reset_ahb2axi_bridge(struct iris_hfi_device *device);
  290. static void power_off_iris2(struct iris_hfi_device *device);
  291. static int __set_ubwc_config(struct iris_hfi_device *device);
  292. static void __noc_error_info_iris2(struct iris_hfi_device *device);
  293. static int __enable_hw_power_collapse(struct iris_hfi_device *device);
  294. static struct iris_hfi_vpu_ops iris2_ops = {
  295. .interrupt_init = interrupt_init_iris2,
  296. .setup_dsp_uc_memmap = setup_dsp_uc_memmap_vpu5,
  297. .clock_config_on_enable = clock_config_on_enable_vpu5,
  298. .reset_ahb2axi_bridge = reset_ahb2axi_bridge,
  299. .power_off = power_off_iris2,
  300. .noc_error_info = __noc_error_info_iris2,
  301. };
  302. /**
  303. * Utility function to enforce some of our assumptions. Spam calls to this
  304. * in hotspots in code to double check some of the assumptions that we hold.
  305. */
  306. static inline void __strict_check(struct iris_hfi_device *device)
  307. {
  308. msm_cvp_res_handle_fatal_hw_error(device->res,
  309. !mutex_is_locked(&device->lock));
  310. }
  311. static inline void __set_state(struct iris_hfi_device *device,
  312. enum iris_hfi_state state)
  313. {
  314. device->state = state;
  315. }
  316. static inline bool __core_in_valid_state(struct iris_hfi_device *device)
  317. {
  318. return device->state != IRIS_STATE_DEINIT;
  319. }
  320. static inline bool is_sys_cache_present(struct iris_hfi_device *device)
  321. {
  322. return device->res->sys_cache_present;
  323. }
  324. #define ROW_SIZE 32
  325. int get_pkt_index(struct cvp_hal_session_cmd_pkt *hdr)
  326. {
  327. int i, pkt_num = ARRAY_SIZE(cvp_hfi_defs);
  328. for (i = 0; i < pkt_num; i++)
  329. if (cvp_hfi_defs[i].type == hdr->packet_type)
  330. return i;
  331. return -EINVAL;
  332. }
  333. int get_hfi_version(void)
  334. {
  335. struct msm_cvp_core *core;
  336. struct iris_hfi_device *hfi;
  337. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  338. hfi = (struct iris_hfi_device *)core->device->hfi_device_data;
  339. return hfi->version;
  340. }
  341. unsigned int get_msg_size(struct cvp_hfi_msg_session_hdr *hdr)
  342. {
  343. struct msm_cvp_core *core;
  344. struct iris_hfi_device *device;
  345. u32 minor_ver;
  346. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  347. if (core)
  348. device = core->device->hfi_device_data;
  349. else
  350. return 0;
  351. if (!device) {
  352. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  353. return 0;
  354. }
  355. minor_ver = (device->version & HFI_VERSION_MINOR_MASK) >>
  356. HFI_VERSION_MINOR_SHIFT;
  357. if (minor_ver < 2)
  358. return sizeof(struct cvp_hfi_msg_session_hdr);
  359. if (hdr->packet_type == HFI_MSG_SESSION_CVP_FD)
  360. return sizeof(struct cvp_hfi_msg_session_hdr_ext);
  361. else
  362. return sizeof(struct cvp_hfi_msg_session_hdr);
  363. }
  364. unsigned int get_msg_session_id(void *msg)
  365. {
  366. struct cvp_hfi_msg_session_hdr *hdr =
  367. (struct cvp_hfi_msg_session_hdr *)msg;
  368. return hdr->session_id;
  369. }
  370. unsigned int get_msg_errorcode(void *msg)
  371. {
  372. struct cvp_hfi_msg_session_hdr *hdr =
  373. (struct cvp_hfi_msg_session_hdr *)msg;
  374. return hdr->error_type;
  375. }
  376. int get_msg_opconfigs(void *msg, unsigned int *session_id,
  377. unsigned int *error_type, unsigned int *config_id)
  378. {
  379. struct cvp_hfi_msg_session_op_cfg_packet *cfg =
  380. (struct cvp_hfi_msg_session_op_cfg_packet *)msg;
  381. *session_id = cfg->session_id;
  382. *error_type = cfg->error_type;
  383. *config_id = cfg->op_conf_id;
  384. return 0;
  385. }
  386. int get_signal_from_pkt_type(unsigned int type)
  387. {
  388. int i, pkt_num = ARRAY_SIZE(cvp_hfi_defs);
  389. for (i = 0; i < pkt_num; i++)
  390. if (cvp_hfi_defs[i].type == type)
  391. return cvp_hfi_defs[i].resp;
  392. return -EINVAL;
  393. }
  394. static void __dump_packet(u8 *packet, enum cvp_msg_prio log_level)
  395. {
  396. u32 c = 0, packet_size = *(u32 *)packet;
  397. /*
  398. * row must contain enough for 0xdeadbaad * 8 to be converted into
  399. * "de ad ba ab " * 8 + '\0'
  400. */
  401. char row[3 * ROW_SIZE];
  402. for (c = 0; c * ROW_SIZE < packet_size; ++c) {
  403. int bytes_to_read = ((c + 1) * ROW_SIZE > packet_size) ?
  404. packet_size % ROW_SIZE : ROW_SIZE;
  405. hex_dump_to_buffer(packet + c * ROW_SIZE, bytes_to_read,
  406. ROW_SIZE, 4, row, sizeof(row), false);
  407. dprintk(log_level, "%s\n", row);
  408. }
  409. }
  410. static int __dsp_suspend(struct iris_hfi_device *device, bool force, u32 flags)
  411. {
  412. int rc;
  413. struct cvp_hal_session *temp;
  414. if (msm_cvp_dsp_disable)
  415. return 0;
  416. list_for_each_entry(temp, &device->sess_head, list) {
  417. /* if forceful suspend, don't check session pause info */
  418. if (force)
  419. continue;
  420. /* don't suspend if cvp session is not paused */
  421. if (!(temp->flags & SESSION_PAUSE)) {
  422. dprintk(CVP_DSP,
  423. "%s: cvp session %x not paused\n",
  424. __func__, hash32_ptr(temp));
  425. return -EBUSY;
  426. }
  427. }
  428. dprintk(CVP_DSP, "%s: suspend dsp\n", __func__);
  429. rc = cvp_dsp_suspend(flags);
  430. if (rc) {
  431. dprintk(CVP_ERR, "%s: dsp suspend failed with error %d\n",
  432. __func__, rc);
  433. return -EINVAL;
  434. }
  435. dprintk(CVP_DSP, "%s: dsp suspended\n", __func__);
  436. return 0;
  437. }
  438. static int __dsp_resume(struct iris_hfi_device *device, u32 flags)
  439. {
  440. int rc;
  441. if (msm_cvp_dsp_disable)
  442. return 0;
  443. dprintk(CVP_DSP, "%s: resume dsp\n", __func__);
  444. rc = cvp_dsp_resume(flags);
  445. if (rc) {
  446. dprintk(CVP_ERR,
  447. "%s: dsp resume failed with error %d\n",
  448. __func__, rc);
  449. return rc;
  450. }
  451. dprintk(CVP_DSP, "%s: dsp resumed\n", __func__);
  452. return rc;
  453. }
  454. static int __dsp_shutdown(struct iris_hfi_device *device, u32 flags)
  455. {
  456. int rc;
  457. if (msm_cvp_dsp_disable)
  458. return 0;
  459. dprintk(CVP_DSP, "%s: shutdown dsp\n", __func__);
  460. rc = cvp_dsp_shutdown(flags);
  461. if (rc) {
  462. dprintk(CVP_ERR,
  463. "%s: dsp shutdown failed with error %d\n",
  464. __func__, rc);
  465. WARN_ON(1);
  466. }
  467. dprintk(CVP_DSP, "%s: dsp shutdown successful\n", __func__);
  468. return rc;
  469. }
  470. static int __acquire_regulator(struct regulator_info *rinfo,
  471. struct iris_hfi_device *device)
  472. {
  473. int rc = 0;
  474. if (rinfo->has_hw_power_collapse) {
  475. rc = regulator_set_mode(rinfo->regulator,
  476. REGULATOR_MODE_NORMAL);
  477. if (rc) {
  478. /*
  479. * This is somewhat fatal, but nothing we can do
  480. * about it. We can't disable the regulator w/o
  481. * getting it back under s/w control
  482. */
  483. dprintk(CVP_WARN,
  484. "Failed to acquire regulator control: %s\n",
  485. rinfo->name);
  486. } else {
  487. dprintk(CVP_PWR,
  488. "Acquire regulator control from HW: %s\n",
  489. rinfo->name);
  490. }
  491. }
  492. if (!regulator_is_enabled(rinfo->regulator)) {
  493. dprintk(CVP_WARN, "Regulator is not enabled %s\n",
  494. rinfo->name);
  495. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  496. }
  497. return rc;
  498. }
  499. static int __hand_off_regulator(struct regulator_info *rinfo)
  500. {
  501. int rc = 0;
  502. if (rinfo->has_hw_power_collapse) {
  503. rc = regulator_set_mode(rinfo->regulator,
  504. REGULATOR_MODE_FAST);
  505. if (rc) {
  506. dprintk(CVP_WARN,
  507. "Failed to hand off regulator control: %s\n",
  508. rinfo->name);
  509. } else {
  510. dprintk(CVP_PWR,
  511. "Hand off regulator control to HW: %s\n",
  512. rinfo->name);
  513. }
  514. }
  515. return rc;
  516. }
  517. static int __hand_off_regulators(struct iris_hfi_device *device)
  518. {
  519. struct regulator_info *rinfo;
  520. int rc = 0, c = 0;
  521. iris_hfi_for_each_regulator(device, rinfo) {
  522. rc = __hand_off_regulator(rinfo);
  523. /*
  524. * If one regulator hand off failed, driver should take
  525. * the control for other regulators back.
  526. */
  527. if (rc)
  528. goto err_reg_handoff_failed;
  529. c++;
  530. }
  531. return rc;
  532. err_reg_handoff_failed:
  533. iris_hfi_for_each_regulator_reverse_continue(device, rinfo, c)
  534. __acquire_regulator(rinfo, device);
  535. return rc;
  536. }
  537. static int __write_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  538. bool *rx_req_is_set)
  539. {
  540. struct cvp_hfi_queue_header *queue;
  541. u32 packet_size_in_words, new_write_idx;
  542. u32 empty_space, read_idx, write_idx;
  543. u32 *write_ptr;
  544. if (!qinfo || !packet) {
  545. dprintk(CVP_ERR, "Invalid Params\n");
  546. return -EINVAL;
  547. } else if (!qinfo->q_array.align_virtual_addr) {
  548. dprintk(CVP_WARN, "Queues have already been freed\n");
  549. return -EINVAL;
  550. }
  551. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  552. if (!queue) {
  553. dprintk(CVP_ERR, "queue not present\n");
  554. return -ENOENT;
  555. }
  556. if (msm_cvp_debug & CVP_PKT) {
  557. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  558. __dump_packet(packet, CVP_PKT);
  559. }
  560. packet_size_in_words = (*(u32 *)packet) >> 2;
  561. if (!packet_size_in_words || packet_size_in_words >
  562. qinfo->q_array.mem_size>>2) {
  563. dprintk(CVP_ERR, "Invalid packet size\n");
  564. return -ENODATA;
  565. }
  566. spin_lock(&qinfo->hfi_lock);
  567. read_idx = queue->qhdr_read_idx;
  568. write_idx = queue->qhdr_write_idx;
  569. empty_space = (write_idx >= read_idx) ?
  570. ((qinfo->q_array.mem_size>>2) - (write_idx - read_idx)) :
  571. (read_idx - write_idx);
  572. if (empty_space <= packet_size_in_words) {
  573. queue->qhdr_tx_req = 1;
  574. spin_unlock(&qinfo->hfi_lock);
  575. dprintk(CVP_ERR, "Insufficient size (%d) to write (%d)\n",
  576. empty_space, packet_size_in_words);
  577. return -ENOTEMPTY;
  578. }
  579. queue->qhdr_tx_req = 0;
  580. new_write_idx = write_idx + packet_size_in_words;
  581. write_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  582. (write_idx << 2));
  583. if (write_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  584. write_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  585. qinfo->q_array.mem_size)) {
  586. spin_unlock(&qinfo->hfi_lock);
  587. dprintk(CVP_ERR, "Invalid write index\n");
  588. return -ENODATA;
  589. }
  590. if (new_write_idx < (qinfo->q_array.mem_size >> 2)) {
  591. memcpy(write_ptr, packet, packet_size_in_words << 2);
  592. } else {
  593. new_write_idx -= qinfo->q_array.mem_size >> 2;
  594. memcpy(write_ptr, packet, (packet_size_in_words -
  595. new_write_idx) << 2);
  596. memcpy((void *)qinfo->q_array.align_virtual_addr,
  597. packet + ((packet_size_in_words - new_write_idx) << 2),
  598. new_write_idx << 2);
  599. }
  600. /*
  601. * Memory barrier to make sure packet is written before updating the
  602. * write index
  603. */
  604. mb();
  605. queue->qhdr_write_idx = new_write_idx;
  606. if (rx_req_is_set)
  607. *rx_req_is_set = queue->qhdr_rx_req == 1;
  608. /*
  609. * Memory barrier to make sure write index is updated before an
  610. * interrupt is raised.
  611. */
  612. mb();
  613. spin_unlock(&qinfo->hfi_lock);
  614. return 0;
  615. }
  616. static int __read_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  617. u32 *pb_tx_req_is_set)
  618. {
  619. struct cvp_hfi_queue_header *queue;
  620. u32 packet_size_in_words, new_read_idx;
  621. u32 *read_ptr;
  622. u32 receive_request = 0;
  623. u32 read_idx, write_idx;
  624. int rc = 0;
  625. if (!qinfo || !packet || !pb_tx_req_is_set) {
  626. dprintk(CVP_ERR, "Invalid Params\n");
  627. return -EINVAL;
  628. } else if (!qinfo->q_array.align_virtual_addr) {
  629. dprintk(CVP_WARN, "Queues have already been freed\n");
  630. return -EINVAL;
  631. }
  632. /*
  633. * Memory barrier to make sure data is valid before
  634. *reading it
  635. */
  636. mb();
  637. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  638. if (!queue) {
  639. dprintk(CVP_ERR, "Queue memory is not allocated\n");
  640. return -ENOMEM;
  641. }
  642. /*
  643. * Do not set receive request for debug queue, if set,
  644. * Iris generates interrupt for debug messages even
  645. * when there is no response message available.
  646. * In general debug queue will not become full as it
  647. * is being emptied out for every interrupt from Iris.
  648. * Iris will anyway generates interrupt if it is full.
  649. */
  650. spin_lock(&qinfo->hfi_lock);
  651. if (queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_MSG_Q)
  652. receive_request = 1;
  653. read_idx = queue->qhdr_read_idx;
  654. write_idx = queue->qhdr_write_idx;
  655. if (read_idx == write_idx) {
  656. queue->qhdr_rx_req = receive_request;
  657. /*
  658. * mb() to ensure qhdr is updated in main memory
  659. * so that iris reads the updated header values
  660. */
  661. mb();
  662. *pb_tx_req_is_set = 0;
  663. if (write_idx != queue->qhdr_write_idx) {
  664. queue->qhdr_rx_req = 0;
  665. } else {
  666. spin_unlock(&qinfo->hfi_lock);
  667. dprintk(CVP_HFI,
  668. "%s queue is empty, rx_req = %u, tx_req = %u, read_idx = %u\n",
  669. receive_request ? "message" : "debug",
  670. queue->qhdr_rx_req, queue->qhdr_tx_req,
  671. queue->qhdr_read_idx);
  672. return -ENODATA;
  673. }
  674. }
  675. read_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  676. (read_idx << 2));
  677. if (read_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  678. read_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  679. qinfo->q_array.mem_size - sizeof(*read_ptr))) {
  680. spin_unlock(&qinfo->hfi_lock);
  681. dprintk(CVP_ERR, "Invalid read index\n");
  682. return -ENODATA;
  683. }
  684. packet_size_in_words = (*read_ptr) >> 2;
  685. if (!packet_size_in_words) {
  686. spin_unlock(&qinfo->hfi_lock);
  687. dprintk(CVP_ERR, "Zero packet size\n");
  688. return -ENODATA;
  689. }
  690. new_read_idx = read_idx + packet_size_in_words;
  691. if (((packet_size_in_words << 2) <= CVP_IFACEQ_VAR_HUGE_PKT_SIZE)
  692. && read_idx <= (qinfo->q_array.mem_size >> 2)) {
  693. if (new_read_idx < (qinfo->q_array.mem_size >> 2)) {
  694. memcpy(packet, read_ptr,
  695. packet_size_in_words << 2);
  696. } else {
  697. new_read_idx -= (qinfo->q_array.mem_size >> 2);
  698. memcpy(packet, read_ptr,
  699. (packet_size_in_words - new_read_idx) << 2);
  700. memcpy(packet + ((packet_size_in_words -
  701. new_read_idx) << 2),
  702. (u8 *)qinfo->q_array.align_virtual_addr,
  703. new_read_idx << 2);
  704. }
  705. } else {
  706. dprintk(CVP_WARN,
  707. "BAD packet received, read_idx: %#x, pkt_size: %d\n",
  708. read_idx, packet_size_in_words << 2);
  709. dprintk(CVP_WARN, "Dropping this packet\n");
  710. new_read_idx = write_idx;
  711. rc = -ENODATA;
  712. }
  713. if (new_read_idx != queue->qhdr_write_idx)
  714. queue->qhdr_rx_req = 0;
  715. else
  716. queue->qhdr_rx_req = receive_request;
  717. queue->qhdr_read_idx = new_read_idx;
  718. /*
  719. * mb() to ensure qhdr is updated in main memory
  720. * so that iris reads the updated header values
  721. */
  722. mb();
  723. *pb_tx_req_is_set = (queue->qhdr_tx_req == 1) ? 1 : 0;
  724. spin_unlock(&qinfo->hfi_lock);
  725. if ((msm_cvp_debug & CVP_PKT) &&
  726. !(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  727. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  728. __dump_packet(packet, CVP_PKT);
  729. }
  730. return rc;
  731. }
  732. static int __smem_alloc(struct iris_hfi_device *dev, struct cvp_mem_addr *mem,
  733. u32 size, u32 align, u32 flags)
  734. {
  735. struct msm_cvp_smem *alloc = &mem->mem_data;
  736. int rc = 0;
  737. if (!dev || !mem || !size) {
  738. dprintk(CVP_ERR, "Invalid Params\n");
  739. return -EINVAL;
  740. }
  741. dprintk(CVP_INFO, "start to alloc size: %d, flags: %d\n", size, flags);
  742. rc = msm_cvp_smem_alloc(size, align, flags, 1, (void *)dev->res, alloc);
  743. if (rc) {
  744. dprintk(CVP_ERR, "Alloc failed\n");
  745. rc = -ENOMEM;
  746. goto fail_smem_alloc;
  747. }
  748. dprintk(CVP_MEM, "%s: ptr = %pK, size = %d\n", __func__,
  749. alloc->kvaddr, size);
  750. mem->mem_size = alloc->size;
  751. mem->align_virtual_addr = alloc->kvaddr;
  752. mem->align_device_addr = alloc->device_addr;
  753. return rc;
  754. fail_smem_alloc:
  755. return rc;
  756. }
  757. static void __smem_free(struct iris_hfi_device *dev, struct msm_cvp_smem *mem)
  758. {
  759. if (!dev || !mem) {
  760. dprintk(CVP_ERR, "invalid param %pK %pK\n", dev, mem);
  761. return;
  762. }
  763. msm_cvp_smem_free(mem);
  764. }
  765. static void __write_register(struct iris_hfi_device *device,
  766. u32 reg, u32 value)
  767. {
  768. u32 hwiosymaddr = reg;
  769. u8 *base_addr;
  770. if (!device) {
  771. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  772. return;
  773. }
  774. __strict_check(device);
  775. if (!device->power_enabled) {
  776. dprintk(CVP_WARN,
  777. "HFI Write register failed : Power is OFF\n");
  778. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  779. return;
  780. }
  781. base_addr = device->cvp_hal_data->register_base;
  782. dprintk(CVP_REG, "Base addr: %pK, written to: %#x, Value: %#x...\n",
  783. base_addr, hwiosymaddr, value);
  784. base_addr += hwiosymaddr;
  785. writel_relaxed(value, base_addr);
  786. /*
  787. * Memory barrier to make sure value is written into the register.
  788. */
  789. wmb();
  790. }
  791. static int __read_register(struct iris_hfi_device *device, u32 reg)
  792. {
  793. int rc = 0;
  794. u8 *base_addr;
  795. if (!device) {
  796. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  797. return -EINVAL;
  798. }
  799. __strict_check(device);
  800. if (!device->power_enabled) {
  801. dprintk(CVP_WARN,
  802. "HFI Read register failed : Power is OFF\n");
  803. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  804. return -EINVAL;
  805. }
  806. base_addr = device->cvp_hal_data->register_base;
  807. rc = readl_relaxed(base_addr + reg);
  808. /*
  809. * Memory barrier to make sure value is read correctly from the
  810. * register.
  811. */
  812. rmb();
  813. dprintk(CVP_REG, "Base addr: %pK, read from: %#x, value: %#x...\n",
  814. base_addr, reg, rc);
  815. return rc;
  816. }
  817. static void __set_registers(struct iris_hfi_device *device)
  818. {
  819. struct reg_set *reg_set;
  820. int i;
  821. if (!device->res) {
  822. dprintk(CVP_ERR,
  823. "device resources null, cannot set registers\n");
  824. return;
  825. }
  826. reg_set = &device->res->reg_set;
  827. for (i = 0; i < reg_set->count; i++) {
  828. __write_register(device, reg_set->reg_tbl[i].reg,
  829. reg_set->reg_tbl[i].value);
  830. dprintk(CVP_REG, "write_reg offset=%x, val=%x\n",
  831. reg_set->reg_tbl[i].reg,
  832. reg_set->reg_tbl[i].value);
  833. }
  834. }
  835. /*
  836. * The existence of this function is a hack for 8996 (or certain Iris versions)
  837. * to overcome a hardware bug. Whenever the GDSCs momentarily power collapse
  838. * (after calling __hand_off_regulators()), the values of the threshold
  839. * registers (typically programmed by TZ) are incorrectly reset. As a result
  840. * reprogram these registers at certain agreed upon points.
  841. */
  842. static void __set_threshold_registers(struct iris_hfi_device *device)
  843. {
  844. u32 version = __read_register(device, CVP_WRAPPER_HW_VERSION);
  845. version &= ~GENMASK(15, 0);
  846. if (version != (0x3 << 28 | 0x43 << 16))
  847. return;
  848. if (__tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESTORE_THRESHOLD))
  849. dprintk(CVP_ERR, "Failed to restore threshold values\n");
  850. }
  851. static int __unvote_buses(struct iris_hfi_device *device)
  852. {
  853. int rc = 0;
  854. struct bus_info *bus = NULL;
  855. kfree(device->bus_vote.data);
  856. device->bus_vote.data = NULL;
  857. device->bus_vote.data_count = 0;
  858. iris_hfi_for_each_bus(device, bus) {
  859. rc = icc_set_bw(bus->client, 0, 0);
  860. if (rc) {
  861. dprintk(CVP_ERR,
  862. "%s: Failed unvoting bus\n", __func__);
  863. goto err_unknown_device;
  864. }
  865. }
  866. err_unknown_device:
  867. return rc;
  868. }
  869. static int __vote_buses(struct iris_hfi_device *device,
  870. struct cvp_bus_vote_data *data, int num_data)
  871. {
  872. int rc = 0;
  873. struct bus_info *bus = NULL;
  874. struct cvp_bus_vote_data *new_data = NULL;
  875. if (!num_data) {
  876. dprintk(CVP_PWR, "No vote data available\n");
  877. goto no_data_count;
  878. } else if (!data) {
  879. dprintk(CVP_ERR, "Invalid voting data\n");
  880. return -EINVAL;
  881. }
  882. new_data = kmemdup(data, num_data * sizeof(*new_data), GFP_KERNEL);
  883. if (!new_data) {
  884. dprintk(CVP_ERR, "Can't alloc memory to cache bus votes\n");
  885. rc = -ENOMEM;
  886. goto err_no_mem;
  887. }
  888. no_data_count:
  889. kfree(device->bus_vote.data);
  890. device->bus_vote.data = new_data;
  891. device->bus_vote.data_count = num_data;
  892. iris_hfi_for_each_bus(device, bus) {
  893. if (bus) {
  894. rc = icc_set_bw(bus->client, bus->range[1], 0);
  895. if (rc)
  896. dprintk(CVP_ERR,
  897. "Failed voting bus %s to ab %u\n",
  898. bus->name, bus->range[1]*1000);
  899. }
  900. }
  901. err_no_mem:
  902. return rc;
  903. }
  904. static int iris_hfi_vote_buses(void *dev, struct cvp_bus_vote_data *d, int n)
  905. {
  906. int rc = 0;
  907. struct iris_hfi_device *device = dev;
  908. if (!device)
  909. return -EINVAL;
  910. mutex_lock(&device->lock);
  911. rc = __vote_buses(device, d, n);
  912. mutex_unlock(&device->lock);
  913. return rc;
  914. }
  915. static int __core_set_resource(struct iris_hfi_device *device,
  916. struct cvp_resource_hdr *resource_hdr, void *resource_value)
  917. {
  918. struct cvp_hfi_cmd_sys_set_resource_packet *pkt;
  919. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  920. int rc = 0;
  921. if (!device || !resource_hdr || !resource_value) {
  922. dprintk(CVP_ERR, "set_res: Invalid Params\n");
  923. return -EINVAL;
  924. }
  925. pkt = (struct cvp_hfi_cmd_sys_set_resource_packet *) packet;
  926. rc = call_hfi_pkt_op(device, sys_set_resource,
  927. pkt, resource_hdr, resource_value);
  928. if (rc) {
  929. dprintk(CVP_ERR, "set_res: failed to create packet\n");
  930. goto err_create_pkt;
  931. }
  932. rc = __iface_cmdq_write(device, pkt);
  933. if (rc)
  934. rc = -ENOTEMPTY;
  935. err_create_pkt:
  936. return rc;
  937. }
  938. static int __core_release_resource(struct iris_hfi_device *device,
  939. struct cvp_resource_hdr *resource_hdr)
  940. {
  941. struct cvp_hfi_cmd_sys_release_resource_packet *pkt;
  942. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  943. int rc = 0;
  944. if (!device || !resource_hdr) {
  945. dprintk(CVP_ERR, "release_res: Invalid Params\n");
  946. return -EINVAL;
  947. }
  948. pkt = (struct cvp_hfi_cmd_sys_release_resource_packet *) packet;
  949. rc = call_hfi_pkt_op(device, sys_release_resource,
  950. pkt, resource_hdr);
  951. if (rc) {
  952. dprintk(CVP_ERR, "release_res: failed to create packet\n");
  953. goto err_create_pkt;
  954. }
  955. rc = __iface_cmdq_write(device, pkt);
  956. if (rc)
  957. rc = -ENOTEMPTY;
  958. err_create_pkt:
  959. return rc;
  960. }
  961. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state)
  962. {
  963. int rc = 0;
  964. rc = qcom_scm_set_remote_state(state, TZBSP_CVP_PAS_ID);
  965. dprintk(CVP_CORE, "Set state %d, resp %d\n", state, rc);
  966. if (rc) {
  967. dprintk(CVP_ERR, "Failed qcom_scm_set_remote_state %d\n", rc);
  968. return rc;
  969. }
  970. return 0;
  971. }
  972. static inline int __boot_firmware(struct iris_hfi_device *device)
  973. {
  974. int rc = 0, loop = 10;
  975. u32 ctrl_init_val = 0, ctrl_status = 0, count = 0, max_tries = 1000;
  976. u32 reg_gdsc;
  977. /*
  978. * Hand off control of regulators to h/w _after_ enabling clocks.
  979. * Note that the GDSC will turn off when switching from normal
  980. * (s/w triggered) to fast (HW triggered) unless the h/w vote is
  981. * present. Since Iris isn't up yet, the GDSC will be off briefly.
  982. */
  983. if (__enable_hw_power_collapse(device))
  984. dprintk(CVP_ERR, "Failed to enabled inter-frame PC\n");
  985. while (loop) {
  986. reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
  987. if (reg_gdsc & 0x80000000) {
  988. usleep_range(100, 200);
  989. loop--;
  990. } else {
  991. break;
  992. }
  993. }
  994. if (!loop)
  995. dprintk(CVP_ERR, "fail to power off CORE during resume\n");
  996. ctrl_init_val = BIT(0);
  997. __write_register(device, CVP_CTRL_INIT, ctrl_init_val);
  998. while (!ctrl_status && count < max_tries) {
  999. ctrl_status = __read_register(device, CVP_CTRL_STATUS);
  1000. if ((ctrl_status & CVP_CTRL_ERROR_STATUS__M) == 0x4) {
  1001. dprintk(CVP_ERR, "invalid setting for UC_REGION\n");
  1002. rc = -ENODATA;
  1003. break;
  1004. }
  1005. /* Reduce to 1/100th and x100 of max_tries */
  1006. usleep_range(500, 1000);
  1007. count++;
  1008. }
  1009. if (!(ctrl_status & CVP_CTRL_INIT_STATUS__M)) {
  1010. dprintk(CVP_ERR, "Failed to boot FW status: %x\n",
  1011. ctrl_status);
  1012. rc = -ENODEV;
  1013. }
  1014. /* Enable interrupt before sending commands to tensilica */
  1015. __write_register(device, CVP_CPU_CS_H2XSOFTINTEN, 0x1);
  1016. __write_register(device, CVP_CPU_CS_X2RPMh, 0x0);
  1017. return rc;
  1018. }
  1019. static int iris_hfi_resume(void *dev)
  1020. {
  1021. int rc = 0;
  1022. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1023. if (!device) {
  1024. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1025. return -EINVAL;
  1026. }
  1027. dprintk(CVP_CORE, "Resuming Iris\n");
  1028. mutex_lock(&device->lock);
  1029. rc = __resume(device);
  1030. mutex_unlock(&device->lock);
  1031. return rc;
  1032. }
  1033. static int iris_hfi_suspend(void *dev)
  1034. {
  1035. int rc = 0;
  1036. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1037. if (!device) {
  1038. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1039. return -EINVAL;
  1040. } else if (!device->res->sw_power_collapsible) {
  1041. return -ENOTSUPP;
  1042. }
  1043. dprintk(CVP_CORE, "Suspending Iris\n");
  1044. mutex_lock(&device->lock);
  1045. rc = __power_collapse(device, true);
  1046. if (rc) {
  1047. dprintk(CVP_WARN, "%s: Iris is busy\n", __func__);
  1048. rc = -EBUSY;
  1049. }
  1050. mutex_unlock(&device->lock);
  1051. /* Cancel pending delayed works if any */
  1052. if (!rc)
  1053. cancel_delayed_work(&iris_hfi_pm_work);
  1054. return rc;
  1055. }
  1056. static void cvp_dump_csr(struct iris_hfi_device *dev)
  1057. {
  1058. u32 reg;
  1059. if (!dev)
  1060. return;
  1061. if (!dev->power_enabled || dev->reg_dumped)
  1062. return;
  1063. reg = __read_register(dev, CVP_WRAPPER_CPU_STATUS);
  1064. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_STATUS: %x\n", reg);
  1065. reg = __read_register(dev, CVP_CPU_CS_SCIACMDARG0);
  1066. dprintk(CVP_ERR, "CVP_CPU_CS_SCIACMDARG0: %x\n", reg);
  1067. reg = __read_register(dev, CVP_WRAPPER_CPU_CLOCK_CONFIG);
  1068. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_CLOCK_CONFIG: %x\n", reg);
  1069. reg = __read_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  1070. dprintk(CVP_ERR, "CVP_WRAPPER_CORE_CLOCK_CONFIG: %x\n", reg);
  1071. reg = __read_register(dev, CVP_WRAPPER_INTR_STATUS);
  1072. dprintk(CVP_ERR, "CVP_WRAPPER_INTR_STATUS: %x\n", reg);
  1073. reg = __read_register(dev, CVP_CPU_CS_H2ASOFTINT);
  1074. dprintk(CVP_ERR, "CVP_CPU_CS_H2ASOFTINT: %x\n", reg);
  1075. reg = __read_register(dev, CVP_CPU_CS_A2HSOFTINT);
  1076. dprintk(CVP_ERR, "CVP_CPU_CS_A2HSOFTINT: %x\n", reg);
  1077. reg = __read_register(dev, CVP_CC_MVS1C_GDSCR);
  1078. dprintk(CVP_ERR, "CVP_CC_MVS1C_GDSCR: %x\n", reg);
  1079. reg = __read_register(dev, CVP_CC_MVS1C_CBCR);
  1080. dprintk(CVP_ERR, "CVP_CC_MVS1C_CBCR: %x\n", reg);
  1081. dev->reg_dumped = true;
  1082. }
  1083. static int iris_hfi_flush_debug_queue(void *dev)
  1084. {
  1085. int rc = 0;
  1086. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1087. if (!device) {
  1088. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1089. return -EINVAL;
  1090. }
  1091. cvp_dump_csr(device);
  1092. mutex_lock(&device->lock);
  1093. if (!device->power_enabled) {
  1094. dprintk(CVP_WARN, "%s: iris power off\n", __func__);
  1095. rc = -EINVAL;
  1096. goto exit;
  1097. }
  1098. __flush_debug_queue(device, NULL);
  1099. exit:
  1100. mutex_unlock(&device->lock);
  1101. return rc;
  1102. }
  1103. static int __set_clocks(struct iris_hfi_device *device, u32 freq)
  1104. {
  1105. struct clock_info *cl;
  1106. int rc = 0;
  1107. int factorsrc2clk = 3; // ratio factor for clock source : clk
  1108. dprintk(CVP_PWR, "%s: entering with freq : %ld\n", __func__, freq);
  1109. iris_hfi_for_each_clock(device, cl) {
  1110. if (cl->has_scaling) {/* has_scaling */
  1111. device->clk_freq = freq;
  1112. if (msm_cvp_clock_voting)
  1113. freq = msm_cvp_clock_voting;
  1114. freq = freq * factorsrc2clk;
  1115. dprintk(CVP_PWR, "%s: clock source rate set to: %ld\n", __func__, freq);
  1116. rc = clk_set_rate(cl->clk, freq);
  1117. if (rc) {
  1118. dprintk(CVP_ERR,
  1119. "Failed to set clock rate %u %s: %d %s\n",
  1120. freq, cl->name, rc, __func__);
  1121. return rc;
  1122. }
  1123. dprintk(CVP_PWR, "Scaling clock %s to %u\n",
  1124. cl->name, freq);
  1125. }
  1126. }
  1127. return 0;
  1128. }
  1129. static int iris_hfi_scale_clocks(void *dev, u32 freq)
  1130. {
  1131. int rc = 0;
  1132. struct iris_hfi_device *device = dev;
  1133. if (!device) {
  1134. dprintk(CVP_ERR, "Invalid args: %pK\n", device);
  1135. return -EINVAL;
  1136. }
  1137. mutex_lock(&device->lock);
  1138. if (__resume(device)) {
  1139. dprintk(CVP_ERR, "Resume from power collapse failed\n");
  1140. rc = -ENODEV;
  1141. goto exit;
  1142. }
  1143. rc = __set_clocks(device, freq);
  1144. exit:
  1145. mutex_unlock(&device->lock);
  1146. return rc;
  1147. }
  1148. static int __scale_clocks(struct iris_hfi_device *device)
  1149. {
  1150. int rc = 0;
  1151. struct allowed_clock_rates_table *allowed_clks_tbl = NULL;
  1152. u32 rate = 0;
  1153. allowed_clks_tbl = device->res->allowed_clks_tbl;
  1154. rate = device->clk_freq ? device->clk_freq :
  1155. allowed_clks_tbl[0].clock_rate;
  1156. dprintk(CVP_PWR, "%s: scale clock rate %d\n", __func__, rate);
  1157. rc = __set_clocks(device, rate);
  1158. return rc;
  1159. }
  1160. /* Writes into cmdq without raising an interrupt */
  1161. static int __iface_cmdq_write_relaxed(struct iris_hfi_device *device,
  1162. void *pkt, bool *requires_interrupt)
  1163. {
  1164. struct cvp_iface_q_info *q_info;
  1165. struct cvp_hal_cmd_pkt_hdr *cmd_packet;
  1166. int result = -E2BIG;
  1167. if (!device || !pkt) {
  1168. dprintk(CVP_ERR, "Invalid Params\n");
  1169. return -EINVAL;
  1170. }
  1171. __strict_check(device);
  1172. if (!__core_in_valid_state(device)) {
  1173. dprintk(CVP_ERR, "%s - fw not in init state\n", __func__);
  1174. result = -EINVAL;
  1175. goto err_q_null;
  1176. }
  1177. cmd_packet = (struct cvp_hal_cmd_pkt_hdr *)pkt;
  1178. device->last_packet_type = cmd_packet->packet_type;
  1179. q_info = &device->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1180. if (!q_info) {
  1181. dprintk(CVP_ERR, "cannot write to shared Q's\n");
  1182. goto err_q_null;
  1183. }
  1184. if (!q_info->q_array.align_virtual_addr) {
  1185. dprintk(CVP_ERR, "cannot write to shared CMD Q's\n");
  1186. result = -ENODATA;
  1187. goto err_q_null;
  1188. }
  1189. if (__resume(device)) {
  1190. dprintk(CVP_ERR, "%s: Power on failed\n", __func__);
  1191. goto err_q_write;
  1192. }
  1193. if (!__write_queue(q_info, (u8 *)pkt, requires_interrupt)) {
  1194. if (device->res->sw_power_collapsible) {
  1195. cancel_delayed_work(&iris_hfi_pm_work);
  1196. if (!queue_delayed_work(device->iris_pm_workq,
  1197. &iris_hfi_pm_work,
  1198. msecs_to_jiffies(
  1199. device->res->msm_cvp_pwr_collapse_delay))) {
  1200. dprintk(CVP_PWR,
  1201. "PM work already scheduled\n");
  1202. }
  1203. }
  1204. result = 0;
  1205. } else {
  1206. dprintk(CVP_ERR, "__iface_cmdq_write: queue full\n");
  1207. }
  1208. err_q_write:
  1209. err_q_null:
  1210. return result;
  1211. }
  1212. static int __iface_cmdq_write(struct iris_hfi_device *device, void *pkt)
  1213. {
  1214. bool needs_interrupt = false;
  1215. int rc = __iface_cmdq_write_relaxed(device, pkt, &needs_interrupt);
  1216. if (!rc && needs_interrupt) {
  1217. /* Consumer of cmdq prefers that we raise an interrupt */
  1218. rc = 0;
  1219. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1220. }
  1221. return rc;
  1222. }
  1223. static int __iface_msgq_read(struct iris_hfi_device *device, void *pkt)
  1224. {
  1225. u32 tx_req_is_set = 0;
  1226. int rc = 0;
  1227. struct cvp_iface_q_info *q_info;
  1228. if (!pkt) {
  1229. dprintk(CVP_ERR, "Invalid Params\n");
  1230. return -EINVAL;
  1231. }
  1232. __strict_check(device);
  1233. if (!__core_in_valid_state(device)) {
  1234. dprintk(CVP_WARN, "%s - fw not in init state\n", __func__);
  1235. rc = -EINVAL;
  1236. goto read_error_null;
  1237. }
  1238. q_info = &device->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1239. if (q_info->q_array.align_virtual_addr == NULL) {
  1240. dprintk(CVP_ERR, "cannot read from shared MSG Q's\n");
  1241. rc = -ENODATA;
  1242. goto read_error_null;
  1243. }
  1244. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1245. if (tx_req_is_set)
  1246. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1247. rc = 0;
  1248. } else
  1249. rc = -ENODATA;
  1250. read_error_null:
  1251. return rc;
  1252. }
  1253. static int __iface_dbgq_read(struct iris_hfi_device *device, void *pkt)
  1254. {
  1255. u32 tx_req_is_set = 0;
  1256. int rc = 0;
  1257. struct cvp_iface_q_info *q_info;
  1258. if (!pkt) {
  1259. dprintk(CVP_ERR, "Invalid Params\n");
  1260. return -EINVAL;
  1261. }
  1262. __strict_check(device);
  1263. q_info = &device->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1264. if (q_info->q_array.align_virtual_addr == NULL) {
  1265. dprintk(CVP_ERR, "cannot read from shared DBG Q's\n");
  1266. rc = -ENODATA;
  1267. goto dbg_error_null;
  1268. }
  1269. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1270. if (tx_req_is_set)
  1271. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1272. rc = 0;
  1273. } else
  1274. rc = -ENODATA;
  1275. dbg_error_null:
  1276. return rc;
  1277. }
  1278. static void __set_queue_hdr_defaults(struct cvp_hfi_queue_header *q_hdr)
  1279. {
  1280. q_hdr->qhdr_status = 0x1;
  1281. q_hdr->qhdr_type = CVP_IFACEQ_DFLT_QHDR;
  1282. q_hdr->qhdr_q_size = CVP_IFACEQ_QUEUE_SIZE / 4;
  1283. q_hdr->qhdr_pkt_size = 0;
  1284. q_hdr->qhdr_rx_wm = 0x1;
  1285. q_hdr->qhdr_tx_wm = 0x1;
  1286. q_hdr->qhdr_rx_req = 0x1;
  1287. q_hdr->qhdr_tx_req = 0x0;
  1288. q_hdr->qhdr_rx_irq_status = 0x0;
  1289. q_hdr->qhdr_tx_irq_status = 0x0;
  1290. q_hdr->qhdr_read_idx = 0x0;
  1291. q_hdr->qhdr_write_idx = 0x0;
  1292. }
  1293. static void __interface_dsp_queues_release(struct iris_hfi_device *device)
  1294. {
  1295. int i;
  1296. struct msm_cvp_smem *mem_data = &device->dsp_iface_q_table.mem_data;
  1297. struct context_bank_info *cb = mem_data->mapping_info.cb_info;
  1298. if (!device->dsp_iface_q_table.align_virtual_addr) {
  1299. dprintk(CVP_ERR, "%s: already released\n", __func__);
  1300. return;
  1301. }
  1302. dma_unmap_single_attrs(cb->dev, mem_data->device_addr,
  1303. mem_data->size, DMA_BIDIRECTIONAL, 0);
  1304. dma_free_coherent(device->res->mem_cdsp.dev, mem_data->size,
  1305. mem_data->kvaddr, mem_data->dma_handle);
  1306. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1307. device->dsp_iface_queues[i].q_hdr = NULL;
  1308. device->dsp_iface_queues[i].q_array.align_virtual_addr = NULL;
  1309. device->dsp_iface_queues[i].q_array.align_device_addr = 0;
  1310. }
  1311. device->dsp_iface_q_table.align_virtual_addr = NULL;
  1312. device->dsp_iface_q_table.align_device_addr = 0;
  1313. }
  1314. static int __interface_dsp_queues_init(struct iris_hfi_device *dev)
  1315. {
  1316. int rc = 0;
  1317. u32 i;
  1318. struct cvp_iface_q_info *iface_q;
  1319. int offset = 0;
  1320. phys_addr_t fw_bias = 0;
  1321. size_t q_size;
  1322. struct msm_cvp_smem *mem_data;
  1323. void *kvaddr;
  1324. dma_addr_t dma_handle;
  1325. dma_addr_t iova;
  1326. struct context_bank_info *cb;
  1327. q_size = ALIGN(QUEUE_SIZE, SZ_1M);
  1328. mem_data = &dev->dsp_iface_q_table.mem_data;
  1329. /* Allocate dsp queues from CDSP device memory */
  1330. kvaddr = dma_alloc_coherent(dev->res->mem_cdsp.dev, q_size,
  1331. &dma_handle, GFP_KERNEL);
  1332. if (IS_ERR_OR_NULL(kvaddr)) {
  1333. dprintk(CVP_ERR, "%s: failed dma allocation\n", __func__);
  1334. goto fail_dma_alloc;
  1335. }
  1336. cb = msm_cvp_smem_get_context_bank(0, dev->res, 0);
  1337. if (!cb) {
  1338. dprintk(CVP_ERR,
  1339. "%s: failed to get context bank\n", __func__);
  1340. goto fail_dma_map;
  1341. }
  1342. iova = dma_map_single_attrs(cb->dev, phys_to_virt(dma_handle),
  1343. q_size, DMA_BIDIRECTIONAL, 0);
  1344. if (dma_mapping_error(cb->dev, iova)) {
  1345. dprintk(CVP_ERR, "%s: failed dma mapping\n", __func__);
  1346. goto fail_dma_map;
  1347. }
  1348. dprintk(CVP_DSP,
  1349. "%s: kvaddr %pK dma_handle %#llx iova %#llx size %zd\n",
  1350. __func__, kvaddr, dma_handle, iova, q_size);
  1351. memset(mem_data, 0, sizeof(struct msm_cvp_smem));
  1352. mem_data->kvaddr = kvaddr;
  1353. mem_data->device_addr = iova;
  1354. mem_data->dma_handle = dma_handle;
  1355. mem_data->size = q_size;
  1356. mem_data->ion_flags = 0;
  1357. mem_data->mapping_info.cb_info = cb;
  1358. if (!is_iommu_present(dev->res))
  1359. fw_bias = dev->cvp_hal_data->firmware_base;
  1360. dev->dsp_iface_q_table.align_virtual_addr = kvaddr;
  1361. dev->dsp_iface_q_table.align_device_addr = iova - fw_bias;
  1362. dev->dsp_iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1363. offset = dev->dsp_iface_q_table.mem_size;
  1364. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1365. iface_q = &dev->dsp_iface_queues[i];
  1366. iface_q->q_array.align_device_addr = iova + offset - fw_bias;
  1367. iface_q->q_array.align_virtual_addr = kvaddr + offset;
  1368. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1369. offset += iface_q->q_array.mem_size;
  1370. spin_lock_init(&iface_q->hfi_lock);
  1371. }
  1372. cvp_dsp_init_hfi_queue_hdr(dev);
  1373. return rc;
  1374. fail_dma_map:
  1375. dma_free_coherent(dev->res->mem_cdsp.dev, q_size, kvaddr, dma_handle);
  1376. fail_dma_alloc:
  1377. return -ENOMEM;
  1378. }
  1379. static void __interface_queues_release(struct iris_hfi_device *device)
  1380. {
  1381. int i;
  1382. struct cvp_hfi_mem_map_table *qdss;
  1383. struct cvp_hfi_mem_map *mem_map;
  1384. int num_entries = device->res->qdss_addr_set.count;
  1385. unsigned long mem_map_table_base_addr;
  1386. struct context_bank_info *cb;
  1387. if (device->qdss.align_virtual_addr) {
  1388. qdss = (struct cvp_hfi_mem_map_table *)
  1389. device->qdss.align_virtual_addr;
  1390. qdss->mem_map_num_entries = num_entries;
  1391. mem_map_table_base_addr =
  1392. device->qdss.align_device_addr +
  1393. sizeof(struct cvp_hfi_mem_map_table);
  1394. qdss->mem_map_table_base_addr =
  1395. (u32)mem_map_table_base_addr;
  1396. if ((unsigned long)qdss->mem_map_table_base_addr !=
  1397. mem_map_table_base_addr) {
  1398. dprintk(CVP_ERR,
  1399. "Invalid mem_map_table_base_addr %#lx",
  1400. mem_map_table_base_addr);
  1401. }
  1402. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1403. cb = msm_cvp_smem_get_context_bank(false, device->res, 0);
  1404. for (i = 0; cb && i < num_entries; i++) {
  1405. iommu_unmap(cb->domain,
  1406. mem_map[i].virtual_addr,
  1407. mem_map[i].size);
  1408. }
  1409. __smem_free(device, &device->qdss.mem_data);
  1410. }
  1411. __smem_free(device, &device->iface_q_table.mem_data);
  1412. __smem_free(device, &device->sfr.mem_data);
  1413. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1414. device->iface_queues[i].q_hdr = NULL;
  1415. device->iface_queues[i].q_array.align_virtual_addr = NULL;
  1416. device->iface_queues[i].q_array.align_device_addr = 0;
  1417. }
  1418. device->iface_q_table.align_virtual_addr = NULL;
  1419. device->iface_q_table.align_device_addr = 0;
  1420. device->qdss.align_virtual_addr = NULL;
  1421. device->qdss.align_device_addr = 0;
  1422. device->sfr.align_virtual_addr = NULL;
  1423. device->sfr.align_device_addr = 0;
  1424. device->mem_addr.align_virtual_addr = NULL;
  1425. device->mem_addr.align_device_addr = 0;
  1426. __interface_dsp_queues_release(device);
  1427. }
  1428. static int __get_qdss_iommu_virtual_addr(struct iris_hfi_device *dev,
  1429. struct cvp_hfi_mem_map *mem_map,
  1430. struct iommu_domain *domain)
  1431. {
  1432. int i;
  1433. int rc = 0;
  1434. dma_addr_t iova = QDSS_IOVA_START;
  1435. int num_entries = dev->res->qdss_addr_set.count;
  1436. struct addr_range *qdss_addr_tbl = dev->res->qdss_addr_set.addr_tbl;
  1437. if (!num_entries)
  1438. return -ENODATA;
  1439. for (i = 0; i < num_entries; i++) {
  1440. if (domain) {
  1441. rc = iommu_map(domain, iova,
  1442. qdss_addr_tbl[i].start,
  1443. qdss_addr_tbl[i].size,
  1444. IOMMU_READ | IOMMU_WRITE);
  1445. if (rc) {
  1446. dprintk(CVP_ERR,
  1447. "IOMMU QDSS mapping failed for addr %#x\n",
  1448. qdss_addr_tbl[i].start);
  1449. rc = -ENOMEM;
  1450. break;
  1451. }
  1452. } else {
  1453. iova = qdss_addr_tbl[i].start;
  1454. }
  1455. mem_map[i].virtual_addr = (u32)iova;
  1456. mem_map[i].physical_addr = qdss_addr_tbl[i].start;
  1457. mem_map[i].size = qdss_addr_tbl[i].size;
  1458. mem_map[i].attr = 0x0;
  1459. iova += mem_map[i].size;
  1460. }
  1461. if (i < num_entries) {
  1462. dprintk(CVP_ERR,
  1463. "QDSS mapping failed, Freeing other entries %d\n", i);
  1464. for (--i; domain && i >= 0; i--) {
  1465. iommu_unmap(domain,
  1466. mem_map[i].virtual_addr,
  1467. mem_map[i].size);
  1468. }
  1469. }
  1470. return rc;
  1471. }
  1472. static void __setup_ucregion_memory_map(struct iris_hfi_device *device)
  1473. {
  1474. __write_register(device, CVP_UC_REGION_ADDR,
  1475. (u32)device->iface_q_table.align_device_addr);
  1476. __write_register(device, CVP_UC_REGION_SIZE, SHARED_QSIZE);
  1477. __write_register(device, CVP_QTBL_ADDR,
  1478. (u32)device->iface_q_table.align_device_addr);
  1479. __write_register(device, CVP_QTBL_INFO, 0x01);
  1480. if (device->sfr.align_device_addr)
  1481. __write_register(device, CVP_SFR_ADDR,
  1482. (u32)device->sfr.align_device_addr);
  1483. if (device->qdss.align_device_addr)
  1484. __write_register(device, CVP_MMAP_ADDR,
  1485. (u32)device->qdss.align_device_addr);
  1486. call_iris_op(device, setup_dsp_uc_memmap, device);
  1487. }
  1488. static int __interface_queues_init(struct iris_hfi_device *dev)
  1489. {
  1490. struct cvp_hfi_queue_table_header *q_tbl_hdr;
  1491. struct cvp_hfi_queue_header *q_hdr;
  1492. u32 i;
  1493. int rc = 0;
  1494. struct cvp_hfi_mem_map_table *qdss;
  1495. struct cvp_hfi_mem_map *mem_map;
  1496. struct cvp_iface_q_info *iface_q;
  1497. struct cvp_hfi_sfr_struct *vsfr;
  1498. struct cvp_mem_addr *mem_addr;
  1499. int offset = 0;
  1500. int num_entries = dev->res->qdss_addr_set.count;
  1501. phys_addr_t fw_bias = 0;
  1502. size_t q_size;
  1503. unsigned long mem_map_table_base_addr;
  1504. struct context_bank_info *cb;
  1505. q_size = SHARED_QSIZE - ALIGNED_SFR_SIZE - ALIGNED_QDSS_SIZE;
  1506. mem_addr = &dev->mem_addr;
  1507. if (!is_iommu_present(dev->res))
  1508. fw_bias = dev->cvp_hal_data->firmware_base;
  1509. rc = __smem_alloc(dev, mem_addr, q_size, 1, SMEM_UNCACHED);
  1510. if (rc) {
  1511. dprintk(CVP_ERR, "iface_q_table_alloc_fail\n");
  1512. goto fail_alloc_queue;
  1513. }
  1514. dev->iface_q_table.align_virtual_addr = mem_addr->align_virtual_addr;
  1515. dev->iface_q_table.align_device_addr = mem_addr->align_device_addr -
  1516. fw_bias;
  1517. dev->iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1518. dev->iface_q_table.mem_data = mem_addr->mem_data;
  1519. offset += dev->iface_q_table.mem_size;
  1520. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1521. iface_q = &dev->iface_queues[i];
  1522. iface_q->q_array.align_device_addr = mem_addr->align_device_addr
  1523. + offset - fw_bias;
  1524. iface_q->q_array.align_virtual_addr =
  1525. mem_addr->align_virtual_addr + offset;
  1526. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1527. offset += iface_q->q_array.mem_size;
  1528. iface_q->q_hdr = CVP_IFACEQ_GET_QHDR_START_ADDR(
  1529. dev->iface_q_table.align_virtual_addr, i);
  1530. __set_queue_hdr_defaults(iface_q->q_hdr);
  1531. spin_lock_init(&iface_q->hfi_lock);
  1532. }
  1533. if ((msm_cvp_fw_debug_mode & HFI_DEBUG_MODE_QDSS) && num_entries) {
  1534. rc = __smem_alloc(dev, mem_addr, ALIGNED_QDSS_SIZE, 1,
  1535. SMEM_UNCACHED);
  1536. if (rc) {
  1537. dprintk(CVP_WARN,
  1538. "qdss_alloc_fail: QDSS messages logging will not work\n");
  1539. dev->qdss.align_device_addr = 0;
  1540. } else {
  1541. dev->qdss.align_device_addr =
  1542. mem_addr->align_device_addr - fw_bias;
  1543. dev->qdss.align_virtual_addr =
  1544. mem_addr->align_virtual_addr;
  1545. dev->qdss.mem_size = ALIGNED_QDSS_SIZE;
  1546. dev->qdss.mem_data = mem_addr->mem_data;
  1547. }
  1548. }
  1549. rc = __smem_alloc(dev, mem_addr, ALIGNED_SFR_SIZE, 1, SMEM_UNCACHED);
  1550. if (rc) {
  1551. dprintk(CVP_WARN, "sfr_alloc_fail: SFR not will work\n");
  1552. dev->sfr.align_device_addr = 0;
  1553. } else {
  1554. dev->sfr.align_device_addr = mem_addr->align_device_addr -
  1555. fw_bias;
  1556. dev->sfr.align_virtual_addr = mem_addr->align_virtual_addr;
  1557. dev->sfr.mem_size = ALIGNED_SFR_SIZE;
  1558. dev->sfr.mem_data = mem_addr->mem_data;
  1559. }
  1560. q_tbl_hdr = (struct cvp_hfi_queue_table_header *)
  1561. dev->iface_q_table.align_virtual_addr;
  1562. q_tbl_hdr->qtbl_version = 0;
  1563. q_tbl_hdr->device_addr = (void *)dev;
  1564. strlcpy(q_tbl_hdr->name, "msm_cvp", sizeof(q_tbl_hdr->name));
  1565. q_tbl_hdr->qtbl_size = CVP_IFACEQ_TABLE_SIZE;
  1566. q_tbl_hdr->qtbl_qhdr0_offset =
  1567. sizeof(struct cvp_hfi_queue_table_header);
  1568. q_tbl_hdr->qtbl_qhdr_size = sizeof(struct cvp_hfi_queue_header);
  1569. q_tbl_hdr->qtbl_num_q = CVP_IFACEQ_NUMQ;
  1570. q_tbl_hdr->qtbl_num_active_q = CVP_IFACEQ_NUMQ;
  1571. iface_q = &dev->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1572. q_hdr = iface_q->q_hdr;
  1573. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1574. q_hdr->qhdr_type |= HFI_Q_ID_HOST_TO_CTRL_CMD_Q;
  1575. iface_q = &dev->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1576. q_hdr = iface_q->q_hdr;
  1577. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1578. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_MSG_Q;
  1579. iface_q = &dev->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1580. q_hdr = iface_q->q_hdr;
  1581. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1582. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q;
  1583. /*
  1584. * Set receive request to zero on debug queue as there is no
  1585. * need of interrupt from cvp hardware for debug messages
  1586. */
  1587. q_hdr->qhdr_rx_req = 0;
  1588. if (dev->qdss.align_virtual_addr) {
  1589. qdss =
  1590. (struct cvp_hfi_mem_map_table *)dev->qdss.align_virtual_addr;
  1591. qdss->mem_map_num_entries = num_entries;
  1592. mem_map_table_base_addr = dev->qdss.align_device_addr +
  1593. sizeof(struct cvp_hfi_mem_map_table);
  1594. qdss->mem_map_table_base_addr = mem_map_table_base_addr;
  1595. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1596. cb = msm_cvp_smem_get_context_bank(false, dev->res, 0);
  1597. if (!cb) {
  1598. dprintk(CVP_ERR,
  1599. "%s: failed to get context bank\n", __func__);
  1600. return -EINVAL;
  1601. }
  1602. rc = __get_qdss_iommu_virtual_addr(dev, mem_map, cb->domain);
  1603. if (rc) {
  1604. dprintk(CVP_ERR,
  1605. "IOMMU mapping failed, Freeing qdss memdata\n");
  1606. __smem_free(dev, &dev->qdss.mem_data);
  1607. dev->qdss.align_virtual_addr = NULL;
  1608. dev->qdss.align_device_addr = 0;
  1609. }
  1610. }
  1611. vsfr = (struct cvp_hfi_sfr_struct *) dev->sfr.align_virtual_addr;
  1612. if (vsfr)
  1613. vsfr->bufSize = ALIGNED_SFR_SIZE;
  1614. rc = __interface_dsp_queues_init(dev);
  1615. if (rc) {
  1616. dprintk(CVP_ERR, "dsp_queues_init failed\n");
  1617. goto fail_alloc_queue;
  1618. }
  1619. __setup_ucregion_memory_map(dev);
  1620. return 0;
  1621. fail_alloc_queue:
  1622. return -ENOMEM;
  1623. }
  1624. static int __sys_set_debug(struct iris_hfi_device *device, u32 debug)
  1625. {
  1626. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1627. int rc = 0;
  1628. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1629. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1630. rc = call_hfi_pkt_op(device, sys_debug_config, pkt, debug);
  1631. if (rc) {
  1632. dprintk(CVP_WARN,
  1633. "Debug mode setting to FW failed\n");
  1634. return -ENOTEMPTY;
  1635. }
  1636. if (__iface_cmdq_write(device, pkt))
  1637. return -ENOTEMPTY;
  1638. return 0;
  1639. }
  1640. static int __sys_set_idle_indicator(struct iris_hfi_device *device,
  1641. bool enable)
  1642. {
  1643. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1644. int rc = 0;
  1645. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1646. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1647. rc = call_hfi_pkt_op(device, sys_set_idle_indicator, pkt, enable);
  1648. if (__iface_cmdq_write(device, pkt))
  1649. return -ENOTEMPTY;
  1650. return 0;
  1651. }
  1652. static int __sys_set_coverage(struct iris_hfi_device *device, u32 mode)
  1653. {
  1654. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1655. int rc = 0;
  1656. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1657. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1658. rc = call_hfi_pkt_op(device, sys_coverage_config,
  1659. pkt, mode);
  1660. if (rc) {
  1661. dprintk(CVP_WARN,
  1662. "Coverage mode setting to FW failed\n");
  1663. return -ENOTEMPTY;
  1664. }
  1665. if (__iface_cmdq_write(device, pkt)) {
  1666. dprintk(CVP_WARN, "Failed to send coverage pkt to f/w\n");
  1667. return -ENOTEMPTY;
  1668. }
  1669. return 0;
  1670. }
  1671. static int __sys_set_power_control(struct iris_hfi_device *device,
  1672. bool enable)
  1673. {
  1674. struct regulator_info *rinfo;
  1675. bool supported = false;
  1676. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1677. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1678. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1679. iris_hfi_for_each_regulator(device, rinfo) {
  1680. if (rinfo->has_hw_power_collapse) {
  1681. supported = true;
  1682. break;
  1683. }
  1684. }
  1685. if (!supported)
  1686. return 0;
  1687. call_hfi_pkt_op(device, sys_power_control, pkt, enable);
  1688. if (__iface_cmdq_write(device, pkt))
  1689. return -ENOTEMPTY;
  1690. return 0;
  1691. }
  1692. static int iris_hfi_core_init(void *device)
  1693. {
  1694. int rc = 0;
  1695. u32 ipcc_iova;
  1696. struct cvp_hfi_cmd_sys_init_packet pkt;
  1697. struct cvp_hfi_cmd_sys_get_property_packet version_pkt;
  1698. struct iris_hfi_device *dev;
  1699. if (!device) {
  1700. dprintk(CVP_ERR, "Invalid device\n");
  1701. return -ENODEV;
  1702. }
  1703. dev = device;
  1704. dprintk(CVP_CORE, "Core initializing\n");
  1705. mutex_lock(&dev->lock);
  1706. dev->bus_vote.data =
  1707. kzalloc(sizeof(struct cvp_bus_vote_data), GFP_KERNEL);
  1708. if (!dev->bus_vote.data) {
  1709. dprintk(CVP_ERR, "Bus vote data memory is not allocated\n");
  1710. rc = -ENOMEM;
  1711. goto err_no_mem;
  1712. }
  1713. dev->bus_vote.data_count = 1;
  1714. dev->bus_vote.data->power_mode = CVP_POWER_TURBO;
  1715. rc = __load_fw(dev);
  1716. if (rc) {
  1717. dprintk(CVP_ERR, "Failed to load Iris FW\n");
  1718. goto err_load_fw;
  1719. }
  1720. __set_state(dev, IRIS_STATE_INIT);
  1721. dev->reg_dumped = false;
  1722. dprintk(CVP_CORE, "Dev_Virt: %pa, Reg_Virt: %pK\n",
  1723. &dev->cvp_hal_data->firmware_base,
  1724. dev->cvp_hal_data->register_base);
  1725. rc = __interface_queues_init(dev);
  1726. if (rc) {
  1727. dprintk(CVP_ERR, "failed to init queues\n");
  1728. rc = -ENOMEM;
  1729. goto err_core_init;
  1730. }
  1731. rc = msm_cvp_map_ipcc_regs(&ipcc_iova);
  1732. if (!rc) {
  1733. dprintk(CVP_CORE, "IPCC iova 0x%x\n", ipcc_iova);
  1734. __write_register(dev, CVP_MMAP_ADDR, ipcc_iova);
  1735. }
  1736. rc = __boot_firmware(dev);
  1737. if (rc) {
  1738. dprintk(CVP_ERR, "Failed to start core\n");
  1739. rc = -ENODEV;
  1740. goto err_core_init;
  1741. }
  1742. dev->version = __read_register(dev, CVP_VERSION_INFO);
  1743. rc = call_hfi_pkt_op(dev, sys_init, &pkt, 0);
  1744. if (rc) {
  1745. dprintk(CVP_ERR, "Failed to create sys init pkt\n");
  1746. goto err_core_init;
  1747. }
  1748. if (__iface_cmdq_write(dev, &pkt)) {
  1749. rc = -ENOTEMPTY;
  1750. goto err_core_init;
  1751. }
  1752. rc = call_hfi_pkt_op(dev, sys_image_version, &version_pkt);
  1753. if (rc || __iface_cmdq_write(dev, &version_pkt))
  1754. dprintk(CVP_WARN, "Failed to send image version pkt to f/w\n");
  1755. __sys_set_debug(device, msm_cvp_fw_debug);
  1756. __enable_subcaches(device);
  1757. __set_subcaches(device);
  1758. __set_ubwc_config(device);
  1759. __sys_set_idle_indicator(device, true);
  1760. if (dev->res->pm_qos_latency_us)
  1761. cpu_latency_qos_add_request(&dev->qos,
  1762. dev->res->pm_qos_latency_us);
  1763. mutex_unlock(&dev->lock);
  1764. cvp_dsp_send_hfi_queue();
  1765. dprintk(CVP_CORE, "Core inited successfully\n");
  1766. return 0;
  1767. err_core_init:
  1768. __set_state(dev, IRIS_STATE_DEINIT);
  1769. __unload_fw(dev);
  1770. err_load_fw:
  1771. err_no_mem:
  1772. dprintk(CVP_ERR, "Core init failed\n");
  1773. mutex_unlock(&dev->lock);
  1774. return rc;
  1775. }
  1776. static int iris_hfi_core_release(void *dev)
  1777. {
  1778. int rc = 0;
  1779. struct iris_hfi_device *device = dev;
  1780. struct cvp_hal_session *session, *next;
  1781. if (!device) {
  1782. dprintk(CVP_ERR, "invalid device\n");
  1783. return -ENODEV;
  1784. }
  1785. mutex_lock(&device->lock);
  1786. dprintk(CVP_WARN, "Core releasing\n");
  1787. if (device->res->pm_qos_latency_us &&
  1788. cpu_latency_qos_request_active(&device->qos))
  1789. cpu_latency_qos_remove_request(&device->qos);
  1790. __resume(device);
  1791. __set_state(device, IRIS_STATE_DEINIT);
  1792. __dsp_shutdown(device, 0);
  1793. __unload_fw(device);
  1794. /* unlink all sessions from device */
  1795. list_for_each_entry_safe(session, next, &device->sess_head, list) {
  1796. list_del(&session->list);
  1797. session->device = NULL;
  1798. }
  1799. dprintk(CVP_CORE, "Core released successfully\n");
  1800. mutex_unlock(&device->lock);
  1801. return rc;
  1802. }
  1803. static void __core_clear_interrupt(struct iris_hfi_device *device)
  1804. {
  1805. u32 intr_status = 0, mask = 0;
  1806. if (!device) {
  1807. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  1808. return;
  1809. }
  1810. intr_status = __read_register(device, CVP_WRAPPER_INTR_STATUS);
  1811. mask = (CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK | CVP_FATAL_INTR_BMSK);
  1812. if (intr_status & mask) {
  1813. device->intr_status |= intr_status;
  1814. device->reg_count++;
  1815. dprintk(CVP_CORE,
  1816. "INTERRUPT for device: %pK: times: %d status: %d\n",
  1817. device, device->reg_count, intr_status);
  1818. } else {
  1819. device->spur_count++;
  1820. }
  1821. __write_register(device, CVP_CPU_CS_A2HSOFTINTCLR, 1);
  1822. }
  1823. static int iris_hfi_core_trigger_ssr(void *device,
  1824. enum hal_ssr_trigger_type type)
  1825. {
  1826. struct cvp_hfi_cmd_sys_test_ssr_packet pkt;
  1827. int rc = 0;
  1828. struct iris_hfi_device *dev;
  1829. if (!device) {
  1830. dprintk(CVP_ERR, "invalid device\n");
  1831. return -ENODEV;
  1832. }
  1833. dev = device;
  1834. if (mutex_trylock(&dev->lock)) {
  1835. rc = call_hfi_pkt_op(dev, ssr_cmd, type, &pkt);
  1836. if (rc) {
  1837. dprintk(CVP_ERR, "%s: failed to create packet\n",
  1838. __func__);
  1839. goto err_create_pkt;
  1840. }
  1841. if (__iface_cmdq_write(dev, &pkt))
  1842. rc = -ENOTEMPTY;
  1843. } else {
  1844. return -EAGAIN;
  1845. }
  1846. err_create_pkt:
  1847. mutex_unlock(&dev->lock);
  1848. return rc;
  1849. }
  1850. static void __set_default_sys_properties(struct iris_hfi_device *device)
  1851. {
  1852. if (__sys_set_debug(device, msm_cvp_fw_debug))
  1853. dprintk(CVP_WARN, "Setting fw_debug msg ON failed\n");
  1854. if (__sys_set_power_control(device, msm_cvp_fw_low_power_mode))
  1855. dprintk(CVP_WARN, "Setting h/w power collapse ON failed\n");
  1856. }
  1857. static void __session_clean(struct cvp_hal_session *session)
  1858. {
  1859. struct cvp_hal_session *temp, *next;
  1860. struct iris_hfi_device *device;
  1861. if (!session || !session->device) {
  1862. dprintk(CVP_WARN, "%s: invalid params\n", __func__);
  1863. return;
  1864. }
  1865. device = session->device;
  1866. dprintk(CVP_SESS, "deleted the session: %pK\n", session);
  1867. /*
  1868. * session might have been removed from the device list in
  1869. * core_release, so check and remove if it is in the list
  1870. */
  1871. list_for_each_entry_safe(temp, next, &device->sess_head, list) {
  1872. if (session == temp) {
  1873. list_del(&session->list);
  1874. break;
  1875. }
  1876. }
  1877. /* Poison the session handle with zeros */
  1878. *session = (struct cvp_hal_session){ {0} };
  1879. kfree(session);
  1880. }
  1881. static int iris_hfi_session_clean(void *session)
  1882. {
  1883. struct cvp_hal_session *sess_close;
  1884. struct iris_hfi_device *device;
  1885. if (!session) {
  1886. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  1887. return -EINVAL;
  1888. }
  1889. sess_close = session;
  1890. device = sess_close->device;
  1891. if (!device) {
  1892. dprintk(CVP_ERR, "Invalid device handle %s\n", __func__);
  1893. return -EINVAL;
  1894. }
  1895. mutex_lock(&device->lock);
  1896. __session_clean(sess_close);
  1897. mutex_unlock(&device->lock);
  1898. return 0;
  1899. }
  1900. static int iris_hfi_session_init(void *device, void *session_id,
  1901. void **new_session)
  1902. {
  1903. struct cvp_hfi_cmd_sys_session_init_packet pkt;
  1904. struct iris_hfi_device *dev;
  1905. struct cvp_hal_session *s;
  1906. if (!device || !new_session) {
  1907. dprintk(CVP_ERR, "%s - invalid input\n", __func__);
  1908. return -EINVAL;
  1909. }
  1910. dev = device;
  1911. mutex_lock(&dev->lock);
  1912. s = kzalloc(sizeof(*s), GFP_KERNEL);
  1913. if (!s) {
  1914. dprintk(CVP_ERR, "new session fail: Out of memory\n");
  1915. goto err_session_init_fail;
  1916. }
  1917. s->session_id = session_id;
  1918. s->device = dev;
  1919. dprintk(CVP_SESS,
  1920. "%s: inst %pK, session %pK\n", __func__, session_id, s);
  1921. list_add_tail(&s->list, &dev->sess_head);
  1922. __set_default_sys_properties(device);
  1923. if (call_hfi_pkt_op(dev, session_init, &pkt, s)) {
  1924. dprintk(CVP_ERR, "session_init: failed to create packet\n");
  1925. goto err_session_init_fail;
  1926. }
  1927. *new_session = s;
  1928. if (__iface_cmdq_write(dev, &pkt))
  1929. goto err_session_init_fail;
  1930. mutex_unlock(&dev->lock);
  1931. return 0;
  1932. err_session_init_fail:
  1933. if (s)
  1934. __session_clean(s);
  1935. *new_session = NULL;
  1936. mutex_unlock(&dev->lock);
  1937. return -EINVAL;
  1938. }
  1939. static int __send_session_cmd(struct cvp_hal_session *session, int pkt_type)
  1940. {
  1941. struct cvp_hal_session_cmd_pkt pkt;
  1942. int rc = 0;
  1943. struct iris_hfi_device *device = session->device;
  1944. if (!__is_session_valid(device, session, __func__))
  1945. return -ECONNRESET;
  1946. rc = call_hfi_pkt_op(device, session_cmd,
  1947. &pkt, pkt_type, session);
  1948. if (rc == -EPERM)
  1949. return 0;
  1950. if (rc) {
  1951. dprintk(CVP_ERR, "send session cmd: create pkt failed\n");
  1952. goto err_create_pkt;
  1953. }
  1954. if (__iface_cmdq_write(session->device, &pkt))
  1955. rc = -ENOTEMPTY;
  1956. err_create_pkt:
  1957. return rc;
  1958. }
  1959. static int iris_hfi_session_end(void *session)
  1960. {
  1961. struct cvp_hal_session *sess;
  1962. struct iris_hfi_device *device;
  1963. int rc = 0;
  1964. if (!session) {
  1965. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  1966. return -EINVAL;
  1967. }
  1968. sess = session;
  1969. device = sess->device;
  1970. if (!device) {
  1971. dprintk(CVP_ERR, "Invalid session %s\n", __func__);
  1972. return -EINVAL;
  1973. }
  1974. mutex_lock(&device->lock);
  1975. if (msm_cvp_fw_coverage) {
  1976. if (__sys_set_coverage(sess->device, msm_cvp_fw_coverage))
  1977. dprintk(CVP_WARN, "Fw_coverage msg ON failed\n");
  1978. }
  1979. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_END);
  1980. mutex_unlock(&device->lock);
  1981. return rc;
  1982. }
  1983. static int iris_hfi_session_abort(void *sess)
  1984. {
  1985. struct cvp_hal_session *session = sess;
  1986. struct iris_hfi_device *device;
  1987. int rc = 0;
  1988. if (!session || !session->device) {
  1989. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  1990. return -EINVAL;
  1991. }
  1992. device = session->device;
  1993. mutex_lock(&device->lock);
  1994. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_ABORT);
  1995. mutex_unlock(&device->lock);
  1996. return rc;
  1997. }
  1998. static int iris_hfi_session_set_buffers(void *sess, u32 iova, u32 size)
  1999. {
  2000. struct cvp_hfi_cmd_session_set_buffers_packet pkt;
  2001. int rc = 0;
  2002. struct cvp_hal_session *session = sess;
  2003. struct iris_hfi_device *device;
  2004. if (!session || !session->device || !iova || !size) {
  2005. dprintk(CVP_ERR, "Invalid Params\n");
  2006. return -EINVAL;
  2007. }
  2008. device = session->device;
  2009. mutex_lock(&device->lock);
  2010. if (!__is_session_valid(device, session, __func__)) {
  2011. rc = -ECONNRESET;
  2012. goto err_create_pkt;
  2013. }
  2014. rc = call_hfi_pkt_op(device, session_set_buffers,
  2015. &pkt, session, iova, size);
  2016. if (rc) {
  2017. dprintk(CVP_ERR, "set buffers: failed to create packet\n");
  2018. goto err_create_pkt;
  2019. }
  2020. if (__iface_cmdq_write(session->device, &pkt))
  2021. rc = -ENOTEMPTY;
  2022. err_create_pkt:
  2023. mutex_unlock(&device->lock);
  2024. return rc;
  2025. }
  2026. static int iris_hfi_session_release_buffers(void *sess)
  2027. {
  2028. struct cvp_session_release_buffers_packet pkt;
  2029. int rc = 0;
  2030. struct cvp_hal_session *session = sess;
  2031. struct iris_hfi_device *device;
  2032. if (!session || !session->device) {
  2033. dprintk(CVP_ERR, "Invalid Params\n");
  2034. return -EINVAL;
  2035. }
  2036. device = session->device;
  2037. mutex_lock(&device->lock);
  2038. if (!__is_session_valid(device, session, __func__)) {
  2039. rc = -ECONNRESET;
  2040. goto err_create_pkt;
  2041. }
  2042. rc = call_hfi_pkt_op(device, session_release_buffers, &pkt, session);
  2043. if (rc) {
  2044. dprintk(CVP_ERR, "release buffers: failed to create packet\n");
  2045. goto err_create_pkt;
  2046. }
  2047. if (__iface_cmdq_write(session->device, &pkt))
  2048. rc = -ENOTEMPTY;
  2049. err_create_pkt:
  2050. mutex_unlock(&device->lock);
  2051. return rc;
  2052. }
  2053. static int iris_hfi_session_send(void *sess,
  2054. struct eva_kmd_hfi_packet *in_pkt)
  2055. {
  2056. int rc = 0;
  2057. struct eva_kmd_hfi_packet pkt;
  2058. struct cvp_hal_session *session = sess;
  2059. struct iris_hfi_device *device;
  2060. if (!session || !session->device) {
  2061. dprintk(CVP_ERR, "invalid session");
  2062. return -ENODEV;
  2063. }
  2064. device = session->device;
  2065. mutex_lock(&device->lock);
  2066. if (!__is_session_valid(device, session, __func__)) {
  2067. rc = -ECONNRESET;
  2068. goto err_send_pkt;
  2069. }
  2070. rc = call_hfi_pkt_op(device, session_send,
  2071. &pkt, session, in_pkt);
  2072. if (rc) {
  2073. dprintk(CVP_ERR,
  2074. "failed to create pkt\n");
  2075. goto err_send_pkt;
  2076. }
  2077. if (__iface_cmdq_write(session->device, &pkt))
  2078. rc = -ENOTEMPTY;
  2079. err_send_pkt:
  2080. mutex_unlock(&device->lock);
  2081. return rc;
  2082. return rc;
  2083. }
  2084. static int iris_hfi_session_flush(void *sess)
  2085. {
  2086. struct cvp_hal_session *session = sess;
  2087. struct iris_hfi_device *device;
  2088. int rc = 0;
  2089. if (!session || !session->device) {
  2090. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2091. return -EINVAL;
  2092. }
  2093. device = session->device;
  2094. mutex_lock(&device->lock);
  2095. rc = __send_session_cmd(session, HFI_CMD_SESSION_CVP_FLUSH);
  2096. mutex_unlock(&device->lock);
  2097. return rc;
  2098. }
  2099. static int __check_core_registered(struct iris_hfi_device *device,
  2100. phys_addr_t fw_addr, u8 *reg_addr, u32 reg_size,
  2101. phys_addr_t irq)
  2102. {
  2103. struct cvp_hal_data *cvp_hal_data;
  2104. if (!device) {
  2105. dprintk(CVP_INFO, "no device Registered\n");
  2106. return -EINVAL;
  2107. }
  2108. cvp_hal_data = device->cvp_hal_data;
  2109. if (!cvp_hal_data)
  2110. return -EINVAL;
  2111. if (cvp_hal_data->irq == irq &&
  2112. (CONTAINS(cvp_hal_data->firmware_base,
  2113. FIRMWARE_SIZE, fw_addr) ||
  2114. CONTAINS(fw_addr, FIRMWARE_SIZE,
  2115. cvp_hal_data->firmware_base) ||
  2116. CONTAINS(cvp_hal_data->register_base,
  2117. reg_size, reg_addr) ||
  2118. CONTAINS(reg_addr, reg_size,
  2119. cvp_hal_data->register_base) ||
  2120. OVERLAPS(cvp_hal_data->register_base,
  2121. reg_size, reg_addr, reg_size) ||
  2122. OVERLAPS(reg_addr, reg_size,
  2123. cvp_hal_data->register_base,
  2124. reg_size) ||
  2125. OVERLAPS(cvp_hal_data->firmware_base,
  2126. FIRMWARE_SIZE, fw_addr,
  2127. FIRMWARE_SIZE) ||
  2128. OVERLAPS(fw_addr, FIRMWARE_SIZE,
  2129. cvp_hal_data->firmware_base,
  2130. FIRMWARE_SIZE))) {
  2131. return 0;
  2132. }
  2133. dprintk(CVP_INFO, "Device not registered\n");
  2134. return -EINVAL;
  2135. }
  2136. static void __process_fatal_error(
  2137. struct iris_hfi_device *device)
  2138. {
  2139. struct msm_cvp_cb_cmd_done cmd_done = {0};
  2140. cmd_done.device_id = device->device_id;
  2141. device->callback(HAL_SYS_ERROR, &cmd_done);
  2142. }
  2143. static int __prepare_pc(struct iris_hfi_device *device)
  2144. {
  2145. int rc = 0;
  2146. struct cvp_hfi_cmd_sys_pc_prep_packet pkt;
  2147. rc = call_hfi_pkt_op(device, sys_pc_prep, &pkt);
  2148. if (rc) {
  2149. dprintk(CVP_ERR, "Failed to create sys pc prep pkt\n");
  2150. goto err_pc_prep;
  2151. }
  2152. if (__iface_cmdq_write(device, &pkt))
  2153. rc = -ENOTEMPTY;
  2154. if (rc)
  2155. dprintk(CVP_ERR, "Failed to prepare iris for power off");
  2156. err_pc_prep:
  2157. return rc;
  2158. }
  2159. static void iris_hfi_pm_handler(struct work_struct *work)
  2160. {
  2161. int rc = 0;
  2162. struct msm_cvp_core *core;
  2163. struct iris_hfi_device *device;
  2164. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  2165. if (core)
  2166. device = core->device->hfi_device_data;
  2167. else
  2168. return;
  2169. if (!device) {
  2170. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2171. return;
  2172. }
  2173. dprintk(CVP_PWR,
  2174. "Entering %s\n", __func__);
  2175. /*
  2176. * It is ok to check this variable outside the lock since
  2177. * it is being updated in this context only
  2178. */
  2179. if (device->skip_pc_count >= CVP_MAX_PC_SKIP_COUNT) {
  2180. dprintk(CVP_WARN, "Failed to PC for %d times\n",
  2181. device->skip_pc_count);
  2182. device->skip_pc_count = 0;
  2183. __process_fatal_error(device);
  2184. return;
  2185. }
  2186. mutex_lock(&device->lock);
  2187. if (gfa_cv.state == DSP_SUSPEND)
  2188. rc = __power_collapse(device, true);
  2189. else
  2190. rc = __power_collapse(device, false);
  2191. mutex_unlock(&device->lock);
  2192. switch (rc) {
  2193. case 0:
  2194. device->skip_pc_count = 0;
  2195. /* Cancel pending delayed works if any */
  2196. cancel_delayed_work(&iris_hfi_pm_work);
  2197. dprintk(CVP_PWR, "%s: power collapse successful!\n",
  2198. __func__);
  2199. break;
  2200. case -EBUSY:
  2201. device->skip_pc_count = 0;
  2202. dprintk(CVP_PWR, "%s: retry PC as cvp is busy\n", __func__);
  2203. queue_delayed_work(device->iris_pm_workq,
  2204. &iris_hfi_pm_work, msecs_to_jiffies(
  2205. device->res->msm_cvp_pwr_collapse_delay));
  2206. break;
  2207. case -EAGAIN:
  2208. device->skip_pc_count++;
  2209. dprintk(CVP_WARN, "%s: retry power collapse (count %d)\n",
  2210. __func__, device->skip_pc_count);
  2211. queue_delayed_work(device->iris_pm_workq,
  2212. &iris_hfi_pm_work, msecs_to_jiffies(
  2213. device->res->msm_cvp_pwr_collapse_delay));
  2214. break;
  2215. default:
  2216. dprintk(CVP_ERR, "%s: power collapse failed\n", __func__);
  2217. break;
  2218. }
  2219. }
  2220. static int __power_collapse(struct iris_hfi_device *device, bool force)
  2221. {
  2222. int rc = 0;
  2223. u32 wfi_status = 0, idle_status = 0, pc_ready = 0;
  2224. u32 flags = 0;
  2225. int count = 0;
  2226. const int max_tries = 150;
  2227. if (!device) {
  2228. dprintk(CVP_ERR, "%s: invalid params\n", __func__);
  2229. return -EINVAL;
  2230. }
  2231. if (!device->power_enabled) {
  2232. dprintk(CVP_PWR, "%s: Power already disabled\n",
  2233. __func__);
  2234. goto exit;
  2235. }
  2236. rc = __core_in_valid_state(device);
  2237. if (!rc) {
  2238. dprintk(CVP_WARN,
  2239. "Core is in bad state, Skipping power collapse\n");
  2240. return -EINVAL;
  2241. }
  2242. rc = __dsp_suspend(device, force, flags);
  2243. if (rc == -EBUSY)
  2244. goto exit;
  2245. else if (rc)
  2246. goto skip_power_off;
  2247. pc_ready = __read_register(device, CVP_CTRL_STATUS) &
  2248. CVP_CTRL_STATUS_PC_READY;
  2249. if (!pc_ready) {
  2250. wfi_status = __read_register(device,
  2251. CVP_WRAPPER_CPU_STATUS);
  2252. idle_status = __read_register(device,
  2253. CVP_CTRL_STATUS);
  2254. if (!(wfi_status & BIT(0))) {
  2255. dprintk(CVP_WARN,
  2256. "Skipping PC as wfi_status (%#x) bit not set\n",
  2257. wfi_status);
  2258. goto skip_power_off;
  2259. }
  2260. if (!(idle_status & BIT(30))) {
  2261. dprintk(CVP_WARN,
  2262. "Skipping PC as idle_status (%#x) bit not set\n",
  2263. idle_status);
  2264. goto skip_power_off;
  2265. }
  2266. rc = __prepare_pc(device);
  2267. if (rc) {
  2268. dprintk(CVP_WARN, "Failed PC %d\n", rc);
  2269. goto skip_power_off;
  2270. }
  2271. while (count < max_tries) {
  2272. wfi_status = __read_register(device,
  2273. CVP_WRAPPER_CPU_STATUS);
  2274. pc_ready = __read_register(device,
  2275. CVP_CTRL_STATUS);
  2276. if ((wfi_status & BIT(0)) && (pc_ready &
  2277. CVP_CTRL_STATUS_PC_READY))
  2278. break;
  2279. usleep_range(150, 250);
  2280. count++;
  2281. }
  2282. if (count == max_tries) {
  2283. dprintk(CVP_ERR,
  2284. "Skip PC. Core is not in right state (%#x, %#x)\n",
  2285. wfi_status, pc_ready);
  2286. goto skip_power_off;
  2287. }
  2288. }
  2289. __flush_debug_queue(device, device->raw_packet);
  2290. rc = __suspend(device);
  2291. if (rc)
  2292. dprintk(CVP_ERR, "Failed __suspend\n");
  2293. exit:
  2294. return rc;
  2295. skip_power_off:
  2296. dprintk(CVP_PWR, "Skip PC(%#x, %#x, %#x)\n",
  2297. wfi_status, idle_status, pc_ready);
  2298. __flush_debug_queue(device, device->raw_packet);
  2299. return -EAGAIN;
  2300. }
  2301. static void __process_sys_error(struct iris_hfi_device *device)
  2302. {
  2303. struct cvp_hfi_sfr_struct *vsfr = NULL;
  2304. vsfr = (struct cvp_hfi_sfr_struct *)device->sfr.align_virtual_addr;
  2305. if (vsfr) {
  2306. void *p = memchr(vsfr->rg_data, '\0', vsfr->bufSize);
  2307. /*
  2308. * SFR isn't guaranteed to be NULL terminated
  2309. * since SYS_ERROR indicates that Iris is in the
  2310. * process of crashing.
  2311. */
  2312. if (p == NULL)
  2313. vsfr->rg_data[vsfr->bufSize - 1] = '\0';
  2314. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2315. vsfr->rg_data);
  2316. }
  2317. }
  2318. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet)
  2319. {
  2320. bool local_packet = false;
  2321. enum cvp_msg_prio log_level = CVP_FW;
  2322. if (!device) {
  2323. dprintk(CVP_ERR, "%s: Invalid params\n", __func__);
  2324. return;
  2325. }
  2326. if (!packet) {
  2327. packet = kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  2328. if (!packet) {
  2329. dprintk(CVP_ERR, "In %s() Fail to allocate mem\n",
  2330. __func__);
  2331. return;
  2332. }
  2333. local_packet = true;
  2334. /*
  2335. * Local packek is used when something FATAL occurred.
  2336. * It is good to print these logs by default.
  2337. */
  2338. log_level = CVP_ERR;
  2339. }
  2340. #define SKIP_INVALID_PKT(pkt_size, payload_size, pkt_hdr_size) ({ \
  2341. if (pkt_size < pkt_hdr_size || \
  2342. payload_size < MIN_PAYLOAD_SIZE || \
  2343. payload_size > \
  2344. (pkt_size - pkt_hdr_size + sizeof(u8))) { \
  2345. dprintk(CVP_ERR, \
  2346. "%s: invalid msg size - %d\n", \
  2347. __func__, pkt->msg_size); \
  2348. continue; \
  2349. } \
  2350. })
  2351. while (!__iface_dbgq_read(device, packet)) {
  2352. struct cvp_hfi_packet_header *pkt =
  2353. (struct cvp_hfi_packet_header *) packet;
  2354. if (pkt->size < sizeof(struct cvp_hfi_packet_header)) {
  2355. dprintk(CVP_ERR, "Invalid pkt size - %s\n",
  2356. __func__);
  2357. continue;
  2358. }
  2359. if (pkt->packet_type == HFI_MSG_SYS_DEBUG) {
  2360. struct cvp_hfi_msg_sys_debug_packet *pkt =
  2361. (struct cvp_hfi_msg_sys_debug_packet *) packet;
  2362. SKIP_INVALID_PKT(pkt->size,
  2363. pkt->msg_size, sizeof(*pkt));
  2364. /*
  2365. * All fw messages starts with new line character. This
  2366. * causes dprintk to print this message in two lines
  2367. * in the kernel log. Ignoring the first character
  2368. * from the message fixes this to print it in a single
  2369. * line.
  2370. */
  2371. pkt->rg_msg_data[pkt->msg_size-1] = '\0';
  2372. dprintk(log_level, "%s", &pkt->rg_msg_data[1]);
  2373. }
  2374. }
  2375. #undef SKIP_INVALID_PKT
  2376. if (local_packet)
  2377. kfree(packet);
  2378. }
  2379. static bool __is_session_valid(struct iris_hfi_device *device,
  2380. struct cvp_hal_session *session, const char *func)
  2381. {
  2382. struct cvp_hal_session *temp = NULL;
  2383. if (!device || !session)
  2384. goto invalid;
  2385. list_for_each_entry(temp, &device->sess_head, list)
  2386. if (session == temp)
  2387. return true;
  2388. invalid:
  2389. dprintk(CVP_WARN, "%s: device %pK, invalid session %pK\n",
  2390. func, device, session);
  2391. return false;
  2392. }
  2393. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  2394. u32 session_id)
  2395. {
  2396. struct cvp_hal_session *temp = NULL;
  2397. list_for_each_entry(temp, &device->sess_head, list) {
  2398. if (session_id == hash32_ptr(temp))
  2399. return temp;
  2400. }
  2401. return NULL;
  2402. }
  2403. #define _INVALID_MSG_ "Unrecognized MSG (%#x) session (%pK), discarding\n"
  2404. #define _INVALID_STATE_ "Ignore responses from %d to %d invalid state\n"
  2405. #define _DEVFREQ_FAIL_ "Failed to add devfreq device bus %s governor %s: %d\n"
  2406. static void process_system_msg(struct msm_cvp_cb_info *info,
  2407. struct iris_hfi_device *device,
  2408. void *raw_packet)
  2409. {
  2410. struct cvp_hal_sys_init_done sys_init_done = {0};
  2411. switch (info->response_type) {
  2412. case HAL_SYS_ERROR:
  2413. __process_sys_error(device);
  2414. break;
  2415. case HAL_SYS_RELEASE_RESOURCE_DONE:
  2416. dprintk(CVP_CORE, "Received SYS_RELEASE_RESOURCE\n");
  2417. break;
  2418. case HAL_SYS_INIT_DONE:
  2419. dprintk(CVP_CORE, "Received SYS_INIT_DONE\n");
  2420. sys_init_done.capabilities =
  2421. device->sys_init_capabilities;
  2422. cvp_hfi_process_sys_init_done_prop_read(
  2423. (struct cvp_hfi_msg_sys_init_done_packet *)
  2424. raw_packet, &sys_init_done);
  2425. info->response.cmd.data.sys_init_done = sys_init_done;
  2426. break;
  2427. default:
  2428. break;
  2429. }
  2430. }
  2431. static void **get_session_id(struct msm_cvp_cb_info *info)
  2432. {
  2433. void **session_id = NULL;
  2434. /* For session-related packets, validate session */
  2435. switch (info->response_type) {
  2436. case HAL_SESSION_INIT_DONE:
  2437. case HAL_SESSION_END_DONE:
  2438. case HAL_SESSION_ABORT_DONE:
  2439. case HAL_SESSION_STOP_DONE:
  2440. case HAL_SESSION_FLUSH_DONE:
  2441. case HAL_SESSION_SET_BUFFER_DONE:
  2442. case HAL_SESSION_SUSPEND_DONE:
  2443. case HAL_SESSION_RESUME_DONE:
  2444. case HAL_SESSION_SET_PROP_DONE:
  2445. case HAL_SESSION_GET_PROP_DONE:
  2446. case HAL_SESSION_RELEASE_BUFFER_DONE:
  2447. case HAL_SESSION_REGISTER_BUFFER_DONE:
  2448. case HAL_SESSION_UNREGISTER_BUFFER_DONE:
  2449. case HAL_SESSION_DFS_CONFIG_CMD_DONE:
  2450. case HAL_SESSION_DME_CONFIG_CMD_DONE:
  2451. case HAL_SESSION_TME_CONFIG_CMD_DONE:
  2452. case HAL_SESSION_ODT_CONFIG_CMD_DONE:
  2453. case HAL_SESSION_OD_CONFIG_CMD_DONE:
  2454. case HAL_SESSION_NCC_CONFIG_CMD_DONE:
  2455. case HAL_SESSION_ICA_CONFIG_CMD_DONE:
  2456. case HAL_SESSION_HCD_CONFIG_CMD_DONE:
  2457. case HAL_SESSION_DCM_CONFIG_CMD_DONE:
  2458. case HAL_SESSION_DC_CONFIG_CMD_DONE:
  2459. case HAL_SESSION_PYS_HCD_CONFIG_CMD_DONE:
  2460. case HAL_SESSION_DME_BASIC_CONFIG_CMD_DONE:
  2461. case HAL_SESSION_DFS_FRAME_CMD_DONE:
  2462. case HAL_SESSION_DME_FRAME_CMD_DONE:
  2463. case HAL_SESSION_ICA_FRAME_CMD_DONE:
  2464. case HAL_SESSION_FD_FRAME_CMD_DONE:
  2465. case HAL_SESSION_PERSIST_SET_DONE:
  2466. case HAL_SESSION_PERSIST_REL_DONE:
  2467. case HAL_SESSION_FD_CONFIG_CMD_DONE:
  2468. case HAL_SESSION_MODEL_BUF_CMD_DONE:
  2469. case HAL_SESSION_PROPERTY_INFO:
  2470. case HAL_SESSION_EVENT_CHANGE:
  2471. session_id = &info->response.cmd.session_id;
  2472. break;
  2473. case HAL_SESSION_ERROR:
  2474. session_id = &info->response.data.session_id;
  2475. break;
  2476. case HAL_RESPONSE_UNUSED:
  2477. default:
  2478. session_id = NULL;
  2479. break;
  2480. }
  2481. return session_id;
  2482. }
  2483. static void print_msg_hdr(void *hdr)
  2484. {
  2485. struct cvp_hfi_msg_session_hdr *new_hdr =
  2486. (struct cvp_hfi_msg_session_hdr *)hdr;
  2487. dprintk(CVP_HFI, "HFI MSG received: %x %x %x %x %x %x %x\n",
  2488. new_hdr->size, new_hdr->packet_type,
  2489. new_hdr->session_id,
  2490. new_hdr->client_data.transaction_id,
  2491. new_hdr->client_data.data1,
  2492. new_hdr->client_data.data2,
  2493. new_hdr->error_type);
  2494. }
  2495. static int __response_handler(struct iris_hfi_device *device)
  2496. {
  2497. struct msm_cvp_cb_info *packets;
  2498. int packet_count = 0;
  2499. u8 *raw_packet = NULL;
  2500. bool requeue_pm_work = true;
  2501. if (!device || device->state != IRIS_STATE_INIT)
  2502. return 0;
  2503. packets = device->response_pkt;
  2504. raw_packet = device->raw_packet;
  2505. if (!raw_packet || !packets) {
  2506. dprintk(CVP_ERR,
  2507. "%s: Invalid args : Res packet = %p, Raw packet = %p\n",
  2508. __func__, packets, raw_packet);
  2509. return 0;
  2510. }
  2511. if (device->intr_status & CVP_FATAL_INTR_BMSK) {
  2512. struct cvp_hfi_sfr_struct *vsfr = (struct cvp_hfi_sfr_struct *)
  2513. device->sfr.align_virtual_addr;
  2514. struct msm_cvp_cb_info info = {
  2515. .response_type = HAL_SYS_WATCHDOG_TIMEOUT,
  2516. .response.cmd = {
  2517. .device_id = device->device_id,
  2518. }
  2519. };
  2520. if (vsfr)
  2521. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2522. vsfr->rg_data);
  2523. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CPU_NOC_BMSK)
  2524. dprintk(CVP_ERR, "Received Xtensa NOC error\n");
  2525. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CORE_NOC_BMSK)
  2526. dprintk(CVP_ERR, "Received CVP core NOC error\n");
  2527. if (device->intr_status & CVP_WRAPPER_INTR_MASK_A2HWD_BMSK)
  2528. dprintk(CVP_ERR, "Received CVP watchdog timeout\n");
  2529. packets[packet_count++] = info;
  2530. goto exit;
  2531. }
  2532. /* Bleed the msg queue dry of packets */
  2533. while (!__iface_msgq_read(device, raw_packet)) {
  2534. void **session_id = NULL;
  2535. struct msm_cvp_cb_info *info = &packets[packet_count++];
  2536. struct cvp_hfi_msg_session_hdr *hdr =
  2537. (struct cvp_hfi_msg_session_hdr *)raw_packet;
  2538. int rc = 0;
  2539. print_msg_hdr(hdr);
  2540. rc = cvp_hfi_process_msg_packet(device->device_id,
  2541. raw_packet, info);
  2542. if (rc) {
  2543. dprintk(CVP_WARN,
  2544. "Corrupt/unknown packet found, discarding\n");
  2545. --packet_count;
  2546. continue;
  2547. } else if (info->response_type == HAL_NO_RESP) {
  2548. --packet_count;
  2549. continue;
  2550. }
  2551. /* Process the packet types that we're interested in */
  2552. process_system_msg(info, device, raw_packet);
  2553. session_id = get_session_id(info);
  2554. /*
  2555. * hfi_process_msg_packet provides a session_id that's a hashed
  2556. * value of struct cvp_hal_session, we need to coerce the hashed
  2557. * value back to pointer that we can use. Ideally, hfi_process\
  2558. * _msg_packet should take care of this, but it doesn't have
  2559. * required information for it
  2560. */
  2561. if (session_id) {
  2562. struct cvp_hal_session *session = NULL;
  2563. if (upper_32_bits((uintptr_t)*session_id) != 0) {
  2564. dprintk(CVP_ERR,
  2565. "Upper 32-bits != 0 for sess_id=%pK\n",
  2566. *session_id);
  2567. }
  2568. session = __get_session(device,
  2569. (u32)(uintptr_t)*session_id);
  2570. if (!session) {
  2571. dprintk(CVP_ERR, _INVALID_MSG_,
  2572. info->response_type,
  2573. *session_id);
  2574. --packet_count;
  2575. continue;
  2576. }
  2577. *session_id = session->session_id;
  2578. }
  2579. if (packet_count >= cvp_max_packets) {
  2580. dprintk(CVP_WARN,
  2581. "Too many packets in message queue!\n");
  2582. break;
  2583. }
  2584. /* do not read packets after sys error packet */
  2585. if (info->response_type == HAL_SYS_ERROR)
  2586. break;
  2587. }
  2588. if (requeue_pm_work && device->res->sw_power_collapsible) {
  2589. cancel_delayed_work(&iris_hfi_pm_work);
  2590. if (!queue_delayed_work(device->iris_pm_workq,
  2591. &iris_hfi_pm_work,
  2592. msecs_to_jiffies(
  2593. device->res->msm_cvp_pwr_collapse_delay))) {
  2594. dprintk(CVP_ERR, "PM work already scheduled\n");
  2595. }
  2596. }
  2597. exit:
  2598. __flush_debug_queue(device, raw_packet);
  2599. return packet_count;
  2600. }
  2601. static void iris_hfi_core_work_handler(struct work_struct *work)
  2602. {
  2603. struct msm_cvp_core *core;
  2604. struct iris_hfi_device *device;
  2605. int num_responses = 0, i = 0;
  2606. u32 intr_status;
  2607. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  2608. if (core)
  2609. device = core->device->hfi_device_data;
  2610. else
  2611. return;
  2612. mutex_lock(&device->lock);
  2613. if (!__core_in_valid_state(device)) {
  2614. dprintk(CVP_WARN, "%s - Core not in init state\n", __func__);
  2615. goto err_no_work;
  2616. }
  2617. if (!device->callback) {
  2618. dprintk(CVP_ERR, "No interrupt callback function: %pK\n",
  2619. device);
  2620. goto err_no_work;
  2621. }
  2622. if (__resume(device)) {
  2623. dprintk(CVP_ERR, "%s: Power enable failed\n", __func__);
  2624. goto err_no_work;
  2625. }
  2626. __core_clear_interrupt(device);
  2627. num_responses = __response_handler(device);
  2628. dprintk(CVP_HFI, "%s:: cvp_driver_debug num_responses = %d ",
  2629. __func__, num_responses);
  2630. err_no_work:
  2631. /* Keep the interrupt status before releasing device lock */
  2632. intr_status = device->intr_status;
  2633. mutex_unlock(&device->lock);
  2634. /*
  2635. * Issue the callbacks outside of the locked contex to preserve
  2636. * re-entrancy.
  2637. */
  2638. for (i = 0; !IS_ERR_OR_NULL(device->response_pkt) &&
  2639. i < num_responses; ++i) {
  2640. struct msm_cvp_cb_info *r = &device->response_pkt[i];
  2641. void *rsp = (void *)&r->response;
  2642. if (!__core_in_valid_state(device)) {
  2643. dprintk(CVP_ERR,
  2644. _INVALID_STATE_, (i + 1), num_responses);
  2645. break;
  2646. }
  2647. dprintk(CVP_HFI, "Processing response %d of %d, type %d\n",
  2648. (i + 1), num_responses, r->response_type);
  2649. device->callback(r->response_type, rsp);
  2650. }
  2651. /* We need re-enable the irq which was disabled in ISR handler */
  2652. if (!(intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  2653. enable_irq(device->cvp_hal_data->irq);
  2654. /*
  2655. * XXX: Don't add any code beyond here. Reacquiring locks after release
  2656. * it above doesn't guarantee the atomicity that we're aiming for.
  2657. */
  2658. }
  2659. static DECLARE_WORK(iris_hfi_work, iris_hfi_core_work_handler);
  2660. static irqreturn_t iris_hfi_isr(int irq, void *dev)
  2661. {
  2662. struct iris_hfi_device *device = dev;
  2663. disable_irq_nosync(irq);
  2664. queue_work(device->cvp_workq, &iris_hfi_work);
  2665. return IRQ_HANDLED;
  2666. }
  2667. static int __init_regs_and_interrupts(struct iris_hfi_device *device,
  2668. struct msm_cvp_platform_resources *res)
  2669. {
  2670. struct cvp_hal_data *hal = NULL;
  2671. int rc = 0;
  2672. rc = __check_core_registered(device, res->firmware_base,
  2673. (u8 *)(uintptr_t)res->register_base,
  2674. res->register_size, res->irq);
  2675. if (!rc) {
  2676. dprintk(CVP_ERR, "Core present/Already added\n");
  2677. rc = -EEXIST;
  2678. goto err_core_init;
  2679. }
  2680. hal = kzalloc(sizeof(*hal), GFP_KERNEL);
  2681. if (!hal) {
  2682. dprintk(CVP_ERR, "Failed to alloc\n");
  2683. rc = -ENOMEM;
  2684. goto err_core_init;
  2685. }
  2686. hal->irq = res->irq;
  2687. hal->firmware_base = res->firmware_base;
  2688. hal->register_base = devm_ioremap(&res->pdev->dev,
  2689. res->register_base, res->register_size);
  2690. hal->register_size = res->register_size;
  2691. if (!hal->register_base) {
  2692. dprintk(CVP_ERR,
  2693. "could not map reg addr %pa of size %d\n",
  2694. &res->register_base, res->register_size);
  2695. goto error_irq_fail;
  2696. }
  2697. device->cvp_hal_data = hal;
  2698. rc = request_irq(res->irq, iris_hfi_isr, IRQF_TRIGGER_HIGH,
  2699. "msm_cvp", device);
  2700. if (unlikely(rc)) {
  2701. dprintk(CVP_ERR, "() :request_irq failed\n");
  2702. goto error_irq_fail;
  2703. }
  2704. disable_irq_nosync(res->irq);
  2705. dprintk(CVP_INFO,
  2706. "firmware_base = %pa, register_base = %pa, register_size = %d\n",
  2707. &res->firmware_base, &res->register_base,
  2708. res->register_size);
  2709. return rc;
  2710. error_irq_fail:
  2711. kfree(hal);
  2712. err_core_init:
  2713. return rc;
  2714. }
  2715. static inline void __deinit_clocks(struct iris_hfi_device *device)
  2716. {
  2717. struct clock_info *cl;
  2718. device->clk_freq = 0;
  2719. iris_hfi_for_each_clock_reverse(device, cl) {
  2720. if (cl->clk) {
  2721. clk_put(cl->clk);
  2722. cl->clk = NULL;
  2723. }
  2724. }
  2725. }
  2726. static inline int __init_clocks(struct iris_hfi_device *device)
  2727. {
  2728. int rc = 0;
  2729. struct clock_info *cl = NULL;
  2730. if (!device) {
  2731. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  2732. return -EINVAL;
  2733. }
  2734. iris_hfi_for_each_clock(device, cl) {
  2735. dprintk(CVP_PWR, "%s: scalable? %d, count %d\n",
  2736. cl->name, cl->has_scaling, cl->count);
  2737. }
  2738. iris_hfi_for_each_clock(device, cl) {
  2739. if (!cl->clk) {
  2740. cl->clk = clk_get(&device->res->pdev->dev, cl->name);
  2741. if (IS_ERR_OR_NULL(cl->clk)) {
  2742. dprintk(CVP_ERR,
  2743. "Failed to get clock: %s\n", cl->name);
  2744. rc = PTR_ERR(cl->clk) ?: -EINVAL;
  2745. cl->clk = NULL;
  2746. goto err_clk_get;
  2747. }
  2748. }
  2749. }
  2750. device->clk_freq = 0;
  2751. return 0;
  2752. err_clk_get:
  2753. __deinit_clocks(device);
  2754. return rc;
  2755. }
  2756. static int __handle_reset_clk(struct msm_cvp_platform_resources *res,
  2757. int reset_index, enum reset_state state,
  2758. enum power_state pwr_state)
  2759. {
  2760. int rc = 0;
  2761. struct reset_control *rst;
  2762. struct reset_info rst_info;
  2763. struct reset_set *rst_set = &res->reset_set;
  2764. if (!rst_set->reset_tbl)
  2765. return 0;
  2766. rst_info = rst_set->reset_tbl[reset_index];
  2767. rst = rst_info.rst;
  2768. dprintk(CVP_PWR, "reset_clk: name %s reset_state %d rst %pK ps=%d\n",
  2769. rst_set->reset_tbl[reset_index].name, state, rst, pwr_state);
  2770. switch (state) {
  2771. case INIT:
  2772. if (rst)
  2773. goto skip_reset_init;
  2774. rst = devm_reset_control_get(&res->pdev->dev,
  2775. rst_set->reset_tbl[reset_index].name);
  2776. if (IS_ERR(rst))
  2777. rc = PTR_ERR(rst);
  2778. rst_set->reset_tbl[reset_index].rst = rst;
  2779. break;
  2780. case ASSERT:
  2781. if (!rst) {
  2782. rc = PTR_ERR(rst);
  2783. goto failed_to_reset;
  2784. }
  2785. if (pwr_state != rst_info.required_state)
  2786. break;
  2787. rc = reset_control_assert(rst);
  2788. break;
  2789. case DEASSERT:
  2790. if (!rst) {
  2791. rc = PTR_ERR(rst);
  2792. goto failed_to_reset;
  2793. }
  2794. if (pwr_state != rst_info.required_state)
  2795. break;
  2796. rc = reset_control_deassert(rst);
  2797. break;
  2798. default:
  2799. dprintk(CVP_ERR, "Invalid reset request\n");
  2800. if (rc)
  2801. goto failed_to_reset;
  2802. }
  2803. return 0;
  2804. skip_reset_init:
  2805. failed_to_reset:
  2806. return rc;
  2807. }
  2808. static inline void __disable_unprepare_clks(struct iris_hfi_device *device)
  2809. {
  2810. struct clock_info *cl;
  2811. if (!device) {
  2812. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  2813. return;
  2814. }
  2815. iris_hfi_for_each_clock_reverse(device, cl) {
  2816. dprintk(CVP_PWR, "Clock: %s disable and unprepare\n",
  2817. cl->name);
  2818. clk_disable_unprepare(cl->clk);
  2819. }
  2820. }
  2821. static int reset_ahb2axi_bridge(struct iris_hfi_device *device)
  2822. {
  2823. int rc, i;
  2824. enum power_state s;
  2825. if (!device) {
  2826. dprintk(CVP_ERR, "NULL device\n");
  2827. rc = -EINVAL;
  2828. goto failed_to_reset;
  2829. }
  2830. if (device->power_enabled)
  2831. s = CVP_POWER_ON;
  2832. else
  2833. s = CVP_POWER_OFF;
  2834. for (i = 0; i < device->res->reset_set.count; i++) {
  2835. rc = __handle_reset_clk(device->res, i, ASSERT, s);
  2836. if (rc) {
  2837. dprintk(CVP_ERR,
  2838. "failed to assert reset clocks\n");
  2839. goto failed_to_reset;
  2840. }
  2841. /* wait for deassert */
  2842. usleep_range(1000, 1050);
  2843. rc = __handle_reset_clk(device->res, i, DEASSERT, s);
  2844. if (rc) {
  2845. dprintk(CVP_ERR,
  2846. "failed to deassert reset clocks\n");
  2847. goto failed_to_reset;
  2848. }
  2849. }
  2850. return 0;
  2851. failed_to_reset:
  2852. return rc;
  2853. }
  2854. static inline int __prepare_enable_clks(struct iris_hfi_device *device)
  2855. {
  2856. struct clock_info *cl = NULL, *cl_fail = NULL;
  2857. int rc = 0, c = 0;
  2858. if (!device) {
  2859. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  2860. return -EINVAL;
  2861. }
  2862. iris_hfi_for_each_clock(device, cl) {
  2863. /*
  2864. * For the clocks we control, set the rate prior to preparing
  2865. * them. Since we don't really have a load at this point, scale
  2866. * it to the lowest frequency possible
  2867. */
  2868. if (cl->has_scaling)
  2869. clk_set_rate(cl->clk, clk_round_rate(cl->clk, 0));
  2870. rc = clk_prepare_enable(cl->clk);
  2871. if (rc) {
  2872. dprintk(CVP_ERR, "Failed to enable clocks\n");
  2873. cl_fail = cl;
  2874. goto fail_clk_enable;
  2875. }
  2876. c++;
  2877. dprintk(CVP_PWR, "Clock: %s prepared and enabled\n", cl->name);
  2878. }
  2879. return rc;
  2880. fail_clk_enable:
  2881. iris_hfi_for_each_clock_reverse_continue(device, cl, c) {
  2882. dprintk(CVP_ERR, "Clock: %s disable and unprepare\n",
  2883. cl->name);
  2884. clk_disable_unprepare(cl->clk);
  2885. }
  2886. return rc;
  2887. }
  2888. static void __deinit_bus(struct iris_hfi_device *device)
  2889. {
  2890. struct bus_info *bus = NULL;
  2891. if (!device)
  2892. return;
  2893. kfree(device->bus_vote.data);
  2894. device->bus_vote = CVP_DEFAULT_BUS_VOTE;
  2895. iris_hfi_for_each_bus_reverse(device, bus) {
  2896. dev_set_drvdata(bus->dev, NULL);
  2897. icc_put(bus->client);
  2898. bus->client = NULL;
  2899. }
  2900. }
  2901. static int __init_bus(struct iris_hfi_device *device)
  2902. {
  2903. struct bus_info *bus = NULL;
  2904. int rc = 0;
  2905. if (!device)
  2906. return -EINVAL;
  2907. iris_hfi_for_each_bus(device, bus) {
  2908. /*
  2909. * This is stupid, but there's no other easy way to ahold
  2910. * of struct bus_info in iris_hfi_devfreq_*()
  2911. */
  2912. WARN(dev_get_drvdata(bus->dev), "%s's drvdata already set\n",
  2913. dev_name(bus->dev));
  2914. dev_set_drvdata(bus->dev, device);
  2915. bus->client = icc_get(&device->res->pdev->dev,
  2916. bus->master, bus->slave);
  2917. if (IS_ERR_OR_NULL(bus->client)) {
  2918. rc = PTR_ERR(bus->client) ?: -EBADHANDLE;
  2919. dprintk(CVP_ERR, "Failed to register bus %s: %d\n",
  2920. bus->name, rc);
  2921. bus->client = NULL;
  2922. goto err_add_dev;
  2923. }
  2924. }
  2925. return 0;
  2926. err_add_dev:
  2927. __deinit_bus(device);
  2928. return rc;
  2929. }
  2930. static void __deinit_regulators(struct iris_hfi_device *device)
  2931. {
  2932. struct regulator_info *rinfo = NULL;
  2933. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  2934. if (rinfo->regulator) {
  2935. regulator_put(rinfo->regulator);
  2936. rinfo->regulator = NULL;
  2937. }
  2938. }
  2939. }
  2940. static int __init_regulators(struct iris_hfi_device *device)
  2941. {
  2942. int rc = 0;
  2943. struct regulator_info *rinfo = NULL;
  2944. iris_hfi_for_each_regulator(device, rinfo) {
  2945. rinfo->regulator = regulator_get(&device->res->pdev->dev,
  2946. rinfo->name);
  2947. if (IS_ERR_OR_NULL(rinfo->regulator)) {
  2948. rc = PTR_ERR(rinfo->regulator) ?: -EBADHANDLE;
  2949. dprintk(CVP_ERR, "Failed to get regulator: %s\n",
  2950. rinfo->name);
  2951. rinfo->regulator = NULL;
  2952. goto err_reg_get;
  2953. }
  2954. }
  2955. return 0;
  2956. err_reg_get:
  2957. __deinit_regulators(device);
  2958. return rc;
  2959. }
  2960. static void __deinit_subcaches(struct iris_hfi_device *device)
  2961. {
  2962. struct subcache_info *sinfo = NULL;
  2963. if (!device) {
  2964. dprintk(CVP_ERR, "deinit_subcaches: invalid device %pK\n",
  2965. device);
  2966. goto exit;
  2967. }
  2968. if (!is_sys_cache_present(device))
  2969. goto exit;
  2970. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  2971. if (sinfo->subcache) {
  2972. dprintk(CVP_CORE, "deinit_subcaches: %s\n",
  2973. sinfo->name);
  2974. llcc_slice_putd(sinfo->subcache);
  2975. sinfo->subcache = NULL;
  2976. }
  2977. }
  2978. exit:
  2979. return;
  2980. }
  2981. static int __init_subcaches(struct iris_hfi_device *device)
  2982. {
  2983. int rc = 0;
  2984. struct subcache_info *sinfo = NULL;
  2985. if (!device) {
  2986. dprintk(CVP_ERR, "init_subcaches: invalid device %pK\n",
  2987. device);
  2988. return -EINVAL;
  2989. }
  2990. if (!is_sys_cache_present(device))
  2991. return 0;
  2992. iris_hfi_for_each_subcache(device, sinfo) {
  2993. if (!strcmp("cvp", sinfo->name)) {
  2994. sinfo->subcache = llcc_slice_getd(LLCC_CVP);
  2995. } else if (!strcmp("cvpfw", sinfo->name)) {
  2996. sinfo->subcache = llcc_slice_getd(LLCC_CVPFW);
  2997. } else {
  2998. dprintk(CVP_ERR, "Invalid subcache name %s\n",
  2999. sinfo->name);
  3000. }
  3001. if (IS_ERR_OR_NULL(sinfo->subcache)) {
  3002. rc = PTR_ERR(sinfo->subcache) ?
  3003. PTR_ERR(sinfo->subcache) : -EBADHANDLE;
  3004. dprintk(CVP_ERR,
  3005. "init_subcaches: invalid subcache: %s rc %d\n",
  3006. sinfo->name, rc);
  3007. sinfo->subcache = NULL;
  3008. goto err_subcache_get;
  3009. }
  3010. dprintk(CVP_CORE, "init_subcaches: %s\n",
  3011. sinfo->name);
  3012. }
  3013. return 0;
  3014. err_subcache_get:
  3015. __deinit_subcaches(device);
  3016. return rc;
  3017. }
  3018. static int __init_resources(struct iris_hfi_device *device,
  3019. struct msm_cvp_platform_resources *res)
  3020. {
  3021. int i, rc = 0;
  3022. rc = __init_regulators(device);
  3023. if (rc) {
  3024. dprintk(CVP_ERR, "Failed to get all regulators\n");
  3025. return -ENODEV;
  3026. }
  3027. rc = __init_clocks(device);
  3028. if (rc) {
  3029. dprintk(CVP_ERR, "Failed to init clocks\n");
  3030. rc = -ENODEV;
  3031. goto err_init_clocks;
  3032. }
  3033. for (i = 0; i < device->res->reset_set.count; i++) {
  3034. rc = __handle_reset_clk(res, i, INIT, 0);
  3035. if (rc) {
  3036. dprintk(CVP_ERR, "Failed to init reset clocks\n");
  3037. rc = -ENODEV;
  3038. goto err_init_reset_clk;
  3039. }
  3040. }
  3041. rc = __init_bus(device);
  3042. if (rc) {
  3043. dprintk(CVP_ERR, "Failed to init bus: %d\n", rc);
  3044. goto err_init_bus;
  3045. }
  3046. rc = __init_subcaches(device);
  3047. if (rc)
  3048. dprintk(CVP_WARN, "Failed to init subcaches: %d\n", rc);
  3049. device->sys_init_capabilities =
  3050. kzalloc(sizeof(struct msm_cvp_capability)
  3051. * CVP_MAX_SESSIONS, GFP_KERNEL);
  3052. return rc;
  3053. err_init_reset_clk:
  3054. err_init_bus:
  3055. __deinit_clocks(device);
  3056. err_init_clocks:
  3057. __deinit_regulators(device);
  3058. return rc;
  3059. }
  3060. static void __deinit_resources(struct iris_hfi_device *device)
  3061. {
  3062. __deinit_subcaches(device);
  3063. __deinit_bus(device);
  3064. __deinit_clocks(device);
  3065. __deinit_regulators(device);
  3066. kfree(device->sys_init_capabilities);
  3067. device->sys_init_capabilities = NULL;
  3068. }
  3069. static int __disable_regulator(struct regulator_info *rinfo,
  3070. struct iris_hfi_device *device)
  3071. {
  3072. int rc = 0;
  3073. dprintk(CVP_PWR, "Disabling regulator %s\n", rinfo->name);
  3074. /*
  3075. * This call is needed. Driver needs to acquire the control back
  3076. * from HW in order to disable the regualtor. Else the behavior
  3077. * is unknown.
  3078. */
  3079. rc = __acquire_regulator(rinfo, device);
  3080. if (rc) {
  3081. /*
  3082. * This is somewhat fatal, but nothing we can do
  3083. * about it. We can't disable the regulator w/o
  3084. * getting it back under s/w control
  3085. */
  3086. dprintk(CVP_WARN,
  3087. "Failed to acquire control on %s\n",
  3088. rinfo->name);
  3089. goto disable_regulator_failed;
  3090. }
  3091. rc = regulator_disable(rinfo->regulator);
  3092. if (rc) {
  3093. dprintk(CVP_WARN,
  3094. "Failed to disable %s: %d\n",
  3095. rinfo->name, rc);
  3096. goto disable_regulator_failed;
  3097. }
  3098. return 0;
  3099. disable_regulator_failed:
  3100. /* Bring attention to this issue */
  3101. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3102. return rc;
  3103. }
  3104. static int __enable_hw_power_collapse(struct iris_hfi_device *device)
  3105. {
  3106. int rc = 0;
  3107. if (!msm_cvp_fw_low_power_mode) {
  3108. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3109. return 0;
  3110. }
  3111. rc = __hand_off_regulators(device);
  3112. if (rc)
  3113. dprintk(CVP_WARN,
  3114. "%s : Failed to enable HW power collapse %d\n",
  3115. __func__, rc);
  3116. return rc;
  3117. }
  3118. static int __enable_regulators(struct iris_hfi_device *device)
  3119. {
  3120. int rc = 0, c = 0;
  3121. struct regulator_info *rinfo;
  3122. dprintk(CVP_PWR, "Enabling regulators\n");
  3123. iris_hfi_for_each_regulator(device, rinfo) {
  3124. rc = regulator_enable(rinfo->regulator);
  3125. if (rc) {
  3126. dprintk(CVP_ERR, "Failed to enable %s: %d\n",
  3127. rinfo->name, rc);
  3128. goto err_reg_enable_failed;
  3129. }
  3130. dprintk(CVP_PWR, "Enabled regulator %s\n", rinfo->name);
  3131. c++;
  3132. }
  3133. return 0;
  3134. err_reg_enable_failed:
  3135. iris_hfi_for_each_regulator_reverse_continue(device, rinfo, c)
  3136. __disable_regulator(rinfo, device);
  3137. return rc;
  3138. }
  3139. static int __disable_regulators(struct iris_hfi_device *device)
  3140. {
  3141. struct regulator_info *rinfo;
  3142. dprintk(CVP_PWR, "Disabling regulators\n");
  3143. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3144. __disable_regulator(rinfo, device);
  3145. if (rinfo->has_hw_power_collapse)
  3146. regulator_set_mode(rinfo->regulator,
  3147. REGULATOR_MODE_NORMAL);
  3148. }
  3149. return 0;
  3150. }
  3151. static int __enable_subcaches(struct iris_hfi_device *device)
  3152. {
  3153. int rc = 0;
  3154. u32 c = 0;
  3155. struct subcache_info *sinfo;
  3156. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3157. return 0;
  3158. /* Activate subcaches */
  3159. iris_hfi_for_each_subcache(device, sinfo) {
  3160. rc = llcc_slice_activate(sinfo->subcache);
  3161. if (rc) {
  3162. dprintk(CVP_WARN, "Failed to activate %s: %d\n",
  3163. sinfo->name, rc);
  3164. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3165. goto err_activate_fail;
  3166. }
  3167. sinfo->isactive = true;
  3168. dprintk(CVP_CORE, "Activated subcache %s\n", sinfo->name);
  3169. c++;
  3170. }
  3171. dprintk(CVP_CORE, "Activated %d Subcaches to CVP\n", c);
  3172. return 0;
  3173. err_activate_fail:
  3174. __release_subcaches(device);
  3175. __disable_subcaches(device);
  3176. return 0;
  3177. }
  3178. static int __set_subcaches(struct iris_hfi_device *device)
  3179. {
  3180. int rc = 0;
  3181. u32 c = 0;
  3182. struct subcache_info *sinfo;
  3183. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3184. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3185. struct cvp_hfi_resource_subcache_type *sc_res;
  3186. struct cvp_resource_hdr rhdr;
  3187. if (device->res->sys_cache_res_set || msm_cvp_syscache_disable) {
  3188. dprintk(CVP_CORE, "Subcaches already set or disabled\n");
  3189. return 0;
  3190. }
  3191. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3192. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3193. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3194. iris_hfi_for_each_subcache(device, sinfo) {
  3195. if (sinfo->isactive) {
  3196. sc_res[c].size = sinfo->subcache->slice_size;
  3197. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3198. c++;
  3199. }
  3200. }
  3201. /* Set resource to CVP for activated subcaches */
  3202. if (c) {
  3203. dprintk(CVP_CORE, "Setting %d Subcaches\n", c);
  3204. rhdr.resource_handle = sc_res_info; /* cookie */
  3205. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3206. sc_res_info->num_entries = c;
  3207. rc = __core_set_resource(device, &rhdr, (void *)sc_res_info);
  3208. if (rc) {
  3209. dprintk(CVP_WARN, "Failed to set subcaches %d\n", rc);
  3210. goto err_fail_set_subacaches;
  3211. }
  3212. iris_hfi_for_each_subcache(device, sinfo) {
  3213. if (sinfo->isactive)
  3214. sinfo->isset = true;
  3215. }
  3216. dprintk(CVP_CORE, "Set Subcaches done to CVP\n");
  3217. device->res->sys_cache_res_set = true;
  3218. }
  3219. return 0;
  3220. err_fail_set_subacaches:
  3221. __disable_subcaches(device);
  3222. return 0;
  3223. }
  3224. static int __release_subcaches(struct iris_hfi_device *device)
  3225. {
  3226. struct subcache_info *sinfo;
  3227. int rc = 0;
  3228. u32 c = 0;
  3229. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3230. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3231. struct cvp_hfi_resource_subcache_type *sc_res;
  3232. struct cvp_resource_hdr rhdr;
  3233. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3234. return 0;
  3235. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3236. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3237. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3238. /* Release resource command to Iris */
  3239. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3240. if (sinfo->isset) {
  3241. /* Update the entry */
  3242. sc_res[c].size = sinfo->subcache->slice_size;
  3243. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3244. c++;
  3245. sinfo->isset = false;
  3246. }
  3247. }
  3248. if (c > 0) {
  3249. dprintk(CVP_CORE, "Releasing %d subcaches\n", c);
  3250. rhdr.resource_handle = sc_res_info; /* cookie */
  3251. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3252. rc = __core_release_resource(device, &rhdr);
  3253. if (rc)
  3254. dprintk(CVP_WARN,
  3255. "Failed to release %d subcaches\n", c);
  3256. }
  3257. device->res->sys_cache_res_set = false;
  3258. return 0;
  3259. }
  3260. static int __disable_subcaches(struct iris_hfi_device *device)
  3261. {
  3262. struct subcache_info *sinfo;
  3263. int rc = 0;
  3264. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3265. return 0;
  3266. /* De-activate subcaches */
  3267. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3268. if (sinfo->isactive) {
  3269. dprintk(CVP_CORE, "De-activate subcache %s\n",
  3270. sinfo->name);
  3271. rc = llcc_slice_deactivate(sinfo->subcache);
  3272. if (rc) {
  3273. dprintk(CVP_WARN,
  3274. "Failed to de-activate %s: %d\n",
  3275. sinfo->name, rc);
  3276. }
  3277. sinfo->isactive = false;
  3278. }
  3279. }
  3280. return 0;
  3281. }
  3282. static void interrupt_init_iris2(struct iris_hfi_device *device)
  3283. {
  3284. u32 mask_val = 0;
  3285. /* All interrupts should be disabled initially 0x1F6 : Reset value */
  3286. mask_val = __read_register(device, CVP_WRAPPER_INTR_MASK);
  3287. /* Write 0 to unmask CPU and WD interrupts */
  3288. mask_val &= ~(CVP_FATAL_INTR_BMSK | CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK);
  3289. __write_register(device, CVP_WRAPPER_INTR_MASK, mask_val);
  3290. dprintk(CVP_REG, "Init irq: reg: %x, mask value %x\n",
  3291. CVP_WRAPPER_INTR_MASK, mask_val);
  3292. }
  3293. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device)
  3294. {
  3295. /* initialize DSP QTBL & UCREGION with CPU queues */
  3296. __write_register(device, HFI_DSP_QTBL_ADDR,
  3297. (u32)device->dsp_iface_q_table.align_device_addr);
  3298. __write_register(device, HFI_DSP_UC_REGION_ADDR,
  3299. (u32)device->dsp_iface_q_table.align_device_addr);
  3300. __write_register(device, HFI_DSP_UC_REGION_SIZE,
  3301. device->dsp_iface_q_table.mem_data.size);
  3302. }
  3303. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device)
  3304. {
  3305. __write_register(device, CVP_WRAPPER_CPU_CLOCK_CONFIG, 0);
  3306. }
  3307. static int __set_ubwc_config(struct iris_hfi_device *device)
  3308. {
  3309. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  3310. int rc = 0;
  3311. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  3312. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  3313. if (!device->res->ubwc_config)
  3314. return 0;
  3315. rc = call_hfi_pkt_op(device, sys_ubwc_config, pkt,
  3316. device->res->ubwc_config);
  3317. if (rc) {
  3318. dprintk(CVP_WARN,
  3319. "ubwc config setting to FW failed\n");
  3320. rc = -ENOTEMPTY;
  3321. goto fail_to_set_ubwc_config;
  3322. }
  3323. if (__iface_cmdq_write(device, pkt)) {
  3324. rc = -ENOTEMPTY;
  3325. goto fail_to_set_ubwc_config;
  3326. }
  3327. fail_to_set_ubwc_config:
  3328. return rc;
  3329. }
  3330. static int __iris_power_on(struct iris_hfi_device *device)
  3331. {
  3332. int rc = 0;
  3333. if (device->power_enabled)
  3334. return 0;
  3335. /* Vote for all hardware resources */
  3336. rc = __vote_buses(device, device->bus_vote.data,
  3337. device->bus_vote.data_count);
  3338. if (rc) {
  3339. dprintk(CVP_ERR, "Failed to vote buses, err: %d\n", rc);
  3340. goto fail_vote_buses;
  3341. }
  3342. rc = __enable_regulators(device);
  3343. if (rc) {
  3344. dprintk(CVP_ERR, "Failed to enable GDSC, err = %d\n", rc);
  3345. goto fail_enable_gdsc;
  3346. }
  3347. rc = call_iris_op(device, reset_ahb2axi_bridge, device);
  3348. if (rc) {
  3349. dprintk(CVP_ERR, "Failed to reset ahb2axi: %d\n", rc);
  3350. goto fail_enable_clks;
  3351. }
  3352. rc = __prepare_enable_clks(device);
  3353. if (rc) {
  3354. dprintk(CVP_ERR, "Failed to enable clocks: %d\n", rc);
  3355. goto fail_enable_clks;
  3356. }
  3357. rc = __scale_clocks(device);
  3358. if (rc) {
  3359. dprintk(CVP_WARN,
  3360. "Failed to scale clocks, perf may regress\n");
  3361. rc = 0;
  3362. }
  3363. /*Do not access registers before this point!*/
  3364. device->power_enabled = true;
  3365. dprintk(CVP_PWR, "Done with scaling\n");
  3366. /*
  3367. * Re-program all of the registers that get reset as a result of
  3368. * regulator_disable() and _enable()
  3369. */
  3370. __set_registers(device);
  3371. dprintk(CVP_CORE, "Done with register set\n");
  3372. call_iris_op(device, interrupt_init, device);
  3373. dprintk(CVP_CORE, "Done with interrupt enabling\n");
  3374. device->intr_status = 0;
  3375. enable_irq(device->cvp_hal_data->irq);
  3376. return rc;
  3377. fail_enable_clks:
  3378. __disable_regulators(device);
  3379. fail_enable_gdsc:
  3380. __unvote_buses(device);
  3381. fail_vote_buses:
  3382. device->power_enabled = false;
  3383. return rc;
  3384. }
  3385. void power_off_common(struct iris_hfi_device *device)
  3386. {
  3387. if (!device->power_enabled)
  3388. return;
  3389. if (!(device->intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  3390. disable_irq_nosync(device->cvp_hal_data->irq);
  3391. device->intr_status = 0;
  3392. __disable_unprepare_clks(device);
  3393. if (__disable_regulators(device))
  3394. dprintk(CVP_WARN, "Failed to disable regulators\n");
  3395. if (__unvote_buses(device))
  3396. dprintk(CVP_WARN, "Failed to unvote for buses\n");
  3397. device->power_enabled = false;
  3398. }
  3399. static inline int __suspend(struct iris_hfi_device *device)
  3400. {
  3401. int rc = 0;
  3402. if (!device) {
  3403. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  3404. return -EINVAL;
  3405. } else if (!device->power_enabled) {
  3406. dprintk(CVP_PWR, "Power already disabled\n");
  3407. return 0;
  3408. }
  3409. dprintk(CVP_PWR, "Entering suspend\n");
  3410. if (device->res->pm_qos_latency_us &&
  3411. cpu_latency_qos_request_active(&device->qos))
  3412. cpu_latency_qos_remove_request(&device->qos);
  3413. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  3414. if (rc) {
  3415. dprintk(CVP_WARN, "Failed to suspend cvp core %d\n", rc);
  3416. goto err_tzbsp_suspend;
  3417. }
  3418. __disable_subcaches(device);
  3419. call_iris_op(device, power_off, device);
  3420. dprintk(CVP_PWR, "Iris power off\n");
  3421. return rc;
  3422. err_tzbsp_suspend:
  3423. return rc;
  3424. }
  3425. static void power_off_iris2(struct iris_hfi_device *device)
  3426. {
  3427. u32 lpi_status, reg_status = 0, count = 0, max_count = 1000;
  3428. u32 pc_ready, wfi_status, sbm_ln0_low;
  3429. u32 main_sbm_ln0_low, main_sbm_ln1_high;
  3430. if (!device->power_enabled || !device->res->sw_power_collapsible)
  3431. return;
  3432. if (!(device->intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  3433. disable_irq_nosync(device->cvp_hal_data->irq);
  3434. device->intr_status = 0;
  3435. /* HPG 6.1.2 Step 1 */
  3436. __write_register(device, CVP_CPU_CS_X2RPMh, 0x3);
  3437. /* HPG 6.1.2 Step 2, noc to low power */
  3438. __write_register(device, CVP_AON_WRAPPER_MVP_NOC_LPI_CONTROL, 0x1);
  3439. while (!reg_status && count < max_count) {
  3440. lpi_status =
  3441. __read_register(device,
  3442. CVP_AON_WRAPPER_MVP_NOC_LPI_STATUS);
  3443. reg_status = lpi_status & BIT(0);
  3444. /* Wait for noc lpi status to be set */
  3445. usleep_range(50, 100);
  3446. count++;
  3447. }
  3448. dprintk(CVP_PWR,
  3449. "Noc: lpi_status %x noc_status %x (count %d)\n",
  3450. lpi_status, reg_status, count);
  3451. if (count == max_count) {
  3452. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  3453. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  3454. sbm_ln0_low =
  3455. __read_register(device, CVP_NOC_SBM_SENSELN0_LOW);
  3456. main_sbm_ln0_low = __read_register(device,
  3457. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_LOW);
  3458. main_sbm_ln1_high = __read_register(device,
  3459. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN1_HIGH);
  3460. dprintk(CVP_WARN,
  3461. "NOC not in qaccept status %x %x %x %x %x %x %x\n",
  3462. reg_status, lpi_status, wfi_status, pc_ready,
  3463. sbm_ln0_low, main_sbm_ln0_low, main_sbm_ln1_high);
  3464. }
  3465. /* HPG 6.1.2 Step 3, debug bridge to low power */
  3466. __write_register(device,
  3467. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x7);
  3468. reg_status = 0;
  3469. count = 0;
  3470. while ((reg_status != 0x7) && count < max_count) {
  3471. lpi_status = __read_register(device,
  3472. CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
  3473. reg_status = lpi_status & 0x7;
  3474. /* Wait for debug bridge lpi status to be set */
  3475. usleep_range(50, 100);
  3476. count++;
  3477. }
  3478. dprintk(CVP_PWR,
  3479. "DBLP Set : lpi_status %d reg_status %d (count %d)\n",
  3480. lpi_status, reg_status, count);
  3481. if (count == max_count) {
  3482. dprintk(CVP_WARN,
  3483. "DBLP Set: status %x %x\n", reg_status, lpi_status);
  3484. }
  3485. /* HPG 6.1.2 Step 4, debug bridge to lpi release */
  3486. __write_register(device,
  3487. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x0);
  3488. lpi_status = 0x1;
  3489. count = 0;
  3490. while (lpi_status && count < max_count) {
  3491. lpi_status = __read_register(device,
  3492. CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
  3493. usleep_range(50, 100);
  3494. count++;
  3495. }
  3496. dprintk(CVP_PWR,
  3497. "DBLP Release: lpi_status %d(count %d)\n",
  3498. lpi_status, count);
  3499. if (count == max_count) {
  3500. dprintk(CVP_WARN,
  3501. "DBLP Release: lpi_status %x\n", lpi_status);
  3502. }
  3503. /* HPG 6.1.2 Step 6 */
  3504. __disable_unprepare_clks(device);
  3505. /*
  3506. * HPG 6.1.2 Step 7 & 8
  3507. * per new HPG update, core clock reset will be unnecessary
  3508. */
  3509. if (__unvote_buses(device))
  3510. dprintk(CVP_WARN, "Failed to unvote for buses\n");
  3511. /* HPG 6.1.2 Step 5 */
  3512. if (__disable_regulators(device))
  3513. dprintk(CVP_WARN, "Failed to disable regulators\n");
  3514. /*Do not access registers after this point!*/
  3515. device->power_enabled = false;
  3516. }
  3517. static inline int __resume(struct iris_hfi_device *device)
  3518. {
  3519. int rc = 0;
  3520. u32 flags = 0, reg_gdsc, reg_cbcr;
  3521. if (!device) {
  3522. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  3523. return -EINVAL;
  3524. } else if (device->power_enabled) {
  3525. goto exit;
  3526. } else if (!__core_in_valid_state(device)) {
  3527. dprintk(CVP_PWR, "iris_hfi_device in deinit state.");
  3528. return -EINVAL;
  3529. }
  3530. dprintk(CVP_PWR, "Resuming from power collapse\n");
  3531. rc = __iris_power_on(device);
  3532. if (rc) {
  3533. dprintk(CVP_ERR, "Failed to power on cvp\n");
  3534. goto err_iris_power_on;
  3535. }
  3536. reg_gdsc = __read_register(device, CVP_CC_MVS1C_GDSCR);
  3537. reg_cbcr = __read_register(device, CVP_CC_MVS1C_CBCR);
  3538. if (!(reg_gdsc & 0x80000000) || (reg_cbcr & 0x80000000))
  3539. dprintk(CVP_ERR, "CVP power on failed gdsc %x cbcr %x\n",
  3540. reg_gdsc, reg_cbcr);
  3541. /* Reboot the firmware */
  3542. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESUME);
  3543. if (rc) {
  3544. dprintk(CVP_ERR, "Failed to resume cvp core %d\n", rc);
  3545. goto err_set_cvp_state;
  3546. }
  3547. __setup_ucregion_memory_map(device);
  3548. /* Wait for boot completion */
  3549. rc = __boot_firmware(device);
  3550. if (rc) {
  3551. dprintk(CVP_ERR, "Failed to reset cvp core\n");
  3552. goto err_reset_core;
  3553. }
  3554. /*
  3555. * Work around for H/W bug, need to reprogram these registers once
  3556. * firmware is out reset
  3557. */
  3558. __set_threshold_registers(device);
  3559. if (device->res->pm_qos_latency_us)
  3560. cpu_latency_qos_add_request(&device->qos,
  3561. device->res->pm_qos_latency_us);
  3562. __sys_set_debug(device, msm_cvp_fw_debug);
  3563. __enable_subcaches(device);
  3564. __set_subcaches(device);
  3565. __dsp_resume(device, flags);
  3566. dprintk(CVP_PWR, "Resumed from power collapse\n");
  3567. exit:
  3568. /* Don't reset skip_pc_count for SYS_PC_PREP cmd */
  3569. if (device->last_packet_type != HFI_CMD_SYS_PC_PREP)
  3570. device->skip_pc_count = 0;
  3571. return rc;
  3572. err_reset_core:
  3573. __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  3574. err_set_cvp_state:
  3575. call_iris_op(device, power_off, device);
  3576. err_iris_power_on:
  3577. dprintk(CVP_ERR, "Failed to resume from power collapse\n");
  3578. return rc;
  3579. }
  3580. static int __load_fw(struct iris_hfi_device *device)
  3581. {
  3582. int rc = 0;
  3583. /* Initialize resources */
  3584. rc = __init_resources(device, device->res);
  3585. if (rc) {
  3586. dprintk(CVP_ERR, "Failed to init resources: %d\n", rc);
  3587. goto fail_init_res;
  3588. }
  3589. rc = __initialize_packetization(device);
  3590. if (rc) {
  3591. dprintk(CVP_ERR, "Failed to initialize packetization\n");
  3592. goto fail_init_pkt;
  3593. }
  3594. rc = __iris_power_on(device);
  3595. if (rc) {
  3596. dprintk(CVP_ERR, "Failed to power on iris in in load_fw\n");
  3597. goto fail_iris_power_on;
  3598. }
  3599. if ((!device->res->use_non_secure_pil && !device->res->firmware_base)
  3600. || device->res->use_non_secure_pil) {
  3601. rc = load_cvp_fw_impl(device);
  3602. if (rc)
  3603. goto fail_load_fw;
  3604. }
  3605. return rc;
  3606. fail_load_fw:
  3607. call_iris_op(device, power_off, device);
  3608. fail_iris_power_on:
  3609. fail_init_pkt:
  3610. __deinit_resources(device);
  3611. fail_init_res:
  3612. return rc;
  3613. }
  3614. static void __unload_fw(struct iris_hfi_device *device)
  3615. {
  3616. if (!device->resources.fw.cookie)
  3617. return;
  3618. cancel_delayed_work(&iris_hfi_pm_work);
  3619. if (device->state != IRIS_STATE_DEINIT)
  3620. flush_workqueue(device->iris_pm_workq);
  3621. unload_cvp_fw_impl(device);
  3622. __interface_queues_release(device);
  3623. call_iris_op(device, power_off, device);
  3624. __deinit_resources(device);
  3625. dprintk(CVP_WARN, "Firmware unloaded\n");
  3626. }
  3627. static int iris_hfi_get_fw_info(void *dev, struct cvp_hal_fw_info *fw_info)
  3628. {
  3629. int i = 0;
  3630. struct iris_hfi_device *device = dev;
  3631. if (!device || !fw_info) {
  3632. dprintk(CVP_ERR,
  3633. "%s Invalid parameter: device = %pK fw_info = %pK\n",
  3634. __func__, device, fw_info);
  3635. return -EINVAL;
  3636. }
  3637. mutex_lock(&device->lock);
  3638. while (cvp_driver->fw_version[i++] != 'V' && i < CVP_VERSION_LENGTH)
  3639. ;
  3640. if (i == CVP_VERSION_LENGTH - 1) {
  3641. dprintk(CVP_WARN, "Iris version string is not proper\n");
  3642. fw_info->version[0] = '\0';
  3643. goto fail_version_string;
  3644. }
  3645. memcpy(&fw_info->version[0], &cvp_driver->fw_version[0],
  3646. CVP_VERSION_LENGTH);
  3647. fw_info->version[CVP_VERSION_LENGTH - 1] = '\0';
  3648. fail_version_string:
  3649. dprintk(CVP_CORE, "F/W version retrieved : %s\n", fw_info->version);
  3650. fw_info->base_addr = device->cvp_hal_data->firmware_base;
  3651. fw_info->register_base = device->res->register_base;
  3652. fw_info->register_size = device->cvp_hal_data->register_size;
  3653. fw_info->irq = device->cvp_hal_data->irq;
  3654. mutex_unlock(&device->lock);
  3655. return 0;
  3656. }
  3657. static int iris_hfi_get_core_capabilities(void *dev)
  3658. {
  3659. dprintk(CVP_CORE, "%s not supported yet!\n", __func__);
  3660. return 0;
  3661. }
  3662. static u32 cvp_arp_test_regs[16];
  3663. static u32 cvp_dma_test_regs[512];
  3664. static const char * const mid_names[16] = {
  3665. "CVP_FW",
  3666. "ARP_DATA",
  3667. "CVP_OD_NON_PIXEL",
  3668. "CVP_OD_ORIG_PIXEL",
  3669. "CVP_OD_WR_PIXEL",
  3670. "CVP_MPU_ORIG_PIXEL",
  3671. "CVP_MPU_REF_PIXEL",
  3672. "CVP_MPU_NON_PIXEL",
  3673. "CVP_MPU_DFS",
  3674. "CVP_FDU_NON_PIXEL",
  3675. "CVP_FDU_PIXEL",
  3676. "CVP_ICA_PIXEL",
  3677. "Invalid",
  3678. "Invalid",
  3679. "Invalid",
  3680. "Invalid"
  3681. };
  3682. static void __print_reg_details(u32 val)
  3683. {
  3684. u32 mid, sid;
  3685. mid = (val >> 5) & 0xF;
  3686. sid = (val >> 2) & 0x7;
  3687. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
  3688. dprintk(CVP_ERR, "Sub-client:%s, SID: %d\n", mid_names[mid], sid);
  3689. }
  3690. static void __noc_error_info_iris2(struct iris_hfi_device *device)
  3691. {
  3692. u32 val = 0, regi, i;
  3693. val = __read_register(device, CVP_NOC_ERR_SWID_LOW_OFFS);
  3694. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_SWID_LOW: %#x\n", val);
  3695. val = __read_register(device, CVP_NOC_ERR_SWID_HIGH_OFFS);
  3696. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_SWID_HIGH: %#x\n", val);
  3697. val = __read_register(device, CVP_NOC_ERR_MAINCTL_LOW_OFFS);
  3698. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_MAINCTL_LOW: %#x\n", val);
  3699. val = __read_register(device, CVP_NOC_ERR_ERRVLD_LOW_OFFS);
  3700. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRVLD_LOW: %#x\n", val);
  3701. val = __read_register(device, CVP_NOC_ERR_ERRCLR_LOW_OFFS);
  3702. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRCLR_LOW: %#x\n", val);
  3703. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_LOW_OFFS);
  3704. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG0_LOW: %#x\n", val);
  3705. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_HIGH_OFFS);
  3706. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG0_HIGH: %#x\n", val);
  3707. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_LOW_OFFS);
  3708. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG1_LOW: %#x\n", val);
  3709. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_HIGH_OFFS);
  3710. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG1_HIGH: %#x\n", val);
  3711. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_LOW_OFFS);
  3712. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG2_LOW: %#x\n", val);
  3713. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_HIGH_OFFS);
  3714. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG2_HIGH: %#x\n", val);
  3715. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_LOW_OFFS);
  3716. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
  3717. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_HIGH_OFFS);
  3718. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG3_HIGH: %#x\n", val);
  3719. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_LOW_OFFS);
  3720. dprintk(CVP_ERR, "CVP_NOC__CORE_ERL_MAIN_SWID_LOW: %#x\n", val);
  3721. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_HIGH_OFFS);
  3722. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_SWID_HIGH: %#x\n", val);
  3723. val = __read_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS);
  3724. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_MAINCTL_LOW: %#x\n", val);
  3725. val = __read_register(device, CVP_NOC_CORE_ERR_ERRVLD_LOW_OFFS);
  3726. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRVLD_LOW: %#x\n", val);
  3727. val = __read_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS);
  3728. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRCLR_LOW: %#x\n", val);
  3729. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_LOW_OFFS);
  3730. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_LOW: %#x\n", val);
  3731. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_HIGH_OFFS);
  3732. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_HIGH: %#x\n", val);
  3733. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_LOW_OFFS);
  3734. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_LOW: %#x\n", val);
  3735. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_HIGH_OFFS);
  3736. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_HIGH: %#x\n", val);
  3737. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_LOW_OFFS);
  3738. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_LOW: %#x\n", val);
  3739. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_HIGH_OFFS);
  3740. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_HIGH: %#x\n", val);
  3741. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_LOW_OFFS);
  3742. __print_reg_details(val);
  3743. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_HIGH_OFFS);
  3744. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_HIGH: %#x\n", val);
  3745. #define CVP_SS_CLK_HALT 0x8
  3746. #define CVP_SS_CLK_EN 0xC
  3747. #define CVP_SS_ARP_TEST_BUS_CONTROL 0x700
  3748. #define CVP_SS_ARP_TEST_BUS_REGISTER 0x704
  3749. #define CVP_DMA_TEST_BUS_CONTROL 0x66A0
  3750. #define CVP_DMA_TEST_BUS_REGISTER 0x66A4
  3751. #define CVP_VPU_WRAPPER_CORE_CONFIG 0xB0088
  3752. __write_register(device, CVP_SS_CLK_HALT, 0);
  3753. __write_register(device, CVP_SS_CLK_EN, 0x3f);
  3754. __write_register(device, CVP_VPU_WRAPPER_CORE_CONFIG, 0);
  3755. for (i = 0; i < 15; i++) {
  3756. regi = 0xC0000000 + i;
  3757. __write_register(device, CVP_SS_ARP_TEST_BUS_CONTROL, regi);
  3758. val = __read_register(device, CVP_SS_ARP_TEST_BUS_REGISTER);
  3759. cvp_arp_test_regs[i] = val;
  3760. dprintk(CVP_ERR, "ARP_CTL:%x - %x\n", regi, val);
  3761. }
  3762. for (i = 0; i < 512; i++) {
  3763. regi = 0x40000000 + i;
  3764. __write_register(device, CVP_DMA_TEST_BUS_CONTROL, regi);
  3765. val = __read_register(device, CVP_DMA_TEST_BUS_REGISTER);
  3766. cvp_dma_test_regs[i] = val;
  3767. dprintk(CVP_ERR, "DMA_CTL:%x - %x\n", regi, val);
  3768. }
  3769. }
  3770. static int iris_hfi_noc_error_info(void *dev)
  3771. {
  3772. struct iris_hfi_device *device;
  3773. if (!dev) {
  3774. dprintk(CVP_ERR, "%s: null device\n", __func__);
  3775. return -EINVAL;
  3776. }
  3777. device = dev;
  3778. mutex_lock(&device->lock);
  3779. dprintk(CVP_ERR, "%s: non error information\n", __func__);
  3780. call_iris_op(device, noc_error_info, device);
  3781. mutex_unlock(&device->lock);
  3782. return 0;
  3783. }
  3784. static int __initialize_packetization(struct iris_hfi_device *device)
  3785. {
  3786. int rc = 0;
  3787. if (!device || !device->res) {
  3788. dprintk(CVP_ERR, "%s - invalid param\n", __func__);
  3789. return -EINVAL;
  3790. }
  3791. device->packetization_type = HFI_PACKETIZATION_4XX;
  3792. device->pkt_ops = cvp_hfi_get_pkt_ops_handle(
  3793. device->packetization_type);
  3794. if (!device->pkt_ops) {
  3795. rc = -EINVAL;
  3796. dprintk(CVP_ERR, "Failed to get pkt_ops handle\n");
  3797. }
  3798. return rc;
  3799. }
  3800. void __init_cvp_ops(struct iris_hfi_device *device)
  3801. {
  3802. device->vpu_ops = &iris2_ops;
  3803. }
  3804. static struct iris_hfi_device *__add_device(u32 device_id,
  3805. struct msm_cvp_platform_resources *res,
  3806. hfi_cmd_response_callback callback)
  3807. {
  3808. struct iris_hfi_device *hdevice = NULL;
  3809. int rc = 0;
  3810. if (!res || !callback) {
  3811. dprintk(CVP_ERR, "Invalid Parameters\n");
  3812. return NULL;
  3813. }
  3814. dprintk(CVP_INFO, "%s: device_id: %d\n", __func__, device_id);
  3815. hdevice = kzalloc(sizeof(*hdevice), GFP_KERNEL);
  3816. if (!hdevice) {
  3817. dprintk(CVP_ERR, "failed to allocate new device\n");
  3818. goto exit;
  3819. }
  3820. hdevice->response_pkt = kmalloc_array(cvp_max_packets,
  3821. sizeof(*hdevice->response_pkt), GFP_KERNEL);
  3822. if (!hdevice->response_pkt) {
  3823. dprintk(CVP_ERR, "failed to allocate response_pkt\n");
  3824. goto err_cleanup;
  3825. }
  3826. hdevice->raw_packet =
  3827. kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  3828. if (!hdevice->raw_packet) {
  3829. dprintk(CVP_ERR, "failed to allocate raw packet\n");
  3830. goto err_cleanup;
  3831. }
  3832. rc = __init_regs_and_interrupts(hdevice, res);
  3833. if (rc)
  3834. goto err_cleanup;
  3835. hdevice->res = res;
  3836. hdevice->device_id = device_id;
  3837. hdevice->callback = callback;
  3838. __init_cvp_ops(hdevice);
  3839. hdevice->cvp_workq = create_singlethread_workqueue(
  3840. "msm_cvp_workerq_iris");
  3841. if (!hdevice->cvp_workq) {
  3842. dprintk(CVP_ERR, ": create cvp workq failed\n");
  3843. goto err_cleanup;
  3844. }
  3845. hdevice->iris_pm_workq = create_singlethread_workqueue(
  3846. "pm_workerq_iris");
  3847. if (!hdevice->iris_pm_workq) {
  3848. dprintk(CVP_ERR, ": create pm workq failed\n");
  3849. goto err_cleanup;
  3850. }
  3851. mutex_init(&hdevice->lock);
  3852. INIT_LIST_HEAD(&hdevice->sess_head);
  3853. return hdevice;
  3854. err_cleanup:
  3855. if (hdevice->iris_pm_workq)
  3856. destroy_workqueue(hdevice->iris_pm_workq);
  3857. if (hdevice->cvp_workq)
  3858. destroy_workqueue(hdevice->cvp_workq);
  3859. kfree(hdevice->response_pkt);
  3860. kfree(hdevice->raw_packet);
  3861. kfree(hdevice);
  3862. exit:
  3863. return NULL;
  3864. }
  3865. static struct iris_hfi_device *__get_device(u32 device_id,
  3866. struct msm_cvp_platform_resources *res,
  3867. hfi_cmd_response_callback callback)
  3868. {
  3869. if (!res || !callback) {
  3870. dprintk(CVP_ERR, "Invalid params: %pK %pK\n", res, callback);
  3871. return NULL;
  3872. }
  3873. return __add_device(device_id, res, callback);
  3874. }
  3875. void cvp_iris_hfi_delete_device(void *device)
  3876. {
  3877. struct msm_cvp_core *core;
  3878. struct iris_hfi_device *dev = NULL;
  3879. if (!device)
  3880. return;
  3881. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  3882. if (core)
  3883. dev = core->device->hfi_device_data;
  3884. if (!dev)
  3885. return;
  3886. mutex_destroy(&dev->lock);
  3887. destroy_workqueue(dev->cvp_workq);
  3888. destroy_workqueue(dev->iris_pm_workq);
  3889. free_irq(dev->cvp_hal_data->irq, dev);
  3890. iounmap(dev->cvp_hal_data->register_base);
  3891. iounmap(dev->cvp_hal_data->gcc_reg_base);
  3892. kfree(dev->cvp_hal_data);
  3893. kfree(dev->response_pkt);
  3894. kfree(dev->raw_packet);
  3895. kfree(dev);
  3896. }
  3897. static int iris_hfi_validate_session(void *sess, const char *func)
  3898. {
  3899. struct cvp_hal_session *session = sess;
  3900. int rc = 0;
  3901. struct iris_hfi_device *device;
  3902. if (!session || !session->device) {
  3903. dprintk(CVP_ERR, " %s Invalid Params %pK\n", __func__, session);
  3904. return -EINVAL;
  3905. }
  3906. device = session->device;
  3907. mutex_lock(&device->lock);
  3908. if (!__is_session_valid(device, session, func))
  3909. rc = -ECONNRESET;
  3910. mutex_unlock(&device->lock);
  3911. return rc;
  3912. }
  3913. static void iris_init_hfi_callbacks(struct cvp_hfi_device *hdev)
  3914. {
  3915. hdev->core_init = iris_hfi_core_init;
  3916. hdev->core_release = iris_hfi_core_release;
  3917. hdev->core_trigger_ssr = iris_hfi_core_trigger_ssr;
  3918. hdev->session_init = iris_hfi_session_init;
  3919. hdev->session_end = iris_hfi_session_end;
  3920. hdev->session_abort = iris_hfi_session_abort;
  3921. hdev->session_clean = iris_hfi_session_clean;
  3922. hdev->session_set_buffers = iris_hfi_session_set_buffers;
  3923. hdev->session_release_buffers = iris_hfi_session_release_buffers;
  3924. hdev->session_send = iris_hfi_session_send;
  3925. hdev->session_flush = iris_hfi_session_flush;
  3926. hdev->scale_clocks = iris_hfi_scale_clocks;
  3927. hdev->vote_bus = iris_hfi_vote_buses;
  3928. hdev->get_fw_info = iris_hfi_get_fw_info;
  3929. hdev->get_core_capabilities = iris_hfi_get_core_capabilities;
  3930. hdev->suspend = iris_hfi_suspend;
  3931. hdev->resume = iris_hfi_resume;
  3932. hdev->flush_debug_queue = iris_hfi_flush_debug_queue;
  3933. hdev->noc_error_info = iris_hfi_noc_error_info;
  3934. hdev->validate_session = iris_hfi_validate_session;
  3935. }
  3936. int cvp_iris_hfi_initialize(struct cvp_hfi_device *hdev, u32 device_id,
  3937. struct msm_cvp_platform_resources *res,
  3938. hfi_cmd_response_callback callback)
  3939. {
  3940. int rc = 0;
  3941. if (!hdev || !res || !callback) {
  3942. dprintk(CVP_ERR, "Invalid params: %pK %pK %pK\n",
  3943. hdev, res, callback);
  3944. rc = -EINVAL;
  3945. goto err_iris_hfi_init;
  3946. }
  3947. hdev->hfi_device_data = __get_device(device_id, res, callback);
  3948. if (IS_ERR_OR_NULL(hdev->hfi_device_data)) {
  3949. rc = PTR_ERR(hdev->hfi_device_data) ?: -EINVAL;
  3950. goto err_iris_hfi_init;
  3951. }
  3952. iris_init_hfi_callbacks(hdev);
  3953. err_iris_hfi_init:
  3954. return rc;
  3955. }