dp_tx.c 162 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef QCA_DP_TX_FW_METADATA_V2
  66. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  67. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  68. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  69. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  78. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  79. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  80. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  82. #else
  83. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  84. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  85. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  86. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  95. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  96. HTT_TCL_METADATA_TYPE_PEER_BASED
  97. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  98. HTT_TCL_METADATA_TYPE_VDEV_BASED
  99. #endif
  100. /*mapping between hal encrypt type and cdp_sec_type*/
  101. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  102. HAL_TX_ENCRYPT_TYPE_WEP_128,
  103. HAL_TX_ENCRYPT_TYPE_WEP_104,
  104. HAL_TX_ENCRYPT_TYPE_WEP_40,
  105. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  106. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  107. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  108. HAL_TX_ENCRYPT_TYPE_WAPI,
  109. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  110. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  111. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  112. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  113. qdf_export_symbol(sec_type_map);
  114. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  115. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  116. {
  117. enum dp_tx_event_type type;
  118. if (flags & DP_TX_DESC_FLAG_FLUSH)
  119. type = DP_TX_DESC_FLUSH;
  120. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  121. type = DP_TX_COMP_UNMAP_ERR;
  122. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  123. type = DP_TX_COMP_UNMAP;
  124. else
  125. type = DP_TX_DESC_UNMAP;
  126. return type;
  127. }
  128. static inline void
  129. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  130. qdf_nbuf_t skb, uint32_t sw_cookie,
  131. enum dp_tx_event_type type)
  132. {
  133. struct dp_tx_desc_event *entry;
  134. uint32_t idx;
  135. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  136. return;
  137. switch (type) {
  138. case DP_TX_COMP_UNMAP:
  139. case DP_TX_COMP_UNMAP_ERR:
  140. case DP_TX_COMP_MSDU_EXT:
  141. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  142. DP_TX_COMP_HISTORY_SIZE);
  143. entry = &soc->tx_comp_history->entry[idx];
  144. break;
  145. case DP_TX_DESC_MAP:
  146. case DP_TX_DESC_UNMAP:
  147. case DP_TX_DESC_COOKIE:
  148. case DP_TX_DESC_FLUSH:
  149. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  150. DP_TX_TCL_HISTORY_SIZE);
  151. entry = &soc->tx_tcl_history->entry[idx];
  152. break;
  153. default:
  154. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  155. return;
  156. }
  157. entry->skb = skb;
  158. entry->paddr = paddr;
  159. entry->sw_cookie = sw_cookie;
  160. entry->type = type;
  161. entry->ts = qdf_get_log_timestamp();
  162. }
  163. static inline void
  164. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  165. struct qdf_tso_seg_elem_t *tso_seg,
  166. qdf_nbuf_t skb, uint32_t sw_cookie,
  167. enum dp_tx_event_type type)
  168. {
  169. int i;
  170. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  171. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  172. skb, sw_cookie, type);
  173. }
  174. if (!tso_seg->next)
  175. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  176. skb, 0xFFFFFFFF, type);
  177. }
  178. static inline void
  179. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  180. qdf_nbuf_t skb, uint32_t sw_cookie,
  181. enum dp_tx_event_type type)
  182. {
  183. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  184. uint32_t num_segs = tso_info.num_segs;
  185. while (num_segs) {
  186. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  187. curr_seg = curr_seg->next;
  188. num_segs--;
  189. }
  190. }
  191. #else
  192. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  193. {
  194. return DP_TX_DESC_INVAL_EVT;
  195. }
  196. static inline void
  197. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  198. qdf_nbuf_t skb, uint32_t sw_cookie,
  199. enum dp_tx_event_type type)
  200. {
  201. }
  202. static inline void
  203. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  204. struct qdf_tso_seg_elem_t *tso_seg,
  205. qdf_nbuf_t skb, uint32_t sw_cookie,
  206. enum dp_tx_event_type type)
  207. {
  208. }
  209. static inline void
  210. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  211. qdf_nbuf_t skb, uint32_t sw_cookie,
  212. enum dp_tx_event_type type)
  213. {
  214. }
  215. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  216. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  217. /**
  218. * dp_is_tput_high() - Check if throughput is high
  219. *
  220. * @soc - core txrx main context
  221. *
  222. * The current function is based of the RTPM tput policy variable where RTPM is
  223. * avoided based on throughput.
  224. */
  225. static inline int dp_is_tput_high(struct dp_soc *soc)
  226. {
  227. return dp_get_rtpm_tput_policy_requirement(soc);
  228. }
  229. #if defined(FEATURE_TSO)
  230. /**
  231. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  232. *
  233. * @soc - core txrx main context
  234. * @seg_desc - tso segment descriptor
  235. * @num_seg_desc - tso number segment descriptor
  236. */
  237. static void dp_tx_tso_unmap_segment(
  238. struct dp_soc *soc,
  239. struct qdf_tso_seg_elem_t *seg_desc,
  240. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  241. {
  242. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  243. if (qdf_unlikely(!seg_desc)) {
  244. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  245. __func__, __LINE__);
  246. qdf_assert(0);
  247. } else if (qdf_unlikely(!num_seg_desc)) {
  248. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  249. __func__, __LINE__);
  250. qdf_assert(0);
  251. } else {
  252. bool is_last_seg;
  253. /* no tso segment left to do dma unmap */
  254. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  255. return;
  256. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  257. true : false;
  258. qdf_nbuf_unmap_tso_segment(soc->osdev,
  259. seg_desc, is_last_seg);
  260. num_seg_desc->num_seg.tso_cmn_num_seg--;
  261. }
  262. }
  263. /**
  264. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  265. * back to the freelist
  266. *
  267. * @soc - soc device handle
  268. * @tx_desc - Tx software descriptor
  269. */
  270. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  271. struct dp_tx_desc_s *tx_desc)
  272. {
  273. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  274. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  275. dp_tx_err("SO desc is NULL!");
  276. qdf_assert(0);
  277. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  278. dp_tx_err("TSO num desc is NULL!");
  279. qdf_assert(0);
  280. } else {
  281. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  282. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  283. msdu_ext_desc->tso_num_desc;
  284. /* Add the tso num segment into the free list */
  285. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  286. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  287. tx_desc->msdu_ext_desc->
  288. tso_num_desc);
  289. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  290. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  291. }
  292. /* Add the tso segment into the free list*/
  293. dp_tx_tso_desc_free(soc,
  294. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  295. tso_desc);
  296. tx_desc->msdu_ext_desc->tso_desc = NULL;
  297. }
  298. }
  299. #else
  300. static void dp_tx_tso_unmap_segment(
  301. struct dp_soc *soc,
  302. struct qdf_tso_seg_elem_t *seg_desc,
  303. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  304. {
  305. }
  306. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  307. struct dp_tx_desc_s *tx_desc)
  308. {
  309. }
  310. #endif
  311. /**
  312. * dp_tx_desc_release() - Release Tx Descriptor
  313. * @tx_desc : Tx Descriptor
  314. * @desc_pool_id: Descriptor Pool ID
  315. *
  316. * Deallocate all resources attached to Tx descriptor and free the Tx
  317. * descriptor.
  318. *
  319. * Return:
  320. */
  321. void
  322. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  323. {
  324. struct dp_pdev *pdev = tx_desc->pdev;
  325. struct dp_soc *soc;
  326. uint8_t comp_status = 0;
  327. qdf_assert(pdev);
  328. soc = pdev->soc;
  329. dp_tx_outstanding_dec(pdev);
  330. if (tx_desc->msdu_ext_desc) {
  331. if (tx_desc->frm_type == dp_tx_frm_tso)
  332. dp_tx_tso_desc_release(soc, tx_desc);
  333. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  334. dp_tx_me_free_buf(tx_desc->pdev,
  335. tx_desc->msdu_ext_desc->me_buffer);
  336. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  337. }
  338. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  339. qdf_atomic_dec(&soc->num_tx_exception);
  340. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  341. tx_desc->buffer_src)
  342. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  343. soc->hal_soc);
  344. else
  345. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  346. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  347. tx_desc->id, comp_status,
  348. qdf_atomic_read(&pdev->num_tx_outstanding));
  349. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  350. return;
  351. }
  352. /**
  353. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  354. * @vdev: DP vdev Handle
  355. * @nbuf: skb
  356. * @msdu_info: msdu_info required to create HTT metadata
  357. *
  358. * Prepares and fills HTT metadata in the frame pre-header for special frames
  359. * that should be transmitted using varying transmit parameters.
  360. * There are 2 VDEV modes that currently needs this special metadata -
  361. * 1) Mesh Mode
  362. * 2) DSRC Mode
  363. *
  364. * Return: HTT metadata size
  365. *
  366. */
  367. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  368. struct dp_tx_msdu_info_s *msdu_info)
  369. {
  370. uint32_t *meta_data = msdu_info->meta_data;
  371. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  372. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  373. uint8_t htt_desc_size;
  374. /* Size rounded of multiple of 8 bytes */
  375. uint8_t htt_desc_size_aligned;
  376. uint8_t *hdr = NULL;
  377. /*
  378. * Metadata - HTT MSDU Extension header
  379. */
  380. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  381. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  382. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  383. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  384. meta_data[0]) ||
  385. msdu_info->exception_fw) {
  386. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  387. htt_desc_size_aligned)) {
  388. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  389. htt_desc_size_aligned);
  390. if (!nbuf) {
  391. /*
  392. * qdf_nbuf_realloc_headroom won't do skb_clone
  393. * as skb_realloc_headroom does. so, no free is
  394. * needed here.
  395. */
  396. DP_STATS_INC(vdev,
  397. tx_i.dropped.headroom_insufficient,
  398. 1);
  399. qdf_print(" %s[%d] skb_realloc_headroom failed",
  400. __func__, __LINE__);
  401. return 0;
  402. }
  403. }
  404. /* Fill and add HTT metaheader */
  405. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  406. if (!hdr) {
  407. dp_tx_err("Error in filling HTT metadata");
  408. return 0;
  409. }
  410. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  411. } else if (vdev->opmode == wlan_op_mode_ocb) {
  412. /* Todo - Add support for DSRC */
  413. }
  414. return htt_desc_size_aligned;
  415. }
  416. /**
  417. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  418. * @tso_seg: TSO segment to process
  419. * @ext_desc: Pointer to MSDU extension descriptor
  420. *
  421. * Return: void
  422. */
  423. #if defined(FEATURE_TSO)
  424. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  425. void *ext_desc)
  426. {
  427. uint8_t num_frag;
  428. uint32_t tso_flags;
  429. /*
  430. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  431. * tcp_flag_mask
  432. *
  433. * Checksum enable flags are set in TCL descriptor and not in Extension
  434. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  435. */
  436. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  437. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  438. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  439. tso_seg->tso_flags.ip_len);
  440. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  441. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  442. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  443. uint32_t lo = 0;
  444. uint32_t hi = 0;
  445. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  446. (tso_seg->tso_frags[num_frag].length));
  447. qdf_dmaaddr_to_32s(
  448. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  449. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  450. tso_seg->tso_frags[num_frag].length);
  451. }
  452. return;
  453. }
  454. #else
  455. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  456. void *ext_desc)
  457. {
  458. return;
  459. }
  460. #endif
  461. #if defined(FEATURE_TSO)
  462. /**
  463. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  464. * allocated and free them
  465. *
  466. * @soc: soc handle
  467. * @free_seg: list of tso segments
  468. * @msdu_info: msdu descriptor
  469. *
  470. * Return - void
  471. */
  472. static void dp_tx_free_tso_seg_list(
  473. struct dp_soc *soc,
  474. struct qdf_tso_seg_elem_t *free_seg,
  475. struct dp_tx_msdu_info_s *msdu_info)
  476. {
  477. struct qdf_tso_seg_elem_t *next_seg;
  478. while (free_seg) {
  479. next_seg = free_seg->next;
  480. dp_tx_tso_desc_free(soc,
  481. msdu_info->tx_queue.desc_pool_id,
  482. free_seg);
  483. free_seg = next_seg;
  484. }
  485. }
  486. /**
  487. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  488. * allocated and free them
  489. *
  490. * @soc: soc handle
  491. * @free_num_seg: list of tso number segments
  492. * @msdu_info: msdu descriptor
  493. * Return - void
  494. */
  495. static void dp_tx_free_tso_num_seg_list(
  496. struct dp_soc *soc,
  497. struct qdf_tso_num_seg_elem_t *free_num_seg,
  498. struct dp_tx_msdu_info_s *msdu_info)
  499. {
  500. struct qdf_tso_num_seg_elem_t *next_num_seg;
  501. while (free_num_seg) {
  502. next_num_seg = free_num_seg->next;
  503. dp_tso_num_seg_free(soc,
  504. msdu_info->tx_queue.desc_pool_id,
  505. free_num_seg);
  506. free_num_seg = next_num_seg;
  507. }
  508. }
  509. /**
  510. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  511. * do dma unmap for each segment
  512. *
  513. * @soc: soc handle
  514. * @free_seg: list of tso segments
  515. * @num_seg_desc: tso number segment descriptor
  516. *
  517. * Return - void
  518. */
  519. static void dp_tx_unmap_tso_seg_list(
  520. struct dp_soc *soc,
  521. struct qdf_tso_seg_elem_t *free_seg,
  522. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  523. {
  524. struct qdf_tso_seg_elem_t *next_seg;
  525. if (qdf_unlikely(!num_seg_desc)) {
  526. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  527. return;
  528. }
  529. while (free_seg) {
  530. next_seg = free_seg->next;
  531. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  532. free_seg = next_seg;
  533. }
  534. }
  535. #ifdef FEATURE_TSO_STATS
  536. /**
  537. * dp_tso_get_stats_idx: Retrieve the tso packet id
  538. * @pdev - pdev handle
  539. *
  540. * Return: id
  541. */
  542. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  543. {
  544. uint32_t stats_idx;
  545. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  546. % CDP_MAX_TSO_PACKETS);
  547. return stats_idx;
  548. }
  549. #else
  550. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  551. {
  552. return 0;
  553. }
  554. #endif /* FEATURE_TSO_STATS */
  555. /**
  556. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  557. * free the tso segments descriptor and
  558. * tso num segments descriptor
  559. *
  560. * @soc: soc handle
  561. * @msdu_info: msdu descriptor
  562. * @tso_seg_unmap: flag to show if dma unmap is necessary
  563. *
  564. * Return - void
  565. */
  566. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  567. struct dp_tx_msdu_info_s *msdu_info,
  568. bool tso_seg_unmap)
  569. {
  570. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  571. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  572. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  573. tso_info->tso_num_seg_list;
  574. /* do dma unmap for each segment */
  575. if (tso_seg_unmap)
  576. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  577. /* free all tso number segment descriptor though looks only have 1 */
  578. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  579. /* free all tso segment descriptor */
  580. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  581. }
  582. /**
  583. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  584. * @vdev: virtual device handle
  585. * @msdu: network buffer
  586. * @msdu_info: meta data associated with the msdu
  587. *
  588. * Return: QDF_STATUS_SUCCESS success
  589. */
  590. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  591. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  592. {
  593. struct qdf_tso_seg_elem_t *tso_seg;
  594. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  595. struct dp_soc *soc = vdev->pdev->soc;
  596. struct dp_pdev *pdev = vdev->pdev;
  597. struct qdf_tso_info_t *tso_info;
  598. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  599. tso_info = &msdu_info->u.tso_info;
  600. tso_info->curr_seg = NULL;
  601. tso_info->tso_seg_list = NULL;
  602. tso_info->num_segs = num_seg;
  603. msdu_info->frm_type = dp_tx_frm_tso;
  604. tso_info->tso_num_seg_list = NULL;
  605. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  606. while (num_seg) {
  607. tso_seg = dp_tx_tso_desc_alloc(
  608. soc, msdu_info->tx_queue.desc_pool_id);
  609. if (tso_seg) {
  610. tso_seg->next = tso_info->tso_seg_list;
  611. tso_info->tso_seg_list = tso_seg;
  612. num_seg--;
  613. } else {
  614. dp_err_rl("Failed to alloc tso seg desc");
  615. DP_STATS_INC_PKT(vdev->pdev,
  616. tso_stats.tso_no_mem_dropped, 1,
  617. qdf_nbuf_len(msdu));
  618. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  619. return QDF_STATUS_E_NOMEM;
  620. }
  621. }
  622. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  623. tso_num_seg = dp_tso_num_seg_alloc(soc,
  624. msdu_info->tx_queue.desc_pool_id);
  625. if (tso_num_seg) {
  626. tso_num_seg->next = tso_info->tso_num_seg_list;
  627. tso_info->tso_num_seg_list = tso_num_seg;
  628. } else {
  629. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  630. __func__);
  631. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  632. return QDF_STATUS_E_NOMEM;
  633. }
  634. msdu_info->num_seg =
  635. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  636. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  637. msdu_info->num_seg);
  638. if (!(msdu_info->num_seg)) {
  639. /*
  640. * Free allocated TSO seg desc and number seg desc,
  641. * do unmap for segments if dma map has done.
  642. */
  643. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  644. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  645. return QDF_STATUS_E_INVAL;
  646. }
  647. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  648. msdu, 0, DP_TX_DESC_MAP);
  649. tso_info->curr_seg = tso_info->tso_seg_list;
  650. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  651. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  652. msdu, msdu_info->num_seg);
  653. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  654. tso_info->msdu_stats_idx);
  655. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  656. return QDF_STATUS_SUCCESS;
  657. }
  658. #else
  659. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  660. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  661. {
  662. return QDF_STATUS_E_NOMEM;
  663. }
  664. #endif
  665. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  666. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  667. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  668. /**
  669. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  670. * @vdev: DP Vdev handle
  671. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  672. * @desc_pool_id: Descriptor Pool ID
  673. *
  674. * Return:
  675. */
  676. static
  677. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  678. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  679. {
  680. uint8_t i;
  681. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  682. struct dp_tx_seg_info_s *seg_info;
  683. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  684. struct dp_soc *soc = vdev->pdev->soc;
  685. /* Allocate an extension descriptor */
  686. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  687. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  688. if (!msdu_ext_desc) {
  689. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  690. return NULL;
  691. }
  692. if (msdu_info->exception_fw &&
  693. qdf_unlikely(vdev->mesh_vdev)) {
  694. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  695. &msdu_info->meta_data[0],
  696. sizeof(struct htt_tx_msdu_desc_ext2_t));
  697. qdf_atomic_inc(&soc->num_tx_exception);
  698. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  699. }
  700. switch (msdu_info->frm_type) {
  701. case dp_tx_frm_sg:
  702. case dp_tx_frm_me:
  703. case dp_tx_frm_raw:
  704. seg_info = msdu_info->u.sg_info.curr_seg;
  705. /* Update the buffer pointers in MSDU Extension Descriptor */
  706. for (i = 0; i < seg_info->frag_cnt; i++) {
  707. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  708. seg_info->frags[i].paddr_lo,
  709. seg_info->frags[i].paddr_hi,
  710. seg_info->frags[i].len);
  711. }
  712. break;
  713. case dp_tx_frm_tso:
  714. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  715. &cached_ext_desc[0]);
  716. break;
  717. default:
  718. break;
  719. }
  720. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  721. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  722. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  723. msdu_ext_desc->vaddr);
  724. return msdu_ext_desc;
  725. }
  726. /**
  727. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  728. *
  729. * @skb: skb to be traced
  730. * @msdu_id: msdu_id of the packet
  731. * @vdev_id: vdev_id of the packet
  732. *
  733. * Return: None
  734. */
  735. #ifdef DP_DISABLE_TX_PKT_TRACE
  736. static void dp_tx_trace_pkt(struct dp_soc *soc,
  737. qdf_nbuf_t skb, uint16_t msdu_id,
  738. uint8_t vdev_id)
  739. {
  740. }
  741. #else
  742. static void dp_tx_trace_pkt(struct dp_soc *soc,
  743. qdf_nbuf_t skb, uint16_t msdu_id,
  744. uint8_t vdev_id)
  745. {
  746. if (dp_is_tput_high(soc))
  747. return;
  748. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  749. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  750. DPTRACE(qdf_dp_trace_ptr(skb,
  751. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  752. QDF_TRACE_DEFAULT_PDEV_ID,
  753. qdf_nbuf_data_addr(skb),
  754. sizeof(qdf_nbuf_data(skb)),
  755. msdu_id, vdev_id, 0));
  756. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  757. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  758. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  759. msdu_id, QDF_TX));
  760. }
  761. #endif
  762. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  763. /**
  764. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  765. * exception by the upper layer (OS_IF)
  766. * @soc: DP soc handle
  767. * @nbuf: packet to be transmitted
  768. *
  769. * Returns: 1 if the packet is marked as exception,
  770. * 0, if the packet is not marked as exception.
  771. */
  772. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  773. qdf_nbuf_t nbuf)
  774. {
  775. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  776. }
  777. #else
  778. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  779. qdf_nbuf_t nbuf)
  780. {
  781. return 0;
  782. }
  783. #endif
  784. #ifdef DP_TRAFFIC_END_INDICATION
  785. /**
  786. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  787. * as indication to fw to inform that
  788. * data stream has ended
  789. * @vdev: DP vdev handle
  790. * @nbuf: original buffer from network stack
  791. *
  792. * Return: NULL on failure,
  793. * nbuf on success
  794. */
  795. static inline qdf_nbuf_t
  796. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  797. qdf_nbuf_t nbuf)
  798. {
  799. /* Packet length should be enough to copy upto L3 header */
  800. uint8_t end_nbuf_len = 64;
  801. uint8_t htt_desc_size_aligned;
  802. uint8_t htt_desc_size;
  803. qdf_nbuf_t end_nbuf;
  804. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  805. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  806. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  807. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  808. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  809. if (!end_nbuf) {
  810. end_nbuf = qdf_nbuf_alloc(NULL,
  811. (htt_desc_size_aligned +
  812. end_nbuf_len),
  813. htt_desc_size_aligned,
  814. 8, false);
  815. if (!end_nbuf) {
  816. dp_err("Packet allocation failed");
  817. goto out;
  818. }
  819. } else {
  820. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  821. }
  822. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  823. end_nbuf_len);
  824. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  825. return end_nbuf;
  826. }
  827. out:
  828. return NULL;
  829. }
  830. /**
  831. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  832. * via exception path.
  833. * @vdev: DP vdev handle
  834. * @end_nbuf: skb to send as indication
  835. * @msdu_info: msdu_info of original nbuf
  836. * @peer_id: peer id
  837. *
  838. * Return: None
  839. */
  840. static inline void
  841. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  842. qdf_nbuf_t end_nbuf,
  843. struct dp_tx_msdu_info_s *msdu_info,
  844. uint16_t peer_id)
  845. {
  846. struct dp_tx_msdu_info_s e_msdu_info = {0};
  847. qdf_nbuf_t nbuf;
  848. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  849. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  850. e_msdu_info.tx_queue = msdu_info->tx_queue;
  851. e_msdu_info.tid = msdu_info->tid;
  852. e_msdu_info.exception_fw = 1;
  853. desc_ext->host_tx_desc_pool = 1;
  854. desc_ext->traffic_end_indication = 1;
  855. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  856. peer_id, NULL);
  857. if (nbuf) {
  858. dp_err("Traffic end indication packet tx failed");
  859. qdf_nbuf_free(nbuf);
  860. }
  861. }
  862. /**
  863. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  864. * mark it trafic end indication
  865. * packet.
  866. * @tx_desc: Tx descriptor pointer
  867. * @msdu_info: msdu_info structure pointer
  868. *
  869. * Return: None
  870. */
  871. static inline void
  872. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  873. struct dp_tx_msdu_info_s *msdu_info)
  874. {
  875. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  876. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  877. if (qdf_unlikely(desc_ext->traffic_end_indication))
  878. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  879. }
  880. /**
  881. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  882. * freeing which are associated
  883. * with traffic end indication
  884. * flagged descriptor.
  885. * @soc: dp soc handle
  886. * @desc: Tx descriptor pointer
  887. * @nbuf: buffer pointer
  888. *
  889. * Return: True if packet gets enqueued else false
  890. */
  891. static bool
  892. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  893. struct dp_tx_desc_s *desc,
  894. qdf_nbuf_t nbuf)
  895. {
  896. struct dp_vdev *vdev = NULL;
  897. if (qdf_unlikely((desc->flags &
  898. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  899. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  900. DP_MOD_ID_TX_COMP);
  901. if (vdev) {
  902. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  903. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  904. return true;
  905. }
  906. }
  907. return false;
  908. }
  909. /**
  910. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  911. * enable/disable status
  912. * @vdev: dp vdev handle
  913. *
  914. * Return: True if feature is enable else false
  915. */
  916. static inline bool
  917. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  918. {
  919. return qdf_unlikely(vdev->traffic_end_ind_en);
  920. }
  921. static inline qdf_nbuf_t
  922. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  923. struct dp_tx_msdu_info_s *msdu_info,
  924. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  925. {
  926. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  927. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  928. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  929. if (qdf_unlikely(end_nbuf))
  930. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  931. msdu_info, peer_id);
  932. return nbuf;
  933. }
  934. #else
  935. static inline qdf_nbuf_t
  936. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  937. qdf_nbuf_t nbuf)
  938. {
  939. return NULL;
  940. }
  941. static inline void
  942. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  943. qdf_nbuf_t end_nbuf,
  944. struct dp_tx_msdu_info_s *msdu_info,
  945. uint16_t peer_id)
  946. {}
  947. static inline void
  948. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  949. struct dp_tx_msdu_info_s *msdu_info)
  950. {}
  951. static inline bool
  952. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  953. struct dp_tx_desc_s *desc,
  954. qdf_nbuf_t nbuf)
  955. {
  956. return false;
  957. }
  958. static inline bool
  959. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  960. {
  961. return false;
  962. }
  963. static inline qdf_nbuf_t
  964. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  965. struct dp_tx_msdu_info_s *msdu_info,
  966. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  967. {
  968. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  969. }
  970. #endif
  971. /**
  972. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  973. * @vdev: DP vdev handle
  974. * @nbuf: skb
  975. * @desc_pool_id: Descriptor pool ID
  976. * @meta_data: Metadata to the fw
  977. * @tx_exc_metadata: Handle that holds exception path metadata
  978. * Allocate and prepare Tx descriptor with msdu information.
  979. *
  980. * Return: Pointer to Tx Descriptor on success,
  981. * NULL on failure
  982. */
  983. static
  984. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  985. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  986. struct dp_tx_msdu_info_s *msdu_info,
  987. struct cdp_tx_exception_metadata *tx_exc_metadata)
  988. {
  989. uint8_t align_pad;
  990. uint8_t is_exception = 0;
  991. uint8_t htt_hdr_size;
  992. struct dp_tx_desc_s *tx_desc;
  993. struct dp_pdev *pdev = vdev->pdev;
  994. struct dp_soc *soc = pdev->soc;
  995. if (dp_tx_limit_check(vdev))
  996. return NULL;
  997. /* Allocate software Tx descriptor */
  998. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  999. if (qdf_unlikely(!tx_desc)) {
  1000. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1001. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1002. return NULL;
  1003. }
  1004. dp_tx_outstanding_inc(pdev);
  1005. /* Initialize the SW tx descriptor */
  1006. tx_desc->nbuf = nbuf;
  1007. tx_desc->frm_type = dp_tx_frm_std;
  1008. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1009. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1010. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1011. tx_desc->vdev_id = vdev->vdev_id;
  1012. tx_desc->pdev = pdev;
  1013. tx_desc->msdu_ext_desc = NULL;
  1014. tx_desc->pkt_offset = 0;
  1015. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1016. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1017. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1018. if (qdf_unlikely(vdev->multipass_en)) {
  1019. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1020. goto failure;
  1021. }
  1022. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1023. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1024. is_exception = 1;
  1025. /*
  1026. * For special modes (vdev_type == ocb or mesh), data frames should be
  1027. * transmitted using varying transmit parameters (tx spec) which include
  1028. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1029. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1030. * These frames are sent as exception packets to firmware.
  1031. *
  1032. * HW requirement is that metadata should always point to a
  1033. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1034. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1035. * to get 8-byte aligned start address along with align_pad added
  1036. *
  1037. * |-----------------------------|
  1038. * | |
  1039. * |-----------------------------| <-----Buffer Pointer Address given
  1040. * | | ^ in HW descriptor (aligned)
  1041. * | HTT Metadata | |
  1042. * | | |
  1043. * | | | Packet Offset given in descriptor
  1044. * | | |
  1045. * |-----------------------------| |
  1046. * | Alignment Pad | v
  1047. * |-----------------------------| <----- Actual buffer start address
  1048. * | SKB Data | (Unaligned)
  1049. * | |
  1050. * | |
  1051. * | |
  1052. * | |
  1053. * | |
  1054. * |-----------------------------|
  1055. */
  1056. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1057. (vdev->opmode == wlan_op_mode_ocb) ||
  1058. (tx_exc_metadata &&
  1059. tx_exc_metadata->is_tx_sniffer)) {
  1060. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1061. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1062. DP_STATS_INC(vdev,
  1063. tx_i.dropped.headroom_insufficient, 1);
  1064. goto failure;
  1065. }
  1066. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1067. dp_tx_err("qdf_nbuf_push_head failed");
  1068. goto failure;
  1069. }
  1070. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1071. msdu_info);
  1072. if (htt_hdr_size == 0)
  1073. goto failure;
  1074. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1075. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1076. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1077. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1078. msdu_info);
  1079. is_exception = 1;
  1080. tx_desc->length -= tx_desc->pkt_offset;
  1081. }
  1082. #if !TQM_BYPASS_WAR
  1083. if (is_exception || tx_exc_metadata)
  1084. #endif
  1085. {
  1086. /* Temporary WAR due to TQM VP issues */
  1087. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1088. qdf_atomic_inc(&soc->num_tx_exception);
  1089. }
  1090. return tx_desc;
  1091. failure:
  1092. dp_tx_desc_release(tx_desc, desc_pool_id);
  1093. return NULL;
  1094. }
  1095. /**
  1096. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1097. * @vdev: DP vdev handle
  1098. * @nbuf: skb
  1099. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1100. * @desc_pool_id : Descriptor Pool ID
  1101. *
  1102. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1103. * information. For frames wth fragments, allocate and prepare
  1104. * an MSDU extension descriptor
  1105. *
  1106. * Return: Pointer to Tx Descriptor on success,
  1107. * NULL on failure
  1108. */
  1109. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1110. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1111. uint8_t desc_pool_id)
  1112. {
  1113. struct dp_tx_desc_s *tx_desc;
  1114. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1115. struct dp_pdev *pdev = vdev->pdev;
  1116. struct dp_soc *soc = pdev->soc;
  1117. if (dp_tx_limit_check(vdev))
  1118. return NULL;
  1119. /* Allocate software Tx descriptor */
  1120. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1121. if (!tx_desc) {
  1122. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1123. return NULL;
  1124. }
  1125. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1126. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1127. dp_tx_outstanding_inc(pdev);
  1128. /* Initialize the SW tx descriptor */
  1129. tx_desc->nbuf = nbuf;
  1130. tx_desc->frm_type = msdu_info->frm_type;
  1131. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1132. tx_desc->vdev_id = vdev->vdev_id;
  1133. tx_desc->pdev = pdev;
  1134. tx_desc->pkt_offset = 0;
  1135. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1136. /* Handle scattered frames - TSO/SG/ME */
  1137. /* Allocate and prepare an extension descriptor for scattered frames */
  1138. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1139. if (!msdu_ext_desc) {
  1140. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1141. goto failure;
  1142. }
  1143. #if TQM_BYPASS_WAR
  1144. /* Temporary WAR due to TQM VP issues */
  1145. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1146. qdf_atomic_inc(&soc->num_tx_exception);
  1147. #endif
  1148. if (qdf_unlikely(msdu_info->exception_fw))
  1149. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1150. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1151. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1152. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1153. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1154. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1155. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1156. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1157. else
  1158. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1159. return tx_desc;
  1160. failure:
  1161. dp_tx_desc_release(tx_desc, desc_pool_id);
  1162. return NULL;
  1163. }
  1164. /**
  1165. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1166. * @vdev: DP vdev handle
  1167. * @nbuf: buffer pointer
  1168. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1169. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1170. * descriptor
  1171. *
  1172. * Return:
  1173. */
  1174. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1175. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1176. {
  1177. qdf_nbuf_t curr_nbuf = NULL;
  1178. uint16_t total_len = 0;
  1179. qdf_dma_addr_t paddr;
  1180. int32_t i;
  1181. int32_t mapped_buf_num = 0;
  1182. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1183. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1184. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1185. /* Continue only if frames are of DATA type */
  1186. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1187. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1188. dp_tx_debug("Pkt. recd is of not data type");
  1189. goto error;
  1190. }
  1191. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1192. if (vdev->raw_mode_war &&
  1193. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1194. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1195. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1196. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1197. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1198. /*
  1199. * Number of nbuf's must not exceed the size of the frags
  1200. * array in seg_info.
  1201. */
  1202. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1203. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1204. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1205. goto error;
  1206. }
  1207. if (QDF_STATUS_SUCCESS !=
  1208. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1209. curr_nbuf,
  1210. QDF_DMA_TO_DEVICE,
  1211. curr_nbuf->len)) {
  1212. dp_tx_err("%s dma map error ", __func__);
  1213. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1214. goto error;
  1215. }
  1216. /* Update the count of mapped nbuf's */
  1217. mapped_buf_num++;
  1218. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1219. seg_info->frags[i].paddr_lo = paddr;
  1220. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1221. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1222. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1223. total_len += qdf_nbuf_len(curr_nbuf);
  1224. }
  1225. seg_info->frag_cnt = i;
  1226. seg_info->total_len = total_len;
  1227. seg_info->next = NULL;
  1228. sg_info->curr_seg = seg_info;
  1229. msdu_info->frm_type = dp_tx_frm_raw;
  1230. msdu_info->num_seg = 1;
  1231. return nbuf;
  1232. error:
  1233. i = 0;
  1234. while (nbuf) {
  1235. curr_nbuf = nbuf;
  1236. if (i < mapped_buf_num) {
  1237. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1238. QDF_DMA_TO_DEVICE,
  1239. curr_nbuf->len);
  1240. i++;
  1241. }
  1242. nbuf = qdf_nbuf_next(nbuf);
  1243. qdf_nbuf_free(curr_nbuf);
  1244. }
  1245. return NULL;
  1246. }
  1247. /**
  1248. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1249. * @soc: DP soc handle
  1250. * @nbuf: Buffer pointer
  1251. *
  1252. * unmap the chain of nbufs that belong to this RAW frame.
  1253. *
  1254. * Return: None
  1255. */
  1256. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1257. qdf_nbuf_t nbuf)
  1258. {
  1259. qdf_nbuf_t cur_nbuf = nbuf;
  1260. do {
  1261. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1262. QDF_DMA_TO_DEVICE,
  1263. cur_nbuf->len);
  1264. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1265. } while (cur_nbuf);
  1266. }
  1267. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1268. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1269. qdf_nbuf_t nbuf)
  1270. {
  1271. qdf_nbuf_t nbuf_local;
  1272. struct dp_vdev *vdev_local = vdev_hdl;
  1273. do {
  1274. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1275. break;
  1276. nbuf_local = nbuf;
  1277. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1278. htt_cmn_pkt_type_raw))
  1279. break;
  1280. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1281. break;
  1282. else if (qdf_nbuf_is_tso((nbuf_local)))
  1283. break;
  1284. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1285. (nbuf_local),
  1286. NULL, 1, 0);
  1287. } while (0);
  1288. }
  1289. #endif
  1290. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1291. /**
  1292. * dp_tx_update_stats() - Update soc level tx stats
  1293. * @soc: DP soc handle
  1294. * @tx_desc: TX descriptor reference
  1295. * @ring_id: TCL ring id
  1296. *
  1297. * Returns: none
  1298. */
  1299. void dp_tx_update_stats(struct dp_soc *soc,
  1300. struct dp_tx_desc_s *tx_desc,
  1301. uint8_t ring_id)
  1302. {
  1303. uint32_t stats_len = 0;
  1304. if (tx_desc->frm_type == dp_tx_frm_tso)
  1305. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1306. else
  1307. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1308. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1309. }
  1310. int
  1311. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1312. struct dp_tx_desc_s *tx_desc,
  1313. uint8_t tid,
  1314. struct dp_tx_msdu_info_s *msdu_info,
  1315. uint8_t ring_id)
  1316. {
  1317. struct dp_swlm *swlm = &soc->swlm;
  1318. union swlm_data swlm_query_data;
  1319. struct dp_swlm_tcl_data tcl_data;
  1320. QDF_STATUS status;
  1321. int ret;
  1322. if (!swlm->is_enabled)
  1323. return msdu_info->skip_hp_update;
  1324. tcl_data.nbuf = tx_desc->nbuf;
  1325. tcl_data.tid = tid;
  1326. tcl_data.ring_id = ring_id;
  1327. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1328. tcl_data.pkt_len =
  1329. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1330. } else {
  1331. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1332. }
  1333. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1334. swlm_query_data.tcl_data = &tcl_data;
  1335. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1336. if (QDF_IS_STATUS_ERROR(status)) {
  1337. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1338. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1339. return 0;
  1340. }
  1341. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1342. if (ret) {
  1343. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1344. } else {
  1345. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1346. }
  1347. return ret;
  1348. }
  1349. void
  1350. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1351. int coalesce)
  1352. {
  1353. if (coalesce)
  1354. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1355. else
  1356. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1357. }
  1358. static inline void
  1359. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1360. {
  1361. if (((i + 1) < msdu_info->num_seg))
  1362. msdu_info->skip_hp_update = 1;
  1363. else
  1364. msdu_info->skip_hp_update = 0;
  1365. }
  1366. static inline void
  1367. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1368. {
  1369. hal_ring_handle_t hal_ring_hdl =
  1370. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1371. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1372. dp_err("Fillmore: SRNG access start failed");
  1373. return;
  1374. }
  1375. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1376. }
  1377. static inline void
  1378. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1379. QDF_STATUS status,
  1380. struct dp_tx_msdu_info_s *msdu_info)
  1381. {
  1382. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1383. dp_flush_tcp_hp(soc,
  1384. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1385. }
  1386. }
  1387. #else
  1388. static inline void
  1389. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1390. {
  1391. }
  1392. static inline void
  1393. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1394. QDF_STATUS status,
  1395. struct dp_tx_msdu_info_s *msdu_info)
  1396. {
  1397. }
  1398. #endif
  1399. #ifdef FEATURE_RUNTIME_PM
  1400. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1401. {
  1402. int ret;
  1403. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1404. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1405. return ret;
  1406. }
  1407. /**
  1408. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1409. * @soc: Datapath soc handle
  1410. * @hal_ring_hdl: HAL ring handle
  1411. * @coalesce: Coalesce the current write or not
  1412. *
  1413. * Wrapper for HAL ring access end for data transmission for
  1414. * FEATURE_RUNTIME_PM
  1415. *
  1416. * Returns: none
  1417. */
  1418. void
  1419. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1420. hal_ring_handle_t hal_ring_hdl,
  1421. int coalesce)
  1422. {
  1423. int ret;
  1424. /*
  1425. * Avoid runtime get and put APIs under high throughput scenarios.
  1426. */
  1427. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1428. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1429. return;
  1430. }
  1431. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1432. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1433. if (hif_system_pm_state_check(soc->hif_handle)) {
  1434. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1435. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1436. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1437. } else {
  1438. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1439. }
  1440. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1441. } else {
  1442. dp_runtime_get(soc);
  1443. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1444. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1445. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1446. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1447. dp_runtime_put(soc);
  1448. }
  1449. }
  1450. #else
  1451. #ifdef DP_POWER_SAVE
  1452. void
  1453. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1454. hal_ring_handle_t hal_ring_hdl,
  1455. int coalesce)
  1456. {
  1457. if (hif_system_pm_state_check(soc->hif_handle)) {
  1458. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1459. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1460. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1461. } else {
  1462. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1463. }
  1464. }
  1465. #endif
  1466. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1467. {
  1468. return 0;
  1469. }
  1470. #endif
  1471. /**
  1472. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1473. * @vdev: DP vdev handle
  1474. * @nbuf: skb
  1475. *
  1476. * Extract the DSCP or PCP information from frame and map into TID value.
  1477. *
  1478. * Return: void
  1479. */
  1480. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1481. struct dp_tx_msdu_info_s *msdu_info)
  1482. {
  1483. uint8_t tos = 0, dscp_tid_override = 0;
  1484. uint8_t *hdr_ptr, *L3datap;
  1485. uint8_t is_mcast = 0;
  1486. qdf_ether_header_t *eh = NULL;
  1487. qdf_ethervlan_header_t *evh = NULL;
  1488. uint16_t ether_type;
  1489. qdf_llc_t *llcHdr;
  1490. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1491. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1492. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1493. eh = (qdf_ether_header_t *)nbuf->data;
  1494. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1495. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1496. } else {
  1497. qdf_dot3_qosframe_t *qos_wh =
  1498. (qdf_dot3_qosframe_t *) nbuf->data;
  1499. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1500. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1501. return;
  1502. }
  1503. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1504. ether_type = eh->ether_type;
  1505. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1506. /*
  1507. * Check if packet is dot3 or eth2 type.
  1508. */
  1509. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1510. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1511. sizeof(*llcHdr));
  1512. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1513. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1514. sizeof(*llcHdr);
  1515. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1516. + sizeof(*llcHdr) +
  1517. sizeof(qdf_net_vlanhdr_t));
  1518. } else {
  1519. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1520. sizeof(*llcHdr);
  1521. }
  1522. } else {
  1523. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1524. evh = (qdf_ethervlan_header_t *) eh;
  1525. ether_type = evh->ether_type;
  1526. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1527. }
  1528. }
  1529. /*
  1530. * Find priority from IP TOS DSCP field
  1531. */
  1532. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1533. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1534. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1535. /* Only for unicast frames */
  1536. if (!is_mcast) {
  1537. /* send it on VO queue */
  1538. msdu_info->tid = DP_VO_TID;
  1539. }
  1540. } else {
  1541. /*
  1542. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1543. * from TOS byte.
  1544. */
  1545. tos = ip->ip_tos;
  1546. dscp_tid_override = 1;
  1547. }
  1548. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1549. /* TODO
  1550. * use flowlabel
  1551. *igmpmld cases to be handled in phase 2
  1552. */
  1553. unsigned long ver_pri_flowlabel;
  1554. unsigned long pri;
  1555. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1556. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1557. DP_IPV6_PRIORITY_SHIFT;
  1558. tos = pri;
  1559. dscp_tid_override = 1;
  1560. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1561. msdu_info->tid = DP_VO_TID;
  1562. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1563. /* Only for unicast frames */
  1564. if (!is_mcast) {
  1565. /* send ucast arp on VO queue */
  1566. msdu_info->tid = DP_VO_TID;
  1567. }
  1568. }
  1569. /*
  1570. * Assign all MCAST packets to BE
  1571. */
  1572. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1573. if (is_mcast) {
  1574. tos = 0;
  1575. dscp_tid_override = 1;
  1576. }
  1577. }
  1578. if (dscp_tid_override == 1) {
  1579. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1580. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1581. }
  1582. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1583. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1584. return;
  1585. }
  1586. /**
  1587. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1588. * @vdev: DP vdev handle
  1589. * @nbuf: skb
  1590. *
  1591. * Software based TID classification is required when more than 2 DSCP-TID
  1592. * mapping tables are needed.
  1593. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1594. *
  1595. * Return: void
  1596. */
  1597. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1598. struct dp_tx_msdu_info_s *msdu_info)
  1599. {
  1600. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1601. /*
  1602. * skip_sw_tid_classification flag will set in below cases-
  1603. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1604. * 2. hlos_tid_override enabled for vdev
  1605. * 3. mesh mode enabled for vdev
  1606. */
  1607. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1608. /* Update tid in msdu_info from skb priority */
  1609. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1610. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1611. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1612. if (tid == DP_TX_INVALID_QOS_TAG)
  1613. return;
  1614. msdu_info->tid = tid;
  1615. return;
  1616. }
  1617. return;
  1618. }
  1619. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1620. }
  1621. #ifdef FEATURE_WLAN_TDLS
  1622. /**
  1623. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1624. * @soc: datapath SOC
  1625. * @vdev: datapath vdev
  1626. * @tx_desc: TX descriptor
  1627. *
  1628. * Return: None
  1629. */
  1630. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1631. struct dp_vdev *vdev,
  1632. struct dp_tx_desc_s *tx_desc)
  1633. {
  1634. if (vdev) {
  1635. if (vdev->is_tdls_frame) {
  1636. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1637. vdev->is_tdls_frame = false;
  1638. }
  1639. }
  1640. }
  1641. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1642. {
  1643. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1644. switch (soc->arch_id) {
  1645. case CDP_ARCH_TYPE_LI:
  1646. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1647. break;
  1648. case CDP_ARCH_TYPE_BE:
  1649. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1650. break;
  1651. default:
  1652. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1653. QDF_BUG(0);
  1654. }
  1655. return tx_status;
  1656. }
  1657. /**
  1658. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1659. * @soc: dp_soc handle
  1660. * @tx_desc: TX descriptor
  1661. * @vdev: datapath vdev handle
  1662. *
  1663. * Return: None
  1664. */
  1665. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1666. struct dp_tx_desc_s *tx_desc)
  1667. {
  1668. uint8_t tx_status = 0;
  1669. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1670. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1671. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1672. DP_MOD_ID_TDLS);
  1673. if (qdf_unlikely(!vdev)) {
  1674. dp_err_rl("vdev is null!");
  1675. goto error;
  1676. }
  1677. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1678. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1679. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1680. if (vdev->tx_non_std_data_callback.func) {
  1681. qdf_nbuf_set_next(nbuf, NULL);
  1682. vdev->tx_non_std_data_callback.func(
  1683. vdev->tx_non_std_data_callback.ctxt,
  1684. nbuf, tx_status);
  1685. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1686. return;
  1687. } else {
  1688. dp_err_rl("callback func is null");
  1689. }
  1690. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1691. error:
  1692. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1693. qdf_nbuf_free(nbuf);
  1694. }
  1695. /**
  1696. * dp_tx_msdu_single_map() - do nbuf map
  1697. * @vdev: DP vdev handle
  1698. * @tx_desc: DP TX descriptor pointer
  1699. * @nbuf: skb pointer
  1700. *
  1701. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1702. * operation done in other component.
  1703. *
  1704. * Return: QDF_STATUS
  1705. */
  1706. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1707. struct dp_tx_desc_s *tx_desc,
  1708. qdf_nbuf_t nbuf)
  1709. {
  1710. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1711. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1712. nbuf,
  1713. QDF_DMA_TO_DEVICE,
  1714. nbuf->len);
  1715. else
  1716. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1717. QDF_DMA_TO_DEVICE);
  1718. }
  1719. #else
  1720. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1721. struct dp_vdev *vdev,
  1722. struct dp_tx_desc_s *tx_desc)
  1723. {
  1724. }
  1725. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1726. struct dp_tx_desc_s *tx_desc)
  1727. {
  1728. }
  1729. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1730. struct dp_tx_desc_s *tx_desc,
  1731. qdf_nbuf_t nbuf)
  1732. {
  1733. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1734. nbuf,
  1735. QDF_DMA_TO_DEVICE,
  1736. nbuf->len);
  1737. }
  1738. #endif
  1739. static inline
  1740. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1741. struct dp_tx_desc_s *tx_desc,
  1742. qdf_nbuf_t nbuf)
  1743. {
  1744. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1745. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1746. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1747. return 0;
  1748. return qdf_nbuf_mapped_paddr_get(nbuf);
  1749. }
  1750. static inline
  1751. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1752. {
  1753. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1754. desc->nbuf,
  1755. desc->dma_addr,
  1756. QDF_DMA_TO_DEVICE,
  1757. desc->length);
  1758. }
  1759. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1760. static inline
  1761. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1762. struct dp_tx_desc_s *tx_desc,
  1763. qdf_nbuf_t nbuf)
  1764. {
  1765. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1766. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1767. (void *)(nbuf->data + nbuf->len));
  1768. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1769. } else {
  1770. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1771. }
  1772. }
  1773. static inline
  1774. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1775. struct dp_tx_desc_s *desc)
  1776. {
  1777. if (qdf_unlikely(!(desc->flags & DP_TX_DESC_FLAG_SIMPLE)))
  1778. return dp_tx_nbuf_unmap_regular(soc, desc);
  1779. }
  1780. #else
  1781. static inline
  1782. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1783. struct dp_tx_desc_s *tx_desc,
  1784. qdf_nbuf_t nbuf)
  1785. {
  1786. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1787. }
  1788. static inline
  1789. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1790. struct dp_tx_desc_s *desc)
  1791. {
  1792. return dp_tx_nbuf_unmap_regular(soc, desc);
  1793. }
  1794. #endif
  1795. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1796. static inline
  1797. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1798. {
  1799. dp_tx_nbuf_unmap(soc, desc);
  1800. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1801. }
  1802. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1803. {
  1804. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1805. dp_tx_nbuf_unmap(soc, desc);
  1806. }
  1807. #else
  1808. static inline
  1809. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1810. {
  1811. }
  1812. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1813. {
  1814. dp_tx_nbuf_unmap(soc, desc);
  1815. }
  1816. #endif
  1817. #ifdef MESH_MODE_SUPPORT
  1818. /**
  1819. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1820. * @soc: datapath SOC
  1821. * @vdev: datapath vdev
  1822. * @tx_desc: TX descriptor
  1823. *
  1824. * Return: None
  1825. */
  1826. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1827. struct dp_vdev *vdev,
  1828. struct dp_tx_desc_s *tx_desc)
  1829. {
  1830. if (qdf_unlikely(vdev->mesh_vdev))
  1831. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1832. }
  1833. /**
  1834. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1835. * @soc: dp_soc handle
  1836. * @tx_desc: TX descriptor
  1837. * @delayed_free: delay the nbuf free
  1838. *
  1839. * Return: nbuf to be freed late
  1840. */
  1841. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1842. struct dp_tx_desc_s *tx_desc,
  1843. bool delayed_free)
  1844. {
  1845. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1846. struct dp_vdev *vdev = NULL;
  1847. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1848. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1849. if (vdev)
  1850. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1851. if (delayed_free)
  1852. return nbuf;
  1853. qdf_nbuf_free(nbuf);
  1854. } else {
  1855. if (vdev && vdev->osif_tx_free_ext) {
  1856. vdev->osif_tx_free_ext((nbuf));
  1857. } else {
  1858. if (delayed_free)
  1859. return nbuf;
  1860. qdf_nbuf_free(nbuf);
  1861. }
  1862. }
  1863. if (vdev)
  1864. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1865. return NULL;
  1866. }
  1867. #else
  1868. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1869. struct dp_vdev *vdev,
  1870. struct dp_tx_desc_s *tx_desc)
  1871. {
  1872. }
  1873. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1874. struct dp_tx_desc_s *tx_desc,
  1875. bool delayed_free)
  1876. {
  1877. return NULL;
  1878. }
  1879. #endif
  1880. /**
  1881. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1882. * @vdev: DP vdev handle
  1883. * @nbuf: skb
  1884. *
  1885. * Return: 1 if frame needs to be dropped else 0
  1886. */
  1887. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1888. {
  1889. struct dp_pdev *pdev = NULL;
  1890. struct dp_ast_entry *src_ast_entry = NULL;
  1891. struct dp_ast_entry *dst_ast_entry = NULL;
  1892. struct dp_soc *soc = NULL;
  1893. qdf_assert(vdev);
  1894. pdev = vdev->pdev;
  1895. qdf_assert(pdev);
  1896. soc = pdev->soc;
  1897. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1898. (soc, dstmac, vdev->pdev->pdev_id);
  1899. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1900. (soc, srcmac, vdev->pdev->pdev_id);
  1901. if (dst_ast_entry && src_ast_entry) {
  1902. if (dst_ast_entry->peer_id ==
  1903. src_ast_entry->peer_id)
  1904. return 1;
  1905. }
  1906. return 0;
  1907. }
  1908. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1909. defined(WLAN_MCAST_MLO)
  1910. /* MLO peer id for reinject*/
  1911. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1912. /* MLO vdev id inc offset */
  1913. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1914. static inline void
  1915. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1916. {
  1917. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1918. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1919. qdf_atomic_inc(&soc->num_tx_exception);
  1920. }
  1921. }
  1922. static inline void
  1923. dp_tx_update_mcast_param(uint16_t peer_id,
  1924. uint16_t *htt_tcl_metadata,
  1925. struct dp_vdev *vdev,
  1926. struct dp_tx_msdu_info_s *msdu_info)
  1927. {
  1928. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1929. *htt_tcl_metadata = 0;
  1930. DP_TX_TCL_METADATA_TYPE_SET(
  1931. *htt_tcl_metadata,
  1932. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1933. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1934. msdu_info->gsn);
  1935. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1936. if (qdf_unlikely(vdev->nawds_enabled))
  1937. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  1938. *htt_tcl_metadata, 1);
  1939. } else {
  1940. msdu_info->vdev_id = vdev->vdev_id;
  1941. }
  1942. }
  1943. #else
  1944. static inline void
  1945. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1946. {
  1947. }
  1948. static inline void
  1949. dp_tx_update_mcast_param(uint16_t peer_id,
  1950. uint16_t *htt_tcl_metadata,
  1951. struct dp_vdev *vdev,
  1952. struct dp_tx_msdu_info_s *msdu_info)
  1953. {
  1954. }
  1955. #endif
  1956. /**
  1957. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1958. * @vdev: DP vdev handle
  1959. * @nbuf: skb
  1960. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1961. * @meta_data: Metadata to the fw
  1962. * @tx_q: Tx queue to be used for this Tx frame
  1963. * @peer_id: peer_id of the peer in case of NAWDS frames
  1964. * @tx_exc_metadata: Handle that holds exception path metadata
  1965. *
  1966. * Return: NULL on success,
  1967. * nbuf when it fails to send
  1968. */
  1969. qdf_nbuf_t
  1970. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1971. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1972. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1973. {
  1974. struct dp_pdev *pdev = vdev->pdev;
  1975. struct dp_soc *soc = pdev->soc;
  1976. struct dp_tx_desc_s *tx_desc;
  1977. QDF_STATUS status;
  1978. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1979. uint16_t htt_tcl_metadata = 0;
  1980. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1981. uint8_t tid = msdu_info->tid;
  1982. struct cdp_tid_tx_stats *tid_stats = NULL;
  1983. qdf_dma_addr_t paddr;
  1984. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1985. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1986. msdu_info, tx_exc_metadata);
  1987. if (!tx_desc) {
  1988. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1989. vdev, tx_q->desc_pool_id);
  1990. drop_code = TX_DESC_ERR;
  1991. goto fail_return;
  1992. }
  1993. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1994. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1995. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1996. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1997. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1998. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1999. DP_TCL_METADATA_TYPE_PEER_BASED);
  2000. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2001. peer_id);
  2002. dp_tx_bypass_reinjection(soc, tx_desc);
  2003. } else
  2004. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2005. if (msdu_info->exception_fw)
  2006. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2007. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2008. !pdev->enhanced_stats_en);
  2009. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2010. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2011. if (!paddr) {
  2012. /* Handle failure */
  2013. dp_err("qdf_nbuf_map failed");
  2014. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2015. drop_code = TX_DMA_MAP_ERR;
  2016. goto release_desc;
  2017. }
  2018. tx_desc->dma_addr = paddr;
  2019. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2020. tx_desc->id, DP_TX_DESC_MAP);
  2021. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2022. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2023. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2024. htt_tcl_metadata,
  2025. tx_exc_metadata, msdu_info);
  2026. if (status != QDF_STATUS_SUCCESS) {
  2027. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2028. tx_desc, tx_q->ring_id);
  2029. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2030. tx_desc->id, DP_TX_DESC_UNMAP);
  2031. dp_tx_nbuf_unmap(soc, tx_desc);
  2032. drop_code = TX_HW_ENQUEUE;
  2033. goto release_desc;
  2034. }
  2035. return NULL;
  2036. release_desc:
  2037. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2038. fail_return:
  2039. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2040. tid_stats = &pdev->stats.tid_stats.
  2041. tid_tx_stats[tx_q->ring_id][tid];
  2042. tid_stats->swdrop_cnt[drop_code]++;
  2043. return nbuf;
  2044. }
  2045. /**
  2046. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2047. * @soc: Soc handle
  2048. * @desc: software Tx descriptor to be processed
  2049. * @delayed_free: defer freeing of nbuf
  2050. *
  2051. * Return: nbuf to be freed later
  2052. */
  2053. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2054. bool delayed_free)
  2055. {
  2056. qdf_nbuf_t nbuf = desc->nbuf;
  2057. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2058. /* nbuf already freed in vdev detach path */
  2059. if (!nbuf)
  2060. return NULL;
  2061. /* If it is TDLS mgmt, don't unmap or free the frame */
  2062. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2063. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2064. return NULL;
  2065. }
  2066. /* 0 : MSDU buffer, 1 : MLE */
  2067. if (desc->msdu_ext_desc) {
  2068. /* TSO free */
  2069. if (hal_tx_ext_desc_get_tso_enable(
  2070. desc->msdu_ext_desc->vaddr)) {
  2071. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2072. desc->id, DP_TX_COMP_MSDU_EXT);
  2073. dp_tx_tso_seg_history_add(soc,
  2074. desc->msdu_ext_desc->tso_desc,
  2075. desc->nbuf, desc->id, type);
  2076. /* unmap eash TSO seg before free the nbuf */
  2077. dp_tx_tso_unmap_segment(soc,
  2078. desc->msdu_ext_desc->tso_desc,
  2079. desc->msdu_ext_desc->
  2080. tso_num_desc);
  2081. goto nbuf_free;
  2082. }
  2083. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2084. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2085. qdf_dma_addr_t iova;
  2086. uint32_t frag_len;
  2087. uint32_t i;
  2088. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2089. QDF_DMA_TO_DEVICE,
  2090. qdf_nbuf_headlen(nbuf));
  2091. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2092. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2093. &iova,
  2094. &frag_len);
  2095. if (!iova || !frag_len)
  2096. break;
  2097. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2098. QDF_DMA_TO_DEVICE);
  2099. }
  2100. goto nbuf_free;
  2101. }
  2102. }
  2103. /* If it's ME frame, dont unmap the cloned nbuf's */
  2104. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2105. goto nbuf_free;
  2106. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2107. dp_tx_unmap(soc, desc);
  2108. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2109. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2110. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2111. return NULL;
  2112. nbuf_free:
  2113. if (delayed_free)
  2114. return nbuf;
  2115. qdf_nbuf_free(nbuf);
  2116. return NULL;
  2117. }
  2118. /**
  2119. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2120. * @soc: DP soc handle
  2121. * @nbuf: skb
  2122. * @msdu_info: MSDU info
  2123. *
  2124. * Return: None
  2125. */
  2126. static inline void
  2127. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2128. struct dp_tx_msdu_info_s *msdu_info)
  2129. {
  2130. uint32_t cur_idx;
  2131. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2132. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2133. qdf_nbuf_headlen(nbuf));
  2134. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2135. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2136. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2137. seg->frags[cur_idx].paddr_hi) << 32),
  2138. seg->frags[cur_idx].len,
  2139. QDF_DMA_TO_DEVICE);
  2140. }
  2141. /**
  2142. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2143. * @vdev: DP vdev handle
  2144. * @nbuf: skb
  2145. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2146. *
  2147. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2148. *
  2149. * Return: NULL on success,
  2150. * nbuf when it fails to send
  2151. */
  2152. #if QDF_LOCK_STATS
  2153. noinline
  2154. #else
  2155. #endif
  2156. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2157. struct dp_tx_msdu_info_s *msdu_info)
  2158. {
  2159. uint32_t i;
  2160. struct dp_pdev *pdev = vdev->pdev;
  2161. struct dp_soc *soc = pdev->soc;
  2162. struct dp_tx_desc_s *tx_desc;
  2163. bool is_cce_classified = false;
  2164. QDF_STATUS status;
  2165. uint16_t htt_tcl_metadata = 0;
  2166. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2167. struct cdp_tid_tx_stats *tid_stats = NULL;
  2168. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2169. if (msdu_info->frm_type == dp_tx_frm_me)
  2170. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2171. i = 0;
  2172. /* Print statement to track i and num_seg */
  2173. /*
  2174. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2175. * descriptors using information in msdu_info
  2176. */
  2177. while (i < msdu_info->num_seg) {
  2178. /*
  2179. * Setup Tx descriptor for an MSDU, and MSDU extension
  2180. * descriptor
  2181. */
  2182. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2183. tx_q->desc_pool_id);
  2184. if (!tx_desc) {
  2185. if (msdu_info->frm_type == dp_tx_frm_me) {
  2186. prep_desc_fail++;
  2187. dp_tx_me_free_buf(pdev,
  2188. (void *)(msdu_info->u.sg_info
  2189. .curr_seg->frags[0].vaddr));
  2190. if (prep_desc_fail == msdu_info->num_seg) {
  2191. /*
  2192. * Unmap is needed only if descriptor
  2193. * preparation failed for all segments.
  2194. */
  2195. qdf_nbuf_unmap(soc->osdev,
  2196. msdu_info->u.sg_info.
  2197. curr_seg->nbuf,
  2198. QDF_DMA_TO_DEVICE);
  2199. }
  2200. /*
  2201. * Free the nbuf for the current segment
  2202. * and make it point to the next in the list.
  2203. * For me, there are as many segments as there
  2204. * are no of clients.
  2205. */
  2206. qdf_nbuf_free(msdu_info->u.sg_info
  2207. .curr_seg->nbuf);
  2208. if (msdu_info->u.sg_info.curr_seg->next) {
  2209. msdu_info->u.sg_info.curr_seg =
  2210. msdu_info->u.sg_info
  2211. .curr_seg->next;
  2212. nbuf = msdu_info->u.sg_info
  2213. .curr_seg->nbuf;
  2214. }
  2215. i++;
  2216. continue;
  2217. }
  2218. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2219. dp_tx_tso_seg_history_add(
  2220. soc,
  2221. msdu_info->u.tso_info.curr_seg,
  2222. nbuf, 0, DP_TX_DESC_UNMAP);
  2223. dp_tx_tso_unmap_segment(soc,
  2224. msdu_info->u.tso_info.
  2225. curr_seg,
  2226. msdu_info->u.tso_info.
  2227. tso_num_seg_list);
  2228. if (msdu_info->u.tso_info.curr_seg->next) {
  2229. msdu_info->u.tso_info.curr_seg =
  2230. msdu_info->u.tso_info.curr_seg->next;
  2231. i++;
  2232. continue;
  2233. }
  2234. }
  2235. if (msdu_info->frm_type == dp_tx_frm_sg)
  2236. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2237. goto done;
  2238. }
  2239. if (msdu_info->frm_type == dp_tx_frm_me) {
  2240. tx_desc->msdu_ext_desc->me_buffer =
  2241. (struct dp_tx_me_buf_t *)msdu_info->
  2242. u.sg_info.curr_seg->frags[0].vaddr;
  2243. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2244. }
  2245. if (is_cce_classified)
  2246. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2247. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2248. if (msdu_info->exception_fw) {
  2249. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2250. }
  2251. dp_tx_is_hp_update_required(i, msdu_info);
  2252. /*
  2253. * For frames with multiple segments (TSO, ME), jump to next
  2254. * segment.
  2255. */
  2256. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2257. if (msdu_info->u.tso_info.curr_seg->next) {
  2258. msdu_info->u.tso_info.curr_seg =
  2259. msdu_info->u.tso_info.curr_seg->next;
  2260. /*
  2261. * If this is a jumbo nbuf, then increment the
  2262. * number of nbuf users for each additional
  2263. * segment of the msdu. This will ensure that
  2264. * the skb is freed only after receiving tx
  2265. * completion for all segments of an nbuf
  2266. */
  2267. qdf_nbuf_inc_users(nbuf);
  2268. /* Check with MCL if this is needed */
  2269. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2270. */
  2271. }
  2272. }
  2273. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2274. &htt_tcl_metadata,
  2275. vdev,
  2276. msdu_info);
  2277. /*
  2278. * Enqueue the Tx MSDU descriptor to HW for transmit
  2279. */
  2280. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2281. htt_tcl_metadata,
  2282. NULL, msdu_info);
  2283. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2284. if (status != QDF_STATUS_SUCCESS) {
  2285. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2286. tx_desc, tx_q->ring_id);
  2287. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2288. tid_stats = &pdev->stats.tid_stats.
  2289. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2290. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2291. if (msdu_info->frm_type == dp_tx_frm_me) {
  2292. hw_enq_fail++;
  2293. if (hw_enq_fail == msdu_info->num_seg) {
  2294. /*
  2295. * Unmap is needed only if enqueue
  2296. * failed for all segments.
  2297. */
  2298. qdf_nbuf_unmap(soc->osdev,
  2299. msdu_info->u.sg_info.
  2300. curr_seg->nbuf,
  2301. QDF_DMA_TO_DEVICE);
  2302. }
  2303. /*
  2304. * Free the nbuf for the current segment
  2305. * and make it point to the next in the list.
  2306. * For me, there are as many segments as there
  2307. * are no of clients.
  2308. */
  2309. qdf_nbuf_free(msdu_info->u.sg_info
  2310. .curr_seg->nbuf);
  2311. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2312. if (msdu_info->u.sg_info.curr_seg->next) {
  2313. msdu_info->u.sg_info.curr_seg =
  2314. msdu_info->u.sg_info
  2315. .curr_seg->next;
  2316. nbuf = msdu_info->u.sg_info
  2317. .curr_seg->nbuf;
  2318. } else
  2319. break;
  2320. i++;
  2321. continue;
  2322. }
  2323. /*
  2324. * For TSO frames, the nbuf users increment done for
  2325. * the current segment has to be reverted, since the
  2326. * hw enqueue for this segment failed
  2327. */
  2328. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2329. msdu_info->u.tso_info.curr_seg) {
  2330. /*
  2331. * unmap and free current,
  2332. * retransmit remaining segments
  2333. */
  2334. dp_tx_comp_free_buf(soc, tx_desc, false);
  2335. i++;
  2336. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2337. continue;
  2338. }
  2339. if (msdu_info->frm_type == dp_tx_frm_sg)
  2340. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2341. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2342. goto done;
  2343. }
  2344. /*
  2345. * TODO
  2346. * if tso_info structure can be modified to have curr_seg
  2347. * as first element, following 2 blocks of code (for TSO and SG)
  2348. * can be combined into 1
  2349. */
  2350. /*
  2351. * For Multicast-Unicast converted packets,
  2352. * each converted frame (for a client) is represented as
  2353. * 1 segment
  2354. */
  2355. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2356. (msdu_info->frm_type == dp_tx_frm_me)) {
  2357. if (msdu_info->u.sg_info.curr_seg->next) {
  2358. msdu_info->u.sg_info.curr_seg =
  2359. msdu_info->u.sg_info.curr_seg->next;
  2360. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2361. } else
  2362. break;
  2363. }
  2364. i++;
  2365. }
  2366. nbuf = NULL;
  2367. done:
  2368. return nbuf;
  2369. }
  2370. /**
  2371. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2372. * for SG frames
  2373. * @vdev: DP vdev handle
  2374. * @nbuf: skb
  2375. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2376. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2377. *
  2378. * Return: NULL on success,
  2379. * nbuf when it fails to send
  2380. */
  2381. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2382. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2383. {
  2384. uint32_t cur_frag, nr_frags, i;
  2385. qdf_dma_addr_t paddr;
  2386. struct dp_tx_sg_info_s *sg_info;
  2387. sg_info = &msdu_info->u.sg_info;
  2388. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2389. if (QDF_STATUS_SUCCESS !=
  2390. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2391. QDF_DMA_TO_DEVICE,
  2392. qdf_nbuf_headlen(nbuf))) {
  2393. dp_tx_err("dma map error");
  2394. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2395. qdf_nbuf_free(nbuf);
  2396. return NULL;
  2397. }
  2398. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2399. seg_info->frags[0].paddr_lo = paddr;
  2400. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2401. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2402. seg_info->frags[0].vaddr = (void *) nbuf;
  2403. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2404. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2405. nbuf, 0,
  2406. QDF_DMA_TO_DEVICE,
  2407. cur_frag)) {
  2408. dp_tx_err("frag dma map error");
  2409. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2410. goto map_err;
  2411. }
  2412. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2413. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2414. seg_info->frags[cur_frag + 1].paddr_hi =
  2415. ((uint64_t) paddr) >> 32;
  2416. seg_info->frags[cur_frag + 1].len =
  2417. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2418. }
  2419. seg_info->frag_cnt = (cur_frag + 1);
  2420. seg_info->total_len = qdf_nbuf_len(nbuf);
  2421. seg_info->next = NULL;
  2422. sg_info->curr_seg = seg_info;
  2423. msdu_info->frm_type = dp_tx_frm_sg;
  2424. msdu_info->num_seg = 1;
  2425. return nbuf;
  2426. map_err:
  2427. /* restore paddr into nbuf before calling unmap */
  2428. qdf_nbuf_mapped_paddr_set(nbuf,
  2429. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2430. ((uint64_t)
  2431. seg_info->frags[0].paddr_hi) << 32));
  2432. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2433. QDF_DMA_TO_DEVICE,
  2434. seg_info->frags[0].len);
  2435. for (i = 1; i <= cur_frag; i++) {
  2436. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2437. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2438. seg_info->frags[i].paddr_hi) << 32),
  2439. seg_info->frags[i].len,
  2440. QDF_DMA_TO_DEVICE);
  2441. }
  2442. qdf_nbuf_free(nbuf);
  2443. return NULL;
  2444. }
  2445. /**
  2446. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2447. * @vdev: DP vdev handle
  2448. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2449. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2450. *
  2451. * Return: NULL on failure,
  2452. * nbuf when extracted successfully
  2453. */
  2454. static
  2455. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2456. struct dp_tx_msdu_info_s *msdu_info,
  2457. uint16_t ppdu_cookie)
  2458. {
  2459. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2460. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2461. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2462. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2463. (msdu_info->meta_data[5], 1);
  2464. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2465. (msdu_info->meta_data[5], 1);
  2466. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2467. (msdu_info->meta_data[6], ppdu_cookie);
  2468. msdu_info->exception_fw = 1;
  2469. msdu_info->is_tx_sniffer = 1;
  2470. }
  2471. #ifdef MESH_MODE_SUPPORT
  2472. /**
  2473. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2474. and prepare msdu_info for mesh frames.
  2475. * @vdev: DP vdev handle
  2476. * @nbuf: skb
  2477. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2478. *
  2479. * Return: NULL on failure,
  2480. * nbuf when extracted successfully
  2481. */
  2482. static
  2483. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2484. struct dp_tx_msdu_info_s *msdu_info)
  2485. {
  2486. struct meta_hdr_s *mhdr;
  2487. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2488. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2489. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2490. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2491. msdu_info->exception_fw = 0;
  2492. goto remove_meta_hdr;
  2493. }
  2494. msdu_info->exception_fw = 1;
  2495. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2496. meta_data->host_tx_desc_pool = 1;
  2497. meta_data->update_peer_cache = 1;
  2498. meta_data->learning_frame = 1;
  2499. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2500. meta_data->power = mhdr->power;
  2501. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2502. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2503. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2504. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2505. meta_data->dyn_bw = 1;
  2506. meta_data->valid_pwr = 1;
  2507. meta_data->valid_mcs_mask = 1;
  2508. meta_data->valid_nss_mask = 1;
  2509. meta_data->valid_preamble_type = 1;
  2510. meta_data->valid_retries = 1;
  2511. meta_data->valid_bw_info = 1;
  2512. }
  2513. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2514. meta_data->encrypt_type = 0;
  2515. meta_data->valid_encrypt_type = 1;
  2516. meta_data->learning_frame = 0;
  2517. }
  2518. meta_data->valid_key_flags = 1;
  2519. meta_data->key_flags = (mhdr->keyix & 0x3);
  2520. remove_meta_hdr:
  2521. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2522. dp_tx_err("qdf_nbuf_pull_head failed");
  2523. qdf_nbuf_free(nbuf);
  2524. return NULL;
  2525. }
  2526. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2527. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2528. " tid %d to_fw %d",
  2529. msdu_info->meta_data[0],
  2530. msdu_info->meta_data[1],
  2531. msdu_info->meta_data[2],
  2532. msdu_info->meta_data[3],
  2533. msdu_info->meta_data[4],
  2534. msdu_info->meta_data[5],
  2535. msdu_info->tid, msdu_info->exception_fw);
  2536. return nbuf;
  2537. }
  2538. #else
  2539. static
  2540. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2541. struct dp_tx_msdu_info_s *msdu_info)
  2542. {
  2543. return nbuf;
  2544. }
  2545. #endif
  2546. /**
  2547. * dp_check_exc_metadata() - Checks if parameters are valid
  2548. * @tx_exc - holds all exception path parameters
  2549. *
  2550. * Returns true when all the parameters are valid else false
  2551. *
  2552. */
  2553. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2554. {
  2555. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2556. HTT_INVALID_TID);
  2557. bool invalid_encap_type =
  2558. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2559. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2560. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2561. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2562. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2563. tx_exc->ppdu_cookie == 0);
  2564. if (tx_exc->is_intrabss_fwd)
  2565. return true;
  2566. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2567. invalid_cookie) {
  2568. return false;
  2569. }
  2570. return true;
  2571. }
  2572. #ifdef ATH_SUPPORT_IQUE
  2573. /**
  2574. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2575. * @vdev: vdev handle
  2576. * @nbuf: skb
  2577. *
  2578. * Return: true on success,
  2579. * false on failure
  2580. */
  2581. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2582. {
  2583. qdf_ether_header_t *eh;
  2584. /* Mcast to Ucast Conversion*/
  2585. if (qdf_likely(!vdev->mcast_enhancement_en))
  2586. return true;
  2587. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2588. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2589. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2590. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2591. qdf_nbuf_set_next(nbuf, NULL);
  2592. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2593. qdf_nbuf_len(nbuf));
  2594. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2595. QDF_STATUS_SUCCESS) {
  2596. return false;
  2597. }
  2598. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2599. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2600. QDF_STATUS_SUCCESS) {
  2601. return false;
  2602. }
  2603. }
  2604. }
  2605. return true;
  2606. }
  2607. #else
  2608. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2609. {
  2610. return true;
  2611. }
  2612. #endif
  2613. /**
  2614. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2615. * @nbuf: qdf_nbuf_t
  2616. * @vdev: struct dp_vdev *
  2617. *
  2618. * Allow packet for processing only if it is for peer client which is
  2619. * connected with same vap. Drop packet if client is connected to
  2620. * different vap.
  2621. *
  2622. * Return: QDF_STATUS
  2623. */
  2624. static inline QDF_STATUS
  2625. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2626. {
  2627. struct dp_ast_entry *dst_ast_entry = NULL;
  2628. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2629. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2630. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2631. return QDF_STATUS_SUCCESS;
  2632. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2633. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2634. eh->ether_dhost,
  2635. vdev->vdev_id);
  2636. /* If there is no ast entry, return failure */
  2637. if (qdf_unlikely(!dst_ast_entry)) {
  2638. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2639. return QDF_STATUS_E_FAILURE;
  2640. }
  2641. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2642. return QDF_STATUS_SUCCESS;
  2643. }
  2644. /**
  2645. * dp_tx_nawds_handler() - NAWDS handler
  2646. *
  2647. * @soc: DP soc handle
  2648. * @vdev_id: id of DP vdev handle
  2649. * @msdu_info: msdu_info required to create HTT metadata
  2650. * @nbuf: skb
  2651. *
  2652. * This API transfers the multicast frames with the peer id
  2653. * on NAWDS enabled peer.
  2654. * Return: none
  2655. */
  2656. static inline
  2657. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2658. struct dp_tx_msdu_info_s *msdu_info,
  2659. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2660. {
  2661. struct dp_peer *peer = NULL;
  2662. qdf_nbuf_t nbuf_clone = NULL;
  2663. uint16_t peer_id = DP_INVALID_PEER;
  2664. struct dp_txrx_peer *txrx_peer;
  2665. /* This check avoids pkt forwarding which is entered
  2666. * in the ast table but still doesn't have valid peerid.
  2667. */
  2668. if (sa_peer_id == HTT_INVALID_PEER)
  2669. return;
  2670. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2671. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2672. txrx_peer = dp_get_txrx_peer(peer);
  2673. if (!txrx_peer)
  2674. continue;
  2675. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2676. peer_id = peer->peer_id;
  2677. if (!dp_peer_is_primary_link_peer(peer))
  2678. continue;
  2679. /* Multicast packets needs to be
  2680. * dropped in case of intra bss forwarding
  2681. */
  2682. if (sa_peer_id == txrx_peer->peer_id) {
  2683. dp_tx_debug("multicast packet");
  2684. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2685. tx.nawds_mcast_drop,
  2686. 1);
  2687. continue;
  2688. }
  2689. nbuf_clone = qdf_nbuf_clone(nbuf);
  2690. if (!nbuf_clone) {
  2691. QDF_TRACE(QDF_MODULE_ID_DP,
  2692. QDF_TRACE_LEVEL_ERROR,
  2693. FL("nbuf clone failed"));
  2694. break;
  2695. }
  2696. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2697. msdu_info, peer_id,
  2698. NULL);
  2699. if (nbuf_clone) {
  2700. dp_tx_debug("pkt send failed");
  2701. qdf_nbuf_free(nbuf_clone);
  2702. } else {
  2703. if (peer_id != DP_INVALID_PEER)
  2704. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2705. tx.nawds_mcast,
  2706. 1, qdf_nbuf_len(nbuf));
  2707. }
  2708. }
  2709. }
  2710. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2711. }
  2712. /**
  2713. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2714. * @soc: DP soc handle
  2715. * @vdev_id: id of DP vdev handle
  2716. * @nbuf: skb
  2717. * @tx_exc_metadata: Handle that holds exception path meta data
  2718. *
  2719. * Entry point for Core Tx layer (DP_TX) invoked from
  2720. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2721. *
  2722. * Return: NULL on success,
  2723. * nbuf when it fails to send
  2724. */
  2725. qdf_nbuf_t
  2726. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2727. qdf_nbuf_t nbuf,
  2728. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2729. {
  2730. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2731. qdf_ether_header_t *eh = NULL;
  2732. struct dp_tx_msdu_info_s msdu_info;
  2733. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2734. DP_MOD_ID_TX_EXCEPTION);
  2735. if (qdf_unlikely(!vdev))
  2736. goto fail;
  2737. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2738. if (!tx_exc_metadata)
  2739. goto fail;
  2740. msdu_info.tid = tx_exc_metadata->tid;
  2741. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2742. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2743. QDF_MAC_ADDR_REF(nbuf->data));
  2744. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2745. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2746. dp_tx_err("Invalid parameters in exception path");
  2747. goto fail;
  2748. }
  2749. /* Basic sanity checks for unsupported packets */
  2750. /* MESH mode */
  2751. if (qdf_unlikely(vdev->mesh_vdev)) {
  2752. dp_tx_err("Mesh mode is not supported in exception path");
  2753. goto fail;
  2754. }
  2755. /*
  2756. * Classify the frame and call corresponding
  2757. * "prepare" function which extracts the segment (TSO)
  2758. * and fragmentation information (for TSO , SG, ME, or Raw)
  2759. * into MSDU_INFO structure which is later used to fill
  2760. * SW and HW descriptors.
  2761. */
  2762. if (qdf_nbuf_is_tso(nbuf)) {
  2763. dp_verbose_debug("TSO frame %pK", vdev);
  2764. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2765. qdf_nbuf_len(nbuf));
  2766. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2767. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2768. qdf_nbuf_len(nbuf));
  2769. goto fail;
  2770. }
  2771. goto send_multiple;
  2772. }
  2773. /* SG */
  2774. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2775. struct dp_tx_seg_info_s seg_info = {0};
  2776. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2777. if (!nbuf)
  2778. goto fail;
  2779. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2780. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2781. qdf_nbuf_len(nbuf));
  2782. goto send_multiple;
  2783. }
  2784. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2785. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2786. qdf_nbuf_len(nbuf));
  2787. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2788. tx_exc_metadata->ppdu_cookie);
  2789. }
  2790. /*
  2791. * Get HW Queue to use for this frame.
  2792. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2793. * dedicated for data and 1 for command.
  2794. * "queue_id" maps to one hardware ring.
  2795. * With each ring, we also associate a unique Tx descriptor pool
  2796. * to minimize lock contention for these resources.
  2797. */
  2798. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2799. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2800. if (qdf_unlikely(vdev->nawds_enabled)) {
  2801. /*
  2802. * This is a multicast packet
  2803. */
  2804. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2805. tx_exc_metadata->peer_id);
  2806. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2807. 1, qdf_nbuf_len(nbuf));
  2808. }
  2809. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2810. DP_INVALID_PEER, NULL);
  2811. } else {
  2812. /*
  2813. * Check exception descriptors
  2814. */
  2815. if (dp_tx_exception_limit_check(vdev))
  2816. goto fail;
  2817. /* Single linear frame */
  2818. /*
  2819. * If nbuf is a simple linear frame, use send_single function to
  2820. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2821. * SRNG. There is no need to setup a MSDU extension descriptor.
  2822. */
  2823. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2824. tx_exc_metadata->peer_id,
  2825. tx_exc_metadata);
  2826. }
  2827. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2828. return nbuf;
  2829. send_multiple:
  2830. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2831. fail:
  2832. if (vdev)
  2833. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2834. dp_verbose_debug("pkt send failed");
  2835. return nbuf;
  2836. }
  2837. /**
  2838. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2839. * in exception path in special case to avoid regular exception path chk.
  2840. * @soc: DP soc handle
  2841. * @vdev_id: id of DP vdev handle
  2842. * @nbuf: skb
  2843. * @tx_exc_metadata: Handle that holds exception path meta data
  2844. *
  2845. * Entry point for Core Tx layer (DP_TX) invoked from
  2846. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2847. *
  2848. * Return: NULL on success,
  2849. * nbuf when it fails to send
  2850. */
  2851. qdf_nbuf_t
  2852. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2853. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2854. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2855. {
  2856. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2857. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2858. DP_MOD_ID_TX_EXCEPTION);
  2859. if (qdf_unlikely(!vdev))
  2860. goto fail;
  2861. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2862. == QDF_STATUS_E_FAILURE)) {
  2863. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2864. goto fail;
  2865. }
  2866. /* Unref count as it will agin be taken inside dp_tx_exception */
  2867. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2868. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2869. fail:
  2870. if (vdev)
  2871. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2872. dp_verbose_debug("pkt send failed");
  2873. return nbuf;
  2874. }
  2875. /**
  2876. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2877. * @soc: DP soc handle
  2878. * @vdev_id: DP vdev handle
  2879. * @nbuf: skb
  2880. *
  2881. * Entry point for Core Tx layer (DP_TX) invoked from
  2882. * hard_start_xmit in OSIF/HDD
  2883. *
  2884. * Return: NULL on success,
  2885. * nbuf when it fails to send
  2886. */
  2887. #ifdef MESH_MODE_SUPPORT
  2888. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2889. qdf_nbuf_t nbuf)
  2890. {
  2891. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2892. struct meta_hdr_s *mhdr;
  2893. qdf_nbuf_t nbuf_mesh = NULL;
  2894. qdf_nbuf_t nbuf_clone = NULL;
  2895. struct dp_vdev *vdev;
  2896. uint8_t no_enc_frame = 0;
  2897. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2898. if (!nbuf_mesh) {
  2899. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2900. "qdf_nbuf_unshare failed");
  2901. return nbuf;
  2902. }
  2903. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2904. if (!vdev) {
  2905. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2906. "vdev is NULL for vdev_id %d", vdev_id);
  2907. return nbuf;
  2908. }
  2909. nbuf = nbuf_mesh;
  2910. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2911. if ((vdev->sec_type != cdp_sec_type_none) &&
  2912. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2913. no_enc_frame = 1;
  2914. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2915. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2916. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2917. !no_enc_frame) {
  2918. nbuf_clone = qdf_nbuf_clone(nbuf);
  2919. if (!nbuf_clone) {
  2920. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2921. "qdf_nbuf_clone failed");
  2922. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2923. return nbuf;
  2924. }
  2925. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2926. }
  2927. if (nbuf_clone) {
  2928. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2929. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2930. } else {
  2931. qdf_nbuf_free(nbuf_clone);
  2932. }
  2933. }
  2934. if (no_enc_frame)
  2935. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2936. else
  2937. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2938. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2939. if ((!nbuf) && no_enc_frame) {
  2940. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2941. }
  2942. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2943. return nbuf;
  2944. }
  2945. #else
  2946. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2947. qdf_nbuf_t nbuf)
  2948. {
  2949. return dp_tx_send(soc, vdev_id, nbuf);
  2950. }
  2951. #endif
  2952. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  2953. static inline
  2954. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2955. {
  2956. if (nbuf) {
  2957. qdf_prefetch(&nbuf->len);
  2958. qdf_prefetch(&nbuf->data);
  2959. }
  2960. }
  2961. #else
  2962. static inline
  2963. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2964. {
  2965. }
  2966. #endif
  2967. #ifdef DP_UMAC_HW_RESET_SUPPORT
  2968. /*
  2969. * dp_tx_drop() - Drop the frame on a given VAP
  2970. * @soc: DP soc handle
  2971. * @vdev_id: id of DP vdev handle
  2972. * @nbuf: skb
  2973. *
  2974. * Drop all the incoming packets
  2975. *
  2976. * Return: nbuf
  2977. *
  2978. */
  2979. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2980. qdf_nbuf_t nbuf)
  2981. {
  2982. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2983. struct dp_vdev *vdev = NULL;
  2984. vdev = soc->vdev_id_map[vdev_id];
  2985. if (qdf_unlikely(!vdev))
  2986. return nbuf;
  2987. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  2988. return nbuf;
  2989. }
  2990. /*
  2991. * dp_tx_exc_drop() - Drop the frame on a given VAP
  2992. * @soc: DP soc handle
  2993. * @vdev_id: id of DP vdev handle
  2994. * @nbuf: skb
  2995. * @tx_exc_metadata: Handle that holds exception path meta data
  2996. *
  2997. * Drop all the incoming packets
  2998. *
  2999. * Return: nbuf
  3000. *
  3001. */
  3002. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3003. qdf_nbuf_t nbuf,
  3004. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3005. {
  3006. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3007. }
  3008. #endif
  3009. /*
  3010. * dp_tx_send() - Transmit a frame on a given VAP
  3011. * @soc: DP soc handle
  3012. * @vdev_id: id of DP vdev handle
  3013. * @nbuf: skb
  3014. *
  3015. * Entry point for Core Tx layer (DP_TX) invoked from
  3016. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3017. * cases
  3018. *
  3019. * Return: NULL on success,
  3020. * nbuf when it fails to send
  3021. */
  3022. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3023. qdf_nbuf_t nbuf)
  3024. {
  3025. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3026. uint16_t peer_id = HTT_INVALID_PEER;
  3027. /*
  3028. * doing a memzero is causing additional function call overhead
  3029. * so doing static stack clearing
  3030. */
  3031. struct dp_tx_msdu_info_s msdu_info = {0};
  3032. struct dp_vdev *vdev = NULL;
  3033. qdf_nbuf_t end_nbuf = NULL;
  3034. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3035. return nbuf;
  3036. /*
  3037. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3038. * this in per packet path.
  3039. *
  3040. * As in this path vdev memory is already protected with netdev
  3041. * tx lock
  3042. */
  3043. vdev = soc->vdev_id_map[vdev_id];
  3044. if (qdf_unlikely(!vdev))
  3045. return nbuf;
  3046. /*
  3047. * Set Default Host TID value to invalid TID
  3048. * (TID override disabled)
  3049. */
  3050. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3051. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_headlen(nbuf));
  3052. if (qdf_unlikely(vdev->mesh_vdev)) {
  3053. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3054. &msdu_info);
  3055. if (!nbuf_mesh) {
  3056. dp_verbose_debug("Extracting mesh metadata failed");
  3057. return nbuf;
  3058. }
  3059. nbuf = nbuf_mesh;
  3060. }
  3061. /*
  3062. * Get HW Queue to use for this frame.
  3063. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3064. * dedicated for data and 1 for command.
  3065. * "queue_id" maps to one hardware ring.
  3066. * With each ring, we also associate a unique Tx descriptor pool
  3067. * to minimize lock contention for these resources.
  3068. */
  3069. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3070. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3071. 1);
  3072. /*
  3073. * TCL H/W supports 2 DSCP-TID mapping tables.
  3074. * Table 1 - Default DSCP-TID mapping table
  3075. * Table 2 - 1 DSCP-TID override table
  3076. *
  3077. * If we need a different DSCP-TID mapping for this vap,
  3078. * call tid_classify to extract DSCP/ToS from frame and
  3079. * map to a TID and store in msdu_info. This is later used
  3080. * to fill in TCL Input descriptor (per-packet TID override).
  3081. */
  3082. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3083. /*
  3084. * Classify the frame and call corresponding
  3085. * "prepare" function which extracts the segment (TSO)
  3086. * and fragmentation information (for TSO , SG, ME, or Raw)
  3087. * into MSDU_INFO structure which is later used to fill
  3088. * SW and HW descriptors.
  3089. */
  3090. if (qdf_nbuf_is_tso(nbuf)) {
  3091. dp_verbose_debug("TSO frame %pK", vdev);
  3092. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3093. qdf_nbuf_len(nbuf));
  3094. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3095. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3096. qdf_nbuf_len(nbuf));
  3097. return nbuf;
  3098. }
  3099. goto send_multiple;
  3100. }
  3101. /* SG */
  3102. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3103. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3104. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3105. return nbuf;
  3106. } else {
  3107. struct dp_tx_seg_info_s seg_info = {0};
  3108. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3109. &msdu_info);
  3110. if (!nbuf)
  3111. return NULL;
  3112. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3113. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3114. qdf_nbuf_len(nbuf));
  3115. goto send_multiple;
  3116. }
  3117. }
  3118. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3119. return NULL;
  3120. /* RAW */
  3121. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3122. struct dp_tx_seg_info_s seg_info = {0};
  3123. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3124. if (!nbuf)
  3125. return NULL;
  3126. dp_verbose_debug("Raw frame %pK", vdev);
  3127. goto send_multiple;
  3128. }
  3129. if (qdf_unlikely(vdev->nawds_enabled)) {
  3130. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3131. qdf_nbuf_data(nbuf);
  3132. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3133. uint16_t sa_peer_id = DP_INVALID_PEER;
  3134. if (!soc->ast_offload_support) {
  3135. struct dp_ast_entry *ast_entry = NULL;
  3136. qdf_spin_lock_bh(&soc->ast_lock);
  3137. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3138. (soc,
  3139. (uint8_t *)(eh->ether_shost),
  3140. vdev->pdev->pdev_id);
  3141. if (ast_entry)
  3142. sa_peer_id = ast_entry->peer_id;
  3143. qdf_spin_unlock_bh(&soc->ast_lock);
  3144. }
  3145. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3146. sa_peer_id);
  3147. }
  3148. peer_id = DP_INVALID_PEER;
  3149. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3150. 1, qdf_nbuf_len(nbuf));
  3151. }
  3152. /* Single linear frame */
  3153. /*
  3154. * If nbuf is a simple linear frame, use send_single function to
  3155. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3156. * SRNG. There is no need to setup a MSDU extension descriptor.
  3157. */
  3158. dp_tx_prefetch_nbuf_data(nbuf);
  3159. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3160. peer_id, end_nbuf);
  3161. return nbuf;
  3162. send_multiple:
  3163. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3164. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3165. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3166. return nbuf;
  3167. }
  3168. /**
  3169. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3170. * case to vaoid check in perpkt path.
  3171. * @soc: DP soc handle
  3172. * @vdev_id: id of DP vdev handle
  3173. * @nbuf: skb
  3174. *
  3175. * Entry point for Core Tx layer (DP_TX) invoked from
  3176. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3177. * with special condition to avoid per pkt check in dp_tx_send
  3178. *
  3179. * Return: NULL on success,
  3180. * nbuf when it fails to send
  3181. */
  3182. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3183. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3184. {
  3185. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3186. struct dp_vdev *vdev = NULL;
  3187. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3188. return nbuf;
  3189. /*
  3190. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3191. * this in per packet path.
  3192. *
  3193. * As in this path vdev memory is already protected with netdev
  3194. * tx lock
  3195. */
  3196. vdev = soc->vdev_id_map[vdev_id];
  3197. if (qdf_unlikely(!vdev))
  3198. return nbuf;
  3199. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3200. == QDF_STATUS_E_FAILURE)) {
  3201. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3202. return nbuf;
  3203. }
  3204. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3205. }
  3206. #ifdef UMAC_SUPPORT_PROXY_ARP
  3207. /**
  3208. * dp_tx_proxy_arp() - Tx proxy arp handler
  3209. * @vdev: datapath vdev handle
  3210. * @buf: sk buffer
  3211. *
  3212. * Return: status
  3213. */
  3214. static inline
  3215. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3216. {
  3217. if (vdev->osif_proxy_arp)
  3218. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3219. /*
  3220. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3221. * osif_proxy_arp has a valid function pointer assigned
  3222. * to it
  3223. */
  3224. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3225. return QDF_STATUS_NOT_INITIALIZED;
  3226. }
  3227. #else
  3228. /**
  3229. * dp_tx_proxy_arp() - Tx proxy arp handler
  3230. * @vdev: datapath vdev handle
  3231. * @buf: sk buffer
  3232. *
  3233. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3234. * is not defined.
  3235. *
  3236. * Return: status
  3237. */
  3238. static inline
  3239. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3240. {
  3241. return QDF_STATUS_SUCCESS;
  3242. }
  3243. #endif
  3244. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3245. #ifdef WLAN_MCAST_MLO
  3246. static bool
  3247. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3248. struct dp_tx_desc_s *tx_desc,
  3249. qdf_nbuf_t nbuf,
  3250. uint8_t reinject_reason)
  3251. {
  3252. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3253. if (soc->arch_ops.dp_tx_mcast_handler)
  3254. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3255. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3256. return true;
  3257. }
  3258. return false;
  3259. }
  3260. #else /* WLAN_MCAST_MLO */
  3261. static inline bool
  3262. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3263. struct dp_tx_desc_s *tx_desc,
  3264. qdf_nbuf_t nbuf,
  3265. uint8_t reinject_reason)
  3266. {
  3267. return false;
  3268. }
  3269. #endif /* WLAN_MCAST_MLO */
  3270. #else
  3271. static inline bool
  3272. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3273. struct dp_tx_desc_s *tx_desc,
  3274. qdf_nbuf_t nbuf,
  3275. uint8_t reinject_reason)
  3276. {
  3277. return false;
  3278. }
  3279. #endif
  3280. /**
  3281. * dp_tx_reinject_handler() - Tx Reinject Handler
  3282. * @soc: datapath soc handle
  3283. * @vdev: datapath vdev handle
  3284. * @tx_desc: software descriptor head pointer
  3285. * @status : Tx completion status from HTT descriptor
  3286. * @reinject_reason : reinject reason from HTT descriptor
  3287. *
  3288. * This function reinjects frames back to Target.
  3289. * Todo - Host queue needs to be added
  3290. *
  3291. * Return: none
  3292. */
  3293. void dp_tx_reinject_handler(struct dp_soc *soc,
  3294. struct dp_vdev *vdev,
  3295. struct dp_tx_desc_s *tx_desc,
  3296. uint8_t *status,
  3297. uint8_t reinject_reason)
  3298. {
  3299. struct dp_peer *peer = NULL;
  3300. uint32_t peer_id = HTT_INVALID_PEER;
  3301. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3302. qdf_nbuf_t nbuf_copy = NULL;
  3303. struct dp_tx_msdu_info_s msdu_info;
  3304. #ifdef WDS_VENDOR_EXTENSION
  3305. int is_mcast = 0, is_ucast = 0;
  3306. int num_peers_3addr = 0;
  3307. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3308. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3309. #endif
  3310. struct dp_txrx_peer *txrx_peer;
  3311. qdf_assert(vdev);
  3312. dp_tx_debug("Tx reinject path");
  3313. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3314. qdf_nbuf_len(tx_desc->nbuf));
  3315. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3316. return;
  3317. #ifdef WDS_VENDOR_EXTENSION
  3318. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3319. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3320. } else {
  3321. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3322. }
  3323. is_ucast = !is_mcast;
  3324. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3325. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3326. txrx_peer = dp_get_txrx_peer(peer);
  3327. if (!txrx_peer || txrx_peer->bss_peer)
  3328. continue;
  3329. /* Detect wds peers that use 3-addr framing for mcast.
  3330. * if there are any, the bss_peer is used to send the
  3331. * the mcast frame using 3-addr format. all wds enabled
  3332. * peers that use 4-addr framing for mcast frames will
  3333. * be duplicated and sent as 4-addr frames below.
  3334. */
  3335. if (!txrx_peer->wds_enabled ||
  3336. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3337. num_peers_3addr = 1;
  3338. break;
  3339. }
  3340. }
  3341. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3342. #endif
  3343. if (qdf_unlikely(vdev->mesh_vdev)) {
  3344. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3345. } else {
  3346. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3347. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3348. txrx_peer = dp_get_txrx_peer(peer);
  3349. if (!txrx_peer)
  3350. continue;
  3351. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3352. #ifdef WDS_VENDOR_EXTENSION
  3353. /*
  3354. * . if 3-addr STA, then send on BSS Peer
  3355. * . if Peer WDS enabled and accept 4-addr mcast,
  3356. * send mcast on that peer only
  3357. * . if Peer WDS enabled and accept 4-addr ucast,
  3358. * send ucast on that peer only
  3359. */
  3360. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3361. (txrx_peer->wds_enabled &&
  3362. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3363. (is_ucast &&
  3364. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3365. #else
  3366. (txrx_peer->bss_peer &&
  3367. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3368. #endif
  3369. peer_id = DP_INVALID_PEER;
  3370. nbuf_copy = qdf_nbuf_copy(nbuf);
  3371. if (!nbuf_copy) {
  3372. dp_tx_debug("nbuf copy failed");
  3373. break;
  3374. }
  3375. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3376. dp_tx_get_queue(vdev, nbuf,
  3377. &msdu_info.tx_queue);
  3378. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3379. nbuf_copy,
  3380. &msdu_info,
  3381. peer_id,
  3382. NULL);
  3383. if (nbuf_copy) {
  3384. dp_tx_debug("pkt send failed");
  3385. qdf_nbuf_free(nbuf_copy);
  3386. }
  3387. }
  3388. }
  3389. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3390. }
  3391. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE,
  3392. nbuf->len);
  3393. qdf_nbuf_free(nbuf);
  3394. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3395. }
  3396. /**
  3397. * dp_tx_inspect_handler() - Tx Inspect Handler
  3398. * @soc: datapath soc handle
  3399. * @vdev: datapath vdev handle
  3400. * @tx_desc: software descriptor head pointer
  3401. * @status : Tx completion status from HTT descriptor
  3402. *
  3403. * Handles Tx frames sent back to Host for inspection
  3404. * (ProxyARP)
  3405. *
  3406. * Return: none
  3407. */
  3408. void dp_tx_inspect_handler(struct dp_soc *soc,
  3409. struct dp_vdev *vdev,
  3410. struct dp_tx_desc_s *tx_desc,
  3411. uint8_t *status)
  3412. {
  3413. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3414. "%s Tx inspect path",
  3415. __func__);
  3416. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3417. qdf_nbuf_len(tx_desc->nbuf));
  3418. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3419. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3420. }
  3421. #ifdef MESH_MODE_SUPPORT
  3422. /**
  3423. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3424. * in mesh meta header
  3425. * @tx_desc: software descriptor head pointer
  3426. * @ts: pointer to tx completion stats
  3427. * Return: none
  3428. */
  3429. static
  3430. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3431. struct hal_tx_completion_status *ts)
  3432. {
  3433. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3434. if (!tx_desc->msdu_ext_desc) {
  3435. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3436. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3437. "netbuf %pK offset %d",
  3438. netbuf, tx_desc->pkt_offset);
  3439. return;
  3440. }
  3441. }
  3442. }
  3443. #else
  3444. static
  3445. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3446. struct hal_tx_completion_status *ts)
  3447. {
  3448. }
  3449. #endif
  3450. #ifdef CONFIG_SAWF
  3451. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3452. struct dp_vdev *vdev,
  3453. struct dp_txrx_peer *txrx_peer,
  3454. struct dp_tx_desc_s *tx_desc,
  3455. struct hal_tx_completion_status *ts,
  3456. uint8_t tid)
  3457. {
  3458. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3459. ts, tid);
  3460. }
  3461. #else
  3462. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3463. struct dp_vdev *vdev,
  3464. struct dp_txrx_peer *txrx_peer,
  3465. struct dp_tx_desc_s *tx_desc,
  3466. struct hal_tx_completion_status *ts,
  3467. uint8_t tid)
  3468. {
  3469. }
  3470. #endif
  3471. #ifdef QCA_PEER_EXT_STATS
  3472. /*
  3473. * dp_tx_compute_tid_delay() - Compute per TID delay
  3474. * @stats: Per TID delay stats
  3475. * @tx_desc: Software Tx descriptor
  3476. *
  3477. * Compute the software enqueue and hw enqueue delays and
  3478. * update the respective histograms
  3479. *
  3480. * Return: void
  3481. */
  3482. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3483. struct dp_tx_desc_s *tx_desc)
  3484. {
  3485. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3486. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3487. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3488. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3489. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3490. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3491. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3492. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3493. timestamp_hw_enqueue);
  3494. /*
  3495. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3496. */
  3497. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3498. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3499. }
  3500. /*
  3501. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3502. * @txrx_peer: DP peer context
  3503. * @tx_desc: Tx software descriptor
  3504. * @tid: Transmission ID
  3505. * @ring_id: Rx CPU context ID/CPU_ID
  3506. *
  3507. * Update the peer extended stats. These are enhanced other
  3508. * delay stats per msdu level.
  3509. *
  3510. * Return: void
  3511. */
  3512. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3513. struct dp_tx_desc_s *tx_desc,
  3514. uint8_t tid, uint8_t ring_id)
  3515. {
  3516. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3517. struct dp_soc *soc = NULL;
  3518. struct dp_peer_delay_stats *delay_stats = NULL;
  3519. soc = pdev->soc;
  3520. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3521. return;
  3522. delay_stats = txrx_peer->delay_stats;
  3523. qdf_assert(delay_stats);
  3524. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3525. /*
  3526. * For non-TID packets use the TID 9
  3527. */
  3528. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3529. tid = CDP_MAX_DATA_TIDS - 1;
  3530. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3531. tx_desc);
  3532. }
  3533. #else
  3534. static inline void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3535. struct dp_tx_desc_s *tx_desc,
  3536. uint8_t tid, uint8_t ring_id)
  3537. {
  3538. }
  3539. #endif
  3540. #ifdef HW_TX_DELAY_STATS_ENABLE
  3541. /**
  3542. * dp_update_tx_delay_stats() - update the delay stats
  3543. * @vdev: vdev handle
  3544. * @delay: delay in ms or us based on the flag delay_in_us
  3545. * @tid: tid value
  3546. * @mode: type of tx delay mode
  3547. * @ring id: ring number
  3548. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3549. *
  3550. * Return: none
  3551. */
  3552. static inline
  3553. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3554. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3555. {
  3556. struct cdp_tid_tx_stats *tstats =
  3557. &vdev->stats.tid_tx_stats[ring_id][tid];
  3558. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3559. delay_in_us);
  3560. }
  3561. #else
  3562. static inline
  3563. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3564. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3565. {
  3566. struct cdp_tid_tx_stats *tstats =
  3567. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3568. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3569. delay_in_us);
  3570. }
  3571. #endif
  3572. /**
  3573. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3574. * to pass in correct fields
  3575. *
  3576. * @vdev: pdev handle
  3577. * @tx_desc: tx descriptor
  3578. * @tid: tid value
  3579. * @ring_id: TCL or WBM ring number for transmit path
  3580. * Return: none
  3581. */
  3582. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3583. uint8_t tid, uint8_t ring_id)
  3584. {
  3585. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3586. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3587. uint32_t fwhw_transmit_delay_us;
  3588. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3589. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3590. return;
  3591. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3592. fwhw_transmit_delay_us =
  3593. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3594. qdf_ktime_to_us(tx_desc->timestamp);
  3595. /*
  3596. * Delay between packet enqueued to HW and Tx completion in us
  3597. */
  3598. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3599. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3600. ring_id, true);
  3601. /*
  3602. * For MCL, only enqueue to completion delay is required
  3603. * so return if the vdev flag is enabled.
  3604. */
  3605. return;
  3606. }
  3607. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3608. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3609. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3610. timestamp_hw_enqueue);
  3611. /*
  3612. * Delay between packet enqueued to HW and Tx completion in ms
  3613. */
  3614. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3615. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3616. false);
  3617. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3618. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3619. interframe_delay = (uint32_t)(timestamp_ingress -
  3620. vdev->prev_tx_enq_tstamp);
  3621. /*
  3622. * Delay in software enqueue
  3623. */
  3624. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3625. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3626. false);
  3627. /*
  3628. * Update interframe delay stats calculated at hardstart receive point.
  3629. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3630. * interframe delay will not be calculate correctly for 1st frame.
  3631. * On the other side, this will help in avoiding extra per packet check
  3632. * of !vdev->prev_tx_enq_tstamp.
  3633. */
  3634. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3635. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3636. false);
  3637. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3638. }
  3639. #ifdef DISABLE_DP_STATS
  3640. static
  3641. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3642. struct dp_txrx_peer *txrx_peer)
  3643. {
  3644. }
  3645. #else
  3646. static inline void
  3647. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3648. {
  3649. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3650. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3651. if (subtype != QDF_PROTO_INVALID)
  3652. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3653. 1);
  3654. }
  3655. #endif
  3656. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3657. #ifdef DP_PEER_EXTENDED_API
  3658. static inline uint8_t
  3659. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3660. {
  3661. return txrx_peer->mpdu_retry_threshold;
  3662. }
  3663. #else
  3664. static inline uint8_t
  3665. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3666. {
  3667. return 0;
  3668. }
  3669. #endif
  3670. /**
  3671. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3672. *
  3673. * @ts: Tx compltion status
  3674. * @txrx_peer: datapath txrx_peer handle
  3675. *
  3676. * Return: void
  3677. */
  3678. static inline void
  3679. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3680. struct dp_txrx_peer *txrx_peer)
  3681. {
  3682. uint8_t mcs, pkt_type, dst_mcs_idx;
  3683. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  3684. mcs = ts->mcs;
  3685. pkt_type = ts->pkt_type;
  3686. /* do HW to SW pkt type conversion */
  3687. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  3688. hal_2_dp_pkt_type_map[pkt_type]);
  3689. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  3690. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  3691. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3692. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  3693. 1);
  3694. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3695. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3696. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3697. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3698. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3699. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3700. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3701. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3702. if (ts->first_msdu) {
  3703. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3704. ts->transmit_cnt > 1);
  3705. if (!retry_threshold)
  3706. return;
  3707. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3708. qdf_do_div(ts->transmit_cnt,
  3709. retry_threshold),
  3710. ts->transmit_cnt > retry_threshold);
  3711. }
  3712. }
  3713. #else
  3714. static inline void
  3715. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3716. struct dp_txrx_peer *txrx_peer)
  3717. {
  3718. }
  3719. #endif
  3720. /**
  3721. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3722. * per wbm ring
  3723. *
  3724. * @tx_desc: software descriptor head pointer
  3725. * @ts: Tx completion status
  3726. * @peer: peer handle
  3727. * @ring_id: ring number
  3728. *
  3729. * Return: None
  3730. */
  3731. static inline void
  3732. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3733. struct hal_tx_completion_status *ts,
  3734. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  3735. {
  3736. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3737. uint8_t tid = ts->tid;
  3738. uint32_t length;
  3739. struct cdp_tid_tx_stats *tid_stats;
  3740. if (!pdev)
  3741. return;
  3742. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3743. tid = CDP_MAX_DATA_TIDS - 1;
  3744. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3745. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3746. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  3747. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  3748. return;
  3749. }
  3750. length = qdf_nbuf_len(tx_desc->nbuf);
  3751. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3752. if (qdf_unlikely(pdev->delay_stats_flag) ||
  3753. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  3754. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  3755. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3756. tid_stats->tqm_status_cnt[ts->status]++;
  3757. }
  3758. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  3759. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  3760. ts->transmit_cnt > 1);
  3761. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  3762. 1, ts->transmit_cnt > 2);
  3763. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  3764. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  3765. ts->msdu_part_of_amsdu);
  3766. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  3767. !ts->msdu_part_of_amsdu);
  3768. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  3769. qdf_system_ticks();
  3770. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  3771. return;
  3772. }
  3773. /*
  3774. * tx_failed is ideally supposed to be updated from HTT ppdu
  3775. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  3776. * hw limitation there are no completions for failed cases.
  3777. * Hence updating tx_failed from data path. Please note that
  3778. * if tx_failed is fixed to be from ppdu, then this has to be
  3779. * removed
  3780. */
  3781. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  3782. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  3783. ts->transmit_cnt > DP_RETRY_COUNT);
  3784. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  3785. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  3786. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  3787. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  3788. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  3789. length);
  3790. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  3791. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  3792. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  3793. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  3794. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  3795. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  3796. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  3797. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  3798. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  3799. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  3800. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  3801. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3802. tx.dropped.fw_rem_queue_disable, 1);
  3803. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  3804. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3805. tx.dropped.fw_rem_no_match, 1);
  3806. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  3807. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3808. tx.dropped.drop_threshold, 1);
  3809. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  3810. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3811. tx.dropped.drop_link_desc_na, 1);
  3812. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  3813. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3814. tx.dropped.invalid_drop, 1);
  3815. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  3816. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3817. tx.dropped.mcast_vdev_drop, 1);
  3818. } else {
  3819. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  3820. }
  3821. }
  3822. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3823. /**
  3824. * dp_tx_flow_pool_lock() - take flow pool lock
  3825. * @soc: core txrx main context
  3826. * @tx_desc: tx desc
  3827. *
  3828. * Return: None
  3829. */
  3830. static inline
  3831. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3832. struct dp_tx_desc_s *tx_desc)
  3833. {
  3834. struct dp_tx_desc_pool_s *pool;
  3835. uint8_t desc_pool_id;
  3836. desc_pool_id = tx_desc->pool_id;
  3837. pool = &soc->tx_desc[desc_pool_id];
  3838. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3839. }
  3840. /**
  3841. * dp_tx_flow_pool_unlock() - release flow pool lock
  3842. * @soc: core txrx main context
  3843. * @tx_desc: tx desc
  3844. *
  3845. * Return: None
  3846. */
  3847. static inline
  3848. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3849. struct dp_tx_desc_s *tx_desc)
  3850. {
  3851. struct dp_tx_desc_pool_s *pool;
  3852. uint8_t desc_pool_id;
  3853. desc_pool_id = tx_desc->pool_id;
  3854. pool = &soc->tx_desc[desc_pool_id];
  3855. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3856. }
  3857. #else
  3858. static inline
  3859. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3860. {
  3861. }
  3862. static inline
  3863. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3864. {
  3865. }
  3866. #endif
  3867. /**
  3868. * dp_tx_notify_completion() - Notify tx completion for this desc
  3869. * @soc: core txrx main context
  3870. * @vdev: datapath vdev handle
  3871. * @tx_desc: tx desc
  3872. * @netbuf: buffer
  3873. * @status: tx status
  3874. *
  3875. * Return: none
  3876. */
  3877. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3878. struct dp_vdev *vdev,
  3879. struct dp_tx_desc_s *tx_desc,
  3880. qdf_nbuf_t netbuf,
  3881. uint8_t status)
  3882. {
  3883. void *osif_dev;
  3884. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3885. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3886. qdf_assert(tx_desc);
  3887. if (!vdev ||
  3888. !vdev->osif_vdev) {
  3889. return;
  3890. }
  3891. osif_dev = vdev->osif_vdev;
  3892. tx_compl_cbk = vdev->tx_comp;
  3893. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3894. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3895. if (tx_compl_cbk)
  3896. tx_compl_cbk(netbuf, osif_dev, flag);
  3897. }
  3898. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3899. * @pdev: pdev handle
  3900. * @tid: tid value
  3901. * @txdesc_ts: timestamp from txdesc
  3902. * @ppdu_id: ppdu id
  3903. *
  3904. * Return: none
  3905. */
  3906. #ifdef FEATURE_PERPKT_INFO
  3907. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3908. struct dp_txrx_peer *txrx_peer,
  3909. uint8_t tid,
  3910. uint64_t txdesc_ts,
  3911. uint32_t ppdu_id)
  3912. {
  3913. uint64_t delta_ms;
  3914. struct cdp_tx_sojourn_stats *sojourn_stats;
  3915. struct dp_peer *primary_link_peer = NULL;
  3916. struct dp_soc *link_peer_soc = NULL;
  3917. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3918. return;
  3919. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3920. tid >= CDP_DATA_TID_MAX))
  3921. return;
  3922. if (qdf_unlikely(!pdev->sojourn_buf))
  3923. return;
  3924. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  3925. txrx_peer->peer_id,
  3926. DP_MOD_ID_TX_COMP);
  3927. if (qdf_unlikely(!primary_link_peer))
  3928. return;
  3929. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3930. qdf_nbuf_data(pdev->sojourn_buf);
  3931. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  3932. sojourn_stats->cookie = (void *)
  3933. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  3934. primary_link_peer);
  3935. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3936. txdesc_ts;
  3937. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  3938. delta_ms);
  3939. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3940. sojourn_stats->num_msdus[tid] = 1;
  3941. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3942. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  3943. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3944. pdev->sojourn_buf, HTT_INVALID_PEER,
  3945. WDI_NO_VAL, pdev->pdev_id);
  3946. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3947. sojourn_stats->num_msdus[tid] = 0;
  3948. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3949. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  3950. }
  3951. #else
  3952. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3953. struct dp_txrx_peer *txrx_peer,
  3954. uint8_t tid,
  3955. uint64_t txdesc_ts,
  3956. uint32_t ppdu_id)
  3957. {
  3958. }
  3959. #endif
  3960. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3961. /**
  3962. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3963. * @soc: dp_soc handle
  3964. * @desc: Tx Descriptor
  3965. * @ts: HAL Tx completion descriptor contents
  3966. *
  3967. * This function is used to send tx completion to packet capture
  3968. */
  3969. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3970. struct dp_tx_desc_s *desc,
  3971. struct hal_tx_completion_status *ts)
  3972. {
  3973. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3974. desc, ts->peer_id,
  3975. WDI_NO_VAL, desc->pdev->pdev_id);
  3976. }
  3977. #endif
  3978. /**
  3979. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3980. * @soc: DP Soc handle
  3981. * @tx_desc: software Tx descriptor
  3982. * @ts : Tx completion status from HAL/HTT descriptor
  3983. *
  3984. * Return: none
  3985. */
  3986. void
  3987. dp_tx_comp_process_desc(struct dp_soc *soc,
  3988. struct dp_tx_desc_s *desc,
  3989. struct hal_tx_completion_status *ts,
  3990. struct dp_txrx_peer *txrx_peer)
  3991. {
  3992. uint64_t time_latency = 0;
  3993. uint16_t peer_id = DP_INVALID_PEER_ID;
  3994. /*
  3995. * m_copy/tx_capture modes are not supported for
  3996. * scatter gather packets
  3997. */
  3998. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3999. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4000. qdf_ktime_to_ms(desc->timestamp));
  4001. }
  4002. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4003. if (dp_tx_pkt_tracepoints_enabled())
  4004. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4005. desc->msdu_ext_desc ?
  4006. desc->msdu_ext_desc->tso_desc : NULL,
  4007. qdf_ktime_to_ms(desc->timestamp));
  4008. if (!(desc->msdu_ext_desc)) {
  4009. dp_tx_enh_unmap(soc, desc);
  4010. if (txrx_peer)
  4011. peer_id = txrx_peer->peer_id;
  4012. if (QDF_STATUS_SUCCESS ==
  4013. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4014. return;
  4015. }
  4016. if (QDF_STATUS_SUCCESS ==
  4017. dp_get_completion_indication_for_stack(soc,
  4018. desc->pdev,
  4019. txrx_peer, ts,
  4020. desc->nbuf,
  4021. time_latency)) {
  4022. dp_send_completion_to_stack(soc,
  4023. desc->pdev,
  4024. ts->peer_id,
  4025. ts->ppdu_id,
  4026. desc->nbuf);
  4027. return;
  4028. }
  4029. }
  4030. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4031. dp_tx_comp_free_buf(soc, desc, false);
  4032. }
  4033. #ifdef DISABLE_DP_STATS
  4034. /**
  4035. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4036. * @soc: core txrx main context
  4037. * @tx_desc: tx desc
  4038. * @status: tx status
  4039. *
  4040. * Return: none
  4041. */
  4042. static inline
  4043. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4044. struct dp_vdev *vdev,
  4045. struct dp_tx_desc_s *tx_desc,
  4046. uint8_t status)
  4047. {
  4048. }
  4049. #else
  4050. static inline
  4051. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4052. struct dp_vdev *vdev,
  4053. struct dp_tx_desc_s *tx_desc,
  4054. uint8_t status)
  4055. {
  4056. void *osif_dev;
  4057. ol_txrx_stats_rx_fp stats_cbk;
  4058. uint8_t pkt_type;
  4059. qdf_assert(tx_desc);
  4060. if (!vdev ||
  4061. !vdev->osif_vdev ||
  4062. !vdev->stats_cb)
  4063. return;
  4064. osif_dev = vdev->osif_vdev;
  4065. stats_cbk = vdev->stats_cb;
  4066. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4067. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4068. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4069. &pkt_type);
  4070. }
  4071. #endif
  4072. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4073. QDF_STATUS
  4074. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4075. uint32_t delta_tsf,
  4076. uint32_t *delay_us)
  4077. {
  4078. uint32_t buffer_ts;
  4079. uint32_t delay;
  4080. if (!delay_us)
  4081. return QDF_STATUS_E_INVAL;
  4082. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4083. if (!ts->valid)
  4084. return QDF_STATUS_E_INVAL;
  4085. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4086. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4087. * valid up to 29 bits.
  4088. */
  4089. buffer_ts = ts->buffer_timestamp << 10;
  4090. delay = ts->tsf - buffer_ts - delta_tsf;
  4091. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4092. if (delay > 0x1000000) {
  4093. dp_info_rl("----------------------\n"
  4094. "Tx completion status:\n"
  4095. "----------------------\n"
  4096. "release_src = %d\n"
  4097. "ppdu_id = 0x%x\n"
  4098. "release_reason = %d\n"
  4099. "tsf = %u (0x%x)\n"
  4100. "buffer_timestamp = %u (0x%x)\n"
  4101. "delta_tsf = %u (0x%x)\n",
  4102. ts->release_src, ts->ppdu_id, ts->status,
  4103. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4104. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4105. return QDF_STATUS_E_FAILURE;
  4106. }
  4107. *delay_us = delay;
  4108. return QDF_STATUS_SUCCESS;
  4109. }
  4110. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4111. uint32_t delta_tsf)
  4112. {
  4113. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4114. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4115. DP_MOD_ID_CDP);
  4116. if (!vdev) {
  4117. dp_err_rl("vdev %d does not exist", vdev_id);
  4118. return;
  4119. }
  4120. vdev->delta_tsf = delta_tsf;
  4121. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4122. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4123. }
  4124. #endif
  4125. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4126. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4127. uint8_t vdev_id, bool enable)
  4128. {
  4129. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4130. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4131. DP_MOD_ID_CDP);
  4132. if (!vdev) {
  4133. dp_err_rl("vdev %d does not exist", vdev_id);
  4134. return QDF_STATUS_E_FAILURE;
  4135. }
  4136. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4137. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4138. return QDF_STATUS_SUCCESS;
  4139. }
  4140. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4141. uint32_t *val)
  4142. {
  4143. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4144. struct dp_vdev *vdev;
  4145. uint32_t delay_accum;
  4146. uint32_t pkts_accum;
  4147. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4148. if (!vdev) {
  4149. dp_err_rl("vdev %d does not exist", vdev_id);
  4150. return QDF_STATUS_E_FAILURE;
  4151. }
  4152. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4153. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4154. return QDF_STATUS_E_FAILURE;
  4155. }
  4156. /* Average uplink delay based on current accumulated values */
  4157. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4158. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4159. *val = delay_accum / pkts_accum;
  4160. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4161. delay_accum, pkts_accum);
  4162. /* Reset accumulated values to 0 */
  4163. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4164. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4165. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4166. return QDF_STATUS_SUCCESS;
  4167. }
  4168. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4169. struct hal_tx_completion_status *ts)
  4170. {
  4171. uint32_t ul_delay;
  4172. if (qdf_unlikely(!vdev)) {
  4173. dp_info_rl("vdev is null or delete in progrss");
  4174. return;
  4175. }
  4176. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4177. return;
  4178. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4179. vdev->delta_tsf,
  4180. &ul_delay)))
  4181. return;
  4182. ul_delay /= 1000; /* in unit of ms */
  4183. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4184. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4185. }
  4186. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4187. static inline
  4188. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4189. struct hal_tx_completion_status *ts)
  4190. {
  4191. }
  4192. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4193. /**
  4194. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4195. * @soc: DP soc handle
  4196. * @tx_desc: software descriptor head pointer
  4197. * @ts: Tx completion status
  4198. * @txrx_peer: txrx peer handle
  4199. * @ring_id: ring number
  4200. *
  4201. * Return: none
  4202. */
  4203. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4204. struct dp_tx_desc_s *tx_desc,
  4205. struct hal_tx_completion_status *ts,
  4206. struct dp_txrx_peer *txrx_peer,
  4207. uint8_t ring_id)
  4208. {
  4209. uint32_t length;
  4210. qdf_ether_header_t *eh;
  4211. struct dp_vdev *vdev = NULL;
  4212. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4213. enum qdf_dp_tx_rx_status dp_status;
  4214. if (!nbuf) {
  4215. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4216. goto out;
  4217. }
  4218. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4219. length = qdf_nbuf_len(nbuf);
  4220. dp_status = dp_tx_hw_to_qdf(ts->status);
  4221. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4222. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4223. QDF_TRACE_DEFAULT_PDEV_ID,
  4224. qdf_nbuf_data_addr(nbuf),
  4225. sizeof(qdf_nbuf_data(nbuf)),
  4226. tx_desc->id, ts->status, dp_status));
  4227. dp_tx_comp_debug("-------------------- \n"
  4228. "Tx Completion Stats: \n"
  4229. "-------------------- \n"
  4230. "ack_frame_rssi = %d \n"
  4231. "first_msdu = %d \n"
  4232. "last_msdu = %d \n"
  4233. "msdu_part_of_amsdu = %d \n"
  4234. "rate_stats valid = %d \n"
  4235. "bw = %d \n"
  4236. "pkt_type = %d \n"
  4237. "stbc = %d \n"
  4238. "ldpc = %d \n"
  4239. "sgi = %d \n"
  4240. "mcs = %d \n"
  4241. "ofdma = %d \n"
  4242. "tones_in_ru = %d \n"
  4243. "tsf = %d \n"
  4244. "ppdu_id = %d \n"
  4245. "transmit_cnt = %d \n"
  4246. "tid = %d \n"
  4247. "peer_id = %d\n"
  4248. "tx_status = %d\n",
  4249. ts->ack_frame_rssi, ts->first_msdu,
  4250. ts->last_msdu, ts->msdu_part_of_amsdu,
  4251. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4252. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4253. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4254. ts->transmit_cnt, ts->tid, ts->peer_id,
  4255. ts->status);
  4256. /* Update SoC level stats */
  4257. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4258. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4259. if (!txrx_peer) {
  4260. dp_info_rl("peer is null or deletion in progress");
  4261. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4262. goto out;
  4263. }
  4264. vdev = txrx_peer->vdev;
  4265. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4266. dp_tx_update_uplink_delay(soc, vdev, ts);
  4267. /* check tx complete notification */
  4268. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4269. dp_tx_notify_completion(soc, vdev, tx_desc,
  4270. nbuf, ts->status);
  4271. /* Update per-packet stats for mesh mode */
  4272. if (qdf_unlikely(vdev->mesh_vdev) &&
  4273. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4274. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4275. /* Update peer level stats */
  4276. if (qdf_unlikely(txrx_peer->bss_peer &&
  4277. vdev->opmode == wlan_op_mode_ap)) {
  4278. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4279. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4280. length);
  4281. if (txrx_peer->vdev->tx_encap_type ==
  4282. htt_cmn_pkt_type_ethernet &&
  4283. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4284. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4285. tx.bcast, 1,
  4286. length);
  4287. }
  4288. }
  4289. } else {
  4290. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4291. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4292. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4293. 1, length);
  4294. if (qdf_unlikely(txrx_peer->in_twt)) {
  4295. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4296. tx.tx_success_twt,
  4297. 1, length);
  4298. }
  4299. }
  4300. }
  4301. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4302. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts->tid, ring_id);
  4303. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4304. ts, ts->tid);
  4305. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4306. #ifdef QCA_SUPPORT_RDK_STATS
  4307. if (soc->peerstats_enabled)
  4308. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4309. qdf_ktime_to_ms(tx_desc->timestamp),
  4310. ts->ppdu_id);
  4311. #endif
  4312. out:
  4313. return;
  4314. }
  4315. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4316. defined(QCA_ENHANCED_STATS_SUPPORT)
  4317. /*
  4318. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4319. * @txrx_peer: Datapath txrx_peer handle
  4320. * @length: Length of the packet
  4321. * @tx_status: Tx status from TQM/FW
  4322. * @update: enhanced flag value present in dp_pdev
  4323. *
  4324. * Return: none
  4325. */
  4326. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4327. uint32_t length, uint8_t tx_status,
  4328. bool update)
  4329. {
  4330. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4331. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4332. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4333. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4334. }
  4335. }
  4336. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4337. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4338. uint32_t length, uint8_t tx_status,
  4339. bool update)
  4340. {
  4341. if (!txrx_peer->hw_txrx_stats_en) {
  4342. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4343. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4344. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4345. }
  4346. }
  4347. #else
  4348. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4349. uint32_t length, uint8_t tx_status,
  4350. bool update)
  4351. {
  4352. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4353. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4354. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4355. }
  4356. #endif
  4357. /*
  4358. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4359. * @nbuf: skb buffer
  4360. *
  4361. * Return: none
  4362. */
  4363. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4364. static inline
  4365. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4366. {
  4367. qdf_nbuf_t nbuf = NULL;
  4368. if (next)
  4369. nbuf = next->nbuf;
  4370. if (nbuf) {
  4371. /* prefetch skb->next and first few bytes of skb->cb */
  4372. qdf_prefetch(next->shinfo_addr);
  4373. qdf_prefetch(nbuf);
  4374. /* prefetch skb fields present in different cachelines */
  4375. qdf_prefetch(&nbuf->len);
  4376. qdf_prefetch(&nbuf->users);
  4377. }
  4378. }
  4379. #else
  4380. static inline
  4381. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4382. {
  4383. }
  4384. #endif
  4385. /**
  4386. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4387. * @soc: core txrx main context
  4388. * @desc: software descriptor
  4389. *
  4390. * Return: true when packet is reinjected
  4391. */
  4392. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4393. defined(WLAN_MCAST_MLO)
  4394. static inline bool
  4395. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4396. {
  4397. struct dp_vdev *vdev = NULL;
  4398. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4399. if (!soc->arch_ops.dp_tx_mcast_handler)
  4400. return false;
  4401. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4402. DP_MOD_ID_REINJECT);
  4403. if (qdf_unlikely(!vdev)) {
  4404. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4405. desc->id);
  4406. return false;
  4407. }
  4408. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4409. qdf_nbuf_len(desc->nbuf));
  4410. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4411. dp_tx_desc_release(desc, desc->pool_id);
  4412. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4413. return true;
  4414. }
  4415. return false;
  4416. }
  4417. #else
  4418. static inline bool
  4419. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4420. {
  4421. return false;
  4422. }
  4423. #endif
  4424. /**
  4425. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4426. * @soc: core txrx main context
  4427. * @comp_head: software descriptor head pointer
  4428. * @ring_id: ring number
  4429. *
  4430. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4431. * and release the software descriptors after processing is complete
  4432. *
  4433. * Return: none
  4434. */
  4435. static void
  4436. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4437. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4438. {
  4439. struct dp_tx_desc_s *desc;
  4440. struct dp_tx_desc_s *next;
  4441. struct hal_tx_completion_status ts;
  4442. struct dp_txrx_peer *txrx_peer = NULL;
  4443. uint16_t peer_id = DP_INVALID_PEER;
  4444. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4445. desc = comp_head;
  4446. while (desc) {
  4447. next = desc->next;
  4448. dp_tx_prefetch_next_nbuf_data(next);
  4449. if (peer_id != desc->peer_id) {
  4450. if (txrx_peer)
  4451. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4452. DP_MOD_ID_TX_COMP);
  4453. peer_id = desc->peer_id;
  4454. txrx_peer =
  4455. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4456. &txrx_ref_handle,
  4457. DP_MOD_ID_TX_COMP);
  4458. }
  4459. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4460. desc = next;
  4461. continue;
  4462. }
  4463. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4464. struct dp_pdev *pdev = desc->pdev;
  4465. if (qdf_likely(txrx_peer))
  4466. dp_tx_update_peer_basic_stats(txrx_peer,
  4467. desc->length,
  4468. desc->tx_status,
  4469. false);
  4470. qdf_assert(pdev);
  4471. dp_tx_outstanding_dec(pdev);
  4472. /*
  4473. * Calling a QDF WRAPPER here is creating signifcant
  4474. * performance impact so avoided the wrapper call here
  4475. */
  4476. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4477. desc->id, DP_TX_COMP_UNMAP);
  4478. dp_tx_nbuf_unmap(soc, desc);
  4479. qdf_nbuf_free_simple(desc->nbuf);
  4480. dp_tx_desc_free(soc, desc, desc->pool_id);
  4481. desc = next;
  4482. continue;
  4483. }
  4484. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4485. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4486. ring_id);
  4487. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4488. dp_tx_desc_release(desc, desc->pool_id);
  4489. desc = next;
  4490. }
  4491. if (txrx_peer)
  4492. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4493. }
  4494. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4495. static inline
  4496. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4497. int max_reap_limit)
  4498. {
  4499. bool limit_hit = false;
  4500. limit_hit =
  4501. (num_reaped >= max_reap_limit) ? true : false;
  4502. if (limit_hit)
  4503. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4504. return limit_hit;
  4505. }
  4506. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4507. {
  4508. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4509. }
  4510. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4511. {
  4512. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4513. return cfg->tx_comp_loop_pkt_limit;
  4514. }
  4515. #else
  4516. static inline
  4517. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4518. int max_reap_limit)
  4519. {
  4520. return false;
  4521. }
  4522. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4523. {
  4524. return false;
  4525. }
  4526. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4527. {
  4528. return 0;
  4529. }
  4530. #endif
  4531. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4532. static inline int
  4533. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4534. int *max_reap_limit)
  4535. {
  4536. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4537. max_reap_limit);
  4538. }
  4539. #else
  4540. static inline int
  4541. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4542. int *max_reap_limit)
  4543. {
  4544. return 0;
  4545. }
  4546. #endif
  4547. #ifdef DP_TX_TRACKING
  4548. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4549. {
  4550. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4551. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4552. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4553. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4554. }
  4555. }
  4556. #endif
  4557. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4558. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4559. uint32_t quota)
  4560. {
  4561. void *tx_comp_hal_desc;
  4562. void *last_prefetched_hw_desc = NULL;
  4563. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4564. hal_soc_handle_t hal_soc;
  4565. uint8_t buffer_src;
  4566. struct dp_tx_desc_s *tx_desc = NULL;
  4567. struct dp_tx_desc_s *head_desc = NULL;
  4568. struct dp_tx_desc_s *tail_desc = NULL;
  4569. uint32_t num_processed = 0;
  4570. uint32_t count;
  4571. uint32_t num_avail_for_reap = 0;
  4572. bool force_break = false;
  4573. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4574. int max_reap_limit, ring_near_full;
  4575. DP_HIST_INIT();
  4576. more_data:
  4577. hal_soc = soc->hal_soc;
  4578. /* Re-initialize local variables to be re-used */
  4579. head_desc = NULL;
  4580. tail_desc = NULL;
  4581. count = 0;
  4582. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4583. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4584. &max_reap_limit);
  4585. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4586. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4587. return 0;
  4588. }
  4589. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4590. if (num_avail_for_reap >= quota)
  4591. num_avail_for_reap = quota;
  4592. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4593. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  4594. hal_ring_hdl,
  4595. num_avail_for_reap);
  4596. /* Find head descriptor from completion ring */
  4597. while (qdf_likely(num_avail_for_reap--)) {
  4598. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4599. if (qdf_unlikely(!tx_comp_hal_desc))
  4600. break;
  4601. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4602. tx_comp_hal_desc);
  4603. /* If this buffer was not released by TQM or FW, then it is not
  4604. * Tx completion indication, assert */
  4605. if (qdf_unlikely(buffer_src !=
  4606. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4607. (qdf_unlikely(buffer_src !=
  4608. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4609. uint8_t wbm_internal_error;
  4610. dp_err_rl(
  4611. "Tx comp release_src != TQM | FW but from %d",
  4612. buffer_src);
  4613. hal_dump_comp_desc(tx_comp_hal_desc);
  4614. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4615. /* When WBM sees NULL buffer_addr_info in any of
  4616. * ingress rings it sends an error indication,
  4617. * with wbm_internal_error=1, to a specific ring.
  4618. * The WBM2SW ring used to indicate these errors is
  4619. * fixed in HW, and that ring is being used as Tx
  4620. * completion ring. These errors are not related to
  4621. * Tx completions, and should just be ignored
  4622. */
  4623. wbm_internal_error = hal_get_wbm_internal_error(
  4624. hal_soc,
  4625. tx_comp_hal_desc);
  4626. if (wbm_internal_error) {
  4627. dp_err_rl("Tx comp wbm_internal_error!!");
  4628. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4629. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4630. buffer_src)
  4631. dp_handle_wbm_internal_error(
  4632. soc,
  4633. tx_comp_hal_desc,
  4634. hal_tx_comp_get_buffer_type(
  4635. tx_comp_hal_desc));
  4636. } else {
  4637. dp_err_rl("Tx comp wbm_internal_error false");
  4638. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4639. }
  4640. continue;
  4641. }
  4642. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4643. tx_comp_hal_desc,
  4644. &tx_desc);
  4645. if (!tx_desc) {
  4646. dp_err("unable to retrieve tx_desc!");
  4647. QDF_BUG(0);
  4648. continue;
  4649. }
  4650. tx_desc->buffer_src = buffer_src;
  4651. /*
  4652. * If the release source is FW, process the HTT status
  4653. */
  4654. if (qdf_unlikely(buffer_src ==
  4655. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4656. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4657. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4658. htt_tx_status);
  4659. /* Collect hw completion contents */
  4660. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4661. &tx_desc->comp, 1);
  4662. soc->arch_ops.dp_tx_process_htt_completion(
  4663. soc,
  4664. tx_desc,
  4665. htt_tx_status,
  4666. ring_id);
  4667. } else {
  4668. tx_desc->tx_status =
  4669. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4670. tx_desc->buffer_src = buffer_src;
  4671. /*
  4672. * If the fast completion mode is enabled extended
  4673. * metadata from descriptor is not copied
  4674. */
  4675. if (qdf_likely(tx_desc->flags &
  4676. DP_TX_DESC_FLAG_SIMPLE))
  4677. goto add_to_pool;
  4678. /*
  4679. * If the descriptor is already freed in vdev_detach,
  4680. * continue to next descriptor
  4681. */
  4682. if (qdf_unlikely
  4683. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4684. !tx_desc->flags)) {
  4685. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4686. tx_desc->id);
  4687. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4688. dp_tx_desc_check_corruption(tx_desc);
  4689. continue;
  4690. }
  4691. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4692. dp_tx_comp_info_rl("pdev in down state %d",
  4693. tx_desc->id);
  4694. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4695. dp_tx_comp_free_buf(soc, tx_desc, false);
  4696. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4697. goto next_desc;
  4698. }
  4699. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4700. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4701. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4702. tx_desc->flags, tx_desc->id);
  4703. qdf_assert_always(0);
  4704. }
  4705. /* Collect hw completion contents */
  4706. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4707. &tx_desc->comp, 1);
  4708. add_to_pool:
  4709. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4710. /* First ring descriptor on the cycle */
  4711. if (!head_desc) {
  4712. head_desc = tx_desc;
  4713. tail_desc = tx_desc;
  4714. }
  4715. tail_desc->next = tx_desc;
  4716. tx_desc->next = NULL;
  4717. tail_desc = tx_desc;
  4718. }
  4719. next_desc:
  4720. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4721. /*
  4722. * Processed packet count is more than given quota
  4723. * stop to processing
  4724. */
  4725. count++;
  4726. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  4727. num_avail_for_reap,
  4728. hal_ring_hdl,
  4729. &last_prefetched_hw_desc,
  4730. &last_prefetched_sw_desc);
  4731. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4732. break;
  4733. }
  4734. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4735. /* Process the reaped descriptors */
  4736. if (head_desc)
  4737. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4738. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  4739. /*
  4740. * If we are processing in near-full condition, there are 3 scenario
  4741. * 1) Ring entries has reached critical state
  4742. * 2) Ring entries are still near high threshold
  4743. * 3) Ring entries are below the safe level
  4744. *
  4745. * One more loop will move te state to normal processing and yield
  4746. */
  4747. if (ring_near_full)
  4748. goto more_data;
  4749. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4750. if (num_processed >= quota)
  4751. force_break = true;
  4752. if (!force_break &&
  4753. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4754. hal_ring_hdl)) {
  4755. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4756. if (!hif_exec_should_yield(soc->hif_handle,
  4757. int_ctx->dp_intr_id))
  4758. goto more_data;
  4759. }
  4760. }
  4761. DP_TX_HIST_STATS_PER_PDEV();
  4762. return num_processed;
  4763. }
  4764. #ifdef FEATURE_WLAN_TDLS
  4765. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4766. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4767. {
  4768. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4769. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4770. DP_MOD_ID_TDLS);
  4771. if (!vdev) {
  4772. dp_err("vdev handle for id %d is NULL", vdev_id);
  4773. return NULL;
  4774. }
  4775. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4776. vdev->is_tdls_frame = true;
  4777. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4778. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4779. }
  4780. #endif
  4781. /**
  4782. * dp_tx_vdev_attach() - attach vdev to dp tx
  4783. * @vdev: virtual device instance
  4784. *
  4785. * Return: QDF_STATUS_SUCCESS: success
  4786. * QDF_STATUS_E_RESOURCES: Error return
  4787. */
  4788. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4789. {
  4790. int pdev_id;
  4791. /*
  4792. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4793. */
  4794. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4795. DP_TCL_METADATA_TYPE_VDEV_BASED);
  4796. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4797. vdev->vdev_id);
  4798. pdev_id =
  4799. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4800. vdev->pdev->pdev_id);
  4801. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4802. /*
  4803. * Set HTT Extension Valid bit to 0 by default
  4804. */
  4805. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4806. dp_tx_vdev_update_search_flags(vdev);
  4807. return QDF_STATUS_SUCCESS;
  4808. }
  4809. #ifndef FEATURE_WDS
  4810. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4811. {
  4812. return false;
  4813. }
  4814. #endif
  4815. /**
  4816. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4817. * @vdev: virtual device instance
  4818. *
  4819. * Return: void
  4820. *
  4821. */
  4822. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4823. {
  4824. struct dp_soc *soc = vdev->pdev->soc;
  4825. /*
  4826. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4827. * for TDLS link
  4828. *
  4829. * Enable AddrY (SA based search) only for non-WDS STA and
  4830. * ProxySTA VAP (in HKv1) modes.
  4831. *
  4832. * In all other VAP modes, only DA based search should be
  4833. * enabled
  4834. */
  4835. if (vdev->opmode == wlan_op_mode_sta &&
  4836. vdev->tdls_link_connected)
  4837. vdev->hal_desc_addr_search_flags =
  4838. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4839. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4840. !dp_tx_da_search_override(vdev))
  4841. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4842. else
  4843. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4844. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  4845. vdev->search_type = soc->sta_mode_search_policy;
  4846. else
  4847. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4848. }
  4849. static inline bool
  4850. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4851. struct dp_vdev *vdev,
  4852. struct dp_tx_desc_s *tx_desc)
  4853. {
  4854. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4855. return false;
  4856. /*
  4857. * if vdev is given, then only check whether desc
  4858. * vdev match. if vdev is NULL, then check whether
  4859. * desc pdev match.
  4860. */
  4861. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4862. (tx_desc->pdev == pdev);
  4863. }
  4864. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4865. /**
  4866. * dp_tx_desc_flush() - release resources associated
  4867. * to TX Desc
  4868. *
  4869. * @dp_pdev: Handle to DP pdev structure
  4870. * @vdev: virtual device instance
  4871. * NULL: no specific Vdev is required and check all allcated TX desc
  4872. * on this pdev.
  4873. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4874. *
  4875. * @force_free:
  4876. * true: flush the TX desc.
  4877. * false: only reset the Vdev in each allocated TX desc
  4878. * that associated to current Vdev.
  4879. *
  4880. * This function will go through the TX desc pool to flush
  4881. * the outstanding TX data or reset Vdev to NULL in associated TX
  4882. * Desc.
  4883. */
  4884. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4885. bool force_free)
  4886. {
  4887. uint8_t i;
  4888. uint32_t j;
  4889. uint32_t num_desc, page_id, offset;
  4890. uint16_t num_desc_per_page;
  4891. struct dp_soc *soc = pdev->soc;
  4892. struct dp_tx_desc_s *tx_desc = NULL;
  4893. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4894. if (!vdev && !force_free) {
  4895. dp_err("Reset TX desc vdev, Vdev param is required!");
  4896. return;
  4897. }
  4898. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4899. tx_desc_pool = &soc->tx_desc[i];
  4900. if (!(tx_desc_pool->pool_size) ||
  4901. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4902. !(tx_desc_pool->desc_pages.cacheable_pages))
  4903. continue;
  4904. /*
  4905. * Add flow pool lock protection in case pool is freed
  4906. * due to all tx_desc is recycled when handle TX completion.
  4907. * this is not necessary when do force flush as:
  4908. * a. double lock will happen if dp_tx_desc_release is
  4909. * also trying to acquire it.
  4910. * b. dp interrupt has been disabled before do force TX desc
  4911. * flush in dp_pdev_deinit().
  4912. */
  4913. if (!force_free)
  4914. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4915. num_desc = tx_desc_pool->pool_size;
  4916. num_desc_per_page =
  4917. tx_desc_pool->desc_pages.num_element_per_page;
  4918. for (j = 0; j < num_desc; j++) {
  4919. page_id = j / num_desc_per_page;
  4920. offset = j % num_desc_per_page;
  4921. if (qdf_unlikely(!(tx_desc_pool->
  4922. desc_pages.cacheable_pages)))
  4923. break;
  4924. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4925. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4926. /*
  4927. * Free TX desc if force free is
  4928. * required, otherwise only reset vdev
  4929. * in this TX desc.
  4930. */
  4931. if (force_free) {
  4932. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4933. dp_tx_comp_free_buf(soc, tx_desc,
  4934. false);
  4935. dp_tx_desc_release(tx_desc, i);
  4936. } else {
  4937. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4938. }
  4939. }
  4940. }
  4941. if (!force_free)
  4942. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4943. }
  4944. }
  4945. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4946. /**
  4947. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4948. *
  4949. * @soc: Handle to DP soc structure
  4950. * @tx_desc: pointer of one TX desc
  4951. * @desc_pool_id: TX Desc pool id
  4952. */
  4953. static inline void
  4954. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4955. uint8_t desc_pool_id)
  4956. {
  4957. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4958. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4959. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4960. }
  4961. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4962. bool force_free)
  4963. {
  4964. uint8_t i, num_pool;
  4965. uint32_t j;
  4966. uint32_t num_desc, page_id, offset;
  4967. uint16_t num_desc_per_page;
  4968. struct dp_soc *soc = pdev->soc;
  4969. struct dp_tx_desc_s *tx_desc = NULL;
  4970. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4971. if (!vdev && !force_free) {
  4972. dp_err("Reset TX desc vdev, Vdev param is required!");
  4973. return;
  4974. }
  4975. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4976. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4977. for (i = 0; i < num_pool; i++) {
  4978. tx_desc_pool = &soc->tx_desc[i];
  4979. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4980. continue;
  4981. num_desc_per_page =
  4982. tx_desc_pool->desc_pages.num_element_per_page;
  4983. for (j = 0; j < num_desc; j++) {
  4984. page_id = j / num_desc_per_page;
  4985. offset = j % num_desc_per_page;
  4986. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4987. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4988. if (force_free) {
  4989. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4990. dp_tx_comp_free_buf(soc, tx_desc,
  4991. false);
  4992. dp_tx_desc_release(tx_desc, i);
  4993. } else {
  4994. dp_tx_desc_reset_vdev(soc, tx_desc,
  4995. i);
  4996. }
  4997. }
  4998. }
  4999. }
  5000. }
  5001. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5002. /**
  5003. * dp_tx_vdev_detach() - detach vdev from dp tx
  5004. * @vdev: virtual device instance
  5005. *
  5006. * Return: QDF_STATUS_SUCCESS: success
  5007. * QDF_STATUS_E_RESOURCES: Error return
  5008. */
  5009. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5010. {
  5011. struct dp_pdev *pdev = vdev->pdev;
  5012. /* Reset TX desc associated to this Vdev as NULL */
  5013. dp_tx_desc_flush(pdev, vdev, false);
  5014. return QDF_STATUS_SUCCESS;
  5015. }
  5016. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5017. /* Pools will be allocated dynamically */
  5018. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5019. int num_desc)
  5020. {
  5021. uint8_t i;
  5022. for (i = 0; i < num_pool; i++) {
  5023. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5024. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5025. }
  5026. return QDF_STATUS_SUCCESS;
  5027. }
  5028. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5029. uint32_t num_desc)
  5030. {
  5031. return QDF_STATUS_SUCCESS;
  5032. }
  5033. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5034. {
  5035. }
  5036. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5037. {
  5038. uint8_t i;
  5039. for (i = 0; i < num_pool; i++)
  5040. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5041. }
  5042. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5043. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5044. uint32_t num_desc)
  5045. {
  5046. uint8_t i, count;
  5047. /* Allocate software Tx descriptor pools */
  5048. for (i = 0; i < num_pool; i++) {
  5049. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5050. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5051. FL("Tx Desc Pool alloc %d failed %pK"),
  5052. i, soc);
  5053. goto fail;
  5054. }
  5055. }
  5056. return QDF_STATUS_SUCCESS;
  5057. fail:
  5058. for (count = 0; count < i; count++)
  5059. dp_tx_desc_pool_free(soc, count);
  5060. return QDF_STATUS_E_NOMEM;
  5061. }
  5062. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5063. uint32_t num_desc)
  5064. {
  5065. uint8_t i;
  5066. for (i = 0; i < num_pool; i++) {
  5067. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5068. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5069. FL("Tx Desc Pool init %d failed %pK"),
  5070. i, soc);
  5071. return QDF_STATUS_E_NOMEM;
  5072. }
  5073. }
  5074. return QDF_STATUS_SUCCESS;
  5075. }
  5076. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5077. {
  5078. uint8_t i;
  5079. for (i = 0; i < num_pool; i++)
  5080. dp_tx_desc_pool_deinit(soc, i);
  5081. }
  5082. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5083. {
  5084. uint8_t i;
  5085. for (i = 0; i < num_pool; i++)
  5086. dp_tx_desc_pool_free(soc, i);
  5087. }
  5088. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5089. /**
  5090. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5091. * @soc: core txrx main context
  5092. * @num_pool: number of pools
  5093. *
  5094. */
  5095. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5096. {
  5097. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5098. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5099. }
  5100. /**
  5101. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5102. * @soc: core txrx main context
  5103. * @num_pool: number of pools
  5104. *
  5105. */
  5106. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5107. {
  5108. dp_tx_tso_desc_pool_free(soc, num_pool);
  5109. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5110. }
  5111. /**
  5112. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5113. * @soc: core txrx main context
  5114. *
  5115. * This function frees all tx related descriptors as below
  5116. * 1. Regular TX descriptors (static pools)
  5117. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5118. * 3. TSO descriptors
  5119. *
  5120. */
  5121. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5122. {
  5123. uint8_t num_pool;
  5124. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5125. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5126. dp_tx_ext_desc_pool_free(soc, num_pool);
  5127. dp_tx_delete_static_pools(soc, num_pool);
  5128. }
  5129. /**
  5130. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5131. * @soc: core txrx main context
  5132. *
  5133. * This function de-initializes all tx related descriptors as below
  5134. * 1. Regular TX descriptors (static pools)
  5135. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5136. * 3. TSO descriptors
  5137. *
  5138. */
  5139. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5140. {
  5141. uint8_t num_pool;
  5142. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5143. dp_tx_flow_control_deinit(soc);
  5144. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5145. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5146. dp_tx_deinit_static_pools(soc, num_pool);
  5147. }
  5148. /**
  5149. * dp_tso_attach() - TSO attach handler
  5150. * @txrx_soc: Opaque Dp handle
  5151. *
  5152. * Reserve TSO descriptor buffers
  5153. *
  5154. * Return: QDF_STATUS_E_FAILURE on failure or
  5155. * QDF_STATUS_SUCCESS on success
  5156. */
  5157. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5158. uint8_t num_pool,
  5159. uint32_t num_desc)
  5160. {
  5161. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5162. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5163. return QDF_STATUS_E_FAILURE;
  5164. }
  5165. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5166. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5167. num_pool, soc);
  5168. return QDF_STATUS_E_FAILURE;
  5169. }
  5170. return QDF_STATUS_SUCCESS;
  5171. }
  5172. /**
  5173. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5174. * @soc: DP soc handle
  5175. * @num_pool: Number of pools
  5176. * @num_desc: Number of descriptors
  5177. *
  5178. * Initialize TSO descriptor pools
  5179. *
  5180. * Return: QDF_STATUS_E_FAILURE on failure or
  5181. * QDF_STATUS_SUCCESS on success
  5182. */
  5183. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5184. uint8_t num_pool,
  5185. uint32_t num_desc)
  5186. {
  5187. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5188. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5189. return QDF_STATUS_E_FAILURE;
  5190. }
  5191. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5192. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5193. num_pool, soc);
  5194. return QDF_STATUS_E_FAILURE;
  5195. }
  5196. return QDF_STATUS_SUCCESS;
  5197. }
  5198. /**
  5199. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5200. * @soc: core txrx main context
  5201. *
  5202. * This function allocates memory for following descriptor pools
  5203. * 1. regular sw tx descriptor pools (static pools)
  5204. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5205. * 3. TSO descriptor pools
  5206. *
  5207. * Return: QDF_STATUS_SUCCESS: success
  5208. * QDF_STATUS_E_RESOURCES: Error return
  5209. */
  5210. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5211. {
  5212. uint8_t num_pool;
  5213. uint32_t num_desc;
  5214. uint32_t num_ext_desc;
  5215. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5216. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5217. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5218. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5219. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5220. __func__, num_pool, num_desc);
  5221. if ((num_pool > MAX_TXDESC_POOLS) ||
  5222. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5223. goto fail1;
  5224. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5225. goto fail1;
  5226. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5227. goto fail2;
  5228. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5229. return QDF_STATUS_SUCCESS;
  5230. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5231. goto fail3;
  5232. return QDF_STATUS_SUCCESS;
  5233. fail3:
  5234. dp_tx_ext_desc_pool_free(soc, num_pool);
  5235. fail2:
  5236. dp_tx_delete_static_pools(soc, num_pool);
  5237. fail1:
  5238. return QDF_STATUS_E_RESOURCES;
  5239. }
  5240. /**
  5241. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5242. * @soc: core txrx main context
  5243. *
  5244. * This function initializes the following TX descriptor pools
  5245. * 1. regular sw tx descriptor pools (static pools)
  5246. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5247. * 3. TSO descriptor pools
  5248. *
  5249. * Return: QDF_STATUS_SUCCESS: success
  5250. * QDF_STATUS_E_RESOURCES: Error return
  5251. */
  5252. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5253. {
  5254. uint8_t num_pool;
  5255. uint32_t num_desc;
  5256. uint32_t num_ext_desc;
  5257. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5258. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5259. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5260. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5261. goto fail1;
  5262. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5263. goto fail2;
  5264. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5265. return QDF_STATUS_SUCCESS;
  5266. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5267. goto fail3;
  5268. dp_tx_flow_control_init(soc);
  5269. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5270. return QDF_STATUS_SUCCESS;
  5271. fail3:
  5272. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5273. fail2:
  5274. dp_tx_deinit_static_pools(soc, num_pool);
  5275. fail1:
  5276. return QDF_STATUS_E_RESOURCES;
  5277. }
  5278. /**
  5279. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5280. * @txrx_soc: dp soc handle
  5281. *
  5282. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5283. * QDF_STATUS_E_FAILURE
  5284. */
  5285. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5286. {
  5287. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5288. uint8_t num_pool;
  5289. uint32_t num_desc;
  5290. uint32_t num_ext_desc;
  5291. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5292. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5293. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5294. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5295. return QDF_STATUS_E_FAILURE;
  5296. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5297. return QDF_STATUS_E_FAILURE;
  5298. return QDF_STATUS_SUCCESS;
  5299. }
  5300. /**
  5301. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5302. * @txrx_soc: dp soc handle
  5303. *
  5304. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5305. */
  5306. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5307. {
  5308. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5309. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5310. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5311. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5312. return QDF_STATUS_SUCCESS;
  5313. }
  5314. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5315. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5316. enum qdf_pkt_timestamp_index index, uint64_t time,
  5317. qdf_nbuf_t nbuf)
  5318. {
  5319. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5320. uint64_t tsf_time;
  5321. if (vdev->get_tsf_time) {
  5322. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5323. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5324. }
  5325. }
  5326. }
  5327. void dp_pkt_get_timestamp(uint64_t *time)
  5328. {
  5329. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5330. *time = qdf_get_log_timestamp();
  5331. }
  5332. #endif