sde_rm.c 71 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  7. #include "sde_kms.h"
  8. #include "sde_hw_lm.h"
  9. #include "sde_hw_ctl.h"
  10. #include "sde_hw_cdm.h"
  11. #include "sde_hw_dspp.h"
  12. #include "sde_hw_ds.h"
  13. #include "sde_hw_pingpong.h"
  14. #include "sde_hw_intf.h"
  15. #include "sde_hw_wb.h"
  16. #include "sde_encoder.h"
  17. #include "sde_connector.h"
  18. #include "sde_hw_dsc.h"
  19. #include "sde_hw_vdc.h"
  20. #include "sde_crtc.h"
  21. #include "sde_hw_qdss.h"
  22. #include "sde_vbif.h"
  23. #include "sde_hw_dnsc_blur.h"
  24. #define RESERVED_BY_OTHER(h, r) \
  25. (((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id)) ||\
  26. ((h)->rsvp_nxt && ((h)->rsvp_nxt->enc_id != (r)->enc_id)))
  27. #define RESERVED_BY_CURRENT(h, r) \
  28. (((h)->rsvp && ((h)->rsvp->enc_id == (r)->enc_id)))
  29. #define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK))
  30. #define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_CLEAR))
  31. #define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DSPP))
  32. #define RM_RQ_DS(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DS))
  33. #define RM_RQ_CWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_CWB))
  34. #define RM_RQ_DCWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DCWB))
  35. #define RM_RQ_DNSC_BLUR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DNSC_BLUR))
  36. #define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \
  37. (t).num_comp_enc == (r).num_enc && \
  38. (t).num_intf == (r).num_intf && \
  39. (t).comp_type == (r).comp_type)
  40. #define IS_COMPATIBLE_PP_DSC(p, d) (p % 2 == d % 2)
  41. /* ~one vsync poll time for rsvp_nxt to cleared by modeset from commit thread */
  42. #define RM_NXT_CLEAR_POLL_TIMEOUT_US 33000
  43. /**
  44. * toplogy information to be used when ctl path version does not
  45. * support driving more than one interface per ctl_path
  46. */
  47. static const struct sde_rm_topology_def g_top_table[SDE_RM_TOPOLOGY_MAX] = {
  48. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  49. MSM_DISPLAY_COMPRESSION_NONE },
  50. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  51. MSM_DISPLAY_COMPRESSION_NONE },
  52. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  53. MSM_DISPLAY_COMPRESSION_DSC },
  54. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 2, true,
  55. MSM_DISPLAY_COMPRESSION_NONE },
  56. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 2, true,
  57. MSM_DISPLAY_COMPRESSION_DSC },
  58. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  59. MSM_DISPLAY_COMPRESSION_NONE },
  60. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  61. MSM_DISPLAY_COMPRESSION_DSC },
  62. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  63. MSM_DISPLAY_COMPRESSION_DSC },
  64. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, true,
  65. MSM_DISPLAY_COMPRESSION_NONE },
  66. };
  67. /**
  68. * topology information to be used when the ctl path version
  69. * is SDE_CTL_CFG_VERSION_1_0_0
  70. */
  71. static const struct sde_rm_topology_def g_top_table_v1[SDE_RM_TOPOLOGY_MAX] = {
  72. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  73. MSM_DISPLAY_COMPRESSION_NONE },
  74. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  75. MSM_DISPLAY_COMPRESSION_NONE },
  76. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  77. MSM_DISPLAY_COMPRESSION_DSC },
  78. { SDE_RM_TOPOLOGY_SINGLEPIPE_VDC, 1, 1, 1, 1, false,
  79. MSM_DISPLAY_COMPRESSION_VDC },
  80. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 1, false,
  81. MSM_DISPLAY_COMPRESSION_NONE },
  82. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 1, false,
  83. MSM_DISPLAY_COMPRESSION_DSC },
  84. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  85. MSM_DISPLAY_COMPRESSION_NONE },
  86. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  87. MSM_DISPLAY_COMPRESSION_DSC },
  88. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_VDC, 2, 1, 1, 1, false,
  89. MSM_DISPLAY_COMPRESSION_VDC },
  90. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  91. MSM_DISPLAY_COMPRESSION_DSC },
  92. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, false,
  93. MSM_DISPLAY_COMPRESSION_NONE },
  94. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE, 4, 0, 2, 1, false,
  95. MSM_DISPLAY_COMPRESSION_NONE },
  96. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE_DSC, 4, 3, 2, 1, false,
  97. MSM_DISPLAY_COMPRESSION_DSC },
  98. { SDE_RM_TOPOLOGY_QUADPIPE_DSCMERGE, 4, 4, 2, 1, false,
  99. MSM_DISPLAY_COMPRESSION_DSC },
  100. { SDE_RM_TOPOLOGY_QUADPIPE_DSC4HSMERGE, 4, 4, 1, 1, false,
  101. MSM_DISPLAY_COMPRESSION_DSC },
  102. };
  103. char sde_hw_blk_str[SDE_HW_BLK_MAX][SDE_HW_BLK_NAME_LEN] = {
  104. "top",
  105. "sspp",
  106. "lm",
  107. "dspp",
  108. "ds",
  109. "ctl",
  110. "cdm",
  111. "pingpong",
  112. "intf",
  113. "wb",
  114. "dsc",
  115. "vdc",
  116. "merge_3d",
  117. "qdss",
  118. "dnsc_blur"
  119. };
  120. /**
  121. * struct sde_rm_requirements - Reservation requirements parameter bundle
  122. * @top_ctrl: topology control preference from kernel client
  123. * @top: selected topology for the display
  124. * @hw_res: Hardware resources required as reported by the encoders
  125. */
  126. struct sde_rm_requirements {
  127. uint64_t top_ctrl;
  128. const struct sde_rm_topology_def *topology;
  129. struct sde_encoder_hw_resources hw_res;
  130. };
  131. /**
  132. * struct sde_rm_rsvp - Use Case Reservation tagging structure
  133. * Used to tag HW blocks as reserved by a CRTC->Encoder->Connector chain
  134. * By using as a tag, rather than lists of pointers to HW blocks used
  135. * we can avoid some list management since we don't know how many blocks
  136. * of each type a given use case may require.
  137. * @list: List head for list of all reservations
  138. * @seq: Global RSVP sequence number for debugging, especially for
  139. * differentiating differenct allocations for same encoder.
  140. * @enc_id: Reservations are tracked by Encoder DRM object ID.
  141. * CRTCs may be connected to multiple Encoders.
  142. * An encoder or connector id identifies the display path.
  143. * @topology: DRM<->HW topology use case
  144. * @pending: True for pending rsvp-nxt, cleared when the rsvp is committed
  145. */
  146. struct sde_rm_rsvp {
  147. struct list_head list;
  148. uint32_t seq;
  149. uint32_t enc_id;
  150. enum sde_rm_topology_name topology;
  151. bool pending;
  152. };
  153. /**
  154. * struct sde_rm_hw_blk - hardware block tracking list member
  155. * @list: List head for list of all hardware blocks tracking items
  156. * @rsvp: Pointer to use case reservation if reserved by a client
  157. * @rsvp_nxt: Temporary pointer used during reservation to the incoming
  158. * request. Will be swapped into rsvp if proposal is accepted
  159. * @type: Type of hardware block this structure tracks
  160. * @id: Hardware ID number, within it's own space, ie. LM_X
  161. * @catalog: Pointer to the hardware catalog entry for this block
  162. * @hw: Pointer to the hardware register access object for this block
  163. */
  164. struct sde_rm_hw_blk {
  165. struct list_head list;
  166. struct sde_rm_rsvp *rsvp;
  167. struct sde_rm_rsvp *rsvp_nxt;
  168. enum sde_hw_blk_type type;
  169. uint32_t id;
  170. struct sde_hw_blk_reg_map *hw;
  171. };
  172. /**
  173. * sde_rm_dbg_rsvp_stage - enum of steps in making reservation for event logging
  174. */
  175. enum sde_rm_dbg_rsvp_stage {
  176. SDE_RM_STAGE_BEGIN,
  177. SDE_RM_STAGE_AFTER_CLEAR,
  178. SDE_RM_STAGE_AFTER_RSVPNEXT,
  179. SDE_RM_STAGE_FINAL
  180. };
  181. static void _sde_rm_inc_resource_info_lm(struct sde_rm *rm,
  182. struct msm_resource_caps_info *avail_res,
  183. struct sde_rm_hw_blk *blk)
  184. {
  185. struct sde_rm_hw_blk *blk2;
  186. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  187. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  188. /* Do not track & expose dummy mixers */
  189. if (lm_cfg->dummy_mixer)
  190. return;
  191. avail_res->num_lm++;
  192. /* Check for 3d muxes by comparing paired lms */
  193. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  194. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  195. /*
  196. * If lm2 is free, or
  197. * lm1 & lm2 reserved by same enc, check mask
  198. */
  199. if ((!blk2->rsvp || (blk->rsvp &&
  200. blk2->rsvp->enc_id == blk->rsvp->enc_id
  201. && lm_cfg->id > lm_cfg2->id)) &&
  202. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  203. avail_res->num_3dmux++;
  204. }
  205. }
  206. static void _sde_rm_dec_resource_info_lm(struct sde_rm *rm,
  207. struct msm_resource_caps_info *avail_res,
  208. struct sde_rm_hw_blk *blk)
  209. {
  210. struct sde_rm_hw_blk *blk2;
  211. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  212. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  213. /* Do not track & expose dummy mixers */
  214. if (lm_cfg->dummy_mixer)
  215. return;
  216. avail_res->num_lm--;
  217. /* Check for 3d muxes by comparing paired lms */
  218. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  219. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  220. /* If lm2 is free and lm1 is now being reserved */
  221. if (!blk2->rsvp &&
  222. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  223. avail_res->num_3dmux--;
  224. }
  225. }
  226. static void _sde_rm_inc_resource_info(struct sde_rm *rm,
  227. struct msm_resource_caps_info *avail_res,
  228. struct sde_rm_hw_blk *blk)
  229. {
  230. enum sde_hw_blk_type type = blk->type;
  231. if (type == SDE_HW_BLK_LM)
  232. _sde_rm_inc_resource_info_lm(rm, avail_res, blk);
  233. else if (type == SDE_HW_BLK_CTL)
  234. avail_res->num_ctl++;
  235. else if (type == SDE_HW_BLK_DSC)
  236. avail_res->num_dsc++;
  237. else if (type == SDE_HW_BLK_VDC)
  238. avail_res->num_vdc++;
  239. }
  240. static void _sde_rm_dec_resource_info(struct sde_rm *rm,
  241. struct msm_resource_caps_info *avail_res,
  242. struct sde_rm_hw_blk *blk)
  243. {
  244. enum sde_hw_blk_type type = blk->type;
  245. if (type == SDE_HW_BLK_LM)
  246. _sde_rm_dec_resource_info_lm(rm, avail_res, blk);
  247. else if (type == SDE_HW_BLK_CTL)
  248. avail_res->num_ctl--;
  249. else if (type == SDE_HW_BLK_DSC)
  250. avail_res->num_dsc--;
  251. else if (type == SDE_HW_BLK_VDC)
  252. avail_res->num_vdc--;
  253. }
  254. void sde_rm_get_resource_info(struct sde_rm *rm,
  255. struct drm_encoder *drm_enc,
  256. struct msm_resource_caps_info *avail_res)
  257. {
  258. struct sde_rm_hw_blk *blk;
  259. enum sde_hw_blk_type type;
  260. struct sde_rm_rsvp rsvp;
  261. const struct sde_lm_cfg *lm_cfg;
  262. bool is_built_in, is_pref;
  263. u32 lm_pref = (BIT(SDE_DISP_PRIMARY_PREF) | BIT(SDE_DISP_SECONDARY_PREF));
  264. /* Get all currently available resources */
  265. memcpy(avail_res, &rm->avail_res,
  266. sizeof(rm->avail_res));
  267. if (!drm_enc)
  268. return;
  269. is_built_in = sde_encoder_is_built_in_display(drm_enc);
  270. rsvp.enc_id = drm_enc->base.id;
  271. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  272. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  273. /* Add back resources allocated to the given encoder */
  274. if (blk->rsvp && blk->rsvp->enc_id == rsvp.enc_id)
  275. _sde_rm_inc_resource_info(rm, avail_res, blk);
  276. /**
  277. * Remove unallocated preferred lms that cannot reserved
  278. * by non built-in displays.
  279. */
  280. if (type == SDE_HW_BLK_LM) {
  281. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  282. is_pref = lm_cfg->features & lm_pref;
  283. if (!blk->rsvp && !is_built_in && is_pref)
  284. _sde_rm_dec_resource_info(rm, avail_res, blk);
  285. }
  286. }
  287. }
  288. }
  289. static void _sde_rm_print_rsvps(
  290. struct sde_rm *rm,
  291. enum sde_rm_dbg_rsvp_stage stage)
  292. {
  293. struct sde_rm_rsvp *rsvp;
  294. struct sde_rm_hw_blk *blk;
  295. enum sde_hw_blk_type type;
  296. SDE_DEBUG("%d\n", stage);
  297. list_for_each_entry(rsvp, &rm->rsvps, list) {
  298. SDE_DEBUG("%d rsvp%s[s%ue%u] topology %d\n", stage, rsvp->pending ? "_nxt" : "",
  299. rsvp->seq, rsvp->enc_id, rsvp->topology);
  300. SDE_EVT32(stage, rsvp->seq, rsvp->enc_id, rsvp->topology, rsvp->pending);
  301. }
  302. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  303. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  304. if (!blk->rsvp && !blk->rsvp_nxt)
  305. continue;
  306. SDE_DEBUG("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
  307. (blk->rsvp) ? blk->rsvp->seq : 0,
  308. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  309. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  310. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  311. blk->type, blk->id);
  312. SDE_EVT32(stage,
  313. (blk->rsvp) ? blk->rsvp->seq : 0,
  314. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  315. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  316. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  317. blk->type, blk->id);
  318. }
  319. }
  320. }
  321. static void _sde_rm_print_rsvps_by_type(
  322. struct sde_rm *rm,
  323. enum sde_hw_blk_type type)
  324. {
  325. struct sde_rm_hw_blk *blk;
  326. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  327. if (!blk->rsvp && !blk->rsvp_nxt)
  328. continue;
  329. SDE_ERROR("rsvp[s%ue%u->s%ue%u] %d %d\n",
  330. (blk->rsvp) ? blk->rsvp->seq : 0,
  331. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  332. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  333. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  334. blk->type, blk->id);
  335. SDE_EVT32((blk->rsvp) ? blk->rsvp->seq : 0,
  336. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  337. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  338. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  339. blk->type, blk->id);
  340. }
  341. }
  342. struct sde_hw_mdp *sde_rm_get_mdp(struct sde_rm *rm)
  343. {
  344. return rm->hw_mdp;
  345. }
  346. void sde_rm_init_hw_iter(
  347. struct sde_rm_hw_iter *iter,
  348. uint32_t enc_id,
  349. enum sde_hw_blk_type type)
  350. {
  351. memset(iter, 0, sizeof(*iter));
  352. iter->enc_id = enc_id;
  353. iter->type = type;
  354. }
  355. enum sde_rm_topology_name sde_rm_get_topology_name(struct sde_rm *rm,
  356. struct msm_display_topology topology)
  357. {
  358. int i;
  359. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  360. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  361. topology))
  362. return rm->topology_tbl[i].top_name;
  363. return SDE_RM_TOPOLOGY_NONE;
  364. }
  365. static bool _sde_rm_get_hw_locked(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  366. {
  367. struct list_head *blk_list;
  368. if (!rm || !i || i->type >= SDE_HW_BLK_MAX) {
  369. SDE_ERROR("invalid rm\n");
  370. return false;
  371. }
  372. i->hw = NULL;
  373. blk_list = &rm->hw_blks[i->type];
  374. if (i->blk && (&i->blk->list == blk_list)) {
  375. SDE_DEBUG("attempt resume iteration past last\n");
  376. return false;
  377. }
  378. i->blk = list_prepare_entry(i->blk, blk_list, list);
  379. list_for_each_entry_continue(i->blk, blk_list, list) {
  380. struct sde_rm_rsvp *rsvp = i->blk->rsvp;
  381. if (i->blk->type != i->type) {
  382. SDE_ERROR("found incorrect block type %d on %d list\n",
  383. i->blk->type, i->type);
  384. return false;
  385. }
  386. if ((i->enc_id == 0) || (rsvp && rsvp->enc_id == i->enc_id)) {
  387. i->hw = i->blk->hw;
  388. SDE_DEBUG("found type %d id %d for enc %d\n",
  389. i->type, i->blk->id, i->enc_id);
  390. return true;
  391. }
  392. }
  393. SDE_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id);
  394. return false;
  395. }
  396. static bool _sde_rm_request_hw_blk_locked(struct sde_rm *rm,
  397. struct sde_rm_hw_request *hw_blk_info)
  398. {
  399. struct list_head *blk_list;
  400. struct sde_rm_hw_blk *blk = NULL;
  401. if (!rm || !hw_blk_info || hw_blk_info->type >= SDE_HW_BLK_MAX) {
  402. SDE_ERROR("invalid rm\n");
  403. return false;
  404. }
  405. hw_blk_info->hw = NULL;
  406. blk_list = &rm->hw_blks[hw_blk_info->type];
  407. blk = list_prepare_entry(blk, blk_list, list);
  408. list_for_each_entry_continue(blk, blk_list, list) {
  409. if (blk->type != hw_blk_info->type) {
  410. SDE_ERROR("found incorrect block type %d on %d list\n",
  411. blk->type, hw_blk_info->type);
  412. return false;
  413. }
  414. if (blk->id == hw_blk_info->id) {
  415. hw_blk_info->hw = blk->hw;
  416. SDE_DEBUG("found type %d id %d\n",
  417. blk->type, blk->id);
  418. return true;
  419. }
  420. }
  421. SDE_DEBUG("no match, type %d id %d\n", hw_blk_info->type,
  422. hw_blk_info->id);
  423. return false;
  424. }
  425. bool sde_rm_get_hw(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  426. {
  427. bool ret;
  428. mutex_lock(&rm->rm_lock);
  429. ret = _sde_rm_get_hw_locked(rm, i);
  430. mutex_unlock(&rm->rm_lock);
  431. return ret;
  432. }
  433. bool sde_rm_request_hw_blk(struct sde_rm *rm, struct sde_rm_hw_request *hw)
  434. {
  435. bool ret;
  436. mutex_lock(&rm->rm_lock);
  437. ret = _sde_rm_request_hw_blk_locked(rm, hw);
  438. mutex_unlock(&rm->rm_lock);
  439. return ret;
  440. }
  441. static void _sde_rm_hw_destroy(enum sde_hw_blk_type type, struct sde_hw_blk_reg_map *hw)
  442. {
  443. switch (type) {
  444. case SDE_HW_BLK_LM:
  445. sde_hw_lm_destroy(hw);
  446. break;
  447. case SDE_HW_BLK_DSPP:
  448. sde_hw_dspp_destroy(hw);
  449. break;
  450. case SDE_HW_BLK_DS:
  451. sde_hw_ds_destroy(hw);
  452. break;
  453. case SDE_HW_BLK_CTL:
  454. sde_hw_ctl_destroy(hw);
  455. break;
  456. case SDE_HW_BLK_CDM:
  457. sde_hw_cdm_destroy(hw);
  458. break;
  459. case SDE_HW_BLK_PINGPONG:
  460. sde_hw_pingpong_destroy(hw);
  461. break;
  462. case SDE_HW_BLK_INTF:
  463. sde_hw_intf_destroy(hw);
  464. break;
  465. case SDE_HW_BLK_WB:
  466. sde_hw_wb_destroy(hw);
  467. break;
  468. case SDE_HW_BLK_DSC:
  469. sde_hw_dsc_destroy(hw);
  470. break;
  471. case SDE_HW_BLK_VDC:
  472. sde_hw_vdc_destroy(hw);
  473. break;
  474. case SDE_HW_BLK_QDSS:
  475. sde_hw_qdss_destroy(hw);
  476. break;
  477. case SDE_HW_BLK_DNSC_BLUR:
  478. sde_hw_dnsc_blur_destroy(hw);
  479. break;
  480. case SDE_HW_BLK_SSPP:
  481. /* SSPPs are not managed by the resource manager */
  482. case SDE_HW_BLK_TOP:
  483. /* Top is a singleton, not managed in hw_blks list */
  484. case SDE_HW_BLK_MAX:
  485. default:
  486. SDE_ERROR("unsupported block type %d\n", type);
  487. break;
  488. }
  489. }
  490. int sde_rm_destroy(struct sde_rm *rm)
  491. {
  492. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  493. struct sde_rm_hw_blk *hw_cur, *hw_nxt;
  494. enum sde_hw_blk_type type;
  495. if (!rm) {
  496. SDE_ERROR("invalid rm\n");
  497. return -EINVAL;
  498. }
  499. list_for_each_entry_safe(rsvp_cur, rsvp_nxt, &rm->rsvps, list) {
  500. list_del(&rsvp_cur->list);
  501. kfree(rsvp_cur);
  502. }
  503. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  504. list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
  505. list) {
  506. list_del(&hw_cur->list);
  507. _sde_rm_hw_destroy(hw_cur->type, hw_cur->hw);
  508. kfree(hw_cur);
  509. }
  510. }
  511. sde_hw_mdp_destroy(rm->hw_mdp);
  512. rm->hw_mdp = NULL;
  513. mutex_destroy(&rm->rm_lock);
  514. return 0;
  515. }
  516. static int _sde_rm_hw_blk_create(
  517. struct sde_rm *rm,
  518. struct sde_mdss_cfg *cat,
  519. void __iomem *mmio,
  520. enum sde_hw_blk_type type,
  521. uint32_t id,
  522. void *hw_catalog_info)
  523. {
  524. int rc;
  525. struct sde_rm_hw_blk *blk;
  526. struct sde_hw_mdp *hw_mdp;
  527. struct sde_hw_blk_reg_map *hw;
  528. struct sde_kms *sde_kms = to_sde_kms(ddev_to_msm_kms(rm->dev));
  529. struct sde_vbif_clk_client clk_client = {0};
  530. hw_mdp = rm->hw_mdp;
  531. switch (type) {
  532. case SDE_HW_BLK_LM:
  533. hw = sde_hw_lm_init(id, mmio, cat);
  534. break;
  535. case SDE_HW_BLK_DSPP:
  536. hw = sde_hw_dspp_init(id, mmio, cat);
  537. break;
  538. case SDE_HW_BLK_DS:
  539. hw = sde_hw_ds_init(id, mmio, cat);
  540. break;
  541. case SDE_HW_BLK_CTL:
  542. hw = sde_hw_ctl_init(id, mmio, cat);
  543. break;
  544. case SDE_HW_BLK_CDM:
  545. hw = sde_hw_cdm_init(id, mmio, cat, hw_mdp);
  546. break;
  547. case SDE_HW_BLK_PINGPONG:
  548. hw = sde_hw_pingpong_init(id, mmio, cat);
  549. break;
  550. case SDE_HW_BLK_INTF:
  551. hw = sde_hw_intf_init(id, mmio, cat);
  552. break;
  553. case SDE_HW_BLK_WB:
  554. hw = sde_hw_wb_init(id, mmio, cat, hw_mdp, &clk_client);
  555. break;
  556. case SDE_HW_BLK_DSC:
  557. hw = sde_hw_dsc_init(id, mmio, cat);
  558. break;
  559. case SDE_HW_BLK_VDC:
  560. hw = sde_hw_vdc_init(id, mmio, cat);
  561. break;
  562. case SDE_HW_BLK_QDSS:
  563. hw = sde_hw_qdss_init(id, mmio, cat);
  564. break;
  565. case SDE_HW_BLK_DNSC_BLUR:
  566. hw = sde_hw_dnsc_blur_init(id, mmio, cat);
  567. break;
  568. case SDE_HW_BLK_SSPP:
  569. /* SSPPs are not managed by the resource manager */
  570. case SDE_HW_BLK_TOP:
  571. /* Top is a singleton, not managed in hw_blks list */
  572. case SDE_HW_BLK_MAX:
  573. default:
  574. SDE_ERROR("unsupported block type %d\n", type);
  575. return -EINVAL;
  576. }
  577. if (IS_ERR_OR_NULL(hw)) {
  578. SDE_ERROR("failed hw object creation: type %d, err %ld\n",
  579. type, PTR_ERR(hw));
  580. return -EFAULT;
  581. }
  582. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  583. if (!blk) {
  584. _sde_rm_hw_destroy(type, hw);
  585. return -ENOMEM;
  586. }
  587. blk->type = type;
  588. blk->id = id;
  589. blk->hw = hw;
  590. list_add_tail(&blk->list, &rm->hw_blks[type]);
  591. _sde_rm_inc_resource_info(rm, &rm->avail_res, blk);
  592. if (sde_kms && sde_kms->catalog &&
  593. test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, sde_kms->catalog->features) &&
  594. SDE_CLK_CTRL_VALID(clk_client.clk_ctrl)) {
  595. rc = sde_vbif_clk_register(sde_kms, &clk_client);
  596. if (rc) {
  597. SDE_ERROR("failed to register vbif client %d\n", clk_client.clk_ctrl);
  598. return -EFAULT;
  599. }
  600. }
  601. return 0;
  602. }
  603. static int _sde_rm_hw_blk_create_new(struct sde_rm *rm,
  604. struct sde_mdss_cfg *cat,
  605. void __iomem *mmio)
  606. {
  607. int i, rc = 0;
  608. for (i = 0; i < cat->dspp_count; i++) {
  609. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSPP,
  610. cat->dspp[i].id, &cat->dspp[i]);
  611. if (rc) {
  612. SDE_ERROR("failed: dspp hw not available\n");
  613. goto fail;
  614. }
  615. }
  616. if (cat->mdp[0].has_dest_scaler) {
  617. for (i = 0; i < cat->ds_count; i++) {
  618. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DS,
  619. cat->ds[i].id, &cat->ds[i]);
  620. if (rc) {
  621. SDE_ERROR("failed: ds hw not available\n");
  622. goto fail;
  623. }
  624. }
  625. }
  626. for (i = 0; i < cat->pingpong_count; i++) {
  627. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_PINGPONG,
  628. cat->pingpong[i].id, &cat->pingpong[i]);
  629. if (rc) {
  630. SDE_ERROR("failed: pp hw not available\n");
  631. goto fail;
  632. }
  633. }
  634. for (i = 0; i < cat->dsc_count; i++) {
  635. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSC,
  636. cat->dsc[i].id, &cat->dsc[i]);
  637. if (rc) {
  638. SDE_ERROR("failed: dsc hw not available\n");
  639. goto fail;
  640. }
  641. }
  642. for (i = 0; i < cat->vdc_count; i++) {
  643. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_VDC,
  644. cat->vdc[i].id, &cat->vdc[i]);
  645. if (rc) {
  646. SDE_ERROR("failed: vdc hw not available\n");
  647. goto fail;
  648. }
  649. }
  650. for (i = 0; i < cat->intf_count; i++) {
  651. if (cat->intf[i].type == INTF_NONE) {
  652. SDE_DEBUG("skip intf %d with type none\n", i);
  653. continue;
  654. }
  655. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_INTF,
  656. cat->intf[i].id, &cat->intf[i]);
  657. if (rc) {
  658. SDE_ERROR("failed: intf hw not available\n");
  659. goto fail;
  660. }
  661. }
  662. for (i = 0; i < cat->wb_count; i++) {
  663. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_WB,
  664. cat->wb[i].id, &cat->wb[i]);
  665. if (rc) {
  666. SDE_ERROR("failed: wb hw not available\n");
  667. goto fail;
  668. }
  669. }
  670. for (i = 0; i < cat->ctl_count; i++) {
  671. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CTL,
  672. cat->ctl[i].id, &cat->ctl[i]);
  673. if (rc) {
  674. SDE_ERROR("failed: ctl hw not available\n");
  675. goto fail;
  676. }
  677. }
  678. for (i = 0; i < cat->cdm_count; i++) {
  679. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CDM,
  680. cat->cdm[i].id, &cat->cdm[i]);
  681. if (rc) {
  682. SDE_ERROR("failed: cdm hw not available\n");
  683. goto fail;
  684. }
  685. }
  686. for (i = 0; i < cat->dnsc_blur_count; i++) {
  687. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DNSC_BLUR,
  688. cat->dnsc_blur[i].id, &cat->dnsc_blur[i]);
  689. if (rc) {
  690. SDE_ERROR("failed: dnsc_blur hw not available\n");
  691. goto fail;
  692. }
  693. }
  694. for (i = 0; i < cat->qdss_count; i++) {
  695. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_QDSS,
  696. cat->qdss[i].id, &cat->qdss[i]);
  697. if (rc) {
  698. SDE_ERROR("failed: qdss hw not available\n");
  699. goto fail;
  700. }
  701. }
  702. fail:
  703. return rc;
  704. }
  705. #if IS_ENABLED(CONFIG_DEBUG_FS)
  706. static int _sde_rm_status_show(struct seq_file *s, void *data)
  707. {
  708. struct sde_rm *rm;
  709. struct sde_rm_hw_blk *blk;
  710. u32 type, allocated, unallocated;
  711. if (!s || !s->private)
  712. return -EINVAL;
  713. rm = s->private;
  714. for (type = SDE_HW_BLK_LM; type < SDE_HW_BLK_MAX; type++) {
  715. allocated = 0;
  716. unallocated = 0;
  717. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  718. if (!blk->rsvp && !blk->rsvp_nxt)
  719. unallocated++;
  720. else
  721. allocated++;
  722. }
  723. seq_printf(s, "type:%d blk:%s allocated:%d unallocated:%d\n",
  724. type, sde_hw_blk_str[type], allocated, unallocated);
  725. }
  726. return 0;
  727. }
  728. static int _sde_rm_debugfs_status_open(struct inode *inode,
  729. struct file *file)
  730. {
  731. return single_open(file, _sde_rm_status_show, inode->i_private);
  732. }
  733. void sde_rm_debugfs_init(struct sde_rm *sde_rm, struct dentry *parent)
  734. {
  735. static const struct file_operations debugfs_rm_status_fops = {
  736. .open = _sde_rm_debugfs_status_open,
  737. .read = seq_read,
  738. };
  739. debugfs_create_file("rm_status", 0400, parent, sde_rm, &debugfs_rm_status_fops);
  740. }
  741. #else
  742. void sde_rm_debugfs_init(struct sde_rm *rm, struct dentry *parent)
  743. {
  744. }
  745. #endif /* CONFIG_DEBUG_FS */
  746. int sde_rm_init(struct sde_rm *rm,
  747. struct sde_mdss_cfg *cat,
  748. void __iomem *mmio,
  749. struct drm_device *dev)
  750. {
  751. int i, rc = 0;
  752. enum sde_hw_blk_type type;
  753. if (!rm || !cat || !mmio || !dev) {
  754. SDE_ERROR("invalid input params\n");
  755. return -EINVAL;
  756. }
  757. /* Clear, setup lists */
  758. memset(rm, 0, sizeof(*rm));
  759. mutex_init(&rm->rm_lock);
  760. INIT_LIST_HEAD(&rm->rsvps);
  761. for (type = 0; type < SDE_HW_BLK_MAX; type++)
  762. INIT_LIST_HEAD(&rm->hw_blks[type]);
  763. rm->dev = dev;
  764. if (IS_SDE_CTL_REV_100(cat->ctl_rev))
  765. rm->topology_tbl = g_top_table_v1;
  766. else
  767. rm->topology_tbl = g_top_table;
  768. /* Some of the sub-blocks require an mdptop to be created */
  769. rm->hw_mdp = sde_hw_mdptop_init(MDP_TOP, mmio, cat);
  770. if (IS_ERR_OR_NULL(rm->hw_mdp)) {
  771. rc = PTR_ERR(rm->hw_mdp);
  772. rm->hw_mdp = NULL;
  773. SDE_ERROR("failed: mdp hw not available\n");
  774. goto fail;
  775. }
  776. /* Interrogate HW catalog and create tracking items for hw blocks */
  777. for (i = 0; i < cat->mixer_count; i++) {
  778. struct sde_lm_cfg *lm = &cat->mixer[i];
  779. if (lm->pingpong == PINGPONG_MAX) {
  780. SDE_ERROR("mixer %d without pingpong\n", lm->id);
  781. goto fail;
  782. }
  783. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_LM,
  784. cat->mixer[i].id, &cat->mixer[i]);
  785. if (rc) {
  786. SDE_ERROR("failed: lm hw not available\n");
  787. goto fail;
  788. }
  789. if (!rm->lm_max_width) {
  790. rm->lm_max_width = lm->sblk->maxwidth;
  791. } else if (rm->lm_max_width != lm->sblk->maxwidth) {
  792. /*
  793. * Don't expect to have hw where lm max widths differ.
  794. * If found, take the min.
  795. */
  796. SDE_ERROR("unsupported: lm maxwidth differs\n");
  797. if (rm->lm_max_width > lm->sblk->maxwidth)
  798. rm->lm_max_width = lm->sblk->maxwidth;
  799. }
  800. }
  801. rc = _sde_rm_hw_blk_create_new(rm, cat, mmio);
  802. if (!rc)
  803. return 0;
  804. fail:
  805. sde_rm_destroy(rm);
  806. return rc;
  807. }
  808. static bool _sde_rm_check_lm(
  809. struct sde_rm *rm,
  810. struct sde_rm_rsvp *rsvp,
  811. struct sde_rm_requirements *reqs,
  812. const struct sde_lm_cfg *lm_cfg,
  813. struct sde_rm_hw_blk *lm,
  814. struct sde_rm_hw_blk **dspp,
  815. struct sde_rm_hw_blk **ds,
  816. struct sde_rm_hw_blk **pp)
  817. {
  818. bool is_valid_dspp, is_valid_ds, ret = true;
  819. is_valid_dspp = (lm_cfg->dspp != DSPP_MAX) ? true : false;
  820. is_valid_ds = (lm_cfg->ds != DS_MAX) ? true : false;
  821. /**
  822. * RM_RQ_X: specification of which LMs to choose
  823. * is_valid_X: indicates whether LM is tied with block X
  824. * ret: true if given LM matches the user requirement,
  825. * false otherwise
  826. */
  827. if (RM_RQ_DSPP(reqs) && RM_RQ_DS(reqs))
  828. ret = (is_valid_dspp && is_valid_ds);
  829. else if (RM_RQ_DSPP(reqs))
  830. ret = is_valid_dspp;
  831. else if (RM_RQ_DS(reqs))
  832. ret = is_valid_ds;
  833. if (!ret) {
  834. SDE_DEBUG(
  835. "fail:lm(%d)req_dspp(%d)dspp(%d)req_ds(%d)ds(%d)\n",
  836. lm_cfg->id, (bool)(RM_RQ_DSPP(reqs)),
  837. lm_cfg->dspp, (bool)(RM_RQ_DS(reqs)),
  838. lm_cfg->ds);
  839. return ret;
  840. }
  841. return true;
  842. }
  843. static bool _sde_rm_reserve_dspp(
  844. struct sde_rm *rm,
  845. struct sde_rm_rsvp *rsvp,
  846. const struct sde_lm_cfg *lm_cfg,
  847. struct sde_rm_hw_blk *lm,
  848. struct sde_rm_hw_blk **dspp)
  849. {
  850. struct sde_rm_hw_iter iter;
  851. if (lm_cfg->dspp != DSPP_MAX) {
  852. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DSPP);
  853. while (_sde_rm_get_hw_locked(rm, &iter)) {
  854. if (iter.blk->id == lm_cfg->dspp) {
  855. *dspp = iter.blk;
  856. break;
  857. }
  858. }
  859. if (!*dspp) {
  860. SDE_DEBUG("lm %d failed to retrieve dspp %d\n", lm->id,
  861. lm_cfg->dspp);
  862. return false;
  863. }
  864. if (RESERVED_BY_OTHER(*dspp, rsvp)) {
  865. SDE_DEBUG("lm %d dspp %d already reserved\n",
  866. lm->id, (*dspp)->id);
  867. return false;
  868. }
  869. }
  870. return true;
  871. }
  872. static bool _sde_rm_reserve_ds(
  873. struct sde_rm *rm,
  874. struct sde_rm_rsvp *rsvp,
  875. const struct sde_lm_cfg *lm_cfg,
  876. struct sde_rm_hw_blk *lm,
  877. struct sde_rm_hw_blk **ds)
  878. {
  879. struct sde_rm_hw_iter iter;
  880. if (lm_cfg->ds != DS_MAX) {
  881. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DS);
  882. while (_sde_rm_get_hw_locked(rm, &iter)) {
  883. if (iter.blk->id == lm_cfg->ds) {
  884. *ds = iter.blk;
  885. break;
  886. }
  887. }
  888. if (!*ds) {
  889. SDE_DEBUG("lm %d failed to retrieve ds %d\n", lm->id,
  890. lm_cfg->ds);
  891. return false;
  892. }
  893. if (RESERVED_BY_OTHER(*ds, rsvp)) {
  894. SDE_DEBUG("lm %d ds %d already reserved\n",
  895. lm->id, (*ds)->id);
  896. return false;
  897. }
  898. }
  899. return true;
  900. }
  901. static bool _sde_rm_reserve_pp(
  902. struct sde_rm *rm,
  903. struct sde_rm_rsvp *rsvp,
  904. struct sde_rm_requirements *reqs,
  905. const struct sde_lm_cfg *lm_cfg,
  906. const struct sde_pingpong_cfg *pp_cfg,
  907. struct sde_rm_hw_blk *lm,
  908. struct sde_rm_hw_blk **dspp,
  909. struct sde_rm_hw_blk **ds,
  910. struct sde_rm_hw_blk **pp)
  911. {
  912. struct sde_rm_hw_iter iter;
  913. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_PINGPONG);
  914. while (_sde_rm_get_hw_locked(rm, &iter)) {
  915. if (iter.blk->id == lm_cfg->pingpong) {
  916. *pp = iter.blk;
  917. break;
  918. }
  919. }
  920. if (!*pp) {
  921. SDE_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong);
  922. return false;
  923. }
  924. if (RESERVED_BY_OTHER(*pp, rsvp)) {
  925. SDE_DEBUG("lm %d pp %d already reserved\n", lm->id,
  926. (*pp)->id);
  927. *dspp = NULL;
  928. *ds = NULL;
  929. return false;
  930. }
  931. pp_cfg = to_sde_hw_pingpong((*pp)->hw)->caps;
  932. if ((reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) &&
  933. !(test_bit(SDE_PINGPONG_SPLIT, &pp_cfg->features))) {
  934. SDE_DEBUG("pp %d doesn't support ppsplit\n", pp_cfg->id);
  935. *dspp = NULL;
  936. *ds = NULL;
  937. return false;
  938. }
  939. return true;
  940. }
  941. /**
  942. * _sde_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets
  943. * proposed use case requirements, incl. hardwired dependent blocks like
  944. * pingpong, and dspp.
  945. * @rm: sde resource manager handle
  946. * @rsvp: reservation currently being created
  947. * @reqs: proposed use case requirements
  948. * @lm: proposed layer mixer, function checks if lm, and all other hardwired
  949. * blocks connected to the lm (pp, dspp) are available and appropriate
  950. * @dspp: output parameter, dspp block attached to the layer mixer.
  951. * NULL if dspp was not available, or not matching requirements.
  952. * @pp: output parameter, pingpong block attached to the layer mixer.
  953. * NULL if dspp was not available, or not matching requirements.
  954. * @primary_lm: if non-null, this function check if lm is compatible primary_lm
  955. * as well as satisfying all other requirements
  956. * @Return: true if lm matches all requirements, false otherwise
  957. */
  958. static bool _sde_rm_check_lm_and_get_connected_blks(
  959. struct sde_rm *rm,
  960. struct sde_rm_rsvp *rsvp,
  961. struct sde_rm_requirements *reqs,
  962. struct sde_rm_hw_blk *lm,
  963. struct sde_rm_hw_blk **dspp,
  964. struct sde_rm_hw_blk **ds,
  965. struct sde_rm_hw_blk **pp,
  966. struct sde_rm_hw_blk *primary_lm)
  967. {
  968. const struct sde_lm_cfg *lm_cfg = to_sde_hw_mixer(lm->hw)->cap;
  969. const struct sde_pingpong_cfg *pp_cfg;
  970. bool ret, is_conn_primary, is_conn_secondary;
  971. u32 lm_primary_pref, lm_secondary_pref, cwb_pref, dcwb_pref;
  972. *dspp = NULL;
  973. *ds = NULL;
  974. *pp = NULL;
  975. lm_primary_pref = lm_cfg->features & BIT(SDE_DISP_PRIMARY_PREF);
  976. lm_secondary_pref = lm_cfg->features & BIT(SDE_DISP_SECONDARY_PREF);
  977. cwb_pref = lm_cfg->features & BIT(SDE_DISP_CWB_PREF);
  978. dcwb_pref = lm_cfg->features & BIT(SDE_DISP_DCWB_PREF);
  979. is_conn_primary = (reqs->hw_res.display_type ==
  980. SDE_CONNECTOR_PRIMARY) ? true : false;
  981. is_conn_secondary = (reqs->hw_res.display_type ==
  982. SDE_CONNECTOR_SECONDARY) ? true : false;
  983. SDE_DEBUG("check lm %d: dspp %d ds %d pp %d features %ld disp type %d\n",
  984. lm_cfg->id, lm_cfg->dspp, lm_cfg->ds, lm_cfg->pingpong,
  985. lm_cfg->features, (int)reqs->hw_res.display_type);
  986. /* Check if this layer mixer is a peer of the proposed primary LM */
  987. if (primary_lm) {
  988. const struct sde_lm_cfg *prim_lm_cfg =
  989. to_sde_hw_mixer(primary_lm->hw)->cap;
  990. if (!test_bit(lm_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
  991. SDE_DEBUG("lm %d not peer of lm %d\n", lm_cfg->id,
  992. prim_lm_cfg->id);
  993. return false;
  994. }
  995. }
  996. /* bypass rest of the checks if LM for primary display is found */
  997. if (!lm_primary_pref && !lm_secondary_pref) {
  998. /* Check lm for valid requirements */
  999. ret = _sde_rm_check_lm(rm, rsvp, reqs, lm_cfg, lm,
  1000. dspp, ds, pp);
  1001. if (!ret)
  1002. return ret;
  1003. /**
  1004. * If CWB is enabled and LM is not CWB supported
  1005. * then return false.
  1006. */
  1007. if ((RM_RQ_CWB(reqs) && !cwb_pref) ||
  1008. (RM_RQ_DCWB(reqs) && !dcwb_pref)) {
  1009. SDE_DEBUG("fail: cwb/dcwb supported lm not allocated\n");
  1010. return false;
  1011. } else if (!RM_RQ_DCWB(reqs) && dcwb_pref) {
  1012. SDE_DEBUG("fail: dcwb supported dummy lm incorrectly allocated\n");
  1013. return false;
  1014. }
  1015. } else if ((!is_conn_primary && lm_primary_pref) ||
  1016. (!is_conn_secondary && lm_secondary_pref)) {
  1017. SDE_DEBUG(
  1018. "display preference is not met. display_type: %d lm_features: %lx\n",
  1019. (int)reqs->hw_res.display_type, lm_cfg->features);
  1020. return false;
  1021. }
  1022. /* Already reserved? */
  1023. if (RESERVED_BY_OTHER(lm, rsvp)) {
  1024. SDE_DEBUG("lm %d already reserved\n", lm_cfg->id);
  1025. return false;
  1026. }
  1027. /* Reserve dspp */
  1028. ret = _sde_rm_reserve_dspp(rm, rsvp, lm_cfg, lm, dspp);
  1029. if (!ret)
  1030. return ret;
  1031. /* Reserve ds */
  1032. ret = _sde_rm_reserve_ds(rm, rsvp, lm_cfg, lm, ds);
  1033. if (!ret)
  1034. return ret;
  1035. /* Reserve pp */
  1036. ret = _sde_rm_reserve_pp(rm, rsvp, reqs, lm_cfg, pp_cfg, lm,
  1037. dspp, ds, pp);
  1038. if (!ret)
  1039. return ret;
  1040. return true;
  1041. }
  1042. static int _sde_rm_reserve_lms(
  1043. struct sde_rm *rm,
  1044. struct sde_rm_rsvp *rsvp,
  1045. struct sde_rm_requirements *reqs,
  1046. u8 *_lm_ids)
  1047. {
  1048. struct sde_rm_hw_blk *lm[MAX_BLOCKS];
  1049. struct sde_rm_hw_blk *dspp[MAX_BLOCKS];
  1050. struct sde_rm_hw_blk *ds[MAX_BLOCKS];
  1051. struct sde_rm_hw_blk *pp[MAX_BLOCKS];
  1052. struct sde_rm_hw_iter iter_i, iter_j;
  1053. u32 lm_mask = 0;
  1054. int lm_count = 0;
  1055. int i, rc = 0;
  1056. if (!reqs->topology->num_lm) {
  1057. SDE_DEBUG("invalid number of lm: %d\n", reqs->topology->num_lm);
  1058. return 0;
  1059. }
  1060. /* Find a primary mixer */
  1061. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_LM);
  1062. while (lm_count != reqs->topology->num_lm &&
  1063. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1064. if (lm_mask & (1 << iter_i.blk->id))
  1065. continue;
  1066. lm[lm_count] = iter_i.blk;
  1067. dspp[lm_count] = NULL;
  1068. ds[lm_count] = NULL;
  1069. pp[lm_count] = NULL;
  1070. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  1071. iter_i.blk->id,
  1072. lm_count,
  1073. _lm_ids ? _lm_ids[lm_count] : -1);
  1074. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  1075. continue;
  1076. if (!_sde_rm_check_lm_and_get_connected_blks(
  1077. rm, rsvp, reqs, lm[lm_count],
  1078. &dspp[lm_count], &ds[lm_count],
  1079. &pp[lm_count], NULL))
  1080. continue;
  1081. lm_mask |= (1 << iter_i.blk->id);
  1082. ++lm_count;
  1083. /* Return if peer is not needed */
  1084. if (lm_count == reqs->topology->num_lm)
  1085. break;
  1086. /* Valid primary mixer found, find matching peers */
  1087. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_LM);
  1088. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  1089. if (lm_mask & (1 << iter_j.blk->id))
  1090. continue;
  1091. lm[lm_count] = iter_j.blk;
  1092. dspp[lm_count] = NULL;
  1093. ds[lm_count] = NULL;
  1094. pp[lm_count] = NULL;
  1095. if (!_sde_rm_check_lm_and_get_connected_blks(
  1096. rm, rsvp, reqs, iter_j.blk,
  1097. &dspp[lm_count], &ds[lm_count],
  1098. &pp[lm_count], iter_i.blk))
  1099. continue;
  1100. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  1101. iter_j.blk->id,
  1102. lm_count,
  1103. _lm_ids ? _lm_ids[lm_count] : -1);
  1104. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  1105. continue;
  1106. lm_mask |= (1 << iter_j.blk->id);
  1107. ++lm_count;
  1108. break;
  1109. }
  1110. /* Rollback primary LM if peer is not found */
  1111. if (!iter_j.hw) {
  1112. lm_mask &= ~(1 << iter_i.blk->id);
  1113. --lm_count;
  1114. }
  1115. }
  1116. if (lm_count != reqs->topology->num_lm) {
  1117. SDE_DEBUG("unable to find appropriate mixers\n");
  1118. return -ENAVAIL;
  1119. }
  1120. for (i = 0; i < lm_count; i++) {
  1121. lm[i]->rsvp_nxt = rsvp;
  1122. pp[i]->rsvp_nxt = rsvp;
  1123. if (dspp[i])
  1124. dspp[i]->rsvp_nxt = rsvp;
  1125. if (ds[i])
  1126. ds[i]->rsvp_nxt = rsvp;
  1127. SDE_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id,
  1128. dspp[i] ? dspp[i]->id : 0,
  1129. ds[i] ? ds[i]->id : 0);
  1130. }
  1131. if (reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) {
  1132. /* reserve a free PINGPONG_SLAVE block */
  1133. rc = -ENAVAIL;
  1134. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_PINGPONG);
  1135. while (_sde_rm_get_hw_locked(rm, &iter_i)) {
  1136. const struct sde_hw_pingpong *pp =
  1137. to_sde_hw_pingpong(iter_i.blk->hw);
  1138. const struct sde_pingpong_cfg *pp_cfg = pp->caps;
  1139. if (!(test_bit(SDE_PINGPONG_SLAVE, &pp_cfg->features)))
  1140. continue;
  1141. if (RESERVED_BY_OTHER(iter_i.blk, rsvp))
  1142. continue;
  1143. iter_i.blk->rsvp_nxt = rsvp;
  1144. rc = 0;
  1145. break;
  1146. }
  1147. }
  1148. return rc;
  1149. }
  1150. static int _sde_rm_reserve_ctls(
  1151. struct sde_rm *rm,
  1152. struct sde_rm_rsvp *rsvp,
  1153. struct sde_rm_requirements *reqs,
  1154. const struct sde_rm_topology_def *top,
  1155. u8 *_ctl_ids)
  1156. {
  1157. struct sde_rm_hw_blk *ctls[MAX_BLOCKS];
  1158. struct sde_rm_hw_iter iter;
  1159. int i = 0;
  1160. if (!top->num_ctl) {
  1161. SDE_DEBUG("invalid number of ctl: %d\n", top->num_ctl);
  1162. return 0;
  1163. }
  1164. memset(&ctls, 0, sizeof(ctls));
  1165. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CTL);
  1166. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1167. const struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter.blk->hw);
  1168. unsigned long features = ctl->caps->features;
  1169. bool has_split_display, has_ppsplit, primary_pref;
  1170. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1171. continue;
  1172. has_split_display = BIT(SDE_CTL_SPLIT_DISPLAY) & features;
  1173. has_ppsplit = BIT(SDE_CTL_PINGPONG_SPLIT) & features;
  1174. primary_pref = BIT(SDE_CTL_PRIMARY_PREF) & features;
  1175. SDE_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
  1176. /*
  1177. * bypass rest feature checks on finding CTL preferred
  1178. * for primary displays.
  1179. */
  1180. if (!primary_pref && !_ctl_ids) {
  1181. if (top->needs_split_display != has_split_display)
  1182. continue;
  1183. if (top->top_name == SDE_RM_TOPOLOGY_PPSPLIT &&
  1184. !has_ppsplit)
  1185. continue;
  1186. } else if (!(reqs->hw_res.display_type ==
  1187. SDE_CONNECTOR_PRIMARY && primary_pref) && !_ctl_ids) {
  1188. SDE_DEBUG(
  1189. "display pref not met. display_type: %d primary_pref: %d\n",
  1190. reqs->hw_res.display_type, primary_pref);
  1191. continue;
  1192. }
  1193. ctls[i] = iter.blk;
  1194. SDE_DEBUG("blk id = %d, _ctl_ids[%d] = %d\n",
  1195. iter.blk->id, i,
  1196. _ctl_ids ? _ctl_ids[i] : -1);
  1197. if (_ctl_ids && (ctls[i]->id != _ctl_ids[i]))
  1198. continue;
  1199. SDE_DEBUG("ctl %d match\n", iter.blk->id);
  1200. if (++i == top->num_ctl)
  1201. break;
  1202. }
  1203. if (i != top->num_ctl)
  1204. return -ENAVAIL;
  1205. for (i = 0; i < ARRAY_SIZE(ctls) && i < top->num_ctl; i++) {
  1206. ctls[i]->rsvp_nxt = rsvp;
  1207. SDE_EVT32(ctls[i]->type, rsvp->enc_id, ctls[i]->id);
  1208. }
  1209. return 0;
  1210. }
  1211. static bool _sde_rm_check_dsc(struct sde_rm *rm,
  1212. struct sde_rm_rsvp *rsvp,
  1213. struct sde_rm_hw_blk *dsc,
  1214. struct sde_rm_hw_blk *paired_dsc,
  1215. struct sde_rm_hw_blk *pp_blk)
  1216. {
  1217. const struct sde_dsc_cfg *dsc_cfg = to_sde_hw_dsc(dsc->hw)->caps;
  1218. /* Already reserved? */
  1219. if (RESERVED_BY_OTHER(dsc, rsvp)) {
  1220. SDE_DEBUG("dsc %d already reserved\n", dsc_cfg->id);
  1221. return false;
  1222. }
  1223. /**
  1224. * This check is required for routing even numbered DSC
  1225. * blks to any of the even numbered PP blks and odd numbered
  1226. * DSC blks to any of the odd numbered PP blks.
  1227. */
  1228. if (!pp_blk || !IS_COMPATIBLE_PP_DSC(pp_blk->id, dsc->id))
  1229. return false;
  1230. /* Check if this dsc is a peer of the proposed paired DSC */
  1231. if (paired_dsc) {
  1232. const struct sde_dsc_cfg *paired_dsc_cfg =
  1233. to_sde_hw_dsc(paired_dsc->hw)->caps;
  1234. if (!test_bit(dsc_cfg->id, paired_dsc_cfg->dsc_pair_mask)) {
  1235. SDE_DEBUG("dsc %d not peer of dsc %d\n", dsc_cfg->id,
  1236. paired_dsc_cfg->id);
  1237. return false;
  1238. }
  1239. }
  1240. return true;
  1241. }
  1242. static bool _sde_rm_check_vdc(struct sde_rm *rm,
  1243. struct sde_rm_rsvp *rsvp,
  1244. struct sde_rm_hw_blk *vdc)
  1245. {
  1246. const struct sde_vdc_cfg *vdc_cfg = to_sde_hw_vdc(vdc->hw)->caps;
  1247. /* Already reserved? */
  1248. if (RESERVED_BY_OTHER(vdc, rsvp)) {
  1249. SDE_DEBUG("vdc %d already reserved\n", vdc_cfg->id);
  1250. return false;
  1251. }
  1252. return true;
  1253. }
  1254. static void sde_rm_get_rsvp_nxt_hw_blks(
  1255. struct sde_rm *rm,
  1256. struct sde_rm_rsvp *rsvp,
  1257. int type,
  1258. struct sde_rm_hw_blk **blk_arr)
  1259. {
  1260. struct sde_rm_hw_blk *blk;
  1261. int i = 0;
  1262. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  1263. if (blk->rsvp_nxt && blk->rsvp_nxt->seq ==
  1264. rsvp->seq)
  1265. blk_arr[i++] = blk;
  1266. }
  1267. }
  1268. static int _sde_rm_reserve_dsc(
  1269. struct sde_rm *rm,
  1270. struct sde_rm_rsvp *rsvp,
  1271. struct sde_rm_requirements *reqs,
  1272. u8 *_dsc_ids)
  1273. {
  1274. struct sde_rm_hw_iter iter_i, iter_j;
  1275. struct sde_rm_hw_blk *dsc[MAX_BLOCKS];
  1276. u32 reserve_mask = 0;
  1277. struct sde_rm_hw_blk *pp[MAX_BLOCKS];
  1278. int alloc_count = 0;
  1279. int num_dsc_enc;
  1280. struct msm_display_dsc_info *dsc_info;
  1281. int i;
  1282. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_DSC) {
  1283. SDE_DEBUG("compression blk dsc not required\n");
  1284. return 0;
  1285. }
  1286. num_dsc_enc = reqs->topology->num_comp_enc;
  1287. dsc_info = &reqs->hw_res.comp_info->dsc_info;
  1288. if ((!num_dsc_enc) || !dsc_info) {
  1289. SDE_DEBUG("invalid topoplogy params: %d, %d\n",
  1290. num_dsc_enc, !(dsc_info == NULL));
  1291. return 0;
  1292. }
  1293. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_DSC);
  1294. sde_rm_get_rsvp_nxt_hw_blks(rm, rsvp, SDE_HW_BLK_PINGPONG, pp);
  1295. /* Find a first DSC */
  1296. while (alloc_count != num_dsc_enc &&
  1297. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1298. const struct sde_hw_dsc *hw_dsc = to_sde_hw_dsc(
  1299. iter_i.blk->hw);
  1300. unsigned long features = hw_dsc->caps->features;
  1301. bool has_422_420_support =
  1302. BIT(SDE_DSC_NATIVE_422_EN) & features;
  1303. if (reserve_mask & (1 << iter_i.blk->id))
  1304. continue;
  1305. if (_dsc_ids && (iter_i.blk->id != _dsc_ids[alloc_count]))
  1306. continue;
  1307. /* if this hw block does not support required feature */
  1308. if (!_dsc_ids && (dsc_info->config.native_422 ||
  1309. dsc_info->config.native_420) && !has_422_420_support)
  1310. continue;
  1311. if (!_sde_rm_check_dsc(rm, rsvp, iter_i.blk, NULL,
  1312. pp[alloc_count]))
  1313. continue;
  1314. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1315. iter_i.blk->id,
  1316. alloc_count,
  1317. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1318. reserve_mask |= (1 << iter_i.blk->id);
  1319. dsc[alloc_count++] = iter_i.blk;
  1320. /* Return if peer is not needed */
  1321. if (alloc_count == num_dsc_enc)
  1322. break;
  1323. /* Valid first dsc found, find matching peers */
  1324. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_DSC);
  1325. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  1326. if (reserve_mask & (1 << iter_j.blk->id))
  1327. continue;
  1328. if (_dsc_ids && (iter_j.blk->id !=
  1329. _dsc_ids[alloc_count]))
  1330. continue;
  1331. if (!_sde_rm_check_dsc(rm, rsvp, iter_j.blk,
  1332. iter_i.blk, pp[alloc_count]))
  1333. continue;
  1334. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1335. iter_j.blk->id,
  1336. alloc_count,
  1337. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1338. reserve_mask |= (1 << iter_j.blk->id);
  1339. dsc[alloc_count++] = iter_j.blk;
  1340. break;
  1341. }
  1342. /* Rollback primary DSC if peer is not found */
  1343. if (!iter_j.hw) {
  1344. reserve_mask &= ~(1 << iter_i.blk->id);
  1345. --alloc_count;
  1346. }
  1347. }
  1348. if (alloc_count != num_dsc_enc) {
  1349. SDE_ERROR("couldn't reserve %d dsc blocks for enc id %d\n",
  1350. num_dsc_enc, rsvp->enc_id);
  1351. return -EINVAL;
  1352. }
  1353. for (i = 0; i < alloc_count; i++) {
  1354. if (!dsc[i])
  1355. break;
  1356. dsc[i]->rsvp_nxt = rsvp;
  1357. SDE_EVT32(dsc[i]->type, rsvp->enc_id, dsc[i]->id);
  1358. }
  1359. return 0;
  1360. }
  1361. static int _sde_rm_reserve_vdc(
  1362. struct sde_rm *rm,
  1363. struct sde_rm_rsvp *rsvp,
  1364. struct sde_rm_requirements *reqs,
  1365. const struct sde_rm_topology_def *top,
  1366. u8 *_vdc_ids)
  1367. {
  1368. struct sde_rm_hw_iter iter_i;
  1369. struct sde_rm_hw_blk *vdc[MAX_BLOCKS];
  1370. int alloc_count = 0;
  1371. int num_vdc_enc = top->num_comp_enc;
  1372. int i;
  1373. if (!top->num_comp_enc)
  1374. return 0;
  1375. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_VDC)
  1376. return 0;
  1377. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_VDC);
  1378. /* Find a VDC */
  1379. while (alloc_count != num_vdc_enc &&
  1380. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1381. memset(&vdc, 0, sizeof(vdc));
  1382. alloc_count = 0;
  1383. if (_vdc_ids && (iter_i.blk->id != _vdc_ids[alloc_count]))
  1384. continue;
  1385. if (!_sde_rm_check_vdc(rm, rsvp, iter_i.blk))
  1386. continue;
  1387. SDE_DEBUG("blk id = %d, _vdc_ids[%d] = %d\n",
  1388. iter_i.blk->id,
  1389. alloc_count,
  1390. _vdc_ids ? _vdc_ids[alloc_count] : -1);
  1391. vdc[alloc_count++] = iter_i.blk;
  1392. }
  1393. if (alloc_count != num_vdc_enc) {
  1394. SDE_ERROR("couldn't reserve %d vdc blocks for enc id %d\n",
  1395. num_vdc_enc, rsvp->enc_id);
  1396. return -EINVAL;
  1397. }
  1398. for (i = 0; i < ARRAY_SIZE(vdc); i++) {
  1399. if (!vdc[i])
  1400. break;
  1401. vdc[i]->rsvp_nxt = rsvp;
  1402. SDE_EVT32(vdc[i]->type, rsvp->enc_id, vdc[i]->id);
  1403. }
  1404. return 0;
  1405. }
  1406. static int _sde_rm_reserve_qdss(
  1407. struct sde_rm *rm,
  1408. struct sde_rm_rsvp *rsvp,
  1409. const struct sde_rm_topology_def *top,
  1410. u8 *_qdss_ids)
  1411. {
  1412. struct sde_rm_hw_iter iter;
  1413. struct msm_drm_private *priv = rm->dev->dev_private;
  1414. struct sde_kms *sde_kms;
  1415. if (!priv->kms) {
  1416. SDE_ERROR("invalid kms\n");
  1417. return -EINVAL;
  1418. }
  1419. sde_kms = to_sde_kms(priv->kms);
  1420. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_QDSS);
  1421. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1422. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1423. continue;
  1424. SDE_DEBUG("blk id = %d\n", iter.blk->id);
  1425. iter.blk->rsvp_nxt = rsvp;
  1426. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1427. return 0;
  1428. }
  1429. if (!iter.hw && sde_kms->catalog->qdss_count) {
  1430. SDE_DEBUG("couldn't reserve qdss for type %d id %d\n",
  1431. SDE_HW_BLK_QDSS, iter.blk->id);
  1432. return -ENAVAIL;
  1433. }
  1434. return 0;
  1435. }
  1436. static int _sde_rm_reserve_dnsc_blur(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1437. uint32_t id, enum sde_hw_blk_type type)
  1438. {
  1439. struct sde_rm_hw_iter iter;
  1440. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DNSC_BLUR);
  1441. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1442. struct sde_hw_dnsc_blur *dnsc_blur = to_sde_hw_dnsc_blur(iter.blk->hw);
  1443. bool match = false;
  1444. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1445. continue;
  1446. if ((type == SDE_HW_BLK_WB) && (id != WB_MAX))
  1447. match = test_bit(id, &dnsc_blur->caps->wb_connect);
  1448. SDE_DEBUG("type %d id %d, dnsc_blur wbs %lu match %d\n",
  1449. type, id, dnsc_blur->caps->wb_connect, match);
  1450. if (!match)
  1451. continue;
  1452. iter.blk->rsvp_nxt = rsvp;
  1453. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1454. break;
  1455. }
  1456. if (!iter.hw) {
  1457. SDE_ERROR("couldn't reserve dnsc_blur for type %d id %d\n", type, id);
  1458. return -ENAVAIL;
  1459. }
  1460. return 0;
  1461. }
  1462. static int _sde_rm_reserve_cdm(
  1463. struct sde_rm *rm,
  1464. struct sde_rm_rsvp *rsvp,
  1465. uint32_t id,
  1466. enum sde_hw_blk_type type)
  1467. {
  1468. struct sde_rm_hw_iter iter;
  1469. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CDM);
  1470. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1471. const struct sde_hw_cdm *cdm = to_sde_hw_cdm(iter.blk->hw);
  1472. const struct sde_cdm_cfg *caps = cdm->caps;
  1473. bool match = false;
  1474. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1475. continue;
  1476. if (type == SDE_HW_BLK_INTF && id != INTF_MAX)
  1477. match = test_bit(id, &caps->intf_connect);
  1478. else if (type == SDE_HW_BLK_WB && id != WB_MAX)
  1479. match = test_bit(id, &caps->wb_connect);
  1480. SDE_DEBUG("type %d id %d, cdm intfs %lu wbs %lu match %d\n",
  1481. type, id, caps->intf_connect, caps->wb_connect,
  1482. match);
  1483. if (!match)
  1484. continue;
  1485. iter.blk->rsvp_nxt = rsvp;
  1486. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1487. break;
  1488. }
  1489. if (!iter.hw) {
  1490. SDE_ERROR("couldn't reserve cdm for type %d id %d\n", type, id);
  1491. return -ENAVAIL;
  1492. }
  1493. return 0;
  1494. }
  1495. static int _sde_rm_reserve_intf_or_wb(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1496. uint32_t id, enum sde_hw_blk_type type, struct sde_rm_requirements *reqs)
  1497. {
  1498. struct sde_encoder_hw_resources *hw_res = &reqs->hw_res;
  1499. struct sde_rm_hw_iter iter;
  1500. int ret = 0;
  1501. /* Find the block entry in the rm, and note the reservation */
  1502. sde_rm_init_hw_iter(&iter, 0, type);
  1503. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1504. if (iter.blk->id != id)
  1505. continue;
  1506. if (RESERVED_BY_OTHER(iter.blk, rsvp)) {
  1507. SDE_ERROR("type %d id %d already reserved\n", type, id);
  1508. return -ENAVAIL;
  1509. }
  1510. iter.blk->rsvp_nxt = rsvp;
  1511. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1512. break;
  1513. }
  1514. /* Shouldn't happen since wbs / intfs are fixed at probe */
  1515. if (!iter.hw) {
  1516. SDE_ERROR("couldn't find type %d id %d\n", type, id);
  1517. return -EINVAL;
  1518. }
  1519. /* Expected only one intf or wb will request cdm */
  1520. if (hw_res->needs_cdm)
  1521. ret = _sde_rm_reserve_cdm(rm, rsvp, id, type);
  1522. if (RM_RQ_DNSC_BLUR(reqs))
  1523. ret = _sde_rm_reserve_dnsc_blur(rm, rsvp, id, type);
  1524. return ret;
  1525. }
  1526. static int _sde_rm_reserve_intf_related_hw(struct sde_rm *rm,
  1527. struct sde_rm_rsvp *rsvp, struct sde_rm_requirements *reqs)
  1528. {
  1529. struct sde_encoder_hw_resources *hw_res = &reqs->hw_res;
  1530. int i, ret = 0;
  1531. u32 id;
  1532. for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
  1533. if (hw_res->intfs[i] == INTF_MODE_NONE)
  1534. continue;
  1535. id = i + INTF_0;
  1536. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id, SDE_HW_BLK_INTF, reqs);
  1537. if (ret)
  1538. return ret;
  1539. }
  1540. for (i = 0; i < ARRAY_SIZE(hw_res->wbs); i++) {
  1541. if (hw_res->wbs[i] == INTF_MODE_NONE)
  1542. continue;
  1543. id = i + WB_0;
  1544. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id, SDE_HW_BLK_WB, reqs);
  1545. if (ret)
  1546. return ret;
  1547. }
  1548. return ret;
  1549. }
  1550. static bool _sde_rm_is_display_in_cont_splash(struct sde_kms *sde_kms,
  1551. struct drm_encoder *enc)
  1552. {
  1553. int i;
  1554. struct sde_splash_display *splash_dpy;
  1555. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1556. splash_dpy = &sde_kms->splash_data.splash_display[i];
  1557. if (splash_dpy->encoder == enc)
  1558. return splash_dpy->cont_splash_enabled;
  1559. }
  1560. return false;
  1561. }
  1562. static int _sde_rm_make_lm_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1563. struct sde_rm_requirements *reqs,
  1564. struct sde_splash_display *splash_display)
  1565. {
  1566. int ret, i;
  1567. u8 *hw_ids = NULL;
  1568. /* Check if splash data provided lm_ids */
  1569. if (splash_display) {
  1570. hw_ids = splash_display->lm_ids;
  1571. for (i = 0; i < splash_display->lm_cnt; i++)
  1572. SDE_DEBUG("splash_display->lm_ids[%d] = %d\n",
  1573. i, splash_display->lm_ids[i]);
  1574. if (splash_display->lm_cnt != reqs->topology->num_lm)
  1575. SDE_DEBUG("Configured splash LMs != needed LM cnt\n");
  1576. }
  1577. /*
  1578. * Assign LMs and blocks whose usage is tied to them:
  1579. * DSPP & Pingpong.
  1580. */
  1581. ret = _sde_rm_reserve_lms(rm, rsvp, reqs, hw_ids);
  1582. return ret;
  1583. }
  1584. static int _sde_rm_make_ctl_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1585. struct sde_rm_requirements *reqs,
  1586. struct sde_splash_display *splash_display)
  1587. {
  1588. int ret, i;
  1589. u8 *hw_ids = NULL;
  1590. struct sde_rm_topology_def topology;
  1591. /* Check if splash data provided ctl_ids */
  1592. if (splash_display) {
  1593. hw_ids = splash_display->ctl_ids;
  1594. for (i = 0; i < splash_display->ctl_cnt; i++)
  1595. SDE_DEBUG("splash_display->ctl_ids[%d] = %d\n",
  1596. i, splash_display->ctl_ids[i]);
  1597. }
  1598. /*
  1599. * Do assignment preferring to give away low-resource CTLs first:
  1600. * - Check mixers without Split Display
  1601. * - Only then allow to grab from CTLs with split display capability
  1602. */
  1603. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, reqs->topology, hw_ids);
  1604. if (ret && !reqs->topology->needs_split_display &&
  1605. reqs->topology->num_ctl > SINGLE_CTL) {
  1606. memcpy(&topology, reqs->topology, sizeof(topology));
  1607. topology.needs_split_display = true;
  1608. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, &topology, hw_ids);
  1609. }
  1610. return ret;
  1611. }
  1612. /*
  1613. * Returns number of dsc hw blocks previously owned by this encoder.
  1614. * Returns 0 if not found or error
  1615. */
  1616. static int _sde_rm_find_prev_dsc(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1617. u8 *prev_dsc, u32 max_cnt)
  1618. {
  1619. int i = 0;
  1620. struct sde_rm_hw_iter iter_dsc;
  1621. if ((!prev_dsc) || (max_cnt < MAX_DATA_PATH_PER_DSIPLAY))
  1622. return 0;
  1623. sde_rm_init_hw_iter(&iter_dsc, 0, SDE_HW_BLK_DSC);
  1624. while (_sde_rm_get_hw_locked(rm, &iter_dsc)) {
  1625. if (RESERVED_BY_CURRENT(iter_dsc.blk, rsvp))
  1626. prev_dsc[i++] = iter_dsc.blk->id;
  1627. if (i >= MAX_DATA_PATH_PER_DSIPLAY)
  1628. return 0;
  1629. }
  1630. return i;
  1631. }
  1632. static int _sde_rm_make_dsc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1633. struct sde_rm_requirements *reqs,
  1634. struct sde_splash_display *splash_display)
  1635. {
  1636. int i;
  1637. u8 *hw_ids = NULL;
  1638. u8 prev_dsc[MAX_DATA_PATH_PER_DSIPLAY] = {0,};
  1639. /* Check if splash data provided dsc_ids */
  1640. if (splash_display) {
  1641. hw_ids = splash_display->dsc_ids;
  1642. if (splash_display->dsc_cnt)
  1643. reqs->hw_res.comp_info->comp_type =
  1644. MSM_DISPLAY_COMPRESSION_DSC;
  1645. for (i = 0; i < splash_display->dsc_cnt; i++)
  1646. SDE_DEBUG("splash_data.dsc_ids[%d] = %d\n",
  1647. i, splash_display->dsc_ids[i]);
  1648. }
  1649. /*
  1650. * find if this encoder has previously allocated dsc hw blocks, use same dsc blocks
  1651. * if found to avoid switching dsc encoders during each modeset, as currently we
  1652. * dont have feasible way of decoupling previously owned dsc blocks by resetting
  1653. * respective dsc encoders mux control and flush them from commit path
  1654. */
  1655. if (!hw_ids && _sde_rm_find_prev_dsc(rm, rsvp, prev_dsc, MAX_DATA_PATH_PER_DSIPLAY))
  1656. return _sde_rm_reserve_dsc(rm, rsvp, reqs, prev_dsc);
  1657. else
  1658. return _sde_rm_reserve_dsc(rm, rsvp, reqs, hw_ids);
  1659. }
  1660. static int _sde_rm_make_vdc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1661. struct sde_rm_requirements *reqs,
  1662. struct sde_splash_display *splash_display)
  1663. {
  1664. int ret, i;
  1665. u8 *hw_ids = NULL;
  1666. /* Check if splash data provided vdc_ids */
  1667. if (splash_display) {
  1668. hw_ids = splash_display->vdc_ids;
  1669. for (i = 0; i < splash_display->vdc_cnt; i++)
  1670. SDE_DEBUG("splash_data.vdc_ids[%d] = %d\n",
  1671. i, splash_display->vdc_ids[i]);
  1672. }
  1673. ret = _sde_rm_reserve_vdc(rm, rsvp, reqs, reqs->topology, hw_ids);
  1674. return ret;
  1675. }
  1676. static int _sde_rm_make_next_rsvp(struct sde_rm *rm, struct drm_encoder *enc,
  1677. struct drm_crtc_state *crtc_state,
  1678. struct drm_connector_state *conn_state,
  1679. struct sde_rm_rsvp *rsvp,
  1680. struct sde_rm_requirements *reqs)
  1681. {
  1682. struct msm_drm_private *priv;
  1683. struct sde_kms *sde_kms;
  1684. struct sde_splash_display *splash_display = NULL;
  1685. struct sde_splash_data *splash_data;
  1686. int i, ret;
  1687. priv = enc->dev->dev_private;
  1688. sde_kms = to_sde_kms(priv->kms);
  1689. splash_data = &sde_kms->splash_data;
  1690. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  1691. for (i = 0; i < ARRAY_SIZE(splash_data->splash_display); i++) {
  1692. if (enc == splash_data->splash_display[i].encoder)
  1693. splash_display =
  1694. &splash_data->splash_display[i];
  1695. }
  1696. if (!splash_display) {
  1697. SDE_ERROR("rm is in cont_splash but data not found\n");
  1698. return -EINVAL;
  1699. }
  1700. }
  1701. /* Create reservation info, tag reserved blocks with it as we go */
  1702. rsvp->seq = ++rm->rsvp_next_seq;
  1703. rsvp->enc_id = enc->base.id;
  1704. rsvp->topology = reqs->topology->top_name;
  1705. rsvp->pending = true;
  1706. list_add_tail(&rsvp->list, &rm->rsvps);
  1707. ret = _sde_rm_make_lm_rsvp(rm, rsvp, reqs, splash_display);
  1708. if (ret) {
  1709. SDE_ERROR("unable to find appropriate mixers\n");
  1710. _sde_rm_print_rsvps_by_type(rm, SDE_HW_BLK_LM);
  1711. return ret;
  1712. }
  1713. ret = _sde_rm_make_ctl_rsvp(rm, rsvp, reqs, splash_display);
  1714. if (ret) {
  1715. SDE_ERROR("unable to find appropriate CTL\n");
  1716. return ret;
  1717. }
  1718. /* Assign INTFs, WBs, and blks whose usage is tied to them: CTL & CDM */
  1719. ret = _sde_rm_reserve_intf_related_hw(rm, rsvp, reqs);
  1720. if (ret)
  1721. return ret;
  1722. ret = _sde_rm_make_dsc_rsvp(rm, rsvp, reqs, splash_display);
  1723. if (ret)
  1724. return ret;
  1725. ret = _sde_rm_make_vdc_rsvp(rm, rsvp, reqs, splash_display);
  1726. if (ret)
  1727. return ret;
  1728. ret = _sde_rm_reserve_qdss(rm, rsvp, reqs->topology, NULL);
  1729. if (ret)
  1730. return ret;
  1731. return ret;
  1732. }
  1733. static int _sde_rm_update_active_only_pipes(
  1734. struct sde_splash_display *splash_display,
  1735. u32 active_pipes_mask)
  1736. {
  1737. struct sde_sspp_index_info *pipe_info;
  1738. int i;
  1739. if (!active_pipes_mask) {
  1740. return 0;
  1741. } else if (!splash_display) {
  1742. SDE_ERROR("invalid splash display provided\n");
  1743. return -EINVAL;
  1744. }
  1745. pipe_info = &splash_display->pipe_info;
  1746. for (i = SSPP_VIG0; i < SSPP_MAX; i++) {
  1747. if (!(active_pipes_mask & BIT(i)))
  1748. continue;
  1749. if (test_bit(i, pipe_info->pipes) || test_bit(i, pipe_info->virt_pipes))
  1750. continue;
  1751. /*
  1752. * A pipe is active but not staged indicates a non-pixel
  1753. * plane. Register both rectangles as we can't differentiate
  1754. */
  1755. set_bit(i, pipe_info->pipes);
  1756. set_bit(i, pipe_info->virt_pipes);
  1757. SDE_DEBUG("pipe %d is active:0x%x but not staged\n", i, active_pipes_mask);
  1758. }
  1759. return 0;
  1760. }
  1761. /**
  1762. * _sde_rm_get_hw_blk_for_cont_splash - retrieve the LM blocks on given CTL
  1763. * and populate the connected HW blk ids in sde_splash_display
  1764. * @rm: Pointer to resource manager structure
  1765. * @ctl: Pointer to CTL hardware block
  1766. * @splash_display: Pointer to struct sde_splash_display
  1767. * return: number of active LM blocks for this CTL block
  1768. */
  1769. static int _sde_rm_get_hw_blk_for_cont_splash(struct sde_rm *rm,
  1770. struct sde_hw_ctl *ctl,
  1771. struct sde_splash_display *splash_display)
  1772. {
  1773. u32 active_pipes_mask = 0;
  1774. struct sde_rm_hw_iter iter_lm, iter_dsc;
  1775. struct sde_kms *sde_kms;
  1776. size_t pipes_per_lm;
  1777. if (!rm || !ctl || !splash_display) {
  1778. SDE_ERROR("invalid input parameters\n");
  1779. return 0;
  1780. }
  1781. sde_kms = container_of(rm, struct sde_kms, rm);
  1782. sde_rm_init_hw_iter(&iter_lm, 0, SDE_HW_BLK_LM);
  1783. sde_rm_init_hw_iter(&iter_dsc, 0, SDE_HW_BLK_DSC);
  1784. while (_sde_rm_get_hw_locked(rm, &iter_lm)) {
  1785. if (splash_display->lm_cnt >= MAX_DATA_PATH_PER_DSIPLAY)
  1786. break;
  1787. if (ctl->ops.get_staged_sspp) {
  1788. // reset bordercolor from previous LM
  1789. splash_display->pipe_info.bordercolor = false;
  1790. pipes_per_lm = ctl->ops.get_staged_sspp(
  1791. ctl, iter_lm.blk->id,
  1792. &splash_display->pipe_info);
  1793. if (pipes_per_lm ||
  1794. splash_display->pipe_info.bordercolor) {
  1795. splash_display->lm_ids[splash_display->lm_cnt++] =
  1796. iter_lm.blk->id;
  1797. SDE_DEBUG("lm_cnt=%d lm_id %d pipe_cnt%d\n",
  1798. splash_display->lm_cnt,
  1799. iter_lm.blk->id - LM_0,
  1800. pipes_per_lm);
  1801. }
  1802. }
  1803. }
  1804. if (ctl->ops.get_active_pipes)
  1805. active_pipes_mask = ctl->ops.get_active_pipes(ctl);
  1806. if (_sde_rm_update_active_only_pipes(splash_display, active_pipes_mask))
  1807. return 0;
  1808. while (_sde_rm_get_hw_locked(rm, &iter_dsc)) {
  1809. if (ctl->ops.read_active_status &&
  1810. !(ctl->ops.read_active_status(ctl,
  1811. SDE_HW_BLK_DSC,
  1812. iter_dsc.blk->id)))
  1813. continue;
  1814. splash_display->dsc_ids[splash_display->dsc_cnt++] =
  1815. iter_dsc.blk->id;
  1816. SDE_DEBUG("CTL[%d] path, using dsc[%d]\n",
  1817. ctl->idx,
  1818. iter_dsc.blk->id - DSC_0);
  1819. }
  1820. return splash_display->lm_cnt;
  1821. }
  1822. int sde_rm_cont_splash_res_init(struct msm_drm_private *priv,
  1823. struct sde_rm *rm,
  1824. struct sde_splash_data *splash_data,
  1825. struct sde_mdss_cfg *cat)
  1826. {
  1827. struct sde_rm_hw_iter iter_c;
  1828. int index = 0, ctl_top_cnt;
  1829. struct sde_kms *sde_kms = NULL;
  1830. struct sde_hw_mdp *hw_mdp;
  1831. struct sde_splash_display *splash_display;
  1832. u8 intf_sel;
  1833. if (!priv || !rm || !cat || !splash_data) {
  1834. SDE_ERROR("invalid input parameters\n");
  1835. return -EINVAL;
  1836. }
  1837. SDE_DEBUG("mixer_count=%d, ctl_count=%d, dsc_count=%d\n",
  1838. cat->mixer_count,
  1839. cat->ctl_count,
  1840. cat->dsc_count);
  1841. ctl_top_cnt = cat->ctl_count;
  1842. if (!priv->kms) {
  1843. SDE_ERROR("invalid kms\n");
  1844. return -EINVAL;
  1845. }
  1846. sde_kms = to_sde_kms(priv->kms);
  1847. hw_mdp = sde_rm_get_mdp(rm);
  1848. sde_rm_init_hw_iter(&iter_c, 0, SDE_HW_BLK_CTL);
  1849. while (_sde_rm_get_hw_locked(rm, &iter_c)
  1850. && (index < splash_data->num_splash_displays)) {
  1851. struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter_c.blk->hw);
  1852. if (!ctl->ops.get_ctl_intf) {
  1853. SDE_ERROR("get_ctl_intf not initialized\n");
  1854. return -EINVAL;
  1855. }
  1856. intf_sel = ctl->ops.get_ctl_intf(ctl);
  1857. if (intf_sel) {
  1858. splash_display = &splash_data->splash_display[index];
  1859. SDE_DEBUG("finding resources for display=%d ctl=%d\n",
  1860. index, iter_c.blk->id - CTL_0);
  1861. _sde_rm_get_hw_blk_for_cont_splash(rm,
  1862. ctl, splash_display);
  1863. splash_display->cont_splash_enabled = true;
  1864. splash_display->ctl_ids[splash_display->ctl_cnt++] =
  1865. iter_c.blk->id;
  1866. }
  1867. index++;
  1868. }
  1869. return 0;
  1870. }
  1871. static int _sde_rm_populate_requirements(
  1872. struct sde_rm *rm,
  1873. struct drm_encoder *enc,
  1874. struct drm_crtc_state *crtc_state,
  1875. struct drm_connector_state *conn_state,
  1876. struct sde_mdss_cfg *cfg,
  1877. struct sde_rm_requirements *reqs)
  1878. {
  1879. const struct drm_display_mode *mode = &crtc_state->mode;
  1880. int i, num_lm;
  1881. reqs->top_ctrl = sde_connector_get_property(conn_state,
  1882. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  1883. sde_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state);
  1884. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++) {
  1885. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  1886. reqs->hw_res.topology)) {
  1887. reqs->topology = &rm->topology_tbl[i];
  1888. break;
  1889. }
  1890. }
  1891. if (!reqs->topology) {
  1892. SDE_ERROR("invalid topology for the display\n");
  1893. return -EINVAL;
  1894. }
  1895. /*
  1896. * select dspp HW block for all dsi displays and ds for only
  1897. * primary dsi display.
  1898. */
  1899. if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI) {
  1900. if (!RM_RQ_DSPP(reqs))
  1901. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DSPP);
  1902. if (!RM_RQ_DS(reqs) && rm->hw_mdp->caps->has_dest_scaler &&
  1903. sde_encoder_is_primary_display(enc))
  1904. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DS);
  1905. }
  1906. /**
  1907. * Set the requirement for LM which has CWB support if CWB is
  1908. * found enabled.
  1909. */
  1910. if ((!RM_RQ_CWB(reqs) || !RM_RQ_DCWB(reqs))
  1911. && sde_crtc_state_in_clone_mode(enc, crtc_state)) {
  1912. if (test_bit(SDE_FEATURE_DEDICATED_CWB, cfg->features))
  1913. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DCWB);
  1914. else
  1915. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_CWB);
  1916. /*
  1917. * topology selection based on conn mode is not valid for CWB
  1918. * as WB conn populates modes based on max_mixer_width check
  1919. * but primary can be using dual LMs. This topology override for
  1920. * CWB is to check number of datapath active in primary and
  1921. * allocate same number of LM/PP blocks reserved for CWB
  1922. */
  1923. reqs->topology =
  1924. &rm->topology_tbl[SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE];
  1925. num_lm = sde_crtc_get_num_datapath(crtc_state->crtc,
  1926. conn_state->connector, crtc_state);
  1927. if (num_lm == 1)
  1928. reqs->topology =
  1929. &rm->topology_tbl[SDE_RM_TOPOLOGY_SINGLEPIPE];
  1930. else if (num_lm == 0)
  1931. SDE_ERROR("Primary layer mixer is not set\n");
  1932. SDE_EVT32(num_lm, reqs->topology->num_lm,
  1933. reqs->topology->top_name, reqs->topology->num_ctl);
  1934. }
  1935. SDE_DEBUG("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
  1936. reqs->hw_res.display_num_of_h_tiles);
  1937. SDE_DEBUG("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
  1938. reqs->topology->num_lm, reqs->topology->num_ctl,
  1939. reqs->topology->top_name,
  1940. reqs->topology->needs_split_display);
  1941. SDE_EVT32(mode->hdisplay, rm->lm_max_width, reqs->topology->num_lm,
  1942. reqs->top_ctrl, reqs->topology->top_name,
  1943. reqs->topology->num_ctl);
  1944. return 0;
  1945. }
  1946. static struct sde_rm_rsvp *_sde_rm_get_rsvp(struct sde_rm *rm, struct drm_encoder *enc, bool nxt)
  1947. {
  1948. struct sde_rm_rsvp *i;
  1949. if (!rm || !enc) {
  1950. SDE_ERROR("invalid params\n");
  1951. return NULL;
  1952. }
  1953. if (list_empty(&rm->rsvps))
  1954. return NULL;
  1955. list_for_each_entry(i, &rm->rsvps, list)
  1956. if (i->pending == nxt && i->enc_id == enc->base.id)
  1957. return i;
  1958. return NULL;
  1959. }
  1960. static struct sde_rm_rsvp *_sde_rm_get_rsvp_nxt(struct sde_rm *rm, struct drm_encoder *enc)
  1961. {
  1962. return _sde_rm_get_rsvp(rm, enc, true);
  1963. }
  1964. static struct sde_rm_rsvp *_sde_rm_get_rsvp_cur(struct sde_rm *rm, struct drm_encoder *enc)
  1965. {
  1966. return _sde_rm_get_rsvp(rm, enc, false);
  1967. }
  1968. static struct drm_connector *_sde_rm_get_connector(
  1969. struct drm_encoder *enc)
  1970. {
  1971. struct drm_connector *conn = NULL, *conn_search;
  1972. struct sde_connector *c_conn = NULL;
  1973. struct drm_connector_list_iter conn_iter;
  1974. drm_connector_list_iter_begin(enc->dev, &conn_iter);
  1975. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1976. c_conn = to_sde_connector(conn_search);
  1977. if (c_conn->encoder == enc) {
  1978. conn = conn_search;
  1979. break;
  1980. }
  1981. }
  1982. drm_connector_list_iter_end(&conn_iter);
  1983. return conn;
  1984. }
  1985. int sde_rm_update_topology(struct sde_rm *rm,
  1986. struct drm_connector_state *conn_state,
  1987. struct msm_display_topology *topology)
  1988. {
  1989. int i, ret = 0;
  1990. struct msm_display_topology top;
  1991. enum sde_rm_topology_name top_name = SDE_RM_TOPOLOGY_NONE;
  1992. if (!conn_state)
  1993. return -EINVAL;
  1994. if (topology) {
  1995. top = *topology;
  1996. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  1997. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i], top)) {
  1998. top_name = rm->topology_tbl[i].top_name;
  1999. break;
  2000. }
  2001. }
  2002. ret = msm_property_set_property(
  2003. sde_connector_get_propinfo(conn_state->connector),
  2004. sde_connector_get_property_state(conn_state),
  2005. CONNECTOR_PROP_TOPOLOGY_NAME, top_name);
  2006. return ret;
  2007. }
  2008. bool sde_rm_topology_is_group(struct sde_rm *rm,
  2009. struct drm_crtc_state *state,
  2010. enum sde_rm_topology_group group)
  2011. {
  2012. int i, ret = 0;
  2013. struct sde_crtc_state *cstate;
  2014. struct drm_connector *conn;
  2015. struct drm_connector_state *conn_state;
  2016. struct msm_display_topology topology;
  2017. enum sde_rm_topology_name name;
  2018. if ((!rm) || (!state) || (!state->state)) {
  2019. pr_err("invalid arguments: rm:%d state:%d atomic state:%d\n",
  2020. !rm, !state, state ? (!state->state) : 0);
  2021. return false;
  2022. }
  2023. cstate = to_sde_crtc_state(state);
  2024. for (i = 0; i < cstate->num_connectors; i++) {
  2025. conn = cstate->connectors[i];
  2026. if (!conn) {
  2027. SDE_DEBUG("invalid connector\n");
  2028. continue;
  2029. }
  2030. conn_state = drm_atomic_get_new_connector_state(state->state,
  2031. conn);
  2032. if (!conn_state) {
  2033. SDE_DEBUG("%s invalid connector state\n", conn->name);
  2034. continue;
  2035. }
  2036. ret = sde_connector_state_get_topology(conn_state, &topology);
  2037. if (ret) {
  2038. SDE_DEBUG("%s invalid topology\n", conn->name);
  2039. continue;
  2040. }
  2041. name = sde_rm_get_topology_name(rm, topology);
  2042. switch (group) {
  2043. case SDE_RM_TOPOLOGY_GROUP_SINGLEPIPE:
  2044. if (TOPOLOGY_SINGLEPIPE_MODE(name))
  2045. return true;
  2046. break;
  2047. case SDE_RM_TOPOLOGY_GROUP_DUALPIPE:
  2048. if (TOPOLOGY_DUALPIPE_MODE(name))
  2049. return true;
  2050. break;
  2051. case SDE_RM_TOPOLOGY_GROUP_QUADPIPE:
  2052. if (TOPOLOGY_QUADPIPE_MODE(name))
  2053. return true;
  2054. break;
  2055. case SDE_RM_TOPOLOGY_GROUP_3DMERGE:
  2056. if (topology.num_lm > topology.num_intf &&
  2057. !topology.num_enc)
  2058. return true;
  2059. break;
  2060. case SDE_RM_TOPOLOGY_GROUP_3DMERGE_DSC:
  2061. if (topology.num_lm > topology.num_enc &&
  2062. topology.num_enc)
  2063. return true;
  2064. break;
  2065. case SDE_RM_TOPOLOGY_GROUP_DSCMERGE:
  2066. if (topology.num_lm == topology.num_enc &&
  2067. topology.num_enc)
  2068. return true;
  2069. break;
  2070. default:
  2071. SDE_ERROR("invalid topology group\n");
  2072. return false;
  2073. }
  2074. }
  2075. return false;
  2076. }
  2077. /**
  2078. * _sde_rm_release_rsvp - release resources and release a reservation
  2079. * @rm: KMS handle
  2080. * @rsvp: RSVP pointer to release and release resources for
  2081. */
  2082. static void _sde_rm_release_rsvp(
  2083. struct sde_rm *rm,
  2084. struct sde_rm_rsvp *rsvp,
  2085. struct drm_connector *conn)
  2086. {
  2087. struct sde_rm_rsvp *rsvp_c, *rsvp_n;
  2088. struct sde_rm_hw_blk *blk;
  2089. enum sde_hw_blk_type type;
  2090. if (!rsvp)
  2091. return;
  2092. SDE_DEBUG("rel rsvp %d enc %d\n", rsvp->seq, rsvp->enc_id);
  2093. list_for_each_entry_safe(rsvp_c, rsvp_n, &rm->rsvps, list) {
  2094. if (rsvp == rsvp_c) {
  2095. list_del(&rsvp_c->list);
  2096. break;
  2097. }
  2098. }
  2099. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  2100. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  2101. if (blk->rsvp == rsvp) {
  2102. blk->rsvp = NULL;
  2103. SDE_DEBUG("rel rsvp %d enc %d %d %d\n",
  2104. rsvp->seq, rsvp->enc_id,
  2105. blk->type, blk->id);
  2106. _sde_rm_inc_resource_info(rm,
  2107. &rm->avail_res, blk);
  2108. }
  2109. if (blk->rsvp_nxt == rsvp) {
  2110. blk->rsvp_nxt = NULL;
  2111. SDE_DEBUG("rel rsvp_nxt %d enc %d %d %d\n",
  2112. rsvp->seq, rsvp->enc_id,
  2113. blk->type, blk->id);
  2114. }
  2115. }
  2116. }
  2117. kfree(rsvp);
  2118. }
  2119. void sde_rm_release(struct sde_rm *rm, struct drm_encoder *enc, bool nxt)
  2120. {
  2121. struct sde_rm_rsvp *rsvp;
  2122. struct drm_connector *conn = NULL;
  2123. struct msm_drm_private *priv;
  2124. struct sde_kms *sde_kms;
  2125. uint64_t top_ctrl = 0;
  2126. if (!rm || !enc) {
  2127. SDE_ERROR("invalid params\n");
  2128. return;
  2129. }
  2130. priv = enc->dev->dev_private;
  2131. if (!priv->kms) {
  2132. SDE_ERROR("invalid kms\n");
  2133. return;
  2134. }
  2135. sde_kms = to_sde_kms(priv->kms);
  2136. mutex_lock(&rm->rm_lock);
  2137. rsvp = _sde_rm_get_rsvp(rm, enc, nxt);
  2138. if (!rsvp) {
  2139. SDE_DEBUG("failed to find rsvp for enc %d, nxt %d",
  2140. enc->base.id, nxt);
  2141. goto end;
  2142. }
  2143. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  2144. _sde_rm_release_rsvp(rm, rsvp, conn);
  2145. goto end;
  2146. }
  2147. conn = _sde_rm_get_connector(enc);
  2148. if (!conn) {
  2149. SDE_EVT32(enc->base.id, 0x0, 0xffffffff);
  2150. _sde_rm_release_rsvp(rm, rsvp, conn);
  2151. SDE_DEBUG("failed to get conn for enc %d nxt %d\n",
  2152. enc->base.id, nxt);
  2153. goto end;
  2154. }
  2155. top_ctrl = sde_connector_get_property(conn->state,
  2156. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  2157. SDE_EVT32(enc->base.id, conn->base.id, rsvp->seq, top_ctrl, nxt);
  2158. if (top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK)) {
  2159. SDE_DEBUG("rsvp[s%de%d] not releasing locked resources\n",
  2160. rsvp->seq, rsvp->enc_id);
  2161. } else {
  2162. SDE_DEBUG("release rsvp[s%de%d]\n", rsvp->seq,
  2163. rsvp->enc_id);
  2164. _sde_rm_release_rsvp(rm, rsvp, conn);
  2165. }
  2166. end:
  2167. mutex_unlock(&rm->rm_lock);
  2168. }
  2169. static void _sde_rm_commit_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  2170. struct drm_connector_state *conn_state)
  2171. {
  2172. struct sde_rm_hw_blk *blk;
  2173. enum sde_hw_blk_type type;
  2174. /* Swap next rsvp to be the active */
  2175. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  2176. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  2177. if (blk->rsvp_nxt && conn_state->best_encoder->base.id
  2178. == blk->rsvp_nxt->enc_id) {
  2179. blk->rsvp = blk->rsvp_nxt;
  2180. blk->rsvp_nxt = NULL;
  2181. _sde_rm_dec_resource_info(rm,
  2182. &rm->avail_res, blk);
  2183. }
  2184. }
  2185. }
  2186. rsvp->pending = false;
  2187. SDE_DEBUG("rsrv enc %d topology %d\n", rsvp->enc_id, rsvp->topology);
  2188. SDE_EVT32(rsvp->enc_id, rsvp->topology);
  2189. }
  2190. /* call this only after rm_mutex held */
  2191. struct sde_rm_rsvp *_sde_rm_poll_get_rsvp_nxt_locked(struct sde_rm *rm,
  2192. struct drm_encoder *enc)
  2193. {
  2194. int i;
  2195. u32 loop_count = 20;
  2196. struct sde_rm_rsvp *rsvp_nxt = NULL;
  2197. u32 sleep = RM_NXT_CLEAR_POLL_TIMEOUT_US / loop_count;
  2198. for (i = 0; i < loop_count; i++) {
  2199. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  2200. if (!rsvp_nxt)
  2201. return rsvp_nxt;
  2202. mutex_unlock(&rm->rm_lock);
  2203. SDE_DEBUG("iteration i:%d sleep range:%uus to %uus\n",
  2204. i, sleep, sleep * 2);
  2205. usleep_range(sleep, sleep * 2);
  2206. mutex_lock(&rm->rm_lock);
  2207. }
  2208. /* make sure to get latest rsvp_next to avoid use after free issues */
  2209. return _sde_rm_get_rsvp_nxt(rm, enc);
  2210. }
  2211. int sde_rm_reserve(
  2212. struct sde_rm *rm,
  2213. struct drm_encoder *enc,
  2214. struct drm_crtc_state *crtc_state,
  2215. struct drm_connector_state *conn_state,
  2216. bool test_only)
  2217. {
  2218. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  2219. struct sde_rm_requirements reqs = {0,};
  2220. struct msm_drm_private *priv;
  2221. struct sde_kms *sde_kms;
  2222. struct msm_compression_info *comp_info;
  2223. int ret = 0;
  2224. if (!rm || !enc || !crtc_state || !conn_state) {
  2225. SDE_ERROR("invalid arguments\n");
  2226. return -EINVAL;
  2227. }
  2228. if (!enc->dev || !enc->dev->dev_private) {
  2229. SDE_ERROR("drm device invalid\n");
  2230. return -EINVAL;
  2231. }
  2232. priv = enc->dev->dev_private;
  2233. if (!priv->kms) {
  2234. SDE_ERROR("invalid kms\n");
  2235. return -EINVAL;
  2236. }
  2237. sde_kms = to_sde_kms(priv->kms);
  2238. /* Check if this is just a page-flip */
  2239. if (!_sde_rm_is_display_in_cont_splash(sde_kms, enc) &&
  2240. !msm_atomic_needs_modeset(crtc_state, conn_state))
  2241. return 0;
  2242. comp_info = kzalloc(sizeof(*comp_info), GFP_KERNEL);
  2243. if (!comp_info)
  2244. return -ENOMEM;
  2245. SDE_DEBUG("reserving hw for conn %d enc %d crtc %d test_only %d\n",
  2246. conn_state->connector->base.id, enc->base.id,
  2247. crtc_state->crtc->base.id, test_only);
  2248. SDE_EVT32(enc->base.id, conn_state->connector->base.id, test_only);
  2249. mutex_lock(&rm->rm_lock);
  2250. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_BEGIN);
  2251. rsvp_cur = _sde_rm_get_rsvp_cur(rm, enc);
  2252. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  2253. /*
  2254. * RM currently relies on rsvp_nxt assigned to the hw blocks to
  2255. * commit rsvps. This rsvp_nxt can be cleared by a back to back
  2256. * check_only commit with modeset when its predecessor atomic
  2257. * commit is delayed / not committed the reservation yet.
  2258. * Poll for rsvp_nxt clear, allow the check_only commit if rsvp_nxt
  2259. * gets cleared and bailout if it does not get cleared before timeout.
  2260. */
  2261. if (test_only && rsvp_nxt) {
  2262. rsvp_nxt = _sde_rm_poll_get_rsvp_nxt_locked(rm, enc);
  2263. rsvp_cur = _sde_rm_get_rsvp_cur(rm, enc);
  2264. if (rsvp_nxt) {
  2265. pr_err("poll timeout cur %d nxt %d enc %d\n",
  2266. (rsvp_cur) ? rsvp_cur->seq : -1,
  2267. rsvp_nxt->seq, enc->base.id);
  2268. SDE_EVT32(enc->base.id, (rsvp_cur) ? rsvp_cur->seq : -1,
  2269. rsvp_nxt->seq, SDE_EVTLOG_ERROR);
  2270. ret = -EAGAIN;
  2271. goto end;
  2272. }
  2273. }
  2274. if (!test_only && rsvp_nxt)
  2275. goto commit_rsvp;
  2276. reqs.hw_res.comp_info = comp_info;
  2277. ret = _sde_rm_populate_requirements(rm, enc, crtc_state,
  2278. conn_state, sde_kms->catalog, &reqs);
  2279. if (ret) {
  2280. SDE_ERROR("failed to populate hw requirements\n");
  2281. goto end;
  2282. }
  2283. /*
  2284. * We only support one active reservation per-hw-block. But to implement
  2285. * transactional semantics for test-only, and for allowing failure while
  2286. * modifying your existing reservation, over the course of this
  2287. * function we can have two reservations:
  2288. * Current: Existing reservation
  2289. * Next: Proposed reservation. The proposed reservation may fail, or may
  2290. * be discarded if in test-only mode.
  2291. * If reservation is successful, and we're not in test-only, then we
  2292. * replace the current with the next.
  2293. */
  2294. rsvp_nxt = kzalloc(sizeof(*rsvp_nxt), GFP_KERNEL);
  2295. if (!rsvp_nxt) {
  2296. ret = -ENOMEM;
  2297. goto end;
  2298. }
  2299. /*
  2300. * User can request that we clear out any reservation during the
  2301. * atomic_check phase by using this CLEAR bit
  2302. */
  2303. if (rsvp_cur && test_only && RM_RQ_CLEAR(&reqs)) {
  2304. SDE_DEBUG("test_only & CLEAR: clear rsvp[s%de%d]\n",
  2305. rsvp_cur->seq, rsvp_cur->enc_id);
  2306. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2307. rsvp_cur = NULL;
  2308. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_CLEAR);
  2309. }
  2310. /* Check the proposed reservation, store it in hw's "next" field */
  2311. ret = _sde_rm_make_next_rsvp(rm, enc, crtc_state, conn_state,
  2312. rsvp_nxt, &reqs);
  2313. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_RSVPNEXT);
  2314. if (ret) {
  2315. SDE_ERROR("failed to reserve hw resources: %d, test_only %d\n",
  2316. ret, test_only);
  2317. _sde_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector);
  2318. goto end;
  2319. } else if (test_only && !RM_RQ_LOCK(&reqs)) {
  2320. /*
  2321. * Normally, if test_only, test the reservation and then undo
  2322. * However, if the user requests LOCK, then keep the reservation
  2323. * made during the atomic_check phase.
  2324. */
  2325. SDE_DEBUG("test_only: rsvp[s%de%d]\n",
  2326. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2327. goto end;
  2328. } else {
  2329. if (test_only && RM_RQ_LOCK(&reqs))
  2330. SDE_DEBUG("test_only & LOCK: lock rsvp[s%de%d]\n",
  2331. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2332. }
  2333. commit_rsvp:
  2334. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2335. _sde_rm_commit_rsvp(rm, rsvp_nxt, conn_state);
  2336. end:
  2337. kfree(comp_info);
  2338. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_FINAL);
  2339. mutex_unlock(&rm->rm_lock);
  2340. return ret;
  2341. }