sde_hw_pingpong.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _SDE_HW_PINGPONG_H
  6. #define _SDE_HW_PINGPONG_H
  7. #include "sde_hw_catalog.h"
  8. #include "sde_hw_mdss.h"
  9. #include "sde_hw_util.h"
  10. #include <drm/msm_drm_pp.h>
  11. struct sde_hw_pingpong;
  12. struct sde_hw_merge_3d;
  13. #define DITHER_DEPTH_MAP_INDEX 9
  14. static u32 dither_depth_map[DITHER_DEPTH_MAP_INDEX] = {
  15. 0, 0, 0, 0, 0, 1, 2, 3, 3
  16. };
  17. struct sde_hw_dsc_cfg {
  18. u8 enable;
  19. };
  20. /**
  21. *
  22. * struct sde_hw_pingpong_ops : Interface to the pingpong Hw driver functions
  23. * Assumption is these functions will be called after clocks are enabled
  24. * @setup_tearcheck : program tear check values
  25. * @enable_tearcheck : enables tear check
  26. * @get_vsync_info : retries timing info of the panel
  27. * @setup_autorefresh : program auto refresh
  28. * @setup_dsc : program DSC block with encoding details
  29. * @enable_dsc : enables DSC encoder
  30. * @disable_dsc : disables DSC encoder
  31. * @setup_dither : function to program the dither hw block
  32. * @get_line_count: obtain current vertical line counter
  33. * @get_hw_caps: returns features supported by this pp block
  34. */
  35. struct sde_hw_pingpong_ops {
  36. /**
  37. * enables vysnc generation and sets up init value of
  38. * read pointer and programs the tear check cofiguration
  39. */
  40. int (*setup_tearcheck)(struct sde_hw_pingpong *pp,
  41. struct sde_hw_tear_check *cfg);
  42. /**
  43. * enables tear check block
  44. */
  45. int (*enable_tearcheck)(struct sde_hw_pingpong *pp,
  46. bool enable);
  47. /**
  48. * updates tearcheck configuration
  49. */
  50. void (*update_tearcheck)(struct sde_hw_pingpong *pp,
  51. struct sde_hw_tear_check *cfg);
  52. /**
  53. * read, modify, write to either set or clear listening to external TE
  54. * @Return: 1 if TE was originally connected, 0 if not, or -ERROR
  55. */
  56. int (*connect_external_te)(struct sde_hw_pingpong *pp,
  57. bool enable_external_te);
  58. /**
  59. * provides the programmed and current
  60. * line_count
  61. */
  62. int (*get_vsync_info)(struct sde_hw_pingpong *pp,
  63. struct sde_hw_pp_vsync_info *info);
  64. /**
  65. * configure and enable the autorefresh config
  66. */
  67. int (*setup_autorefresh)(struct sde_hw_pingpong *pp,
  68. struct sde_hw_autorefresh *cfg);
  69. /**
  70. * retrieve autorefresh config from hardware
  71. */
  72. int (*get_autorefresh)(struct sde_hw_pingpong *pp,
  73. struct sde_hw_autorefresh *cfg);
  74. /**
  75. * poll until write pointer transmission starts
  76. * @Return: 0 on success, -ETIMEDOUT on timeout
  77. */
  78. int (*poll_timeout_wr_ptr)(struct sde_hw_pingpong *pp, u32 timeout_us);
  79. /**
  80. * Program the dsc compression block
  81. */
  82. int (*setup_dsc)(struct sde_hw_pingpong *pp);
  83. /**
  84. * Enables DSC encoder
  85. */
  86. void (*enable_dsc)(struct sde_hw_pingpong *pp);
  87. /**
  88. * Disables DSC encoder
  89. */
  90. void (*disable_dsc)(struct sde_hw_pingpong *pp);
  91. /**
  92. * Program the dither hw block
  93. */
  94. int (*setup_dither)(struct sde_hw_pingpong *pp, void *cfg, size_t len);
  95. /**
  96. * Obtain current vertical line counter
  97. */
  98. u32 (*get_line_count)(struct sde_hw_pingpong *pp);
  99. /**
  100. * Programs the 3d blend configuration
  101. */
  102. void (*setup_3d_mode)(struct sde_hw_pingpong *pp,
  103. enum sde_3d_blend_mode cfg);
  104. /**
  105. * reset 3d blend configuration
  106. */
  107. void (*reset_3d_mode)(struct sde_hw_pingpong *pp);
  108. /**
  109. * get PP features supported by this instance
  110. */
  111. unsigned long (*get_hw_caps)(struct sde_hw_pingpong *pp);
  112. };
  113. struct sde_hw_merge_3d_ops {
  114. /**
  115. * setup the 3d blend mode configuration
  116. */
  117. void (*setup_blend_mode)(struct sde_hw_merge_3d *id,
  118. enum sde_3d_blend_mode cfg);
  119. /**
  120. * reset 3d blend mode configuration
  121. */
  122. void (*reset_blend_mode)(struct sde_hw_merge_3d *id);
  123. };
  124. struct sde_hw_merge_3d {
  125. struct sde_hw_blk_reg_map hw;
  126. /* merge_3d */
  127. enum sde_merge_3d idx;
  128. const struct sde_merge_3d_cfg *caps;
  129. /* ops */
  130. struct sde_hw_merge_3d_ops ops;
  131. };
  132. struct sde_hw_pingpong {
  133. struct sde_hw_blk_reg_map hw;
  134. /* pingpong */
  135. enum sde_pingpong idx;
  136. const struct sde_pingpong_cfg *caps;
  137. /* associated 3d_merge */
  138. struct sde_hw_merge_3d *merge_3d;
  139. /* ops */
  140. struct sde_hw_pingpong_ops ops;
  141. };
  142. /**
  143. * to_sde_hw_pingpong - convert base hw object to sde_hw_pingpong container
  144. * @hw: Pointer to hardware block register map object
  145. * return: Pointer to hardware block container
  146. */
  147. static inline struct sde_hw_pingpong *to_sde_hw_pingpong(struct sde_hw_blk_reg_map *hw)
  148. {
  149. return container_of(hw, struct sde_hw_pingpong, hw);
  150. }
  151. /**
  152. * sde_hw_pingpong_init - initializes the pingpong driver for the passed
  153. * pingpong idx.
  154. * @idx: Pingpong index for which driver object is required
  155. * @addr: Mapped register io address of MDP
  156. * @m: Pointer to mdss catalog data
  157. * Returns: Error code or allocated sde_hw_pingpong context
  158. */
  159. struct sde_hw_blk_reg_map *sde_hw_pingpong_init(enum sde_pingpong idx,
  160. void __iomem *addr,
  161. struct sde_mdss_cfg *m);
  162. /**
  163. * sde_hw_pingpong_destroy - destroys pingpong driver context
  164. * should be called to free the context
  165. * @hw: Pointer to hardware block register map object
  166. */
  167. void sde_hw_pingpong_destroy(struct sde_hw_blk_reg_map *hw);
  168. #endif /*_SDE_HW_PINGPONG_H */