sde_hw_ctl.h 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _SDE_HW_CTL_H
  6. #define _SDE_HW_CTL_H
  7. #include "sde_hw_mdss.h"
  8. #include "sde_hw_util.h"
  9. #include "sde_hw_catalog.h"
  10. #include "sde_hw_sspp.h"
  11. #define INVALID_CTL_STATUS 0xfffff88e
  12. #define CTL_MAX_DSPP_COUNT (DSPP_MAX - DSPP_0)
  13. /**
  14. * sde_ctl_mode_sel: Interface mode selection
  15. * SDE_CTL_MODE_SEL_VID: Video mode interface
  16. * SDE_CTL_MODE_SEL_CMD: Command mode interface
  17. */
  18. enum sde_ctl_mode_sel {
  19. SDE_CTL_MODE_SEL_VID = 0,
  20. SDE_CTL_MODE_SEL_CMD
  21. };
  22. /**
  23. * sde_ctl_rot_op_mode - inline rotation mode
  24. * SDE_CTL_ROT_OP_MODE_OFFLINE: offline rotation
  25. * SDE_CTL_ROT_OP_MODE_RESERVED: reserved
  26. * SDE_CTL_ROT_OP_MODE_INLINE_SYNC: inline rotation synchronous mode
  27. * SDE_CTL_ROT_OP_MODE_INLINE_ASYNC: inline rotation asynchronous mode
  28. */
  29. enum sde_ctl_rot_op_mode {
  30. SDE_CTL_ROT_OP_MODE_OFFLINE,
  31. SDE_CTL_ROT_OP_MODE_RESERVED,
  32. SDE_CTL_ROT_OP_MODE_INLINE_SYNC,
  33. SDE_CTL_ROT_OP_MODE_INLINE_ASYNC,
  34. };
  35. /**
  36. * ctl_hw_flush_type - active ctl hw types
  37. * SDE_HW_FLUSH_WB: WB block
  38. * SDE_HW_FLUSH_DSC: DSC block
  39. * SDE_HW_FLUSH_VDC: VDC bits of DSC block
  40. * SDE_HW_FLUSH_MERGE_3D: Merge 3D block
  41. * SDE_HW_FLUSH_CDM: CDM block
  42. * SDE_HW_FLUSH_CWB: CWB block
  43. * SDE_HW_FLUSH_PERIPH: Peripheral
  44. * SDE_HW_FLUSH_INTF: Interface
  45. */
  46. enum ctl_hw_flush_type {
  47. SDE_HW_FLUSH_WB,
  48. SDE_HW_FLUSH_DSC,
  49. SDE_HW_FLUSH_VDC,
  50. SDE_HW_FLUSH_MERGE_3D,
  51. SDE_HW_FLUSH_CDM,
  52. SDE_HW_FLUSH_CWB,
  53. SDE_HW_FLUSH_PERIPH,
  54. SDE_HW_FLUSH_INTF,
  55. SDE_HW_FLUSH_MAX
  56. };
  57. struct sde_hw_ctl;
  58. /**
  59. * struct sde_hw_stage_cfg - blending stage cfg
  60. * @stage : SSPP_ID at each stage
  61. * @multirect_index: index of the rectangle of SSPP.
  62. */
  63. struct sde_hw_stage_cfg {
  64. enum sde_sspp stage[SDE_STAGE_MAX][PIPES_PER_STAGE];
  65. enum sde_sspp_multirect_index multirect_index
  66. [SDE_STAGE_MAX][PIPES_PER_STAGE];
  67. };
  68. /**
  69. * struct sde_hw_intf_cfg :Describes how the SDE writes data to output interface
  70. * @intf : Interface id
  71. * @wb: Writeback id
  72. * @mode_3d: 3d mux configuration
  73. * @intf_mode_sel: Interface mode, cmd / vid
  74. * @stream_sel: Stream selection for multi-stream interfaces
  75. */
  76. struct sde_hw_intf_cfg {
  77. enum sde_intf intf;
  78. enum sde_wb wb;
  79. enum sde_3d_blend_mode mode_3d;
  80. enum sde_ctl_mode_sel intf_mode_sel;
  81. int stream_sel;
  82. };
  83. /**
  84. * struct sde_hw_intf_cfg_v1 :Describes the data strcuture to configure the
  85. * output interfaces for a particular display on a
  86. * platform which supports ctl path version 1.
  87. * @intf_count: No. of active interfaces for this display
  88. * @intf : Interface ids of active interfaces
  89. * @intf_mode_sel: Interface mode, cmd / vid
  90. * @intf_master: Master interface for split display
  91. * @wb_count: No. of active writebacks
  92. * @wb: Writeback ids of active writebacks
  93. * @merge_3d_count No. of active merge_3d blocks
  94. * @merge_3d: Id of the active merge 3d blocks
  95. * @cwb_count: No. of active concurrent writebacks
  96. * @cwb: Id of active cwb blocks
  97. * @cdm_count: No. of active chroma down module
  98. * @cdm: Id of active cdm blocks
  99. * @dsc_count: No. of active dsc blocks
  100. * @dsc: Id of active dsc blocks
  101. * @vdc_count: No. of active vdc blocks
  102. * @vdc: Id of active vdc blocks
  103. * @dnsc_blur_count: No. of active downscale blur blocks
  104. * @dnsc_blur: Id of active downscale blur blocks
  105. */
  106. struct sde_hw_intf_cfg_v1 {
  107. uint32_t intf_count;
  108. enum sde_intf intf[MAX_INTF_PER_CTL_V1];
  109. enum sde_ctl_mode_sel intf_mode_sel;
  110. enum sde_intf intf_master;
  111. uint32_t wb_count;
  112. enum sde_wb wb[MAX_WB_PER_CTL_V1];
  113. uint32_t merge_3d_count;
  114. enum sde_merge_3d merge_3d[MAX_MERGE_3D_PER_CTL_V1];
  115. uint32_t cwb_count;
  116. enum sde_cwb cwb[MAX_CWB_PER_CTL_V1];
  117. uint32_t cdm_count;
  118. enum sde_cdm cdm[MAX_CDM_PER_CTL_V1];
  119. uint32_t dsc_count;
  120. enum sde_dsc dsc[MAX_DSC_PER_CTL_V1];
  121. uint32_t vdc_count;
  122. enum sde_vdc vdc[MAX_VDC_PER_CTL_V1];
  123. uint32_t dnsc_blur_count;
  124. enum sde_dnsc_blur dnsc_blur[MAX_VDC_PER_CTL_V1];
  125. };
  126. /**
  127. * struct sde_ctl_flush_cfg - struct describing flush configuration managed
  128. * via set, trigger and clear ops.
  129. * set ops corresponding to the hw_block is called, when the block's
  130. * configuration is changed and needs to be committed on Hw. Flush mask caches
  131. * the different bits for the ongoing commit.
  132. * clear ops clears the bitmask and cancels the update to the corresponding
  133. * hw block.
  134. * trigger op will trigger the update on the hw for the blocks cached in the
  135. * pending flush mask.
  136. *
  137. * @pending_flush_mask: pending ctl_flush
  138. * CTL path version SDE_CTL_CFG_VERSION_1_0_0 has * two level flush mechanism
  139. * for lower pipe controls. individual control should be flushed before
  140. * exercising top level flush
  141. * @pending_hw_flush_mask: pending flush mask for each active HW blk
  142. * @pending_dspp_flush_masks: pending flush masks for sub-blks of each DSPP
  143. */
  144. struct sde_ctl_flush_cfg {
  145. u32 pending_flush_mask;
  146. u32 pending_hw_flush_mask[SDE_HW_FLUSH_MAX];
  147. u32 pending_dspp_flush_masks[CTL_MAX_DSPP_COUNT];
  148. };
  149. /**
  150. * struct sde_hw_ctl_ops - Interface to the wb Hw driver functions
  151. * Assumption is these functions will be called after clocks are enabled
  152. */
  153. struct sde_hw_ctl_ops {
  154. /**
  155. * kickoff hw operation for Sw controlled interfaces
  156. * DSI cmd mode and WB interface are SW controlled
  157. * @ctx : ctl path ctx pointer
  158. * @Return: error code
  159. */
  160. int (*trigger_start)(struct sde_hw_ctl *ctx);
  161. /**
  162. * kickoff prepare is in progress hw operation for sw
  163. * controlled interfaces: DSI cmd mode and WB interface
  164. * are SW controlled
  165. * @ctx : ctl path ctx pointer
  166. * @Return: error code
  167. */
  168. int (*trigger_pending)(struct sde_hw_ctl *ctx);
  169. /**
  170. * kickoff rotator operation for Sw controlled interfaces
  171. * DSI cmd mode and WB interface are SW controlled
  172. * @ctx : ctl path ctx pointer
  173. * @Return: error code
  174. */
  175. int (*trigger_rot_start)(struct sde_hw_ctl *ctx);
  176. /**
  177. * enable/disable UIDLE feature
  178. * @ctx : ctl path ctx pointer
  179. * @enable: true to enable the feature
  180. */
  181. void (*uidle_enable)(struct sde_hw_ctl *ctx, bool enable);
  182. /**
  183. * Clear the value of the cached pending_flush_mask
  184. * No effect on hardware
  185. * @ctx : ctl path ctx pointer
  186. * @Return: error code
  187. */
  188. int (*clear_pending_flush)(struct sde_hw_ctl *ctx);
  189. /**
  190. * Query the value of the cached pending_flush_mask
  191. * No effect on hardware
  192. * @ctx : ctl path ctx pointer
  193. * @cfg : current flush configuration
  194. * @Return: error code
  195. */
  196. int (*get_pending_flush)(struct sde_hw_ctl *ctx,
  197. struct sde_ctl_flush_cfg *cfg);
  198. /**
  199. * OR in the given flushbits to the flush_cfg
  200. * No effect on hardware
  201. * @ctx : ctl path ctx pointer
  202. * @cfg : flush configuration pointer
  203. * @Return: error code
  204. */
  205. int (*update_pending_flush)(struct sde_hw_ctl *ctx,
  206. struct sde_ctl_flush_cfg *cfg);
  207. /**
  208. * Write the value of the pending_flush_mask to hardware
  209. * @ctx : ctl path ctx pointer
  210. * @Return: error code
  211. */
  212. int (*trigger_flush)(struct sde_hw_ctl *ctx);
  213. /**
  214. * Read the value of the flush register
  215. * @ctx : ctl path ctx pointer
  216. * @Return: value of the ctl flush register.
  217. */
  218. u32 (*get_flush_register)(struct sde_hw_ctl *ctx);
  219. /**
  220. * Setup ctl_path interface config
  221. * @ctx
  222. * @cfg : interface config structure pointer
  223. * @Return: error code
  224. */
  225. int (*setup_intf_cfg)(struct sde_hw_ctl *ctx,
  226. struct sde_hw_intf_cfg *cfg);
  227. /**
  228. * Reset ctl_path interface config
  229. * @ctx : ctl path ctx pointer
  230. * @cfg : interface config structure pointer
  231. * @merge_3d_idx : index of merge3d blk
  232. * @Return: error code
  233. */
  234. int (*reset_post_disable)(struct sde_hw_ctl *ctx,
  235. struct sde_hw_intf_cfg_v1 *cfg, u32 merge_3d_idx);
  236. /** update cwb for ctl_path
  237. * @ctx : ctl path ctx pointer
  238. * @cfg : interface config structure pointer
  239. * @enable : enable/disable the dynamic sub-blocks in interface cfg
  240. * @Return: error code
  241. */
  242. int (*update_intf_cfg)(struct sde_hw_ctl *ctx,
  243. struct sde_hw_intf_cfg_v1 *cfg, bool enable);
  244. /**
  245. * Setup ctl_path interface config for SDE_CTL_ACTIVE_CFG
  246. * @ctx : ctl path ctx pointer
  247. * @cfg : interface config structure pointer
  248. * @Return: error code
  249. */
  250. int (*setup_intf_cfg_v1)(struct sde_hw_ctl *ctx,
  251. struct sde_hw_intf_cfg_v1 *cfg);
  252. /**
  253. * Update the interface selection with input WB config
  254. * @ctx : ctl path ctx pointer
  255. * @cfg : pointer to input wb config
  256. * @enable : set if true, clear otherwise
  257. */
  258. void (*update_wb_cfg)(struct sde_hw_ctl *ctx,
  259. struct sde_hw_intf_cfg *cfg, bool enable);
  260. int (*reset)(struct sde_hw_ctl *c);
  261. /**
  262. * get_reset - check ctl reset status bit
  263. * @ctx : ctl path ctx pointer
  264. * Returns: current value of ctl reset status
  265. */
  266. u32 (*get_reset)(struct sde_hw_ctl *ctx);
  267. /**
  268. * get_scheduler_reset - check ctl scheduler status bit
  269. * @ctx : ctl path ctx pointer
  270. * Returns: current value of ctl scheduler and idle status
  271. */
  272. u32 (*get_scheduler_status)(struct sde_hw_ctl *ctx);
  273. /**
  274. * hard_reset - force reset on ctl_path
  275. * @ctx : ctl path ctx pointer
  276. * @enable : whether to enable/disable hard reset
  277. */
  278. void (*hard_reset)(struct sde_hw_ctl *c, bool enable);
  279. /*
  280. * wait_reset_status - checks ctl reset status
  281. * @ctx : ctl path ctx pointer
  282. *
  283. * This function checks the ctl reset status bit.
  284. * If the reset bit is set, it keeps polling the status till the hw
  285. * reset is complete.
  286. * Returns: 0 on success or -error if reset incomplete within interval
  287. */
  288. int (*wait_reset_status)(struct sde_hw_ctl *ctx);
  289. /**
  290. * update_bitmask_sspp: updates mask corresponding to sspp
  291. * @blk : blk id
  292. * @enable : true to enable, 0 to disable
  293. */
  294. int (*update_bitmask_sspp)(struct sde_hw_ctl *ctx,
  295. enum sde_sspp blk, bool enable);
  296. /**
  297. * update_bitmask_mixer: updates mask corresponding to mixer
  298. * @blk : blk id
  299. * @enable : true to enable, 0 to disable
  300. */
  301. int (*update_bitmask_mixer)(struct sde_hw_ctl *ctx,
  302. enum sde_lm blk, bool enable);
  303. /**
  304. * update_bitmask_dspp: updates mask corresponding to dspp
  305. * @blk : blk id
  306. * @enable : true to enable, 0 to disable
  307. */
  308. int (*update_bitmask_dspp)(struct sde_hw_ctl *ctx,
  309. enum sde_dspp blk, bool enable);
  310. /**
  311. * update_bitmask_dspp_pavlut: updates mask corresponding to dspp pav
  312. * @blk : blk id
  313. * @enable : true to enable, 0 to disable
  314. */
  315. int (*update_bitmask_dspp_pavlut)(struct sde_hw_ctl *ctx,
  316. enum sde_dspp blk, bool enable);
  317. /**
  318. * Program DSPP sub block specific bit of dspp flush register.
  319. * @ctx : ctl path ctx pointer
  320. * @dspp : HW block ID of dspp block
  321. * @sub_blk : enum of DSPP sub block to flush
  322. * @enable : true to enable, 0 to disable
  323. *
  324. * This API is for CTL with DSPP flush hierarchy registers.
  325. */
  326. int (*update_bitmask_dspp_subblk)(struct sde_hw_ctl *ctx,
  327. enum sde_dspp dspp, u32 sub_blk, bool enable);
  328. /**
  329. * update_bitmask_sspp: updates mask corresponding to sspp
  330. * @blk : blk id
  331. * @enable : true to enable, 0 to disable
  332. */
  333. int (*update_bitmask_rot)(struct sde_hw_ctl *ctx,
  334. enum sde_rot blk, bool enable);
  335. /**
  336. * update_bitmask: updates flush mask
  337. * @type : blk type to flush
  338. * @blk_idx : blk idx
  339. * @enable : true to enable, 0 to disable
  340. */
  341. int (*update_bitmask)(struct sde_hw_ctl *ctx,
  342. enum ctl_hw_flush_type type, u32 blk_idx, bool enable);
  343. /**
  344. * update_dnsc_blur_bitmask: updates dnsc_blur flush mask
  345. * @type : blk type to flush
  346. * @blk_idx : blk idx
  347. * @enable : true to enable, 0 to disable
  348. */
  349. void (*update_dnsc_blur_bitmask)(struct sde_hw_ctl *ctx, u32 blk_idx, bool enable);
  350. /**
  351. * get interfaces for the active CTL .
  352. * @ctx : ctl path ctx pointer
  353. * @return : bit mask with the active interfaces for the CTL
  354. */
  355. u32 (*get_ctl_intf)(struct sde_hw_ctl *ctx);
  356. /**
  357. * read CTL layers register value and return
  358. * the data.
  359. * @ctx : ctl path ctx pointer
  360. * @index : layer index for this ctl path
  361. * @return : CTL layers register value
  362. */
  363. u32 (*read_ctl_layers)(struct sde_hw_ctl *ctx, int index);
  364. /**
  365. * read active register configuration for this block
  366. * @ctx : ctl path ctx pointer
  367. * @blk : hw blk type, supported blocks are DSC, MERGE_3D, INTF,
  368. * CDM, WB
  369. * @index : blk index
  370. * @return : true if blk at idx is active or false
  371. */
  372. bool (*read_active_status)(struct sde_hw_ctl *ctx,
  373. enum sde_hw_blk_type blk, int index);
  374. /**
  375. * Set all blend stages to disabled
  376. * @ctx : ctl path ctx pointer
  377. */
  378. void (*clear_all_blendstages)(struct sde_hw_ctl *ctx);
  379. /**
  380. * Configure layer mixer to pipe configuration
  381. * @ctx : ctl path ctx pointer
  382. * @lm : layer mixer enumeration
  383. * @cfg : blend stage configuration
  384. * @disable_border: if true disable border, else enable border out
  385. */
  386. void (*setup_blendstage)(struct sde_hw_ctl *ctx,
  387. enum sde_lm lm, struct sde_hw_stage_cfg *cfg,
  388. bool disable_border);
  389. /**
  390. * Get all the sspp staged on a layer mixer
  391. * @ctx : ctl path ctx pointer
  392. * @lm : layer mixer enumeration
  393. * @info : structure to populate connected sspp index info
  394. * @Return: count of sspps info elements populated
  395. */
  396. u32 (*get_staged_sspp)(struct sde_hw_ctl *ctx, enum sde_lm lm,
  397. struct sde_sspp_index_info *info);
  398. /**
  399. * Flush the reg dma by sending last command.
  400. * @ctx : ctl path ctx pointer
  401. * @blocking : if set to true api will block until flush is done
  402. * @Return: error code
  403. */
  404. int (*reg_dma_flush)(struct sde_hw_ctl *ctx, bool blocking);
  405. /**
  406. * check if ctl start trigger state to confirm the frame pending
  407. * status
  408. * @ctx : ctl path ctx pointer
  409. * @Return: error code
  410. */
  411. int (*get_start_state)(struct sde_hw_ctl *ctx);
  412. /**
  413. * set the active fetch pipes attached to this CTL
  414. * @ctx : ctl path ctx pointer
  415. * @fetch_active: bitmap of enum sde_sspp pipes attached
  416. */
  417. void (*set_active_pipes)(struct sde_hw_ctl *ctx,
  418. unsigned long *fetch_active);
  419. /**
  420. * Get all the sspp marked for fetching on the control path.
  421. * @ctx : ctl path ctx pointer
  422. * @Return: bitmap of enum sde_sspp pipes found
  423. */
  424. u32 (*get_active_pipes)(struct sde_hw_ctl *ctx);
  425. };
  426. /**
  427. * struct sde_hw_ctl : CTL PATH driver object
  428. * @base: hardware block base structure
  429. * @hw: block register map object
  430. * @idx: control path index
  431. * @caps: control path capabilities
  432. * @mixer_count: number of mixers
  433. * @mixer_hw_caps: mixer hardware capabilities
  434. * @flush: storage for pending ctl_flush managed via ops
  435. * @ops: operation list
  436. */
  437. struct sde_hw_ctl {
  438. struct sde_hw_blk_reg_map hw;
  439. /* ctl path */
  440. int idx;
  441. const struct sde_ctl_cfg *caps;
  442. int mixer_count;
  443. const struct sde_lm_cfg *mixer_hw_caps;
  444. struct sde_ctl_flush_cfg flush;
  445. /* ops */
  446. struct sde_hw_ctl_ops ops;
  447. };
  448. /**
  449. * to_sde_hw_ctl - convert base hw object to sde_hw_ctl container
  450. * @hw: Pointer to hardware block register map object
  451. * return: Pointer to hardware block container
  452. */
  453. static inline struct sde_hw_ctl *to_sde_hw_ctl(struct sde_hw_blk_reg_map *hw)
  454. {
  455. return container_of(hw, struct sde_hw_ctl, hw);
  456. }
  457. /**
  458. * sde_hw_ctl_init(): Initializes the ctl_path hw driver object.
  459. * should be called before accessing every ctl path registers.
  460. * @idx: ctl_path index for which driver object is required
  461. * @addr: mapped register io address of MDP
  462. * @m : pointer to mdss catalog data
  463. */
  464. struct sde_hw_blk_reg_map *sde_hw_ctl_init(enum sde_ctl idx,
  465. void __iomem *addr,
  466. struct sde_mdss_cfg *m);
  467. /**
  468. * sde_hw_ctl_destroy(): Destroys ctl driver context
  469. * @hw: Pointer to hardware block register map object
  470. */
  471. void sde_hw_ctl_destroy(struct sde_hw_blk_reg_map *hw);
  472. #endif /*_SDE_HW_CTL_H */