dp_catalog.c 71 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/iopoll.h>
  8. #include "dp_catalog.h"
  9. #include "dp_reg.h"
  10. #include "dp_debug.h"
  11. #include "dp_link.h"
  12. #define DP_GET_MSB(x) (x >> 8)
  13. #define DP_GET_LSB(x) (x & 0xff)
  14. #define DP_PHY_READY BIT(1)
  15. #define dp_catalog_get_priv(x) ({ \
  16. struct dp_catalog *dp_catalog; \
  17. dp_catalog = container_of(x, struct dp_catalog, x); \
  18. container_of(dp_catalog, struct dp_catalog_private, \
  19. dp_catalog); \
  20. })
  21. #define DP_INTERRUPT_STATUS1 \
  22. (DP_INTR_AUX_I2C_DONE| \
  23. DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
  24. DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \
  25. DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \
  26. DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR)
  27. #define DP_INTR_MASK1 (DP_INTERRUPT_STATUS1 << 2)
  28. #define DP_INTERRUPT_STATUS2 \
  29. (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \
  30. DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED)
  31. #define DP_INTR_MASK2 (DP_INTERRUPT_STATUS2 << 2)
  32. #define DP_INTERRUPT_STATUS5 \
  33. (DP_INTR_MST_DP0_VCPF_SENT | DP_INTR_MST_DP1_VCPF_SENT)
  34. #define DP_INTR_MASK5 (DP_INTERRUPT_STATUS5 << 2)
  35. #define dp_catalog_fill_io(x) { \
  36. catalog->io.x = parser->get_io(parser, #x); \
  37. }
  38. #define dp_catalog_fill_io_buf(x) { \
  39. parser->get_io_buf(parser, #x); \
  40. }
  41. #define dp_read(x) ({ \
  42. catalog->read(catalog, io_data, x); \
  43. })
  44. #define dp_write(x, y) ({ \
  45. catalog->write(catalog, io_data, x, y); \
  46. })
  47. static u8 const vm_pre_emphasis[4][4] = {
  48. {0x00, 0x0B, 0x12, 0xFF}, /* pe0, 0 db */
  49. {0x00, 0x0A, 0x12, 0xFF}, /* pe1, 3.5 db */
  50. {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */
  51. {0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
  52. };
  53. /* voltage swing, 0.2v and 1.0v are not support */
  54. static u8 const vm_voltage_swing[4][4] = {
  55. {0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v */
  56. {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */
  57. {0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */
  58. {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */
  59. };
  60. static u8 const vm_pre_emphasis_hbr3_hbr2[4][4] = {
  61. {0x00, 0x0C, 0x15, 0x1A},
  62. {0x02, 0x0E, 0x16, 0xFF},
  63. {0x02, 0x11, 0xFF, 0xFF},
  64. {0x04, 0xFF, 0xFF, 0xFF}
  65. };
  66. static u8 const vm_voltage_swing_hbr3_hbr2[4][4] = {
  67. {0x02, 0x12, 0x16, 0x1A},
  68. {0x09, 0x19, 0x1F, 0xFF},
  69. {0x10, 0x1F, 0xFF, 0xFF},
  70. {0x1F, 0xFF, 0xFF, 0xFF}
  71. };
  72. static u8 const vm_pre_emphasis_hbr_rbr[4][4] = {
  73. {0x00, 0x0C, 0x14, 0x19},
  74. {0x00, 0x0B, 0x12, 0xFF},
  75. {0x00, 0x0B, 0xFF, 0xFF},
  76. {0x04, 0xFF, 0xFF, 0xFF}
  77. };
  78. static u8 const vm_voltage_swing_hbr_rbr[4][4] = {
  79. {0x08, 0x0F, 0x16, 0x1F},
  80. {0x11, 0x1E, 0x1F, 0xFF},
  81. {0x19, 0x1F, 0xFF, 0xFF},
  82. {0x1F, 0xFF, 0xFF, 0xFF}
  83. };
  84. enum dp_flush_bit {
  85. DP_PPS_FLUSH,
  86. DP_DHDR_FLUSH,
  87. };
  88. /* audio related catalog functions */
  89. struct dp_catalog_private {
  90. struct device *dev;
  91. struct dp_catalog_io io;
  92. struct dp_parser *parser;
  93. u32 (*read)(struct dp_catalog_private *catalog,
  94. struct dp_io_data *io_data, u32 offset);
  95. void (*write)(struct dp_catalog_private *catlog,
  96. struct dp_io_data *io_data, u32 offset, u32 data);
  97. u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX];
  98. struct dp_catalog dp_catalog;
  99. char exe_mode[SZ_4];
  100. u32 dp_core_version;
  101. u32 dp_phy_version;
  102. };
  103. static u32 dp_read_sw(struct dp_catalog_private *catalog,
  104. struct dp_io_data *io_data, u32 offset)
  105. {
  106. u32 data = 0;
  107. if (io_data->buf)
  108. memcpy(&data, io_data->buf + offset, sizeof(offset));
  109. return data;
  110. }
  111. static void dp_write_sw(struct dp_catalog_private *catalog,
  112. struct dp_io_data *io_data, u32 offset, u32 data)
  113. {
  114. if (io_data->buf)
  115. memcpy(io_data->buf + offset, &data, sizeof(data));
  116. }
  117. static u32 dp_read_hw(struct dp_catalog_private *catalog,
  118. struct dp_io_data *io_data, u32 offset)
  119. {
  120. u32 data = 0;
  121. data = readl_relaxed(io_data->io.base + offset);
  122. return data;
  123. }
  124. static void dp_write_hw(struct dp_catalog_private *catalog,
  125. struct dp_io_data *io_data, u32 offset, u32 data)
  126. {
  127. writel_relaxed(data, io_data->io.base + offset);
  128. }
  129. static u32 dp_read_sub_sw(struct dp_catalog *dp_catalog,
  130. struct dp_io_data *io_data, u32 offset)
  131. {
  132. struct dp_catalog_private *catalog = container_of(dp_catalog,
  133. struct dp_catalog_private, dp_catalog);
  134. return dp_read_sw(catalog, io_data, offset);
  135. }
  136. static void dp_write_sub_sw(struct dp_catalog *dp_catalog,
  137. struct dp_io_data *io_data, u32 offset, u32 data)
  138. {
  139. struct dp_catalog_private *catalog = container_of(dp_catalog,
  140. struct dp_catalog_private, dp_catalog);
  141. dp_write_sw(catalog, io_data, offset, data);
  142. }
  143. static u32 dp_read_sub_hw(struct dp_catalog *dp_catalog,
  144. struct dp_io_data *io_data, u32 offset)
  145. {
  146. struct dp_catalog_private *catalog = container_of(dp_catalog,
  147. struct dp_catalog_private, dp_catalog);
  148. return dp_read_hw(catalog, io_data, offset);
  149. }
  150. static void dp_write_sub_hw(struct dp_catalog *dp_catalog,
  151. struct dp_io_data *io_data, u32 offset, u32 data)
  152. {
  153. struct dp_catalog_private *catalog = container_of(dp_catalog,
  154. struct dp_catalog_private, dp_catalog);
  155. dp_write_hw(catalog, io_data, offset, data);
  156. }
  157. /* aux related catalog functions */
  158. static u32 dp_catalog_aux_read_data(struct dp_catalog_aux *aux)
  159. {
  160. struct dp_catalog_private *catalog;
  161. struct dp_io_data *io_data;
  162. if (!aux) {
  163. DP_ERR("invalid input\n");
  164. goto end;
  165. }
  166. catalog = dp_catalog_get_priv(aux);
  167. io_data = catalog->io.dp_aux;
  168. return dp_read(DP_AUX_DATA);
  169. end:
  170. return 0;
  171. }
  172. static int dp_catalog_aux_write_data(struct dp_catalog_aux *aux)
  173. {
  174. int rc = 0;
  175. struct dp_catalog_private *catalog;
  176. struct dp_io_data *io_data;
  177. if (!aux) {
  178. DP_ERR("invalid input\n");
  179. rc = -EINVAL;
  180. goto end;
  181. }
  182. catalog = dp_catalog_get_priv(aux);
  183. io_data = catalog->io.dp_aux;
  184. dp_write(DP_AUX_DATA, aux->data);
  185. end:
  186. return rc;
  187. }
  188. static int dp_catalog_aux_write_trans(struct dp_catalog_aux *aux)
  189. {
  190. int rc = 0;
  191. struct dp_catalog_private *catalog;
  192. struct dp_io_data *io_data;
  193. if (!aux) {
  194. DP_ERR("invalid input\n");
  195. rc = -EINVAL;
  196. goto end;
  197. }
  198. catalog = dp_catalog_get_priv(aux);
  199. io_data = catalog->io.dp_aux;
  200. dp_write(DP_AUX_TRANS_CTRL, aux->data);
  201. end:
  202. return rc;
  203. }
  204. static int dp_catalog_aux_clear_trans(struct dp_catalog_aux *aux, bool read)
  205. {
  206. int rc = 0;
  207. u32 data = 0;
  208. struct dp_catalog_private *catalog;
  209. struct dp_io_data *io_data;
  210. if (!aux) {
  211. DP_ERR("invalid input\n");
  212. rc = -EINVAL;
  213. goto end;
  214. }
  215. catalog = dp_catalog_get_priv(aux);
  216. io_data = catalog->io.dp_aux;
  217. if (read) {
  218. data = dp_read(DP_AUX_TRANS_CTRL);
  219. data &= ~BIT(9);
  220. dp_write(DP_AUX_TRANS_CTRL, data);
  221. } else {
  222. dp_write(DP_AUX_TRANS_CTRL, 0);
  223. }
  224. end:
  225. return rc;
  226. }
  227. static void dp_catalog_aux_clear_hw_interrupts(struct dp_catalog_aux *aux)
  228. {
  229. struct dp_catalog_private *catalog;
  230. struct dp_io_data *io_data;
  231. u32 data = 0;
  232. if (!aux) {
  233. DP_ERR("invalid input\n");
  234. return;
  235. }
  236. catalog = dp_catalog_get_priv(aux);
  237. io_data = catalog->io.dp_phy;
  238. data = dp_read(DP_PHY_AUX_INTERRUPT_STATUS);
  239. dp_write(DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f);
  240. wmb(); /* make sure 0x1f is written before next write */
  241. dp_write(DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f);
  242. wmb(); /* make sure 0x9f is written before next write */
  243. dp_write(DP_PHY_AUX_INTERRUPT_CLEAR, 0);
  244. wmb(); /* make sure register is cleared */
  245. }
  246. static void dp_catalog_aux_reset(struct dp_catalog_aux *aux)
  247. {
  248. u32 aux_ctrl;
  249. struct dp_catalog_private *catalog;
  250. struct dp_io_data *io_data;
  251. if (!aux) {
  252. DP_ERR("invalid input\n");
  253. return;
  254. }
  255. catalog = dp_catalog_get_priv(aux);
  256. io_data = catalog->io.dp_aux;
  257. aux_ctrl = dp_read(DP_AUX_CTRL);
  258. aux_ctrl |= BIT(1);
  259. dp_write(DP_AUX_CTRL, aux_ctrl);
  260. usleep_range(1000, 1010); /* h/w recommended delay */
  261. aux_ctrl &= ~BIT(1);
  262. dp_write(DP_AUX_CTRL, aux_ctrl);
  263. wmb(); /* make sure AUX reset is done here */
  264. }
  265. static void dp_catalog_aux_enable(struct dp_catalog_aux *aux, bool enable)
  266. {
  267. u32 aux_ctrl;
  268. struct dp_catalog_private *catalog;
  269. struct dp_io_data *io_data;
  270. if (!aux) {
  271. DP_ERR("invalid input\n");
  272. return;
  273. }
  274. catalog = dp_catalog_get_priv(aux);
  275. io_data = catalog->io.dp_aux;
  276. aux_ctrl = dp_read(DP_AUX_CTRL);
  277. if (enable) {
  278. aux_ctrl |= BIT(0);
  279. dp_write(DP_AUX_CTRL, aux_ctrl);
  280. wmb(); /* make sure AUX module is enabled */
  281. dp_write(DP_TIMEOUT_COUNT, 0xffff);
  282. dp_write(DP_AUX_LIMITS, 0xffff);
  283. } else {
  284. aux_ctrl &= ~BIT(0);
  285. dp_write(DP_AUX_CTRL, aux_ctrl);
  286. }
  287. }
  288. static void dp_catalog_aux_update_cfg(struct dp_catalog_aux *aux,
  289. struct dp_aux_cfg *cfg, enum dp_phy_aux_config_type type)
  290. {
  291. struct dp_catalog_private *catalog;
  292. u32 new_index = 0, current_index = 0;
  293. struct dp_io_data *io_data;
  294. if (!aux || !cfg || (type >= PHY_AUX_CFG_MAX)) {
  295. DP_ERR("invalid input\n");
  296. return;
  297. }
  298. catalog = dp_catalog_get_priv(aux);
  299. io_data = catalog->io.dp_phy;
  300. current_index = cfg[type].current_index;
  301. new_index = (current_index + 1) % cfg[type].cfg_cnt;
  302. DP_DEBUG("Updating %s from 0x%08x to 0x%08x\n",
  303. dp_phy_aux_config_type_to_string(type),
  304. cfg[type].lut[current_index], cfg[type].lut[new_index]);
  305. dp_write(cfg[type].offset, cfg[type].lut[new_index]);
  306. cfg[type].current_index = new_index;
  307. }
  308. static void dp_catalog_aux_setup(struct dp_catalog_aux *aux,
  309. struct dp_aux_cfg *cfg)
  310. {
  311. struct dp_catalog_private *catalog;
  312. struct dp_io_data *io_data;
  313. int i = 0;
  314. if (!aux || !cfg) {
  315. DP_ERR("invalid input\n");
  316. return;
  317. }
  318. catalog = dp_catalog_get_priv(aux);
  319. io_data = catalog->io.dp_phy;
  320. dp_write(DP_PHY_PD_CTL, 0x65);
  321. wmb(); /* make sure PD programming happened */
  322. /* Turn on BIAS current for PHY/PLL */
  323. io_data = catalog->io.dp_pll;
  324. dp_write(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1b);
  325. io_data = catalog->io.dp_phy;
  326. dp_write(DP_PHY_PD_CTL, 0x02);
  327. wmb(); /* make sure PD programming happened */
  328. dp_write(DP_PHY_PD_CTL, 0x7d);
  329. /* Turn on BIAS current for PHY/PLL */
  330. io_data = catalog->io.dp_pll;
  331. dp_write(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f);
  332. /* DP AUX CFG register programming */
  333. io_data = catalog->io.dp_phy;
  334. for (i = 0; i < PHY_AUX_CFG_MAX; i++)
  335. dp_write(cfg[i].offset, cfg[i].lut[cfg[i].current_index]);
  336. dp_write(DP_PHY_AUX_INTERRUPT_MASK, 0x1F);
  337. wmb(); /* make sure AUX configuration is done before enabling it */
  338. }
  339. static void dp_catalog_aux_get_irq(struct dp_catalog_aux *aux, bool cmd_busy)
  340. {
  341. u32 ack;
  342. struct dp_catalog_private *catalog;
  343. struct dp_io_data *io_data;
  344. if (!aux) {
  345. DP_ERR("invalid input\n");
  346. return;
  347. }
  348. catalog = dp_catalog_get_priv(aux);
  349. io_data = catalog->io.dp_ahb;
  350. aux->isr = dp_read(DP_INTR_STATUS);
  351. aux->isr &= ~DP_INTR_MASK1;
  352. ack = aux->isr & DP_INTERRUPT_STATUS1;
  353. ack <<= 1;
  354. ack |= DP_INTR_MASK1;
  355. dp_write(DP_INTR_STATUS, ack);
  356. }
  357. static bool dp_catalog_ctrl_wait_for_phy_ready(
  358. struct dp_catalog_private *catalog)
  359. {
  360. u32 phy_version;
  361. u32 reg, state;
  362. void __iomem *base = catalog->io.dp_phy->io.base;
  363. bool success = true;
  364. u32 const poll_sleep_us = 500;
  365. u32 const pll_timeout_us = 10000;
  366. phy_version = dp_catalog_get_dp_phy_version(&catalog->dp_catalog);
  367. if (phy_version >= 0x60000000) {
  368. reg = DP_PHY_STATUS_V600;
  369. } else {
  370. reg = DP_PHY_STATUS;
  371. }
  372. if (readl_poll_timeout_atomic((base + reg), state,
  373. ((state & DP_PHY_READY) > 0),
  374. poll_sleep_us, pll_timeout_us)) {
  375. DP_ERR("PHY status failed, status=%x\n", state);
  376. success = false;
  377. }
  378. return success;
  379. }
  380. /* controller related catalog functions */
  381. static int dp_catalog_ctrl_late_phy_init(struct dp_catalog_ctrl *ctrl,
  382. u8 lane_cnt, bool flipped)
  383. {
  384. int rc = 0;
  385. u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
  386. struct dp_catalog_private *catalog;
  387. struct dp_io_data *io_data;
  388. if (!ctrl) {
  389. DP_ERR("invalid input\n");
  390. return -EINVAL;
  391. }
  392. catalog = dp_catalog_get_priv(ctrl);
  393. switch (lane_cnt) {
  394. case 1:
  395. drvr0_en = flipped ? 0x13 : 0x10;
  396. bias0_en = flipped ? 0x3E : 0x15;
  397. drvr1_en = flipped ? 0x10 : 0x13;
  398. bias1_en = flipped ? 0x15 : 0x3E;
  399. break;
  400. case 2:
  401. drvr0_en = flipped ? 0x10 : 0x10;
  402. bias0_en = flipped ? 0x3F : 0x15;
  403. drvr1_en = flipped ? 0x10 : 0x10;
  404. bias1_en = flipped ? 0x15 : 0x3F;
  405. break;
  406. case 4:
  407. default:
  408. drvr0_en = 0x10;
  409. bias0_en = 0x3F;
  410. drvr1_en = 0x10;
  411. bias1_en = 0x3F;
  412. break;
  413. }
  414. io_data = catalog->io.dp_ln_tx0;
  415. dp_write(TXn_HIGHZ_DRVR_EN_V420, drvr0_en);
  416. dp_write(TXn_TRANSCEIVER_BIAS_EN_V420, bias0_en);
  417. io_data = catalog->io.dp_ln_tx1;
  418. dp_write(TXn_HIGHZ_DRVR_EN_V420, drvr1_en);
  419. dp_write(TXn_TRANSCEIVER_BIAS_EN_V420, bias1_en);
  420. io_data = catalog->io.dp_phy;
  421. dp_write(DP_PHY_CFG, 0x18);
  422. /* add hardware recommended delay */
  423. udelay(2000);
  424. dp_write(DP_PHY_CFG, 0x19);
  425. /*
  426. * Make sure all the register writes are completed before
  427. * doing any other operation
  428. */
  429. wmb();
  430. if (!dp_catalog_ctrl_wait_for_phy_ready(catalog)) {
  431. rc = -EINVAL;
  432. goto lock_err;
  433. }
  434. io_data = catalog->io.dp_ln_tx0;
  435. dp_write(TXn_TX_POL_INV_V420, 0x0a);
  436. io_data = catalog->io.dp_ln_tx1;
  437. dp_write(TXn_TX_POL_INV_V420, 0x0a);
  438. io_data = catalog->io.dp_ln_tx0;
  439. dp_write(TXn_TX_DRV_LVL_V420, 0x27);
  440. io_data = catalog->io.dp_ln_tx1;
  441. dp_write(TXn_TX_DRV_LVL_V420, 0x27);
  442. io_data = catalog->io.dp_ln_tx0;
  443. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  444. io_data = catalog->io.dp_ln_tx1;
  445. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  446. /* Make sure the PHY register writes are done */
  447. wmb();
  448. lock_err:
  449. return rc;
  450. }
  451. static u32 dp_catalog_ctrl_read_hdcp_status(struct dp_catalog_ctrl *ctrl)
  452. {
  453. struct dp_catalog_private *catalog;
  454. struct dp_io_data *io_data;
  455. if (!ctrl) {
  456. DP_ERR("invalid input\n");
  457. return -EINVAL;
  458. }
  459. catalog = dp_catalog_get_priv(ctrl);
  460. io_data = catalog->io.dp_ahb;
  461. return dp_read(DP_HDCP_STATUS);
  462. }
  463. static void dp_catalog_panel_sdp_update(struct dp_catalog_panel *panel)
  464. {
  465. struct dp_catalog_private *catalog;
  466. struct dp_io_data *io_data;
  467. u32 sdp_cfg3_off = 0;
  468. if (panel->stream_id >= DP_STREAM_MAX) {
  469. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  470. return;
  471. }
  472. if (panel->stream_id == DP_STREAM_1)
  473. sdp_cfg3_off = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3;
  474. catalog = dp_catalog_get_priv(panel);
  475. io_data = catalog->io.dp_link;
  476. dp_write(MMSS_DP_SDP_CFG3 + sdp_cfg3_off, 0x01);
  477. dp_write(MMSS_DP_SDP_CFG3 + sdp_cfg3_off, 0x00);
  478. }
  479. static void dp_catalog_panel_setup_vsif_infoframe_sdp(
  480. struct dp_catalog_panel *panel)
  481. {
  482. struct dp_catalog_private *catalog;
  483. struct drm_msm_ext_hdr_metadata *hdr;
  484. struct dp_io_data *io_data;
  485. u32 header, parity, data, mst_offset = 0;
  486. u8 buf[SZ_64], off = 0;
  487. if (panel->stream_id >= DP_STREAM_MAX) {
  488. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  489. return;
  490. }
  491. if (panel->stream_id == DP_STREAM_1)
  492. mst_offset = MMSS_DP1_VSCEXT_0 - MMSS_DP_VSCEXT_0;
  493. catalog = dp_catalog_get_priv(panel);
  494. hdr = &panel->hdr_meta;
  495. io_data = catalog->io.dp_link;
  496. /* HEADER BYTE 1 */
  497. header = panel->dhdr_vsif_sdp.HB1;
  498. parity = dp_header_get_parity(header);
  499. data = ((header << HEADER_BYTE_1_BIT)
  500. | (parity << PARITY_BYTE_1_BIT));
  501. dp_write(MMSS_DP_VSCEXT_0 + mst_offset, data);
  502. memcpy(buf + off, &data, sizeof(data));
  503. off += sizeof(data);
  504. /* HEADER BYTE 2 */
  505. header = panel->dhdr_vsif_sdp.HB2;
  506. parity = dp_header_get_parity(header);
  507. data = ((header << HEADER_BYTE_2_BIT)
  508. | (parity << PARITY_BYTE_2_BIT));
  509. dp_write(MMSS_DP_VSCEXT_1 + mst_offset, data);
  510. /* HEADER BYTE 3 */
  511. header = panel->dhdr_vsif_sdp.HB3;
  512. parity = dp_header_get_parity(header);
  513. data = ((header << HEADER_BYTE_3_BIT)
  514. | (parity << PARITY_BYTE_3_BIT));
  515. data |= dp_read(MMSS_DP_VSCEXT_1 + mst_offset);
  516. dp_write(MMSS_DP_VSCEXT_1 + mst_offset, data);
  517. memcpy(buf + off, &data, sizeof(data));
  518. off += sizeof(data);
  519. print_hex_dump_debug("[drm-dp] VSCEXT: ",
  520. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  521. }
  522. static void dp_catalog_panel_setup_hdr_infoframe_sdp(
  523. struct dp_catalog_panel *panel)
  524. {
  525. struct dp_catalog_private *catalog;
  526. struct drm_msm_ext_hdr_metadata *hdr;
  527. struct dp_io_data *io_data;
  528. u32 header, parity, data, mst_offset = 0;
  529. u8 buf[SZ_64], off = 0;
  530. u32 const version = 0x01;
  531. u32 const length = 0x1a;
  532. if (panel->stream_id >= DP_STREAM_MAX) {
  533. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  534. return;
  535. }
  536. if (panel->stream_id == DP_STREAM_1)
  537. mst_offset = MMSS_DP1_GENERIC2_0 - MMSS_DP_GENERIC2_0;
  538. catalog = dp_catalog_get_priv(panel);
  539. hdr = &panel->hdr_meta;
  540. io_data = catalog->io.dp_link;
  541. /* HEADER BYTE 1 */
  542. header = panel->shdr_if_sdp.HB1;
  543. parity = dp_header_get_parity(header);
  544. data = ((header << HEADER_BYTE_1_BIT)
  545. | (parity << PARITY_BYTE_1_BIT));
  546. dp_write(MMSS_DP_GENERIC2_0 + mst_offset,
  547. data);
  548. memcpy(buf + off, &data, sizeof(data));
  549. off += sizeof(data);
  550. /* HEADER BYTE 2 */
  551. header = panel->shdr_if_sdp.HB2;
  552. parity = dp_header_get_parity(header);
  553. data = ((header << HEADER_BYTE_2_BIT)
  554. | (parity << PARITY_BYTE_2_BIT));
  555. dp_write(MMSS_DP_GENERIC2_1 + mst_offset, data);
  556. /* HEADER BYTE 3 */
  557. header = panel->shdr_if_sdp.HB3;
  558. parity = dp_header_get_parity(header);
  559. data = ((header << HEADER_BYTE_3_BIT)
  560. | (parity << PARITY_BYTE_3_BIT));
  561. data |= dp_read(MMSS_DP_VSCEXT_1 + mst_offset);
  562. dp_write(MMSS_DP_GENERIC2_1 + mst_offset,
  563. data);
  564. memcpy(buf + off, &data, sizeof(data));
  565. off += sizeof(data);
  566. data = version;
  567. data |= length << 8;
  568. data |= hdr->eotf << 16;
  569. dp_write(MMSS_DP_GENERIC2_2 + mst_offset, data);
  570. memcpy(buf + off, &data, sizeof(data));
  571. off += sizeof(data);
  572. data = (DP_GET_LSB(hdr->display_primaries_x[0]) |
  573. (DP_GET_MSB(hdr->display_primaries_x[0]) << 8) |
  574. (DP_GET_LSB(hdr->display_primaries_y[0]) << 16) |
  575. (DP_GET_MSB(hdr->display_primaries_y[0]) << 24));
  576. dp_write(MMSS_DP_GENERIC2_3 + mst_offset, data);
  577. memcpy(buf + off, &data, sizeof(data));
  578. off += sizeof(data);
  579. data = (DP_GET_LSB(hdr->display_primaries_x[1]) |
  580. (DP_GET_MSB(hdr->display_primaries_x[1]) << 8) |
  581. (DP_GET_LSB(hdr->display_primaries_y[1]) << 16) |
  582. (DP_GET_MSB(hdr->display_primaries_y[1]) << 24));
  583. dp_write(MMSS_DP_GENERIC2_4 + mst_offset, data);
  584. memcpy(buf + off, &data, sizeof(data));
  585. off += sizeof(data);
  586. data = (DP_GET_LSB(hdr->display_primaries_x[2]) |
  587. (DP_GET_MSB(hdr->display_primaries_x[2]) << 8) |
  588. (DP_GET_LSB(hdr->display_primaries_y[2]) << 16) |
  589. (DP_GET_MSB(hdr->display_primaries_y[2]) << 24));
  590. dp_write(MMSS_DP_GENERIC2_5 + mst_offset, data);
  591. memcpy(buf + off, &data, sizeof(data));
  592. off += sizeof(data);
  593. data = (DP_GET_LSB(hdr->white_point_x) |
  594. (DP_GET_MSB(hdr->white_point_x) << 8) |
  595. (DP_GET_LSB(hdr->white_point_y) << 16) |
  596. (DP_GET_MSB(hdr->white_point_y) << 24));
  597. dp_write(MMSS_DP_GENERIC2_6 + mst_offset, data);
  598. memcpy(buf + off, &data, sizeof(data));
  599. off += sizeof(data);
  600. data = (DP_GET_LSB(hdr->max_luminance) |
  601. (DP_GET_MSB(hdr->max_luminance) << 8) |
  602. (DP_GET_LSB(hdr->min_luminance) << 16) |
  603. (DP_GET_MSB(hdr->min_luminance) << 24));
  604. dp_write(MMSS_DP_GENERIC2_7 + mst_offset, data);
  605. memcpy(buf + off, &data, sizeof(data));
  606. off += sizeof(data);
  607. data = (DP_GET_LSB(hdr->max_content_light_level) |
  608. (DP_GET_MSB(hdr->max_content_light_level) << 8) |
  609. (DP_GET_LSB(hdr->max_average_light_level) << 16) |
  610. (DP_GET_MSB(hdr->max_average_light_level) << 24));
  611. dp_write(MMSS_DP_GENERIC2_8 + mst_offset, data);
  612. memcpy(buf + off, &data, sizeof(data));
  613. off += sizeof(data);
  614. data = 0;
  615. dp_write(MMSS_DP_GENERIC2_9 + mst_offset, data);
  616. memcpy(buf + off, &data, sizeof(data));
  617. off += sizeof(data);
  618. print_hex_dump_debug("[drm-dp] HDR: ",
  619. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  620. }
  621. static void dp_catalog_panel_setup_vsc_sdp(struct dp_catalog_panel *panel)
  622. {
  623. struct dp_catalog_private *catalog;
  624. struct dp_io_data *io_data;
  625. u32 header, parity, data, mst_offset = 0;
  626. u8 off = 0;
  627. u8 buf[SZ_128];
  628. if (!panel) {
  629. DP_ERR("invalid input\n");
  630. return;
  631. }
  632. if (panel->stream_id >= DP_STREAM_MAX) {
  633. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  634. return;
  635. }
  636. if (panel->stream_id == DP_STREAM_1)
  637. mst_offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  638. catalog = dp_catalog_get_priv(panel);
  639. io_data = catalog->io.dp_link;
  640. /* HEADER BYTE 1 */
  641. header = panel->vsc_colorimetry.header.HB1;
  642. parity = dp_header_get_parity(header);
  643. data = ((header << HEADER_BYTE_1_BIT)
  644. | (parity << PARITY_BYTE_1_BIT));
  645. dp_write(MMSS_DP_GENERIC0_0 + mst_offset, data);
  646. memcpy(buf + off, &data, sizeof(data));
  647. off += sizeof(data);
  648. /* HEADER BYTE 2 */
  649. header = panel->vsc_colorimetry.header.HB2;
  650. parity = dp_header_get_parity(header);
  651. data = ((header << HEADER_BYTE_2_BIT)
  652. | (parity << PARITY_BYTE_2_BIT));
  653. dp_write(MMSS_DP_GENERIC0_1 + mst_offset, data);
  654. /* HEADER BYTE 3 */
  655. header = panel->vsc_colorimetry.header.HB3;
  656. parity = dp_header_get_parity(header);
  657. data = ((header << HEADER_BYTE_3_BIT)
  658. | (parity << PARITY_BYTE_3_BIT));
  659. data |= dp_read(MMSS_DP_GENERIC0_1 + mst_offset);
  660. dp_write(MMSS_DP_GENERIC0_1 + mst_offset, data);
  661. memcpy(buf + off, &data, sizeof(data));
  662. off += sizeof(data);
  663. data = 0;
  664. dp_write(MMSS_DP_GENERIC0_2 + mst_offset, data);
  665. memcpy(buf + off, &data, sizeof(data));
  666. off += sizeof(data);
  667. dp_write(MMSS_DP_GENERIC0_3 + mst_offset, data);
  668. memcpy(buf + off, &data, sizeof(data));
  669. off += sizeof(data);
  670. dp_write(MMSS_DP_GENERIC0_4 + mst_offset, data);
  671. memcpy(buf + off, &data, sizeof(data));
  672. off += sizeof(data);
  673. dp_write(MMSS_DP_GENERIC0_5 + mst_offset, data);
  674. memcpy(buf + off, &data, sizeof(data));
  675. off += sizeof(data);
  676. data = (panel->vsc_colorimetry.data[16] & 0xFF) |
  677. ((panel->vsc_colorimetry.data[17] & 0xFF) << 8) |
  678. ((panel->vsc_colorimetry.data[18] & 0x7) << 16);
  679. dp_write(MMSS_DP_GENERIC0_6 + mst_offset, data);
  680. memcpy(buf + off, &data, sizeof(data));
  681. off += sizeof(data);
  682. data = 0;
  683. dp_write(MMSS_DP_GENERIC0_7 + mst_offset, data);
  684. memcpy(buf + off, &data, sizeof(data));
  685. off += sizeof(data);
  686. dp_write(MMSS_DP_GENERIC0_8 + mst_offset, data);
  687. memcpy(buf + off, &data, sizeof(data));
  688. off += sizeof(data);
  689. dp_write(MMSS_DP_GENERIC0_9 + mst_offset, data);
  690. memcpy(buf + off, &data, sizeof(data));
  691. off += sizeof(data);
  692. print_hex_dump_debug("[drm-dp] VSC: ",
  693. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  694. }
  695. static void dp_catalog_panel_config_sdp(struct dp_catalog_panel *panel,
  696. bool en)
  697. {
  698. struct dp_catalog_private *catalog;
  699. struct dp_io_data *io_data;
  700. u32 cfg, cfg2;
  701. u32 sdp_cfg_off = 0;
  702. u32 sdp_cfg2_off = 0;
  703. if (panel->stream_id >= DP_STREAM_MAX) {
  704. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  705. return;
  706. }
  707. catalog = dp_catalog_get_priv(panel);
  708. io_data = catalog->io.dp_link;
  709. if (panel->stream_id == DP_STREAM_1) {
  710. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  711. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  712. }
  713. cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  714. cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  715. if (en) {
  716. /* GEN0_SDP_EN */
  717. cfg |= BIT(17);
  718. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  719. /* GENERIC0_SDPSIZE */
  720. cfg2 |= BIT(16);
  721. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  722. /* setup the GENERIC0 in case of en = true */
  723. dp_catalog_panel_setup_vsc_sdp(panel);
  724. } else {
  725. /* GEN0_SDP_EN */
  726. cfg &= ~BIT(17);
  727. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  728. /* GENERIC0_SDPSIZE */
  729. cfg2 &= ~BIT(16);
  730. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  731. }
  732. dp_catalog_panel_sdp_update(panel);
  733. }
  734. static void dp_catalog_panel_config_misc(struct dp_catalog_panel *panel)
  735. {
  736. struct dp_catalog_private *catalog;
  737. struct dp_io_data *io_data;
  738. u32 reg_offset = 0;
  739. if (!panel) {
  740. DP_ERR("invalid input\n");
  741. return;
  742. }
  743. if (panel->stream_id >= DP_STREAM_MAX) {
  744. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  745. return;
  746. }
  747. catalog = dp_catalog_get_priv(panel);
  748. io_data = catalog->io.dp_link;
  749. if (panel->stream_id == DP_STREAM_1)
  750. reg_offset = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  751. DP_DEBUG("misc settings = 0x%x\n", panel->misc_val);
  752. dp_write(DP_MISC1_MISC0 + reg_offset, panel->misc_val);
  753. }
  754. static int dp_catalog_panel_set_colorspace(struct dp_catalog_panel *panel,
  755. bool vsc_supported)
  756. {
  757. struct dp_catalog_private *catalog;
  758. struct dp_io_data *io_data;
  759. if (!panel) {
  760. DP_ERR("invalid input\n");
  761. return -EINVAL;
  762. }
  763. if (panel->stream_id >= DP_STREAM_MAX) {
  764. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  765. return -EINVAL;
  766. }
  767. catalog = dp_catalog_get_priv(panel);
  768. io_data = catalog->io.dp_link;
  769. if (vsc_supported) {
  770. dp_catalog_panel_setup_vsc_sdp(panel);
  771. dp_catalog_panel_sdp_update(panel);
  772. } else
  773. dp_catalog_panel_config_misc(panel);
  774. return 0;
  775. }
  776. static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en,
  777. u32 dhdr_max_pkts, bool flush)
  778. {
  779. struct dp_catalog_private *catalog;
  780. struct dp_io_data *io_data;
  781. u32 cfg, cfg2, cfg4, misc;
  782. u32 sdp_cfg_off = 0;
  783. u32 sdp_cfg2_off = 0;
  784. u32 sdp_cfg4_off = 0;
  785. u32 misc1_misc0_off = 0;
  786. if (!panel) {
  787. DP_ERR("invalid input\n");
  788. return;
  789. }
  790. if (panel->stream_id >= DP_STREAM_MAX) {
  791. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  792. return;
  793. }
  794. catalog = dp_catalog_get_priv(panel);
  795. io_data = catalog->io.dp_link;
  796. if (panel->stream_id == DP_STREAM_1) {
  797. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  798. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  799. sdp_cfg4_off = MMSS_DP1_SDP_CFG4 - MMSS_DP_SDP_CFG4;
  800. misc1_misc0_off = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  801. }
  802. cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  803. cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  804. misc = dp_read(DP_MISC1_MISC0 + misc1_misc0_off);
  805. if (en) {
  806. if (dhdr_max_pkts) {
  807. /* VSCEXT_SDP_EN */
  808. cfg |= BIT(16);
  809. /* DHDR_EN, DHDR_PACKET_LIMIT */
  810. cfg4 = (dhdr_max_pkts << 1) | BIT(0);
  811. dp_write(MMSS_DP_SDP_CFG4 + sdp_cfg4_off, cfg4);
  812. dp_catalog_panel_setup_vsif_infoframe_sdp(panel);
  813. }
  814. /* GEN2_SDP_EN */
  815. cfg |= BIT(19);
  816. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  817. /* GENERIC2_SDPSIZE */
  818. cfg2 |= BIT(20);
  819. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  820. dp_catalog_panel_setup_hdr_infoframe_sdp(panel);
  821. if (panel->hdr_meta.eotf)
  822. DP_DEBUG("Enabled\n");
  823. else
  824. DP_DEBUG("Reset\n");
  825. } else {
  826. /* VSCEXT_SDP_ENG */
  827. cfg &= ~BIT(16) & ~BIT(19);
  828. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  829. /* GENERIC0_SDPSIZE GENERIC2_SDPSIZE */
  830. cfg2 &= ~BIT(20);
  831. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  832. /* DHDR_EN, DHDR_PACKET_LIMIT */
  833. cfg4 = 0;
  834. dp_write(MMSS_DP_SDP_CFG4 + sdp_cfg4_off, cfg4);
  835. DP_DEBUG("Disabled\n");
  836. }
  837. if (flush) {
  838. DP_DEBUG("flushing HDR metadata\n");
  839. dp_catalog_panel_sdp_update(panel);
  840. }
  841. }
  842. static void dp_catalog_panel_update_transfer_unit(
  843. struct dp_catalog_panel *panel)
  844. {
  845. struct dp_catalog_private *catalog;
  846. struct dp_io_data *io_data;
  847. if (!panel || panel->stream_id >= DP_STREAM_MAX) {
  848. DP_ERR("invalid input\n");
  849. return;
  850. }
  851. catalog = dp_catalog_get_priv(panel);
  852. io_data = catalog->io.dp_link;
  853. dp_write(DP_VALID_BOUNDARY, panel->valid_boundary);
  854. dp_write(DP_TU, panel->dp_tu);
  855. dp_write(DP_VALID_BOUNDARY_2, panel->valid_boundary2);
  856. }
  857. static void dp_catalog_ctrl_state_ctrl(struct dp_catalog_ctrl *ctrl, u32 state)
  858. {
  859. struct dp_catalog_private *catalog;
  860. struct dp_io_data *io_data;
  861. if (!ctrl) {
  862. DP_ERR("invalid input\n");
  863. return;
  864. }
  865. catalog = dp_catalog_get_priv(ctrl);
  866. io_data = catalog->io.dp_link;
  867. dp_write(DP_STATE_CTRL, state);
  868. /* make sure to change the hw state */
  869. wmb();
  870. }
  871. static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u8 ln_cnt)
  872. {
  873. struct dp_catalog_private *catalog;
  874. struct dp_io_data *io_data;
  875. u32 cfg;
  876. if (!ctrl) {
  877. DP_ERR("invalid input\n");
  878. return;
  879. }
  880. catalog = dp_catalog_get_priv(ctrl);
  881. io_data = catalog->io.dp_link;
  882. cfg = dp_read(DP_CONFIGURATION_CTRL);
  883. /*
  884. * Reset ASSR (alternate scrambler seed reset) by resetting BIT(10).
  885. * ASSR should be set to disable for TPS4 link training pattern.
  886. * Forcing it to 0 as the power on reset value of register enables it.
  887. */
  888. cfg &= ~(BIT(4) | BIT(5) | BIT(10));
  889. cfg |= (ln_cnt - 1) << 4;
  890. dp_write(DP_CONFIGURATION_CTRL, cfg);
  891. cfg = dp_read(DP_MAINLINK_CTRL);
  892. cfg |= 0x02000000;
  893. dp_write(DP_MAINLINK_CTRL, cfg);
  894. DP_DEBUG("DP_MAINLINK_CTRL=0x%x\n", cfg);
  895. }
  896. static void dp_catalog_panel_config_ctrl(struct dp_catalog_panel *panel,
  897. u32 cfg)
  898. {
  899. struct dp_catalog_private *catalog;
  900. struct dp_io_data *io_data;
  901. u32 strm_reg_off = 0, mainlink_ctrl;
  902. if (!panel) {
  903. DP_ERR("invalid input\n");
  904. return;
  905. }
  906. if (panel->stream_id >= DP_STREAM_MAX) {
  907. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  908. return;
  909. }
  910. catalog = dp_catalog_get_priv(panel);
  911. io_data = catalog->io.dp_link;
  912. if (panel->stream_id == DP_STREAM_1)
  913. strm_reg_off = DP1_CONFIGURATION_CTRL - DP_CONFIGURATION_CTRL;
  914. DP_DEBUG("DP_CONFIGURATION_CTRL=0x%x\n", cfg);
  915. dp_write(DP_CONFIGURATION_CTRL + strm_reg_off, cfg);
  916. mainlink_ctrl = dp_read(DP_MAINLINK_CTRL);
  917. if (panel->stream_id == DP_STREAM_0)
  918. io_data = catalog->io.dp_p0;
  919. else if (panel->stream_id == DP_STREAM_1)
  920. io_data = catalog->io.dp_p1;
  921. if (mainlink_ctrl & BIT(8))
  922. dp_write(MMSS_DP_ASYNC_FIFO_CONFIG, 0x01);
  923. else
  924. dp_write(MMSS_DP_ASYNC_FIFO_CONFIG, 0x00);
  925. }
  926. static void dp_catalog_panel_config_dto(struct dp_catalog_panel *panel,
  927. bool ack)
  928. {
  929. struct dp_catalog_private *catalog;
  930. struct dp_io_data *io_data;
  931. u32 dsc_dto;
  932. if (!panel) {
  933. DP_ERR("invalid input\n");
  934. return;
  935. }
  936. if (panel->stream_id >= DP_STREAM_MAX) {
  937. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  938. return;
  939. }
  940. catalog = dp_catalog_get_priv(panel);
  941. io_data = catalog->io.dp_link;
  942. switch (panel->stream_id) {
  943. case DP_STREAM_0:
  944. io_data = catalog->io.dp_p0;
  945. break;
  946. case DP_STREAM_1:
  947. io_data = catalog->io.dp_p1;
  948. break;
  949. default:
  950. DP_ERR("invalid stream id\n");
  951. return;
  952. }
  953. dsc_dto = dp_read(MMSS_DP_DSC_DTO);
  954. if (ack)
  955. dsc_dto = BIT(1);
  956. else
  957. dsc_dto &= ~BIT(1);
  958. dp_write(MMSS_DP_DSC_DTO, dsc_dto);
  959. }
  960. static void dp_catalog_ctrl_lane_mapping(struct dp_catalog_ctrl *ctrl,
  961. bool flipped, char *lane_map)
  962. {
  963. struct dp_catalog_private *catalog;
  964. struct dp_io_data *io_data;
  965. if (!ctrl) {
  966. DP_ERR("invalid input\n");
  967. return;
  968. }
  969. catalog = dp_catalog_get_priv(ctrl);
  970. io_data = catalog->io.dp_link;
  971. dp_write(DP_LOGICAL2PHYSICAL_LANE_MAPPING, 0xe4);
  972. }
  973. static void dp_catalog_ctrl_lane_pnswap(struct dp_catalog_ctrl *ctrl,
  974. u8 ln_pnswap)
  975. {
  976. struct dp_catalog_private *catalog;
  977. struct dp_io_data *io_data;
  978. u32 cfg0, cfg1;
  979. catalog = dp_catalog_get_priv(ctrl);
  980. cfg0 = 0x0a;
  981. cfg1 = 0x0a;
  982. cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0;
  983. cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2;
  984. cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0;
  985. cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2;
  986. io_data = catalog->io.dp_ln_tx0;
  987. dp_write(TXn_TX_POL_INV, cfg0);
  988. io_data = catalog->io.dp_ln_tx1;
  989. dp_write(TXn_TX_POL_INV, cfg1);
  990. }
  991. static void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog_ctrl *ctrl,
  992. bool enable)
  993. {
  994. u32 mainlink_ctrl, reg;
  995. struct dp_catalog_private *catalog;
  996. struct dp_io_data *io_data;
  997. if (!ctrl) {
  998. DP_ERR("invalid input\n");
  999. return;
  1000. }
  1001. catalog = dp_catalog_get_priv(ctrl);
  1002. io_data = catalog->io.dp_link;
  1003. if (enable) {
  1004. reg = dp_read(DP_MAINLINK_CTRL);
  1005. mainlink_ctrl = reg & ~(0x03);
  1006. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  1007. wmb(); /* make sure mainlink is turned off before reset */
  1008. mainlink_ctrl = reg | 0x02;
  1009. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  1010. wmb(); /* make sure mainlink entered reset */
  1011. mainlink_ctrl = reg & ~(0x03);
  1012. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  1013. wmb(); /* make sure mainlink reset done */
  1014. mainlink_ctrl = reg | 0x01;
  1015. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  1016. wmb(); /* make sure mainlink turned on */
  1017. } else {
  1018. mainlink_ctrl = dp_read(DP_MAINLINK_CTRL);
  1019. mainlink_ctrl &= ~BIT(0);
  1020. dp_write(DP_MAINLINK_CTRL, mainlink_ctrl);
  1021. }
  1022. }
  1023. static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel,
  1024. u32 rate, u32 stream_rate_khz)
  1025. {
  1026. u32 pixel_m, pixel_n;
  1027. u32 mvid, nvid;
  1028. u32 const nvid_fixed = 0x8000;
  1029. u32 const link_rate_hbr2 = 540000;
  1030. u32 const link_rate_hbr3 = 810000;
  1031. struct dp_catalog_private *catalog;
  1032. struct dp_io_data *io_data;
  1033. u32 strm_reg_off = 0;
  1034. u32 mvid_reg_off = 0, nvid_reg_off = 0;
  1035. if (!panel) {
  1036. DP_ERR("invalid input\n");
  1037. return;
  1038. }
  1039. if (panel->stream_id >= DP_STREAM_MAX) {
  1040. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1041. return;
  1042. }
  1043. catalog = dp_catalog_get_priv(panel);
  1044. io_data = catalog->io.dp_mmss_cc;
  1045. if (panel->stream_id == DP_STREAM_1)
  1046. strm_reg_off = MMSS_DP_PIXEL1_M - MMSS_DP_PIXEL_M;
  1047. pixel_m = dp_read(MMSS_DP_PIXEL_M + strm_reg_off);
  1048. pixel_n = dp_read(MMSS_DP_PIXEL_N + strm_reg_off);
  1049. DP_DEBUG("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n);
  1050. mvid = (pixel_m & 0xFFFF) * 5;
  1051. nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);
  1052. if (nvid < nvid_fixed) {
  1053. u32 temp;
  1054. temp = (nvid_fixed / nvid) * nvid;
  1055. mvid = (nvid_fixed / nvid) * mvid;
  1056. nvid = temp;
  1057. }
  1058. DP_DEBUG("rate = %d\n", rate);
  1059. if (panel->widebus_en)
  1060. mvid <<= 1;
  1061. if (link_rate_hbr2 == rate)
  1062. nvid *= 2;
  1063. if (link_rate_hbr3 == rate)
  1064. nvid *= 3;
  1065. io_data = catalog->io.dp_link;
  1066. if (panel->stream_id == DP_STREAM_1) {
  1067. mvid_reg_off = DP1_SOFTWARE_MVID - DP_SOFTWARE_MVID;
  1068. nvid_reg_off = DP1_SOFTWARE_NVID - DP_SOFTWARE_NVID;
  1069. }
  1070. DP_DEBUG("mvid=0x%x, nvid=0x%x\n", mvid, nvid);
  1071. dp_write(DP_SOFTWARE_MVID + mvid_reg_off, mvid);
  1072. dp_write(DP_SOFTWARE_NVID + nvid_reg_off, nvid);
  1073. }
  1074. static void dp_catalog_ctrl_set_pattern(struct dp_catalog_ctrl *ctrl,
  1075. u32 pattern)
  1076. {
  1077. int bit, cnt = 10;
  1078. u32 data;
  1079. const u32 link_training_offset = 3;
  1080. struct dp_catalog_private *catalog;
  1081. struct dp_io_data *io_data;
  1082. if (!ctrl) {
  1083. DP_ERR("invalid input\n");
  1084. return;
  1085. }
  1086. catalog = dp_catalog_get_priv(ctrl);
  1087. io_data = catalog->io.dp_link;
  1088. switch (pattern) {
  1089. case DP_TRAINING_PATTERN_4:
  1090. bit = 3;
  1091. break;
  1092. case DP_TRAINING_PATTERN_3:
  1093. case DP_TRAINING_PATTERN_2:
  1094. case DP_TRAINING_PATTERN_1:
  1095. bit = pattern - 1;
  1096. break;
  1097. default:
  1098. DP_ERR("invalid pattern\n");
  1099. return;
  1100. }
  1101. DP_DEBUG("hw: bit=%d train=%d\n", bit, pattern);
  1102. dp_write(DP_STATE_CTRL, BIT(bit));
  1103. bit += link_training_offset;
  1104. while (cnt--) {
  1105. data = dp_read(DP_MAINLINK_READY);
  1106. if (data & BIT(bit))
  1107. break;
  1108. }
  1109. if (cnt == 0)
  1110. DP_ERR("set link_train=%d failed\n", pattern);
  1111. }
  1112. static void dp_catalog_ctrl_usb_reset(struct dp_catalog_ctrl *ctrl, bool flip)
  1113. {
  1114. struct dp_catalog_private *catalog;
  1115. struct dp_io_data *io_data;
  1116. if (!ctrl) {
  1117. DP_ERR("invalid input\n");
  1118. return;
  1119. }
  1120. catalog = dp_catalog_get_priv(ctrl);
  1121. io_data = catalog->io.usb3_dp_com;
  1122. DP_DEBUG("Program PHYMODE to DP only\n");
  1123. dp_write(USB3_DP_COM_RESET_OVRD_CTRL, 0x0a);
  1124. dp_write(USB3_DP_COM_PHY_MODE_CTRL, 0x02);
  1125. dp_write(USB3_DP_COM_SW_RESET, 0x01);
  1126. /* make sure usb3 com phy software reset is done */
  1127. wmb();
  1128. if (!flip) /* CC1 */
  1129. dp_write(USB3_DP_COM_TYPEC_CTRL, 0x02);
  1130. else /* CC2 */
  1131. dp_write(USB3_DP_COM_TYPEC_CTRL, 0x03);
  1132. dp_write(USB3_DP_COM_SWI_CTRL, 0x00);
  1133. dp_write(USB3_DP_COM_SW_RESET, 0x00);
  1134. /* make sure the software reset is done */
  1135. wmb();
  1136. dp_write(USB3_DP_COM_POWER_DOWN_CTRL, 0x01);
  1137. dp_write(USB3_DP_COM_RESET_OVRD_CTRL, 0x00);
  1138. /* make sure phy is brought out of reset */
  1139. wmb();
  1140. }
  1141. static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel,
  1142. bool enable)
  1143. {
  1144. struct dp_catalog_private *catalog;
  1145. struct dp_io_data *io_data;
  1146. u32 reg;
  1147. if (!panel) {
  1148. DP_ERR("invalid input\n");
  1149. return;
  1150. }
  1151. if (panel->stream_id >= DP_STREAM_MAX) {
  1152. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1153. return;
  1154. }
  1155. catalog = dp_catalog_get_priv(panel);
  1156. if (panel->stream_id == DP_STREAM_0)
  1157. io_data = catalog->io.dp_p0;
  1158. else if (panel->stream_id == DP_STREAM_1)
  1159. io_data = catalog->io.dp_p1;
  1160. if (!enable) {
  1161. dp_write(MMSS_DP_TPG_MAIN_CONTROL, 0x0);
  1162. dp_write(MMSS_DP_BIST_ENABLE, 0x0);
  1163. reg = dp_read(MMSS_DP_TIMING_ENGINE_EN);
  1164. reg &= ~0x1;
  1165. dp_write(MMSS_DP_TIMING_ENGINE_EN, reg);
  1166. wmb(); /* ensure Timing generator is turned off */
  1167. return;
  1168. }
  1169. dp_write(MMSS_DP_INTF_HSYNC_CTL,
  1170. panel->hsync_ctl);
  1171. dp_write(MMSS_DP_INTF_VSYNC_PERIOD_F0,
  1172. panel->vsync_period * panel->hsync_period);
  1173. dp_write(MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0,
  1174. panel->v_sync_width * panel->hsync_period);
  1175. dp_write(MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);
  1176. dp_write(MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0);
  1177. dp_write(MMSS_DP_INTF_DISPLAY_HCTL, panel->display_hctl);
  1178. dp_write(MMSS_DP_INTF_ACTIVE_HCTL, 0);
  1179. dp_write(MMSS_INTF_DISPLAY_V_START_F0, panel->display_v_start);
  1180. dp_write(MMSS_DP_INTF_DISPLAY_V_END_F0, panel->display_v_end);
  1181. dp_write(MMSS_INTF_DISPLAY_V_START_F1, 0);
  1182. dp_write(MMSS_DP_INTF_DISPLAY_V_END_F1, 0);
  1183. dp_write(MMSS_DP_INTF_ACTIVE_V_START_F0, 0);
  1184. dp_write(MMSS_DP_INTF_ACTIVE_V_END_F0, 0);
  1185. dp_write(MMSS_DP_INTF_ACTIVE_V_START_F1, 0);
  1186. dp_write(MMSS_DP_INTF_ACTIVE_V_END_F1, 0);
  1187. dp_write(MMSS_DP_INTF_POLARITY_CTL, 0);
  1188. wmb(); /* ensure TPG registers are programmed */
  1189. dp_write(MMSS_DP_TPG_MAIN_CONTROL, 0x100);
  1190. dp_write(MMSS_DP_TPG_VIDEO_CONFIG, 0x5);
  1191. wmb(); /* ensure TPG config is programmed */
  1192. dp_write(MMSS_DP_BIST_ENABLE, 0x1);
  1193. reg = dp_read(MMSS_DP_TIMING_ENGINE_EN);
  1194. reg |= 0x1;
  1195. dp_write(MMSS_DP_TIMING_ENGINE_EN, reg);
  1196. wmb(); /* ensure Timing generator is turned on */
  1197. }
  1198. static void dp_catalog_panel_dsc_cfg(struct dp_catalog_panel *panel)
  1199. {
  1200. struct dp_catalog_private *catalog;
  1201. struct dp_io_data *io_data;
  1202. u32 reg, offset;
  1203. int i;
  1204. if (!panel) {
  1205. DP_ERR("invalid input\n");
  1206. return;
  1207. }
  1208. if (panel->stream_id >= DP_STREAM_MAX) {
  1209. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1210. return;
  1211. }
  1212. catalog = dp_catalog_get_priv(panel);
  1213. if (panel->stream_id == DP_STREAM_0)
  1214. io_data = catalog->io.dp_p0;
  1215. else
  1216. io_data = catalog->io.dp_p1;
  1217. dp_write(MMSS_DP_DSC_DTO_COUNT, panel->dsc.dto_count);
  1218. reg = dp_read(MMSS_DP_DSC_DTO);
  1219. if (panel->dsc.dto_en) {
  1220. reg |= BIT(0);
  1221. reg |= BIT(3);
  1222. reg |= (panel->dsc.dto_n << 8);
  1223. reg |= (panel->dsc.dto_d << 16);
  1224. }
  1225. dp_write(MMSS_DP_DSC_DTO, reg);
  1226. io_data = catalog->io.dp_link;
  1227. if (panel->stream_id == DP_STREAM_0)
  1228. offset = 0;
  1229. else
  1230. offset = DP1_COMPRESSION_MODE_CTRL - DP_COMPRESSION_MODE_CTRL;
  1231. dp_write(DP_PPS_HB_0_3 + offset, 0x7F1000);
  1232. dp_write(DP_PPS_PB_0_3 + offset, 0xA22300);
  1233. for (i = 0; i < panel->dsc.parity_word_len; i++)
  1234. dp_write(DP_PPS_PB_4_7 + (i << 2) + offset,
  1235. panel->dsc.parity_word[i]);
  1236. for (i = 0; i < panel->dsc.pps_word_len; i++)
  1237. dp_write(DP_PPS_PPS_0_3 + (i << 2) + offset,
  1238. panel->dsc.pps_word[i]);
  1239. reg = 0;
  1240. if (panel->dsc.dsc_en) {
  1241. reg = BIT(0);
  1242. reg |= (panel->dsc.eol_byte_num << 3);
  1243. reg |= (panel->dsc.slice_per_pkt << 5);
  1244. reg |= (panel->dsc.bytes_per_pkt << 16);
  1245. reg |= (panel->dsc.be_in_lane << 10);
  1246. }
  1247. dp_write(DP_COMPRESSION_MODE_CTRL + offset, reg);
  1248. DP_DEBUG("compression:0x%x for stream:%d\n",
  1249. reg, panel->stream_id);
  1250. }
  1251. static void dp_catalog_panel_dp_flush(struct dp_catalog_panel *panel,
  1252. enum dp_flush_bit flush_bit)
  1253. {
  1254. struct dp_catalog_private *catalog;
  1255. struct dp_io_data *io_data;
  1256. u32 dp_flush, offset;
  1257. struct dp_dsc_cfg_data *dsc;
  1258. if (!panel) {
  1259. DP_ERR("invalid input\n");
  1260. return;
  1261. }
  1262. if (panel->stream_id >= DP_STREAM_MAX) {
  1263. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1264. return;
  1265. }
  1266. catalog = dp_catalog_get_priv(panel);
  1267. io_data = catalog->io.dp_link;
  1268. dsc = &panel->dsc;
  1269. if (panel->stream_id == DP_STREAM_0)
  1270. offset = 0;
  1271. else
  1272. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1273. dp_flush = dp_read(MMSS_DP_FLUSH + offset);
  1274. if ((flush_bit == DP_PPS_FLUSH) &&
  1275. dsc->continuous_pps)
  1276. dp_flush &= ~BIT(2);
  1277. dp_flush |= BIT(flush_bit);
  1278. dp_write(MMSS_DP_FLUSH + offset, dp_flush);
  1279. }
  1280. static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel)
  1281. {
  1282. dp_catalog_panel_dp_flush(panel, DP_PPS_FLUSH);
  1283. DP_DEBUG("pps flush for stream:%d\n", panel->stream_id);
  1284. }
  1285. static void dp_catalog_panel_dhdr_flush(struct dp_catalog_panel *panel)
  1286. {
  1287. dp_catalog_panel_dp_flush(panel, DP_DHDR_FLUSH);
  1288. DP_DEBUG("dhdr flush for stream:%d\n", panel->stream_id);
  1289. }
  1290. static bool dp_catalog_panel_dhdr_busy(struct dp_catalog_panel *panel)
  1291. {
  1292. struct dp_catalog_private *catalog;
  1293. struct dp_io_data *io_data;
  1294. u32 dp_flush, offset;
  1295. if (panel->stream_id >= DP_STREAM_MAX) {
  1296. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1297. return false;
  1298. }
  1299. catalog = dp_catalog_get_priv(panel);
  1300. io_data = catalog->io.dp_link;
  1301. if (panel->stream_id == DP_STREAM_0)
  1302. offset = 0;
  1303. else
  1304. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1305. dp_flush = dp_read(MMSS_DP_FLUSH + offset);
  1306. return dp_flush & BIT(DP_DHDR_FLUSH) ? true : false;
  1307. }
  1308. static void dp_catalog_ctrl_reset(struct dp_catalog_ctrl *ctrl)
  1309. {
  1310. u32 sw_reset;
  1311. struct dp_catalog_private *catalog;
  1312. struct dp_io_data *io_data;
  1313. if (!ctrl) {
  1314. DP_ERR("invalid input\n");
  1315. return;
  1316. }
  1317. catalog = dp_catalog_get_priv(ctrl);
  1318. io_data = catalog->io.dp_ahb;
  1319. sw_reset = dp_read(DP_SW_RESET);
  1320. sw_reset |= BIT(0);
  1321. dp_write(DP_SW_RESET, sw_reset);
  1322. usleep_range(1000, 1010); /* h/w recommended delay */
  1323. sw_reset &= ~BIT(0);
  1324. dp_write(DP_SW_RESET, sw_reset);
  1325. }
  1326. static bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog_ctrl *ctrl)
  1327. {
  1328. u32 data;
  1329. int cnt = 10;
  1330. struct dp_catalog_private *catalog;
  1331. struct dp_io_data *io_data;
  1332. if (!ctrl) {
  1333. DP_ERR("invalid input\n");
  1334. goto end;
  1335. }
  1336. catalog = dp_catalog_get_priv(ctrl);
  1337. io_data = catalog->io.dp_link;
  1338. while (--cnt) {
  1339. /* DP_MAINLINK_READY */
  1340. data = dp_read(DP_MAINLINK_READY);
  1341. if (data & BIT(0))
  1342. return true;
  1343. usleep_range(1000, 1010); /* 1ms wait before next reg read */
  1344. }
  1345. DP_ERR("mainlink not ready\n");
  1346. end:
  1347. return false;
  1348. }
  1349. static void dp_catalog_ctrl_enable_irq(struct dp_catalog_ctrl *ctrl,
  1350. bool enable)
  1351. {
  1352. struct dp_catalog_private *catalog;
  1353. struct dp_io_data *io_data;
  1354. if (!ctrl) {
  1355. DP_ERR("invalid input\n");
  1356. return;
  1357. }
  1358. catalog = dp_catalog_get_priv(ctrl);
  1359. io_data = catalog->io.dp_ahb;
  1360. if (enable) {
  1361. dp_write(DP_INTR_STATUS, DP_INTR_MASK1);
  1362. dp_write(DP_INTR_STATUS2, DP_INTR_MASK2);
  1363. dp_write(DP_INTR_STATUS5, DP_INTR_MASK5);
  1364. } else {
  1365. /* disable interrupts */
  1366. dp_write(DP_INTR_STATUS, 0x00);
  1367. dp_write(DP_INTR_STATUS2, 0x00);
  1368. dp_write(DP_INTR_STATUS5, 0x00);
  1369. wmb();
  1370. /* clear all pending interrupts */
  1371. dp_write(DP_INTR_STATUS, DP_INTERRUPT_STATUS1 << 1);
  1372. dp_write(DP_INTR_STATUS2, DP_INTERRUPT_STATUS2 << 1);
  1373. dp_write(DP_INTR_STATUS5, DP_INTERRUPT_STATUS5 << 1);
  1374. wmb();
  1375. }
  1376. }
  1377. static void dp_catalog_ctrl_get_interrupt(struct dp_catalog_ctrl *ctrl)
  1378. {
  1379. u32 ack = 0;
  1380. struct dp_catalog_private *catalog;
  1381. struct dp_io_data *io_data;
  1382. if (!ctrl) {
  1383. DP_ERR("invalid input\n");
  1384. return;
  1385. }
  1386. catalog = dp_catalog_get_priv(ctrl);
  1387. io_data = catalog->io.dp_ahb;
  1388. ctrl->isr = dp_read(DP_INTR_STATUS2);
  1389. ctrl->isr &= ~DP_INTR_MASK2;
  1390. ack = ctrl->isr & DP_INTERRUPT_STATUS2;
  1391. ack <<= 1;
  1392. ack |= DP_INTR_MASK2;
  1393. dp_write(DP_INTR_STATUS2, ack);
  1394. ctrl->isr5 = dp_read(DP_INTR_STATUS5);
  1395. ctrl->isr5 &= ~DP_INTR_MASK5;
  1396. ack = ctrl->isr5 & DP_INTERRUPT_STATUS5;
  1397. ack <<= 1;
  1398. ack |= DP_INTR_MASK5;
  1399. dp_write(DP_INTR_STATUS5, ack);
  1400. }
  1401. static void dp_catalog_ctrl_phy_reset(struct dp_catalog_ctrl *ctrl)
  1402. {
  1403. struct dp_catalog_private *catalog;
  1404. struct dp_io_data *io_data;
  1405. if (!ctrl) {
  1406. DP_ERR("invalid input\n");
  1407. return;
  1408. }
  1409. catalog = dp_catalog_get_priv(ctrl);
  1410. io_data = catalog->io.dp_ahb;
  1411. dp_write(DP_PHY_CTRL, 0x5); /* bit 0 & 2 */
  1412. usleep_range(1000, 1010); /* h/w recommended delay */
  1413. dp_write(DP_PHY_CTRL, 0x0);
  1414. wmb(); /* make sure PHY reset done */
  1415. }
  1416. static void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog_ctrl *ctrl,
  1417. bool flipped, u8 ln_cnt)
  1418. {
  1419. u32 info = 0x0;
  1420. struct dp_catalog_private *catalog;
  1421. struct dp_io_data *io_data;
  1422. u8 orientation = BIT(!!flipped);
  1423. if (!ctrl) {
  1424. DP_ERR("invalid input\n");
  1425. return;
  1426. }
  1427. catalog = dp_catalog_get_priv(ctrl);
  1428. io_data = catalog->io.dp_phy;
  1429. info |= (ln_cnt & 0x0F);
  1430. info |= ((orientation & 0x0F) << 4);
  1431. DP_DEBUG("Shared Info = 0x%x\n", info);
  1432. dp_write(DP_PHY_SPARE0, info);
  1433. }
  1434. static void dp_catalog_ctrl_update_vx_px(struct dp_catalog_ctrl *ctrl,
  1435. u8 v_level, u8 p_level, bool high)
  1436. {
  1437. struct dp_catalog_private *catalog;
  1438. struct dp_io_data *io_data;
  1439. u8 value0, value1;
  1440. u32 version;
  1441. if (!ctrl) {
  1442. DP_ERR("invalid input\n");
  1443. return;
  1444. }
  1445. catalog = dp_catalog_get_priv(ctrl);
  1446. DP_DEBUG("hw: v=%d p=%d\n", v_level, p_level);
  1447. io_data = catalog->io.dp_ahb;
  1448. version = dp_read(DP_HW_VERSION);
  1449. if (version == 0x10020004) {
  1450. if (high) {
  1451. value0 = vm_voltage_swing_hbr3_hbr2[v_level][p_level];
  1452. value1 = vm_pre_emphasis_hbr3_hbr2[v_level][p_level];
  1453. } else {
  1454. value0 = vm_voltage_swing_hbr_rbr[v_level][p_level];
  1455. value1 = vm_pre_emphasis_hbr_rbr[v_level][p_level];
  1456. }
  1457. } else {
  1458. value0 = vm_voltage_swing[v_level][p_level];
  1459. value1 = vm_pre_emphasis[v_level][p_level];
  1460. }
  1461. /* program default setting first */
  1462. io_data = catalog->io.dp_ln_tx0;
  1463. dp_write(TXn_TX_DRV_LVL, 0x2A);
  1464. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  1465. io_data = catalog->io.dp_ln_tx1;
  1466. dp_write(TXn_TX_DRV_LVL, 0x2A);
  1467. dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
  1468. /* Enable MUX to use Cursor values from these registers */
  1469. value0 |= BIT(5);
  1470. value1 |= BIT(5);
  1471. /* Configure host and panel only if both values are allowed */
  1472. if (value0 != 0xFF && value1 != 0xFF) {
  1473. io_data = catalog->io.dp_ln_tx0;
  1474. dp_write(TXn_TX_DRV_LVL, value0);
  1475. dp_write(TXn_TX_EMP_POST1_LVL, value1);
  1476. io_data = catalog->io.dp_ln_tx1;
  1477. dp_write(TXn_TX_DRV_LVL, value0);
  1478. dp_write(TXn_TX_EMP_POST1_LVL, value1);
  1479. DP_DEBUG("hw: vx_value=0x%x px_value=0x%x\n",
  1480. value0, value1);
  1481. } else {
  1482. DP_ERR("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n",
  1483. v_level, value0, p_level, value1);
  1484. }
  1485. }
  1486. static void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog_ctrl *ctrl,
  1487. u32 pattern)
  1488. {
  1489. struct dp_catalog_private *catalog;
  1490. u32 value = 0x0;
  1491. struct dp_io_data *io_data = NULL;
  1492. if (!ctrl) {
  1493. DP_ERR("invalid input\n");
  1494. return;
  1495. }
  1496. catalog = dp_catalog_get_priv(ctrl);
  1497. io_data = catalog->io.dp_link;
  1498. dp_write(DP_STATE_CTRL, 0x0);
  1499. switch (pattern) {
  1500. case DP_PHY_TEST_PATTERN_D10_2:
  1501. dp_write(DP_STATE_CTRL, 0x1);
  1502. break;
  1503. case DP_PHY_TEST_PATTERN_ERROR_COUNT:
  1504. value &= ~(1 << 16);
  1505. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1506. value |= 0xFC;
  1507. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1508. dp_write(DP_MAINLINK_LEVELS, 0x2);
  1509. dp_write(DP_STATE_CTRL, 0x10);
  1510. break;
  1511. case DP_PHY_TEST_PATTERN_PRBS7:
  1512. dp_write(DP_STATE_CTRL, 0x20);
  1513. break;
  1514. case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
  1515. dp_write(DP_STATE_CTRL, 0x40);
  1516. /* 00111110000011111000001111100000 */
  1517. dp_write(DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 0x3E0F83E0);
  1518. /* 00001111100000111110000011111000 */
  1519. dp_write(DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 0x0F83E0F8);
  1520. /* 1111100000111110 */
  1521. dp_write(DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 0x0000F83E);
  1522. break;
  1523. case DP_PHY_TEST_PATTERN_CP2520:
  1524. value = dp_read(DP_MAINLINK_CTRL);
  1525. value &= ~BIT(4);
  1526. dp_write(DP_MAINLINK_CTRL, value);
  1527. value = BIT(16);
  1528. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1529. value |= 0xFC;
  1530. dp_write(DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1531. dp_write(DP_MAINLINK_LEVELS, 0x2);
  1532. dp_write(DP_STATE_CTRL, 0x10);
  1533. value = dp_read(DP_MAINLINK_CTRL);
  1534. value |= BIT(0);
  1535. dp_write(DP_MAINLINK_CTRL, value);
  1536. break;
  1537. case DP_PHY_TEST_PATTERN_CP2520_3:
  1538. dp_write(DP_MAINLINK_CTRL, 0x01);
  1539. dp_write(DP_STATE_CTRL, 0x8);
  1540. break;
  1541. default:
  1542. DP_DEBUG("No valid test pattern requested: 0x%x\n", pattern);
  1543. return;
  1544. }
  1545. /* Make sure the test pattern is programmed in the hardware */
  1546. wmb();
  1547. }
  1548. static u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog_ctrl *ctrl)
  1549. {
  1550. struct dp_catalog_private *catalog;
  1551. struct dp_io_data *io_data = NULL;
  1552. if (!ctrl) {
  1553. DP_ERR("invalid input\n");
  1554. return 0;
  1555. }
  1556. catalog = dp_catalog_get_priv(ctrl);
  1557. io_data = catalog->io.dp_link;
  1558. return dp_read(DP_MAINLINK_READY);
  1559. }
  1560. static void dp_catalog_ctrl_fec_config(struct dp_catalog_ctrl *ctrl,
  1561. bool enable)
  1562. {
  1563. struct dp_catalog_private *catalog;
  1564. struct dp_io_data *io_data = NULL;
  1565. u32 reg;
  1566. if (!ctrl) {
  1567. DP_ERR("invalid input\n");
  1568. return;
  1569. }
  1570. catalog = dp_catalog_get_priv(ctrl);
  1571. io_data = catalog->io.dp_link;
  1572. reg = dp_read(DP_MAINLINK_CTRL);
  1573. /*
  1574. * fec_en = BIT(12)
  1575. * fec_seq_mode = BIT(22)
  1576. * sde_flush = BIT(23) | BIT(24)
  1577. * fb_boundary_sel = BIT(25)
  1578. */
  1579. if (enable)
  1580. reg |= BIT(12) | BIT(22) | BIT(23) | BIT(24) | BIT(25);
  1581. else
  1582. reg &= ~BIT(12);
  1583. dp_write(DP_MAINLINK_CTRL, reg);
  1584. /* make sure mainlink configuration is updated with fec sequence */
  1585. wmb();
  1586. }
  1587. u32 dp_catalog_get_dp_core_version(struct dp_catalog *dp_catalog)
  1588. {
  1589. struct dp_catalog_private *catalog;
  1590. struct dp_io_data *io_data;
  1591. if (!dp_catalog) {
  1592. DP_ERR("invalid input\n");
  1593. return 0;
  1594. }
  1595. catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog);
  1596. if (catalog->dp_core_version)
  1597. return catalog->dp_core_version;
  1598. io_data = catalog->io.dp_ahb;
  1599. return dp_read(DP_HW_VERSION);
  1600. }
  1601. u32 dp_catalog_get_dp_phy_version(struct dp_catalog *dp_catalog)
  1602. {
  1603. struct dp_catalog_private *catalog;
  1604. struct dp_io_data *io_data;
  1605. if (!dp_catalog) {
  1606. DP_ERR("invalid input\n");
  1607. return 0;
  1608. }
  1609. catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog);
  1610. if (catalog->dp_phy_version)
  1611. return catalog->dp_phy_version;
  1612. io_data = catalog->io.dp_phy;
  1613. catalog->dp_phy_version = (dp_read(DP_PHY_REVISION_ID3) << 24) |
  1614. (dp_read(DP_PHY_REVISION_ID2) << 16) |
  1615. (dp_read(DP_PHY_REVISION_ID1) << 8) |
  1616. dp_read(DP_PHY_REVISION_ID0);
  1617. return catalog->dp_phy_version;
  1618. }
  1619. static int dp_catalog_reg_dump(struct dp_catalog *dp_catalog,
  1620. char *name, u8 **out_buf, u32 *out_buf_len)
  1621. {
  1622. int ret = 0;
  1623. u8 *buf;
  1624. u32 len;
  1625. struct dp_io_data *io_data;
  1626. struct dp_catalog_private *catalog;
  1627. struct dp_parser *parser;
  1628. if (!dp_catalog) {
  1629. DP_ERR("invalid input\n");
  1630. return -EINVAL;
  1631. }
  1632. catalog = container_of(dp_catalog, struct dp_catalog_private,
  1633. dp_catalog);
  1634. parser = catalog->parser;
  1635. parser->get_io_buf(parser, name);
  1636. io_data = parser->get_io(parser, name);
  1637. if (!io_data) {
  1638. DP_ERR("IO %s not found\n", name);
  1639. ret = -EINVAL;
  1640. goto end;
  1641. }
  1642. buf = io_data->buf;
  1643. len = io_data->io.len;
  1644. if (!buf || !len) {
  1645. DP_ERR("no buffer available\n");
  1646. ret = -ENOMEM;
  1647. goto end;
  1648. }
  1649. if (!strcmp(catalog->exe_mode, "hw") ||
  1650. !strcmp(catalog->exe_mode, "all")) {
  1651. u32 i, data;
  1652. u32 const rowsize = 4;
  1653. void __iomem *addr = io_data->io.base;
  1654. memset(buf, 0, len);
  1655. for (i = 0; i < len / rowsize; i++) {
  1656. data = readl_relaxed(addr);
  1657. memcpy(buf + (rowsize * i), &data, sizeof(u32));
  1658. addr += rowsize;
  1659. }
  1660. }
  1661. *out_buf = buf;
  1662. *out_buf_len = len;
  1663. end:
  1664. if (ret)
  1665. parser->clear_io_buf(parser);
  1666. return ret;
  1667. }
  1668. static void dp_catalog_ctrl_mst_config(struct dp_catalog_ctrl *ctrl,
  1669. bool enable)
  1670. {
  1671. struct dp_catalog_private *catalog;
  1672. struct dp_io_data *io_data = NULL;
  1673. u32 reg;
  1674. if (!ctrl) {
  1675. DP_ERR("invalid input\n");
  1676. return;
  1677. }
  1678. catalog = dp_catalog_get_priv(ctrl);
  1679. io_data = catalog->io.dp_link;
  1680. reg = dp_read(DP_MAINLINK_CTRL);
  1681. if (enable)
  1682. reg |= (0x04000100);
  1683. else
  1684. reg &= ~(0x04000100);
  1685. dp_write(DP_MAINLINK_CTRL, reg);
  1686. /* make sure mainlink MST configuration is updated */
  1687. wmb();
  1688. }
  1689. static void dp_catalog_ctrl_trigger_act(struct dp_catalog_ctrl *ctrl)
  1690. {
  1691. struct dp_catalog_private *catalog;
  1692. struct dp_io_data *io_data = NULL;
  1693. if (!ctrl) {
  1694. DP_ERR("invalid input\n");
  1695. return;
  1696. }
  1697. catalog = dp_catalog_get_priv(ctrl);
  1698. io_data = catalog->io.dp_link;
  1699. dp_write(DP_MST_ACT, 0x1);
  1700. /* make sure ACT signal is performed */
  1701. wmb();
  1702. }
  1703. static void dp_catalog_ctrl_read_act_complete_sts(struct dp_catalog_ctrl *ctrl,
  1704. bool *sts)
  1705. {
  1706. struct dp_catalog_private *catalog;
  1707. struct dp_io_data *io_data = NULL;
  1708. u32 reg;
  1709. if (!ctrl || !sts) {
  1710. DP_ERR("invalid input\n");
  1711. return;
  1712. }
  1713. *sts = false;
  1714. catalog = dp_catalog_get_priv(ctrl);
  1715. io_data = catalog->io.dp_link;
  1716. reg = dp_read(DP_MST_ACT);
  1717. if (!reg)
  1718. *sts = true;
  1719. }
  1720. static void dp_catalog_ctrl_channel_alloc(struct dp_catalog_ctrl *ctrl,
  1721. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1722. {
  1723. struct dp_catalog_private *catalog;
  1724. struct dp_io_data *io_data = NULL;
  1725. u32 i, slot_reg_1, slot_reg_2, slot;
  1726. u32 reg_off = 0;
  1727. int const num_slots_per_reg = 32;
  1728. if (!ctrl || ch >= DP_STREAM_MAX) {
  1729. DP_ERR("invalid input. ch %d\n", ch);
  1730. return;
  1731. }
  1732. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1733. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1734. DP_ERR("invalid slots start %d, tot %d\n",
  1735. ch_start_slot, tot_slot_cnt);
  1736. return;
  1737. }
  1738. catalog = dp_catalog_get_priv(ctrl);
  1739. io_data = catalog->io.dp_link;
  1740. DP_DEBUG("ch %d, start_slot %d, tot_slot %d\n",
  1741. ch, ch_start_slot, tot_slot_cnt);
  1742. if (ch == DP_STREAM_1)
  1743. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1744. slot_reg_1 = 0;
  1745. slot_reg_2 = 0;
  1746. if (ch_start_slot && tot_slot_cnt) {
  1747. ch_start_slot--;
  1748. for (i = 0; i < tot_slot_cnt; i++) {
  1749. if (ch_start_slot < num_slots_per_reg) {
  1750. slot_reg_1 |= BIT(ch_start_slot);
  1751. } else {
  1752. slot = ch_start_slot - num_slots_per_reg;
  1753. slot_reg_2 |= BIT(slot);
  1754. }
  1755. ch_start_slot++;
  1756. }
  1757. }
  1758. DP_DEBUG("ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1759. slot_reg_1, slot_reg_2);
  1760. dp_write(DP_DP0_TIMESLOT_1_32 + reg_off, slot_reg_1);
  1761. dp_write(DP_DP0_TIMESLOT_33_63 + reg_off, slot_reg_2);
  1762. }
  1763. static void dp_catalog_ctrl_channel_dealloc(struct dp_catalog_ctrl *ctrl,
  1764. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1765. {
  1766. struct dp_catalog_private *catalog;
  1767. struct dp_io_data *io_data = NULL;
  1768. u32 i, slot_reg_1, slot_reg_2, slot;
  1769. u32 reg_off = 0;
  1770. if (!ctrl || ch >= DP_STREAM_MAX) {
  1771. DP_ERR("invalid input. ch %d\n", ch);
  1772. return;
  1773. }
  1774. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1775. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1776. DP_ERR("invalid slots start %d, tot %d\n",
  1777. ch_start_slot, tot_slot_cnt);
  1778. return;
  1779. }
  1780. catalog = dp_catalog_get_priv(ctrl);
  1781. io_data = catalog->io.dp_link;
  1782. DP_DEBUG("dealloc ch %d, start_slot %d, tot_slot %d\n",
  1783. ch, ch_start_slot, tot_slot_cnt);
  1784. if (ch == DP_STREAM_1)
  1785. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1786. slot_reg_1 = dp_read(DP_DP0_TIMESLOT_1_32 + reg_off);
  1787. slot_reg_2 = dp_read(DP_DP0_TIMESLOT_33_63 + reg_off);
  1788. ch_start_slot = ch_start_slot - 1;
  1789. for (i = 0; i < tot_slot_cnt; i++) {
  1790. if (ch_start_slot < 33) {
  1791. slot_reg_1 &= ~BIT(ch_start_slot);
  1792. } else {
  1793. slot = ch_start_slot - 33;
  1794. slot_reg_2 &= ~BIT(slot);
  1795. }
  1796. ch_start_slot++;
  1797. }
  1798. DP_DEBUG("dealloc ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1799. slot_reg_1, slot_reg_2);
  1800. dp_write(DP_DP0_TIMESLOT_1_32 + reg_off, slot_reg_1);
  1801. dp_write(DP_DP0_TIMESLOT_33_63 + reg_off, slot_reg_2);
  1802. }
  1803. static void dp_catalog_ctrl_update_rg(struct dp_catalog_ctrl *ctrl, u32 ch,
  1804. u32 x_int, u32 y_frac_enum)
  1805. {
  1806. struct dp_catalog_private *catalog;
  1807. struct dp_io_data *io_data = NULL;
  1808. u32 rg, reg_off = 0;
  1809. if (!ctrl || ch >= DP_STREAM_MAX) {
  1810. DP_ERR("invalid input. ch %d\n", ch);
  1811. return;
  1812. }
  1813. catalog = dp_catalog_get_priv(ctrl);
  1814. io_data = catalog->io.dp_link;
  1815. rg = y_frac_enum;
  1816. rg |= (x_int << 16);
  1817. DP_DEBUG("ch: %d x_int:%d y_frac_enum:%d rg:%d\n", ch, x_int,
  1818. y_frac_enum, rg);
  1819. if (ch == DP_STREAM_1)
  1820. reg_off = DP_DP1_RG - DP_DP0_RG;
  1821. dp_write(DP_DP0_RG + reg_off, rg);
  1822. }
  1823. static void dp_catalog_ctrl_mainlink_levels(struct dp_catalog_ctrl *ctrl,
  1824. u8 lane_cnt)
  1825. {
  1826. struct dp_catalog_private *catalog;
  1827. struct dp_io_data *io_data;
  1828. u32 mainlink_levels, safe_to_exit_level = 14;
  1829. catalog = dp_catalog_get_priv(ctrl);
  1830. io_data = catalog->io.dp_link;
  1831. switch (lane_cnt) {
  1832. case 1:
  1833. safe_to_exit_level = 14;
  1834. break;
  1835. case 2:
  1836. safe_to_exit_level = 8;
  1837. break;
  1838. case 4:
  1839. safe_to_exit_level = 5;
  1840. break;
  1841. default:
  1842. DP_DEBUG("setting the default safe_to_exit_level = %u\n",
  1843. safe_to_exit_level);
  1844. break;
  1845. }
  1846. mainlink_levels = dp_read(DP_MAINLINK_LEVELS);
  1847. mainlink_levels &= 0xFE0;
  1848. mainlink_levels |= safe_to_exit_level;
  1849. DP_DEBUG("mainlink_level = 0x%x, safe_to_exit_level = 0x%x\n",
  1850. mainlink_levels, safe_to_exit_level);
  1851. dp_write(DP_MAINLINK_LEVELS, mainlink_levels);
  1852. }
  1853. /* panel related catalog functions */
  1854. static int dp_catalog_panel_timing_cfg(struct dp_catalog_panel *panel)
  1855. {
  1856. struct dp_catalog_private *catalog;
  1857. struct dp_io_data *io_data;
  1858. u32 offset = 0, reg;
  1859. if (!panel) {
  1860. DP_ERR("invalid input\n");
  1861. goto end;
  1862. }
  1863. if (panel->stream_id >= DP_STREAM_MAX) {
  1864. DP_ERR("invalid stream_id:%d\n", panel->stream_id);
  1865. goto end;
  1866. }
  1867. catalog = dp_catalog_get_priv(panel);
  1868. io_data = catalog->io.dp_link;
  1869. if (panel->stream_id == DP_STREAM_1)
  1870. offset = DP1_TOTAL_HOR_VER - DP_TOTAL_HOR_VER;
  1871. dp_write(DP_TOTAL_HOR_VER + offset, panel->total);
  1872. dp_write(DP_START_HOR_VER_FROM_SYNC + offset, panel->sync_start);
  1873. dp_write(DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, panel->width_blanking);
  1874. dp_write(DP_ACTIVE_HOR_VER + offset, panel->dp_active);
  1875. if (panel->stream_id == DP_STREAM_0)
  1876. io_data = catalog->io.dp_p0;
  1877. else
  1878. io_data = catalog->io.dp_p1;
  1879. reg = dp_read(MMSS_DP_INTF_CONFIG);
  1880. if (panel->widebus_en)
  1881. reg |= BIT(4);
  1882. else
  1883. reg &= ~BIT(4);
  1884. dp_write(MMSS_DP_INTF_CONFIG, reg);
  1885. end:
  1886. return 0;
  1887. }
  1888. static void dp_catalog_hpd_config_hpd(struct dp_catalog_hpd *hpd, bool en)
  1889. {
  1890. struct dp_catalog_private *catalog;
  1891. struct dp_io_data *io_data;
  1892. if (!hpd) {
  1893. DP_ERR("invalid input\n");
  1894. return;
  1895. }
  1896. catalog = dp_catalog_get_priv(hpd);
  1897. io_data = catalog->io.dp_aux;
  1898. if (en) {
  1899. u32 reftimer = dp_read(DP_DP_HPD_REFTIMER);
  1900. /* Arm only the UNPLUG and HPD_IRQ interrupts */
  1901. dp_write(DP_DP_HPD_INT_ACK, 0xF);
  1902. dp_write(DP_DP_HPD_INT_MASK, 0xA);
  1903. /* Enable REFTIMER to count 1ms */
  1904. reftimer |= BIT(16);
  1905. dp_write(DP_DP_HPD_REFTIMER, reftimer);
  1906. /* Connect_time is 250us & disconnect_time is 2ms */
  1907. dp_write(DP_DP_HPD_EVENT_TIME_0, 0x3E800FA);
  1908. dp_write(DP_DP_HPD_EVENT_TIME_1, 0x1F407D0);
  1909. /* Enable HPD */
  1910. dp_write(DP_DP_HPD_CTRL, 0x1);
  1911. } else {
  1912. /* Disable HPD */
  1913. dp_write(DP_DP_HPD_CTRL, 0x0);
  1914. }
  1915. }
  1916. static u32 dp_catalog_hpd_get_interrupt(struct dp_catalog_hpd *hpd)
  1917. {
  1918. u32 isr = 0;
  1919. struct dp_catalog_private *catalog;
  1920. struct dp_io_data *io_data;
  1921. if (!hpd) {
  1922. DP_ERR("invalid input\n");
  1923. return isr;
  1924. }
  1925. catalog = dp_catalog_get_priv(hpd);
  1926. io_data = catalog->io.dp_aux;
  1927. isr = dp_read(DP_DP_HPD_INT_STATUS);
  1928. dp_write(DP_DP_HPD_INT_ACK, (isr & 0xf));
  1929. return isr;
  1930. }
  1931. static void dp_catalog_audio_init(struct dp_catalog_audio *audio)
  1932. {
  1933. struct dp_catalog_private *catalog;
  1934. static u32 sdp_map[][DP_AUDIO_SDP_HEADER_MAX] = {
  1935. {
  1936. MMSS_DP_AUDIO_STREAM_0,
  1937. MMSS_DP_AUDIO_STREAM_1,
  1938. MMSS_DP_AUDIO_STREAM_1,
  1939. },
  1940. {
  1941. MMSS_DP_AUDIO_TIMESTAMP_0,
  1942. MMSS_DP_AUDIO_TIMESTAMP_1,
  1943. MMSS_DP_AUDIO_TIMESTAMP_1,
  1944. },
  1945. {
  1946. MMSS_DP_AUDIO_INFOFRAME_0,
  1947. MMSS_DP_AUDIO_INFOFRAME_1,
  1948. MMSS_DP_AUDIO_INFOFRAME_1,
  1949. },
  1950. {
  1951. MMSS_DP_AUDIO_COPYMANAGEMENT_0,
  1952. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1953. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1954. },
  1955. {
  1956. MMSS_DP_AUDIO_ISRC_0,
  1957. MMSS_DP_AUDIO_ISRC_1,
  1958. MMSS_DP_AUDIO_ISRC_1,
  1959. },
  1960. };
  1961. if (!audio)
  1962. return;
  1963. catalog = dp_catalog_get_priv(audio);
  1964. catalog->audio_map = sdp_map;
  1965. }
  1966. static void dp_catalog_audio_config_sdp(struct dp_catalog_audio *audio)
  1967. {
  1968. struct dp_catalog_private *catalog;
  1969. struct dp_io_data *io_data;
  1970. u32 sdp_cfg = 0, sdp_cfg_off = 0;
  1971. u32 sdp_cfg2 = 0, sdp_cfg2_off = 0;
  1972. if (!audio)
  1973. return;
  1974. if (audio->stream_id >= DP_STREAM_MAX) {
  1975. DP_ERR("invalid stream id:%d\n", audio->stream_id);
  1976. return;
  1977. }
  1978. if (audio->stream_id == DP_STREAM_1) {
  1979. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  1980. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  1981. }
  1982. catalog = dp_catalog_get_priv(audio);
  1983. io_data = catalog->io.dp_link;
  1984. sdp_cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  1985. /* AUDIO_TIMESTAMP_SDP_EN */
  1986. sdp_cfg |= BIT(1);
  1987. /* AUDIO_STREAM_SDP_EN */
  1988. sdp_cfg |= BIT(2);
  1989. /* AUDIO_COPY_MANAGEMENT_SDP_EN */
  1990. sdp_cfg |= BIT(5);
  1991. /* AUDIO_ISRC_SDP_EN */
  1992. sdp_cfg |= BIT(6);
  1993. /* AUDIO_INFOFRAME_SDP_EN */
  1994. sdp_cfg |= BIT(20);
  1995. DP_DEBUG("sdp_cfg = 0x%x\n", sdp_cfg);
  1996. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, sdp_cfg);
  1997. sdp_cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg_off);
  1998. /* IFRM_REGSRC -> Do not use reg values */
  1999. sdp_cfg2 &= ~BIT(0);
  2000. /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */
  2001. sdp_cfg2 &= ~BIT(1);
  2002. DP_DEBUG("sdp_cfg2 = 0x%x\n", sdp_cfg2);
  2003. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg_off, sdp_cfg2);
  2004. }
  2005. static void dp_catalog_audio_get_header(struct dp_catalog_audio *audio)
  2006. {
  2007. struct dp_catalog_private *catalog;
  2008. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  2009. struct dp_io_data *io_data;
  2010. enum dp_catalog_audio_sdp_type sdp;
  2011. enum dp_catalog_audio_header_type header;
  2012. if (!audio)
  2013. return;
  2014. catalog = dp_catalog_get_priv(audio);
  2015. io_data = catalog->io.dp_link;
  2016. sdp_map = catalog->audio_map;
  2017. sdp = audio->sdp_type;
  2018. header = audio->sdp_header;
  2019. audio->data = dp_read(sdp_map[sdp][header]);
  2020. }
  2021. static void dp_catalog_audio_set_header(struct dp_catalog_audio *audio)
  2022. {
  2023. struct dp_catalog_private *catalog;
  2024. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  2025. struct dp_io_data *io_data;
  2026. enum dp_catalog_audio_sdp_type sdp;
  2027. enum dp_catalog_audio_header_type header;
  2028. u32 data;
  2029. if (!audio)
  2030. return;
  2031. catalog = dp_catalog_get_priv(audio);
  2032. io_data = catalog->io.dp_link;
  2033. sdp_map = catalog->audio_map;
  2034. sdp = audio->sdp_type;
  2035. header = audio->sdp_header;
  2036. data = audio->data;
  2037. dp_write(sdp_map[sdp][header], data);
  2038. }
  2039. static void dp_catalog_audio_config_acr(struct dp_catalog_audio *audio)
  2040. {
  2041. struct dp_catalog_private *catalog;
  2042. struct dp_io_data *io_data;
  2043. u32 acr_ctrl, select;
  2044. catalog = dp_catalog_get_priv(audio);
  2045. select = audio->data;
  2046. io_data = catalog->io.dp_link;
  2047. acr_ctrl = select << 4 | BIT(31) | BIT(8) | BIT(14);
  2048. DP_DEBUG("select = 0x%x, acr_ctrl = 0x%x\n", select, acr_ctrl);
  2049. dp_write(MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl);
  2050. }
  2051. static void dp_catalog_audio_enable(struct dp_catalog_audio *audio)
  2052. {
  2053. struct dp_catalog_private *catalog;
  2054. struct dp_io_data *io_data;
  2055. bool enable;
  2056. u32 audio_ctrl;
  2057. catalog = dp_catalog_get_priv(audio);
  2058. io_data = catalog->io.dp_link;
  2059. enable = !!audio->data;
  2060. audio_ctrl = dp_read(MMSS_DP_AUDIO_CFG);
  2061. if (enable)
  2062. audio_ctrl |= BIT(0);
  2063. else
  2064. audio_ctrl &= ~BIT(0);
  2065. DP_DEBUG("dp_audio_cfg = 0x%x\n", audio_ctrl);
  2066. dp_write(MMSS_DP_AUDIO_CFG, audio_ctrl);
  2067. /* make sure audio engine is disabled */
  2068. wmb();
  2069. }
  2070. static void dp_catalog_config_spd_header(struct dp_catalog_panel *panel)
  2071. {
  2072. struct dp_catalog_private *catalog;
  2073. struct dp_io_data *io_data;
  2074. u32 value, new_value, offset = 0;
  2075. u8 parity_byte;
  2076. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  2077. return;
  2078. catalog = dp_catalog_get_priv(panel);
  2079. io_data = catalog->io.dp_link;
  2080. if (panel->stream_id == DP_STREAM_1)
  2081. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  2082. /* Config header and parity byte 1 */
  2083. value = dp_read(MMSS_DP_GENERIC1_0 + offset);
  2084. new_value = 0x83;
  2085. parity_byte = dp_header_get_parity(new_value);
  2086. value |= ((new_value << HEADER_BYTE_1_BIT)
  2087. | (parity_byte << PARITY_BYTE_1_BIT));
  2088. DP_DEBUG("Header Byte 1: value = 0x%x, parity_byte = 0x%x\n",
  2089. value, parity_byte);
  2090. dp_write(MMSS_DP_GENERIC1_0 + offset, value);
  2091. /* Config header and parity byte 2 */
  2092. value = dp_read(MMSS_DP_GENERIC1_1 + offset);
  2093. new_value = 0x1b;
  2094. parity_byte = dp_header_get_parity(new_value);
  2095. value |= ((new_value << HEADER_BYTE_2_BIT)
  2096. | (parity_byte << PARITY_BYTE_2_BIT));
  2097. DP_DEBUG("Header Byte 2: value = 0x%x, parity_byte = 0x%x\n",
  2098. value, parity_byte);
  2099. dp_write(MMSS_DP_GENERIC1_1 + offset, value);
  2100. /* Config header and parity byte 3 */
  2101. value = dp_read(MMSS_DP_GENERIC1_1 + offset);
  2102. new_value = (0x0 | (0x12 << 2));
  2103. parity_byte = dp_header_get_parity(new_value);
  2104. value |= ((new_value << HEADER_BYTE_3_BIT)
  2105. | (parity_byte << PARITY_BYTE_3_BIT));
  2106. DP_DEBUG("Header Byte 3: value = 0x%x, parity_byte = 0x%x\n",
  2107. new_value, parity_byte);
  2108. dp_write(MMSS_DP_GENERIC1_1 + offset, value);
  2109. }
  2110. static void dp_catalog_panel_config_spd(struct dp_catalog_panel *panel)
  2111. {
  2112. struct dp_catalog_private *catalog;
  2113. struct dp_io_data *io_data;
  2114. u32 spd_cfg = 0, spd_cfg2 = 0;
  2115. u8 *vendor = NULL, *product = NULL;
  2116. u32 offset = 0;
  2117. u32 sdp_cfg_off = 0;
  2118. u32 sdp_cfg2_off = 0;
  2119. /*
  2120. * Source Device Information
  2121. * 00h unknown
  2122. * 01h Digital STB
  2123. * 02h DVD
  2124. * 03h D-VHS
  2125. * 04h HDD Video
  2126. * 05h DVC
  2127. * 06h DSC
  2128. * 07h Video CD
  2129. * 08h Game
  2130. * 09h PC general
  2131. * 0ah Bluray-Disc
  2132. * 0bh Super Audio CD
  2133. * 0ch HD DVD
  2134. * 0dh PMP
  2135. * 0eh-ffh reserved
  2136. */
  2137. u32 device_type = 0;
  2138. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  2139. return;
  2140. catalog = dp_catalog_get_priv(panel);
  2141. io_data = catalog->io.dp_link;
  2142. if (panel->stream_id == DP_STREAM_1)
  2143. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  2144. dp_catalog_config_spd_header(panel);
  2145. vendor = panel->spd_vendor_name;
  2146. product = panel->spd_product_description;
  2147. dp_write(MMSS_DP_GENERIC1_2 + offset,
  2148. ((vendor[0] & 0x7f) |
  2149. ((vendor[1] & 0x7f) << 8) |
  2150. ((vendor[2] & 0x7f) << 16) |
  2151. ((vendor[3] & 0x7f) << 24)));
  2152. dp_write(MMSS_DP_GENERIC1_3 + offset,
  2153. ((vendor[4] & 0x7f) |
  2154. ((vendor[5] & 0x7f) << 8) |
  2155. ((vendor[6] & 0x7f) << 16) |
  2156. ((vendor[7] & 0x7f) << 24)));
  2157. dp_write(MMSS_DP_GENERIC1_4 + offset,
  2158. ((product[0] & 0x7f) |
  2159. ((product[1] & 0x7f) << 8) |
  2160. ((product[2] & 0x7f) << 16) |
  2161. ((product[3] & 0x7f) << 24)));
  2162. dp_write(MMSS_DP_GENERIC1_5 + offset,
  2163. ((product[4] & 0x7f) |
  2164. ((product[5] & 0x7f) << 8) |
  2165. ((product[6] & 0x7f) << 16) |
  2166. ((product[7] & 0x7f) << 24)));
  2167. dp_write(MMSS_DP_GENERIC1_6 + offset,
  2168. ((product[8] & 0x7f) |
  2169. ((product[9] & 0x7f) << 8) |
  2170. ((product[10] & 0x7f) << 16) |
  2171. ((product[11] & 0x7f) << 24)));
  2172. dp_write(MMSS_DP_GENERIC1_7 + offset,
  2173. ((product[12] & 0x7f) |
  2174. ((product[13] & 0x7f) << 8) |
  2175. ((product[14] & 0x7f) << 16) |
  2176. ((product[15] & 0x7f) << 24)));
  2177. dp_write(MMSS_DP_GENERIC1_8 + offset, device_type);
  2178. dp_write(MMSS_DP_GENERIC1_9 + offset, 0x00);
  2179. if (panel->stream_id == DP_STREAM_1) {
  2180. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  2181. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  2182. }
  2183. spd_cfg = dp_read(MMSS_DP_SDP_CFG + sdp_cfg_off);
  2184. /* GENERIC1_SDP for SPD Infoframe */
  2185. spd_cfg |= BIT(18);
  2186. dp_write(MMSS_DP_SDP_CFG + sdp_cfg_off, spd_cfg);
  2187. spd_cfg2 = dp_read(MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  2188. /* 28 data bytes for SPD Infoframe with GENERIC1 set */
  2189. spd_cfg2 |= BIT(17);
  2190. dp_write(MMSS_DP_SDP_CFG2 + sdp_cfg2_off, spd_cfg2);
  2191. dp_catalog_panel_sdp_update(panel);
  2192. }
  2193. static void dp_catalog_get_io_buf(struct dp_catalog_private *catalog)
  2194. {
  2195. struct dp_parser *parser = catalog->parser;
  2196. dp_catalog_fill_io_buf(dp_ahb);
  2197. dp_catalog_fill_io_buf(dp_aux);
  2198. dp_catalog_fill_io_buf(dp_link);
  2199. dp_catalog_fill_io_buf(dp_p0);
  2200. dp_catalog_fill_io_buf(dp_phy);
  2201. dp_catalog_fill_io_buf(dp_ln_tx0);
  2202. dp_catalog_fill_io_buf(dp_ln_tx1);
  2203. dp_catalog_fill_io_buf(dp_pll);
  2204. dp_catalog_fill_io_buf(usb3_dp_com);
  2205. dp_catalog_fill_io_buf(dp_mmss_cc);
  2206. dp_catalog_fill_io_buf(hdcp_physical);
  2207. dp_catalog_fill_io_buf(dp_p1);
  2208. dp_catalog_fill_io_buf(dp_tcsr);
  2209. }
  2210. static void dp_catalog_get_io(struct dp_catalog_private *catalog)
  2211. {
  2212. struct dp_parser *parser = catalog->parser;
  2213. dp_catalog_fill_io(dp_ahb);
  2214. dp_catalog_fill_io(dp_aux);
  2215. dp_catalog_fill_io(dp_link);
  2216. dp_catalog_fill_io(dp_p0);
  2217. dp_catalog_fill_io(dp_phy);
  2218. dp_catalog_fill_io(dp_ln_tx0);
  2219. dp_catalog_fill_io(dp_ln_tx1);
  2220. dp_catalog_fill_io(dp_pll);
  2221. dp_catalog_fill_io(usb3_dp_com);
  2222. dp_catalog_fill_io(dp_mmss_cc);
  2223. dp_catalog_fill_io(hdcp_physical);
  2224. dp_catalog_fill_io(dp_p1);
  2225. dp_catalog_fill_io(dp_tcsr);
  2226. }
  2227. static void dp_catalog_set_exe_mode(struct dp_catalog *dp_catalog, char *mode)
  2228. {
  2229. struct dp_catalog_private *catalog;
  2230. if (!dp_catalog) {
  2231. DP_ERR("invalid input\n");
  2232. return;
  2233. }
  2234. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2235. dp_catalog);
  2236. strlcpy(catalog->exe_mode, mode, sizeof(catalog->exe_mode));
  2237. if (!strcmp(catalog->exe_mode, "hw"))
  2238. catalog->parser->clear_io_buf(catalog->parser);
  2239. else
  2240. dp_catalog_get_io_buf(catalog);
  2241. if (!strcmp(catalog->exe_mode, "hw") ||
  2242. !strcmp(catalog->exe_mode, "all")) {
  2243. catalog->read = dp_read_hw;
  2244. catalog->write = dp_write_hw;
  2245. dp_catalog->sub->read = dp_read_sub_hw;
  2246. dp_catalog->sub->write = dp_write_sub_hw;
  2247. } else {
  2248. catalog->read = dp_read_sw;
  2249. catalog->write = dp_write_sw;
  2250. dp_catalog->sub->read = dp_read_sub_sw;
  2251. dp_catalog->sub->write = dp_write_sub_sw;
  2252. }
  2253. }
  2254. static int dp_catalog_init(struct device *dev, struct dp_catalog *dp_catalog,
  2255. struct dp_parser *parser)
  2256. {
  2257. int rc = 0;
  2258. struct dp_catalog_private *catalog = container_of(dp_catalog,
  2259. struct dp_catalog_private, dp_catalog);
  2260. if (parser->hw_cfg.phy_version >= DP_PHY_VERSION_4_2_0)
  2261. dp_catalog->sub = dp_catalog_get_v420(dev, dp_catalog, &catalog->io);
  2262. else if (parser->hw_cfg.phy_version == DP_PHY_VERSION_2_0_0)
  2263. dp_catalog->sub = dp_catalog_get_v200(dev, dp_catalog, &catalog->io);
  2264. else
  2265. goto end;
  2266. if (IS_ERR(dp_catalog->sub)) {
  2267. rc = PTR_ERR(dp_catalog->sub);
  2268. dp_catalog->sub = NULL;
  2269. } else {
  2270. dp_catalog->sub->read = dp_read_sub_hw;
  2271. dp_catalog->sub->write = dp_write_sub_hw;
  2272. }
  2273. end:
  2274. return rc;
  2275. }
  2276. void dp_catalog_put(struct dp_catalog *dp_catalog)
  2277. {
  2278. struct dp_catalog_private *catalog;
  2279. if (!dp_catalog)
  2280. return;
  2281. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2282. dp_catalog);
  2283. if (dp_catalog->sub && dp_catalog->sub->put)
  2284. dp_catalog->sub->put(dp_catalog);
  2285. catalog->parser->clear_io_buf(catalog->parser);
  2286. devm_kfree(catalog->dev, catalog);
  2287. }
  2288. struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser)
  2289. {
  2290. int rc = 0;
  2291. struct dp_catalog *dp_catalog;
  2292. struct dp_catalog_private *catalog;
  2293. struct dp_catalog_aux aux = {
  2294. .read_data = dp_catalog_aux_read_data,
  2295. .write_data = dp_catalog_aux_write_data,
  2296. .write_trans = dp_catalog_aux_write_trans,
  2297. .clear_trans = dp_catalog_aux_clear_trans,
  2298. .reset = dp_catalog_aux_reset,
  2299. .update_aux_cfg = dp_catalog_aux_update_cfg,
  2300. .enable = dp_catalog_aux_enable,
  2301. .setup = dp_catalog_aux_setup,
  2302. .get_irq = dp_catalog_aux_get_irq,
  2303. .clear_hw_interrupts = dp_catalog_aux_clear_hw_interrupts,
  2304. };
  2305. struct dp_catalog_ctrl ctrl = {
  2306. .state_ctrl = dp_catalog_ctrl_state_ctrl,
  2307. .config_ctrl = dp_catalog_ctrl_config_ctrl,
  2308. .lane_mapping = dp_catalog_ctrl_lane_mapping,
  2309. .lane_pnswap = dp_catalog_ctrl_lane_pnswap,
  2310. .mainlink_ctrl = dp_catalog_ctrl_mainlink_ctrl,
  2311. .set_pattern = dp_catalog_ctrl_set_pattern,
  2312. .reset = dp_catalog_ctrl_reset,
  2313. .usb_reset = dp_catalog_ctrl_usb_reset,
  2314. .mainlink_ready = dp_catalog_ctrl_mainlink_ready,
  2315. .enable_irq = dp_catalog_ctrl_enable_irq,
  2316. .phy_reset = dp_catalog_ctrl_phy_reset,
  2317. .phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg,
  2318. .update_vx_px = dp_catalog_ctrl_update_vx_px,
  2319. .get_interrupt = dp_catalog_ctrl_get_interrupt,
  2320. .read_hdcp_status = dp_catalog_ctrl_read_hdcp_status,
  2321. .send_phy_pattern = dp_catalog_ctrl_send_phy_pattern,
  2322. .read_phy_pattern = dp_catalog_ctrl_read_phy_pattern,
  2323. .mst_config = dp_catalog_ctrl_mst_config,
  2324. .trigger_act = dp_catalog_ctrl_trigger_act,
  2325. .read_act_complete_sts = dp_catalog_ctrl_read_act_complete_sts,
  2326. .channel_alloc = dp_catalog_ctrl_channel_alloc,
  2327. .update_rg = dp_catalog_ctrl_update_rg,
  2328. .channel_dealloc = dp_catalog_ctrl_channel_dealloc,
  2329. .fec_config = dp_catalog_ctrl_fec_config,
  2330. .mainlink_levels = dp_catalog_ctrl_mainlink_levels,
  2331. .late_phy_init = dp_catalog_ctrl_late_phy_init,
  2332. };
  2333. struct dp_catalog_hpd hpd = {
  2334. .config_hpd = dp_catalog_hpd_config_hpd,
  2335. .get_interrupt = dp_catalog_hpd_get_interrupt,
  2336. };
  2337. struct dp_catalog_audio audio = {
  2338. .init = dp_catalog_audio_init,
  2339. .config_acr = dp_catalog_audio_config_acr,
  2340. .enable = dp_catalog_audio_enable,
  2341. .config_sdp = dp_catalog_audio_config_sdp,
  2342. .set_header = dp_catalog_audio_set_header,
  2343. .get_header = dp_catalog_audio_get_header,
  2344. };
  2345. struct dp_catalog_panel panel = {
  2346. .timing_cfg = dp_catalog_panel_timing_cfg,
  2347. .config_hdr = dp_catalog_panel_config_hdr,
  2348. .config_sdp = dp_catalog_panel_config_sdp,
  2349. .tpg_config = dp_catalog_panel_tpg_cfg,
  2350. .config_spd = dp_catalog_panel_config_spd,
  2351. .config_misc = dp_catalog_panel_config_misc,
  2352. .set_colorspace = dp_catalog_panel_set_colorspace,
  2353. .config_msa = dp_catalog_panel_config_msa,
  2354. .update_transfer_unit = dp_catalog_panel_update_transfer_unit,
  2355. .config_ctrl = dp_catalog_panel_config_ctrl,
  2356. .config_dto = dp_catalog_panel_config_dto,
  2357. .dsc_cfg = dp_catalog_panel_dsc_cfg,
  2358. .pps_flush = dp_catalog_panel_pps_flush,
  2359. .dhdr_flush = dp_catalog_panel_dhdr_flush,
  2360. .dhdr_busy = dp_catalog_panel_dhdr_busy,
  2361. };
  2362. if (!dev || !parser) {
  2363. DP_ERR("invalid input\n");
  2364. rc = -EINVAL;
  2365. goto error;
  2366. }
  2367. catalog = devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL);
  2368. if (!catalog) {
  2369. rc = -ENOMEM;
  2370. goto error;
  2371. }
  2372. catalog->dev = dev;
  2373. catalog->parser = parser;
  2374. catalog->read = dp_read_hw;
  2375. catalog->write = dp_write_hw;
  2376. dp_catalog_get_io(catalog);
  2377. strlcpy(catalog->exe_mode, "hw", sizeof(catalog->exe_mode));
  2378. dp_catalog = &catalog->dp_catalog;
  2379. dp_catalog->aux = aux;
  2380. dp_catalog->ctrl = ctrl;
  2381. dp_catalog->hpd = hpd;
  2382. dp_catalog->audio = audio;
  2383. dp_catalog->panel = panel;
  2384. rc = dp_catalog_init(dev, dp_catalog, parser);
  2385. if (rc) {
  2386. dp_catalog_put(dp_catalog);
  2387. goto error;
  2388. }
  2389. dp_catalog->set_exe_mode = dp_catalog_set_exe_mode;
  2390. dp_catalog->get_reg_dump = dp_catalog_reg_dump;
  2391. return dp_catalog;
  2392. error:
  2393. return ERR_PTR(rc);
  2394. }