e46707f810
This is requirement change about correcting the registers when populate CFR elements from tlv. Change-Id: I424a0d3ae569dae3378137b84067a30b0fa28413 CRs-Fixed: 3218220
209 lines
6.7 KiB
C
209 lines
6.7 KiB
C
/*
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* Copyright (c) 2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HAL_KIWI_RX_H_
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#define _HAL_KIWI_RX_H_
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#include "qdf_util.h"
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#include "qdf_types.h"
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#include "qdf_lock.h"
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#include "qdf_mem.h"
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#include "qdf_nbuf.h"
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#include "tcl_data_cmd.h"
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//#include "mac_tcl_reg_seq_hwioreg.h"
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#include "phyrx_rssi_legacy.h"
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#include "rx_msdu_start.h"
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#include "tlv_tag_def.h"
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#include "hal_hw_headers.h"
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#include "hal_internal.h"
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#include "cdp_txrx_mon_struct.h"
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#include "qdf_trace.h"
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#include "hal_rx.h"
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#include "hal_tx.h"
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#include "dp_types.h"
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#include "hal_api_mon.h"
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#include "phyrx_other_receive_info_ru_details.h"
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#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
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(uint8_t *)(link_desc_va) + \
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RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
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#define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
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(uint8_t *)(msdu0) + \
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RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
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#define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
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(uint8_t *)(ent_ring_desc) + \
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RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
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#define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
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(uint8_t *)(dst_ring_desc) + \
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REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
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#define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID)
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#define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID)
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#define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_PEER_ID)
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#define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
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do { \
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reg_val &= \
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~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\
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HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
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reg_val |= \
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HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
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AGING_LIST_ENABLE, 1) |\
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HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
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AGING_FLUSH_ENABLE, 1);\
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HAL_REG_WRITE((soc), \
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HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
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REO_REG_REG_BASE), \
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(reg_val)); \
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reg_val = \
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HAL_REG_READ((soc), \
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HWIO_REO_R0_MISC_CTL_ADDR( \
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REO_REG_REG_BASE)); \
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reg_val &= \
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~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
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reg_val |= \
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HAL_SM(HWIO_REO_R0_MISC_CTL, \
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FRAGMENT_DEST_RING, \
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(reo_params)->frag_dst_ring); \
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reg_val &= \
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(~HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK |\
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(REO_REMAP_TCL << HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT)); \
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HAL_REG_WRITE((soc), \
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HWIO_REO_R0_MISC_CTL_ADDR( \
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REO_REG_REG_BASE), \
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(reg_val)); \
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} while (0)
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#define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
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((struct rx_msdu_desc_info *) \
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_OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
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RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
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#define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
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((struct rx_msdu_details *) \
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_OFFSET_TO_BYTE_PTR((link_desc),\
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RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET))
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#if defined(QCA_WIFI_KIWI) && defined(WLAN_CFR_ENABLE) && \
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defined(WLAN_ENH_CFR_ENABLE)
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#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK 0x00000006
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#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB 1
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#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_MSB 2
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#define HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv) \
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((HAL_RX_GET_64((rx_tlv), \
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, \
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RTT_CFR_STATUS) & \
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK) >> \
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB)
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static inline
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void hal_rx_get_bb_info_kiwi(void *rx_tlv,
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void *ppdu_info_hdl)
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{
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struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
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ppdu_info->cfr_info.bb_captured_channel =
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HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
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ppdu_info->cfr_info.bb_captured_timeout =
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HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
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ppdu_info->cfr_info.bb_captured_reason =
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HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
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}
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static inline
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void hal_rx_get_rtt_info_kiwi(void *rx_tlv,
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void *ppdu_info_hdl)
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{
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struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
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ppdu_info->cfr_info.rx_location_info_valid =
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HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RX_LOCATION_INFO_VALID);
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ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RTT_CHE_BUFFER_POINTER_LOW32);
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ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RTT_CHE_BUFFER_POINTER_HIGH8);
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ppdu_info->cfr_info.chan_capture_status =
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HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
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ppdu_info->cfr_info.rx_start_ts =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RX_START_TS);
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ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RTT_CFO_MEASUREMENT);
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ppdu_info->cfr_info.agc_gain_info0 =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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GAIN_CHAIN0);
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ppdu_info->cfr_info.agc_gain_info0 |=
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(((uint32_t)HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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GAIN_CHAIN1)) << 16);
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ppdu_info->cfr_info.agc_gain_info1 =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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GAIN_CHAIN2);
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ppdu_info->cfr_info.agc_gain_info1 |=
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(((uint32_t)HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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GAIN_CHAIN3)) << 16);
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ppdu_info->cfr_info.agc_gain_info2 = 0;
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ppdu_info->cfr_info.agc_gain_info3 = 0;
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ppdu_info->cfr_info.mcs_rate =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RTT_MCS_RATE);
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ppdu_info->cfr_info.gi_type =
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HAL_RX_GET_64(rx_tlv,
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PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
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RTT_GI_TYPE);
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}
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#endif
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#endif
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