872c22a405
Added QCA5424 target header files based on E2R38 under QCA5424 to make fw-api project compatible to host. Update the CE base address for QCA5424. patch_3: updated the E3R42 hw header files Change-Id: I2c0d42d37faa2082199c8b1f97bac31f1d5ddea5 CRs-Fixed: 3822334
386 lines
19 KiB
C
386 lines
19 KiB
C
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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* SPDX-License-Identifier: ISC
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*/
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#ifndef _RECEIVE_USER_INFO_H_
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#define _RECEIVE_USER_INFO_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
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struct receive_user_info {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t phy_ppdu_id : 16,
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user_rssi : 8,
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pkt_type : 4,
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stbc : 1,
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reception_type : 3;
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uint32_t rate_mcs : 4,
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sgi : 2,
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he_ranging_ndp : 1,
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reserved_1a : 1,
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mimo_ss_bitmap : 8,
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receive_bandwidth : 3,
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reserved_1b : 5,
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dl_ofdma_user_index : 8;
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uint32_t dl_ofdma_content_channel : 1,
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reserved_2a : 7,
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nss : 3,
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stream_offset : 3,
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sta_dcm : 1,
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ldpc : 1,
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ru_type_80_0 : 4,
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ru_type_80_1 : 4,
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ru_type_80_2 : 4,
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ru_type_80_3 : 4;
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uint32_t ru_start_index_80_0 : 6,
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reserved_3a : 2,
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ru_start_index_80_1 : 6,
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reserved_3b : 2,
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ru_start_index_80_2 : 6,
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reserved_3c : 2,
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ru_start_index_80_3 : 6,
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reserved_3d : 2;
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uint32_t user_fd_rssi_seg0 : 32;
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uint32_t user_fd_rssi_seg1 : 32;
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uint32_t user_fd_rssi_seg2 : 32;
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uint32_t user_fd_rssi_seg3 : 32;
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#else
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uint32_t reception_type : 3,
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stbc : 1,
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pkt_type : 4,
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user_rssi : 8,
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phy_ppdu_id : 16;
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uint32_t dl_ofdma_user_index : 8,
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reserved_1b : 5,
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receive_bandwidth : 3,
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mimo_ss_bitmap : 8,
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reserved_1a : 1,
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he_ranging_ndp : 1,
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sgi : 2,
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rate_mcs : 4;
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uint32_t ru_type_80_3 : 4,
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ru_type_80_2 : 4,
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ru_type_80_1 : 4,
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ru_type_80_0 : 4,
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ldpc : 1,
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sta_dcm : 1,
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stream_offset : 3,
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nss : 3,
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reserved_2a : 7,
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dl_ofdma_content_channel : 1;
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uint32_t reserved_3d : 2,
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ru_start_index_80_3 : 6,
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reserved_3c : 2,
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ru_start_index_80_2 : 6,
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reserved_3b : 2,
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ru_start_index_80_1 : 6,
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reserved_3a : 2,
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ru_start_index_80_0 : 6;
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uint32_t user_fd_rssi_seg0 : 32;
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uint32_t user_fd_rssi_seg1 : 32;
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uint32_t user_fd_rssi_seg2 : 32;
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uint32_t user_fd_rssi_seg3 : 32;
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#endif
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};
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#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000
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#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0
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#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15
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#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff
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#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000
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#define RECEIVE_USER_INFO_USER_RSSI_LSB 16
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#define RECEIVE_USER_INFO_USER_RSSI_MSB 23
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#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000
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#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000
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#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24
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#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27
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#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000
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#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000
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#define RECEIVE_USER_INFO_STBC_LSB 28
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#define RECEIVE_USER_INFO_STBC_MSB 28
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#define RECEIVE_USER_INFO_STBC_MASK 0x10000000
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#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000
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#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29
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#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31
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#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000
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#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004
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#define RECEIVE_USER_INFO_RATE_MCS_LSB 0
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#define RECEIVE_USER_INFO_RATE_MCS_MSB 3
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#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f
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#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004
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#define RECEIVE_USER_INFO_SGI_LSB 4
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#define RECEIVE_USER_INFO_SGI_MSB 5
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#define RECEIVE_USER_INFO_SGI_MASK 0x00000030
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#define RECEIVE_USER_INFO_HE_RANGING_NDP_OFFSET 0x00000004
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#define RECEIVE_USER_INFO_HE_RANGING_NDP_LSB 6
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#define RECEIVE_USER_INFO_HE_RANGING_NDP_MSB 6
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#define RECEIVE_USER_INFO_HE_RANGING_NDP_MASK 0x00000040
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#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004
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#define RECEIVE_USER_INFO_RESERVED_1A_LSB 7
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#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7
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#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x00000080
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#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004
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#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8
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#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15
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#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00
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#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004
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#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16
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#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18
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#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000
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#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004
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#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19
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#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23
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#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000
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#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004
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#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24
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#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31
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#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000
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#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008
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#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0
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#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0
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#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001
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#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008
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#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1
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#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7
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#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe
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#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008
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#define RECEIVE_USER_INFO_NSS_LSB 8
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#define RECEIVE_USER_INFO_NSS_MSB 10
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#define RECEIVE_USER_INFO_NSS_MASK 0x00000700
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#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008
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#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11
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#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13
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#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800
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#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008
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#define RECEIVE_USER_INFO_STA_DCM_LSB 14
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#define RECEIVE_USER_INFO_STA_DCM_MSB 14
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#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000
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#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008
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#define RECEIVE_USER_INFO_LDPC_LSB 15
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#define RECEIVE_USER_INFO_LDPC_MSB 15
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#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000
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#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008
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#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16
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#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19
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#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000
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#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008
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#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20
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#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23
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#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000
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#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008
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#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24
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#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27
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#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000
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#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008
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#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28
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#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31
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#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f
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#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c
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#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6
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#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7
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#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00
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#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c
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#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14
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#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15
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#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000
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#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c
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#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22
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#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23
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#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29
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#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000
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#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c
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#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30
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#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31
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#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31
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#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff
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#endif
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