872c22a405
Added QCA5424 target header files based on E2R38 under QCA5424 to make fw-api project compatible to host. Update the CE base address for QCA5424. patch_3: updated the E3R42 hw header files Change-Id: I2c0d42d37faa2082199c8b1f97bac31f1d5ddea5 CRs-Fixed: 3822334
118 lines
4.7 KiB
C
118 lines
4.7 KiB
C
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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* SPDX-License-Identifier: ISC
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*/
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#ifndef _MON_BUFFER_ADDR_H_
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#define _MON_BUFFER_ADDR_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4
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#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2
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struct mon_buffer_addr {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t buffer_virt_addr_31_0 : 32;
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uint32_t buffer_virt_addr_63_32 : 32;
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uint32_t dma_length : 12,
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reserved_2a : 4,
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msdu_continuation : 1,
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truncated : 1,
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reserved_2b : 14;
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uint32_t tlv64_padding : 32;
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#else
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uint32_t buffer_virt_addr_31_0 : 32;
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uint32_t buffer_virt_addr_63_32 : 32;
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uint32_t reserved_2b : 14,
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truncated : 1,
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msdu_continuation : 1,
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reserved_2a : 4,
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dma_length : 12;
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uint32_t tlv64_padding : 32;
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#endif
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};
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000
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#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008
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#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0
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#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11
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#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff
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#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008
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#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12
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#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15
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#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000
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#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008
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#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16
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#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16
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#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000
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#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008
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#define MON_BUFFER_ADDR_TRUNCATED_LSB 17
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#define MON_BUFFER_ADDR_TRUNCATED_MSB 17
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#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000
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#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008
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#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18
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#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31
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#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000
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#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008
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#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32
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#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63
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#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000
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#endif
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