872c22a405
Added QCA5424 target header files based on E2R38 under QCA5424 to make fw-api project compatible to host. Update the CE base address for QCA5424. patch_3: updated the E3R42 hw header files Change-Id: I2c0d42d37faa2082199c8b1f97bac31f1d5ddea5 CRs-Fixed: 3822334
196 lines
8.8 KiB
C
196 lines
8.8 KiB
C
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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* SPDX-License-Identifier: ISC
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*/
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#ifndef _HT_SIG_INFO_H_
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#define _HT_SIG_INFO_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_HT_SIG_INFO 2
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struct ht_sig_info {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t mcs : 7,
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cbw : 1,
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length : 16,
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reserved_0 : 8;
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uint32_t smoothing : 1,
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not_sounding : 1,
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ht_reserved : 1,
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aggregation : 1,
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stbc : 2,
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fec_coding : 1,
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short_gi : 1,
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num_ext_sp_str : 2,
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crc : 8,
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signal_tail : 6,
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reserved_1 : 7,
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rx_integrity_check_passed : 1;
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#else
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uint32_t reserved_0 : 8,
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length : 16,
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cbw : 1,
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mcs : 7;
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uint32_t rx_integrity_check_passed : 1,
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reserved_1 : 7,
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signal_tail : 6,
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crc : 8,
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num_ext_sp_str : 2,
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short_gi : 1,
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fec_coding : 1,
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stbc : 2,
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aggregation : 1,
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ht_reserved : 1,
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not_sounding : 1,
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smoothing : 1;
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#endif
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};
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#define HT_SIG_INFO_MCS_OFFSET 0x00000000
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#define HT_SIG_INFO_MCS_LSB 0
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#define HT_SIG_INFO_MCS_MSB 6
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#define HT_SIG_INFO_MCS_MASK 0x0000007f
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#define HT_SIG_INFO_CBW_OFFSET 0x00000000
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#define HT_SIG_INFO_CBW_LSB 7
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#define HT_SIG_INFO_CBW_MSB 7
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#define HT_SIG_INFO_CBW_MASK 0x00000080
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#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000
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#define HT_SIG_INFO_LENGTH_LSB 8
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#define HT_SIG_INFO_LENGTH_MSB 23
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#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00
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#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000
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#define HT_SIG_INFO_RESERVED_0_LSB 24
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#define HT_SIG_INFO_RESERVED_0_MSB 31
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#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000
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#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004
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#define HT_SIG_INFO_SMOOTHING_LSB 0
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#define HT_SIG_INFO_SMOOTHING_MSB 0
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#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001
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#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004
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#define HT_SIG_INFO_NOT_SOUNDING_LSB 1
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#define HT_SIG_INFO_NOT_SOUNDING_MSB 1
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#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002
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#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004
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#define HT_SIG_INFO_HT_RESERVED_LSB 2
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#define HT_SIG_INFO_HT_RESERVED_MSB 2
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#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004
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#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004
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#define HT_SIG_INFO_AGGREGATION_LSB 3
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#define HT_SIG_INFO_AGGREGATION_MSB 3
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#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008
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#define HT_SIG_INFO_STBC_OFFSET 0x00000004
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#define HT_SIG_INFO_STBC_LSB 4
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#define HT_SIG_INFO_STBC_MSB 5
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#define HT_SIG_INFO_STBC_MASK 0x00000030
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#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004
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#define HT_SIG_INFO_FEC_CODING_LSB 6
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#define HT_SIG_INFO_FEC_CODING_MSB 6
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#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040
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#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004
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#define HT_SIG_INFO_SHORT_GI_LSB 7
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#define HT_SIG_INFO_SHORT_GI_MSB 7
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#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080
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#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004
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#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8
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#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9
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#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300
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#define HT_SIG_INFO_CRC_OFFSET 0x00000004
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#define HT_SIG_INFO_CRC_LSB 10
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#define HT_SIG_INFO_CRC_MSB 17
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#define HT_SIG_INFO_CRC_MASK 0x0003fc00
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#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004
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#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18
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#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23
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#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000
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#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004
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#define HT_SIG_INFO_RESERVED_1_LSB 24
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#define HT_SIG_INFO_RESERVED_1_MSB 30
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#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000
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#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
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#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
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#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
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#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
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#endif
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