872c22a405
Added QCA5424 target header files based on E2R38 under QCA5424 to make fw-api project compatible to host. Update the CE base address for QCA5424. patch_3: updated the E3R42 hw header files Change-Id: I2c0d42d37faa2082199c8b1f97bac31f1d5ddea5 CRs-Fixed: 3822334
178 lines
8.0 KiB
C
178 lines
8.0 KiB
C
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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* SPDX-License-Identifier: ISC
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*/
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#ifndef _COEX_TX_STATUS_H_
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#define _COEX_TX_STATUS_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_COEX_TX_STATUS 4
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#define NUM_OF_QWORDS_COEX_TX_STATUS 2
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struct coex_tx_status {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t reserved_0a : 7,
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tx_bw : 3,
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tx_status_reason : 3,
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tx_wait_ack : 1,
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fes_tx_is_gen_frame : 1,
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sch_tx_burst_ongoing : 1,
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current_tx_duration : 16;
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uint32_t next_rx_active_time : 16,
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remaining_fes_time : 16;
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uint32_t tx_antenna_mask : 8,
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shared_ant_tx_pwr : 8,
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other_ant_tx_pwr : 8,
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reserved_2 : 8;
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uint32_t tlv64_padding : 32;
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#else
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uint32_t current_tx_duration : 16,
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sch_tx_burst_ongoing : 1,
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fes_tx_is_gen_frame : 1,
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tx_wait_ack : 1,
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tx_status_reason : 3,
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tx_bw : 3,
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reserved_0a : 7;
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uint32_t remaining_fes_time : 16,
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next_rx_active_time : 16;
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uint32_t reserved_2 : 8,
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other_ant_tx_pwr : 8,
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shared_ant_tx_pwr : 8,
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tx_antenna_mask : 8;
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uint32_t tlv64_padding : 32;
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#endif
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};
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#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000
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#define COEX_TX_STATUS_RESERVED_0A_LSB 0
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#define COEX_TX_STATUS_RESERVED_0A_MSB 6
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#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f
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#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000
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#define COEX_TX_STATUS_TX_BW_LSB 7
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#define COEX_TX_STATUS_TX_BW_MSB 9
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#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380
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#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000
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#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10
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#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12
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#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00
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#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000
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#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13
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#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13
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#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000
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#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000
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#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14
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#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14
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#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000
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#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000
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#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15
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#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15
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#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000
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#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000
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#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16
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#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31
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#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000
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#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000
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#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32
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#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47
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#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000
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#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000
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#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48
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#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63
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#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000
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#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008
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#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0
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#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7
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#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff
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#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008
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#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8
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#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15
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#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00
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#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008
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#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16
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#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23
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#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000
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#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008
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#define COEX_TX_STATUS_RESERVED_2_LSB 24
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#define COEX_TX_STATUS_RESERVED_2_MSB 31
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#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000
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#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008
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#define COEX_TX_STATUS_TLV64_PADDING_LSB 32
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#define COEX_TX_STATUS_TLV64_PADDING_MSB 63
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#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000
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#endif
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