872c22a405
Added QCA5424 target header files based on E2R38 under QCA5424 to make fw-api project compatible to host. Update the CE base address for QCA5424. patch_3: updated the E3R42 hw header files Change-Id: I2c0d42d37faa2082199c8b1f97bac31f1d5ddea5 CRs-Fixed: 3822334
76 lines
2.5 KiB
C
76 lines
2.5 KiB
C
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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* SPDX-License-Identifier: ISC
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*/
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#ifndef _BUFFER_ADDR_INFO_H_
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#define _BUFFER_ADDR_INFO_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
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struct buffer_addr_info {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t buffer_addr_31_0 : 32;
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uint32_t buffer_addr_39_32 : 8,
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return_buffer_manager : 4,
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sw_buffer_cookie : 20;
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#else
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uint32_t buffer_addr_31_0 : 32;
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uint32_t sw_buffer_cookie : 20,
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return_buffer_manager : 4,
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buffer_addr_39_32 : 8;
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#endif
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};
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#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
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#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
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#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
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#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
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#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
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#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
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#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
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#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
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#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
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#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
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#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
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#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
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#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
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#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
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#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
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#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
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#endif
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