d9794d82cd
The sde_hw_blk was meant to be a generic base object for all SDE HW blocks, however, it enforces using a common set of ops which is not practical when blocks have different capabilities. Since this object was never used as intended and is not doing anything functional today, remove the dead weight. Change-Id: If76006c1ae5c62e8d7d77b100837dbaf6c661bd3 Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
354 行
9.8 KiB
C
354 行
9.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_HW_DSPP_H
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#define _SDE_HW_DSPP_H
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struct sde_hw_dspp;
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/**
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* struct sde_hw_dspp_ops - interface to the dspp hardware driver functions
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* Caller must call the init function to get the dspp context for each dspp
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* Assumption is these functions will be called after clocks are enabled
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*/
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struct sde_hw_dspp_ops {
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/**
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* setup_histogram - setup dspp histogram
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_histogram)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* read_histogram - read dspp histogram
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*read_histogram)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* lock_histogram - lock dspp histogram buffer
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*lock_histogram)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_igc - update dspp igc
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_igc)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_pa_hsic - setup dspp pa hsic
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_pa_hsic)(struct sde_hw_dspp *dspp, void *cfg);
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/**
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* setup_pcc - setup dspp pcc
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_pcc)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_sharpening - setup dspp sharpening
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_sharpening)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_pa_memcol_skin - setup dspp memcolor skin
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_pa_memcol_skin)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_pa_memcol_sky - setup dspp memcolor sky
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_pa_memcol_sky)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_pa_memcol_foliage - setup dspp memcolor foliage
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_pa_memcol_foliage)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_pa_memcol_prot - setup dspp memcolor protection
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_pa_memcol_prot)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_sixzone - setup dspp six zone
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_sixzone)(struct sde_hw_dspp *dspp, void *cfg);
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/**
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* setup_danger_safe - setup danger safe LUTS
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_danger_safe)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_pa_dither - setup dspp PA dither
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_pa_dither)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_vlut - setup dspp PA VLUT
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_vlut)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_gc - update dspp gc
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_gc)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_gamut - update dspp gamut
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_gamut)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* validate_ad - check if ad property can be set
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* @ctx: Pointer to dspp context
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* @prop: Pointer to ad property being validated
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*/
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int (*validate_ad)(struct sde_hw_dspp *ctx, u32 *prop);
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/**
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* setup_ad - update the ad property
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to ad configuration
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*/
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void (*setup_ad)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* ad_read_intr_resp - function to get interrupt response for ad
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* @event: Event for which response needs to be read
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* @resp_in: Pointer to u32 where resp ad4 input value is dumped.
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* @resp_out: Pointer to u32 where resp ad4 output value is dumped.
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*/
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void (*ad_read_intr_resp)(struct sde_hw_dspp *ctx, u32 event,
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u32 *resp_in, u32 *resp_out);
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/**
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* setup_ltm_init - setup LTM INIT
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_ltm_init)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_ltm_roi - setup LTM ROI
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_ltm_roi)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_ltm_vlut - setup LTM VLUT
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_ltm_vlut)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_ltm_hist_ctrl - setup LTM histogram control
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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* @enable: feature enable/disable value
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* @iova: aligned hist buffer address
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*/
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void (*setup_ltm_hist_ctrl)(struct sde_hw_dspp *ctx, void *cfg,
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bool enable, u64 iova);
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/**
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* setup_ltm_hist_buffer - setup LTM histogram buffer
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* @ctx: Pointer to dspp context
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* @iova: aligned hist buffer address
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*/
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void (*setup_ltm_hist_buffer)(struct sde_hw_dspp *ctx, u64 iova);
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/**
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* setup_ltm_thresh - setup LTM histogram thresh
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_ltm_thresh)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* ltm_read_intr_status - function to read ltm interrupt status
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* @ctx: Pointer to dspp context
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* @status: Pointer to u32 where ltm status value is dumped.
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*/
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void (*ltm_read_intr_status)(struct sde_hw_dspp *ctx, u32 *status);
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/**
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* clear_ltm_merge_mode - clear LTM merge_mode bit
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* @ctx: Pointer to dspp context
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*/
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void (*clear_ltm_merge_mode)(struct sde_hw_dspp *ctx);
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/**
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* validate_rc_mask - Validate RC mask configuration
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* @ctx: Pointer to dspp context.
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* @cfg: Pointer to configuration.
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* Return: 0 on success, non-zero otherwise.
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*/
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int (*validate_rc_mask)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_rc_mask - Setup RC mask configuration
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* @ctx: Pointer to dspp context.
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* @cfg: Pointer to configuration.
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* Return: 0 on success, non-zero otherwise.
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*/
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int (*setup_rc_mask)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* validate_rc_pu_roi - Validate RC regions in during partial update.
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* @ctx: Pointer to dspp context.
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* @cfg: Pointer to configuration.
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* Return: 0 on success, non-zero otherwise.
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*/
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int (*validate_rc_pu_roi)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_rc_pu_roi - Setup RC regions in during partial update.
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* @ctx: Pointer to dspp context.
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* @cfg: Pointer to configuration.
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* Return: 0 on success, non-zero otherwise.
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*/
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int (*setup_rc_pu_roi)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_rc_data - Program RC mask data
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* @ctx: Pointer to dspp context.
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* @cfg: Pointer to configuration.
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* Return: 0 on success, non-zero otherwise.
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*/
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int (*setup_rc_data)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_spr_init_config - function to configure spr hw block
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_spr_init_config)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_spr_pu_config - function to configure spr hw block pu offsets
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_spr_pu_config)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_demura_cfg - function to program demura cfg
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* @ctx: Pointer to dspp context
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* @status: Pointer to configuration.
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*/
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void (*setup_demura_cfg)(struct sde_hw_dspp *ctx, void *cfg);
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/**
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* setup_demura_backlight_cfg - function to program demura backlight
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* @ctx: Pointer to dspp context
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* @status: Pointer to configuration.
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*/
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void (*setup_demura_backlight_cfg)(struct sde_hw_dspp *ctx, u64 val);
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/**
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* demura_read_plane_status - Query demura plane status
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* @ctx: Pointer to dspp context
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* @status: Demura plane used by DSPP. demura_fetch_planes enum value.
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*/
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void (*demura_read_plane_status)(struct sde_hw_dspp *ctx, u32 *status);
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/**
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* setup_demura_pu_config - function to configure demura hw block pu offsets
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* @ctx: Pointer to dspp context
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* @cfg: Pointer to configuration
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*/
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void (*setup_demura_pu_config)(struct sde_hw_dspp *ctx, void *cfg);
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};
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/**
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* struct sde_hw_dspp - dspp description
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* @base: Hardware block base structure
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* @hw: Block hardware details
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* @hw_top: Block hardware top details
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* @idx: DSPP index
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* @cap: Pointer to layer_cfg
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* @sb_dma_in_use: hint indicating if sb dma is being used for this dspp
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* @ops: Pointer to operations possible for this DSPP
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* @ltm_checksum_support: flag to check if checksum present
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*/
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struct sde_hw_dspp {
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struct sde_hw_blk_reg_map hw;
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/* dspp top */
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struct sde_hw_blk_reg_map hw_top;
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/* dspp */
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enum sde_dspp idx;
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const struct sde_dspp_cfg *cap;
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bool sb_dma_in_use;
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bool ltm_checksum_support;
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/* Ops */
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struct sde_hw_dspp_ops ops;
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};
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/**
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* to_sde_hw_dspp - convert base hw object to sde_hw_dspp container
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* @hw: Pointer to hardware block register map object
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* return: Pointer to hardware block container
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*/
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static inline struct sde_hw_dspp *to_sde_hw_dspp(struct sde_hw_blk_reg_map *hw)
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{
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return container_of(hw, struct sde_hw_dspp, hw);
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}
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/**
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* sde_hw_dspp_init - initializes the dspp hw driver object.
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* should be called once before accessing every dspp.
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* @idx: DSPP index for which driver object is required
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* @addr: Mapped register io address of MDP
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* @Return: pointer to structure or ERR_PTR
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*/
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struct sde_hw_blk_reg_map *sde_hw_dspp_init(enum sde_dspp idx,
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void __iomem *addr,
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struct sde_mdss_cfg *m);
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/**
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* sde_hw_dspp_destroy(): Destroys DSPP driver context
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* @hw: Pointer to hardware block register map object
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*/
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void sde_hw_dspp_destroy(struct sde_hw_blk_reg_map *hw);
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#endif /*_SDE_HW_DSPP_H */
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