d9794d82cd
The sde_hw_blk was meant to be a generic base object for all SDE HW blocks, however, it enforces using a common set of ops which is not practical when blocks have different capabilities. Since this object was never used as intended and is not doing anything functional today, remove the dead weight. Change-Id: If76006c1ae5c62e8d7d77b100837dbaf6c661bd3 Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
127 lines
2.9 KiB
C
127 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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*/
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#include "sde_hw_ds.h"
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#include "sde_formats.h"
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#include "sde_dbg.h"
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#include "sde_kms.h"
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/* Destination scaler TOP registers */
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#define DEST_SCALER_OP_MODE 0x00
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#define DEST_SCALER_HW_VERSION 0x10
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static void sde_hw_ds_setup_opmode(struct sde_hw_ds *hw_ds,
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u32 op_mode)
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{
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struct sde_hw_blk_reg_map *hw = &hw_ds->hw;
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SDE_REG_WRITE(hw, DEST_SCALER_OP_MODE, op_mode);
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}
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static void sde_hw_ds_setup_scaler3(struct sde_hw_ds *hw_ds,
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void *scaler_cfg, void *scaler_lut_cfg)
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{
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struct sde_hw_scaler3_cfg *scl3_cfg = scaler_cfg;
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struct sde_hw_scaler3_lut_cfg *scl3_lut_cfg = scaler_lut_cfg;
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if (!hw_ds || !hw_ds->scl || !scl3_cfg || !scl3_lut_cfg)
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return;
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/*
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* copy LUT values to scaler structure
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*/
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if (scl3_lut_cfg->is_configured) {
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scl3_cfg->dir_lut = scl3_lut_cfg->dir_lut;
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scl3_cfg->dir_len = scl3_lut_cfg->dir_len;
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scl3_cfg->cir_lut = scl3_lut_cfg->cir_lut;
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scl3_cfg->cir_len = scl3_lut_cfg->cir_len;
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scl3_cfg->sep_lut = scl3_lut_cfg->sep_lut;
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scl3_cfg->sep_len = scl3_lut_cfg->sep_len;
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}
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sde_hw_setup_scaler3(&hw_ds->hw, scl3_cfg, hw_ds->scl->version,
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hw_ds->scl->base,
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sde_get_sde_format(DRM_FORMAT_XBGR2101010));
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}
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static void _setup_ds_ops(struct sde_hw_ds_ops *ops, unsigned long features)
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{
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ops->setup_opmode = sde_hw_ds_setup_opmode;
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if (test_bit(SDE_SSPP_SCALER_QSEED3, &features) ||
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test_bit(SDE_SSPP_SCALER_QSEED3LITE, &features))
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ops->setup_scaler = sde_hw_ds_setup_scaler3;
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}
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static struct sde_ds_cfg *_ds_offset(enum sde_ds ds,
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struct sde_mdss_cfg *m,
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void __iomem *addr,
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struct sde_hw_blk_reg_map *b)
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{
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int i;
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if (!m || !addr || !b)
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return ERR_PTR(-EINVAL);
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for (i = 0; i < m->ds_count; i++) {
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if ((ds == m->ds[i].id) &&
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(m->ds[i].top)) {
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b->base_off = addr;
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b->blk_off = m->ds[i].top->base;
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b->length = m->ds[i].top->len;
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b->hw_rev = m->hw_rev;
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b->log_mask = SDE_DBG_MASK_DS;
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return &m->ds[i];
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}
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}
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return ERR_PTR(-EINVAL);
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}
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struct sde_hw_blk_reg_map *sde_hw_ds_init(enum sde_ds idx,
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void __iomem *addr,
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struct sde_mdss_cfg *m)
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{
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struct sde_hw_ds *hw_ds;
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struct sde_ds_cfg *cfg;
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if (!addr || !m)
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return ERR_PTR(-EINVAL);
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hw_ds = kzalloc(sizeof(*hw_ds), GFP_KERNEL);
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if (!hw_ds)
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return ERR_PTR(-ENOMEM);
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cfg = _ds_offset(idx, m, addr, &hw_ds->hw);
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if (IS_ERR_OR_NULL(cfg)) {
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SDE_ERROR("failed to get ds cfg\n");
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kfree(hw_ds);
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return ERR_PTR(-EINVAL);
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}
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/* Assign ops */
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hw_ds->idx = idx;
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hw_ds->scl = cfg;
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_setup_ds_ops(&hw_ds->ops, hw_ds->scl->features);
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if (m->qseed_hw_rev)
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hw_ds->scl->version = m->qseed_hw_rev;
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if (cfg->len) {
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
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hw_ds->hw.blk_off + cfg->base,
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hw_ds->hw.blk_off + cfg->base + cfg->len,
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hw_ds->hw.xin_id);
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}
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return &hw_ds->hw;
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}
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void sde_hw_ds_destroy(struct sde_hw_blk_reg_map *hw)
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{
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if (hw)
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kfree(to_sde_hw_ds(hw));
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}
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