880d405719
git-subtree-dir: qcom/opensource/graphics-kernel git-subtree-mainline:992813d9c1git-subtree-split:b4fdc4c042Change-Id: repo: https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-kernel tag: GRAPHICS.LA.14.0.r1-07700-lanai.0
412 lines
15 KiB
C
412 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include "adreno.h"
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#include "adreno_a3xx.h"
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#include "adreno_perfcounter.h"
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#include "kgsl_device.h"
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/* Bit flag for RBMM_PERFCTR_CTL */
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#define RBBM_PERFCTR_CTL_ENABLE 0x00000001
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#define VBIF2_PERF_CNT_SEL_MASK 0x7F
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/* offset of clear register from select register */
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#define VBIF2_PERF_CLR_REG_SEL_OFF 8
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/* offset of enable register from select register */
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#define VBIF2_PERF_EN_REG_SEL_OFF 16
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/* offset of clear register from the enable register */
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#define VBIF2_PERF_PWR_CLR_REG_EN_OFF 8
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static void a3xx_counter_load(struct adreno_device *adreno_dev,
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struct adreno_perfcount_register *reg)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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int index = reg->load_bit / 32;
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u32 enable = BIT(reg->load_bit & 31);
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kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_VALUE_LO,
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lower_32_bits(reg->value));
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kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_VALUE_HI,
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upper_32_bits(reg->value));
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if (index == 0)
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kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD0, enable);
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else
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kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD1, enable);
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}
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static int a3xx_counter_enable(struct adreno_device *adreno_dev,
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const struct adreno_perfcount_group *group,
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unsigned int counter, unsigned int countable)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_perfcount_register *reg = &group->regs[counter];
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kgsl_regwrite(device, reg->select, countable);
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reg->value = 0;
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return 0;
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}
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static u64 a3xx_counter_read(struct adreno_device *adreno_dev,
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const struct adreno_perfcount_group *group,
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unsigned int counter)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_perfcount_register *reg = &group->regs[counter];
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u32 val, hi, lo;
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kgsl_regread(device, A3XX_RBBM_PERFCTR_CTL, &val);
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kgsl_regwrite(device, A3XX_RBBM_PERFCTR_CTL,
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val & ~RBBM_PERFCTR_CTL_ENABLE);
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kgsl_regread(device, reg->offset, &lo);
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kgsl_regread(device, reg->offset_hi, &hi);
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kgsl_regwrite(device, A3XX_RBBM_PERFCTR_CTL, val);
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return (((u64) hi) << 32) | lo;
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}
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static int a3xx_counter_pwr_enable(struct adreno_device *adreno_dev,
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const struct adreno_perfcount_group *group,
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unsigned int counter, unsigned int countable)
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{
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return 0;
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}
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static u64 a3xx_counter_pwr_read(struct adreno_device *adreno_dev,
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const struct adreno_perfcount_group *group,
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unsigned int counter)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_perfcount_register *reg = &group->regs[counter];
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u32 val, hi, lo;
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kgsl_regread(device, A3XX_RBBM_RBBM_CTL, &val);
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/* Freeze the counter so we can read it */
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if (!counter)
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kgsl_regwrite(device, A3XX_RBBM_RBBM_CTL, val & ~0x10000);
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else
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kgsl_regwrite(device, A3XX_RBBM_RBBM_CTL, val & ~0x20000);
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kgsl_regread(device, reg->offset, &lo);
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kgsl_regread(device, reg->offset_hi, &hi);
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kgsl_regwrite(device, A3XX_RBBM_RBBM_CTL, val);
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return ((((u64) hi) << 32) | lo) + reg->value;
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}
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static int a3xx_counter_vbif_enable(struct adreno_device *adreno_dev,
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const struct adreno_perfcount_group *group,
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unsigned int counter, unsigned int countable)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_perfcount_register *reg = &group->regs[counter];
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if (countable > VBIF2_PERF_CNT_SEL_MASK)
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return -EINVAL;
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/*
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* Write 1, followed by 0 to CLR register for
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* clearing the counter
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*/
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kgsl_regwrite(device,
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reg->select - VBIF2_PERF_CLR_REG_SEL_OFF, 1);
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kgsl_regwrite(device,
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reg->select - VBIF2_PERF_CLR_REG_SEL_OFF, 0);
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kgsl_regwrite(device,
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reg->select, countable & VBIF2_PERF_CNT_SEL_MASK);
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/* enable reg is 8 DWORDS before select reg */
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kgsl_regwrite(device,
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reg->select - VBIF2_PERF_EN_REG_SEL_OFF, 1);
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kgsl_regwrite(device, reg->select, countable);
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reg->value = 0;
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return 0;
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}
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static u64 a3xx_counter_vbif_read(struct adreno_device *adreno_dev,
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const struct adreno_perfcount_group *group,
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unsigned int counter)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_perfcount_register *reg = &group->regs[counter];
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u32 hi, lo;
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/* freeze counter */
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kgsl_regwrite(device, reg->select - VBIF2_PERF_EN_REG_SEL_OFF, 0);
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kgsl_regread(device, reg->offset, &lo);
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kgsl_regread(device, reg->offset_hi, &hi);
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/* un-freeze counter */
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kgsl_regwrite(device, reg->select - VBIF2_PERF_EN_REG_SEL_OFF, 1);
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return ((((u64) hi) << 32) | lo) + reg->value;
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}
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static int a3xx_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
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const struct adreno_perfcount_group *group,
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unsigned int counter, unsigned int countable)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_perfcount_register *reg = &group->regs[counter];
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/*
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* Write 1, followed by 0 to CLR register for
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* clearing the counter
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*/
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kgsl_regwrite(device, reg->select +
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VBIF2_PERF_PWR_CLR_REG_EN_OFF, 1);
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kgsl_regwrite(device, reg->select +
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VBIF2_PERF_PWR_CLR_REG_EN_OFF, 0);
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kgsl_regwrite(device, reg->select, 1);
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reg->value = 0;
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return 0;
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}
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static u64 a3xx_counter_vbif_pwr_read(struct adreno_device *adreno_dev,
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const struct adreno_perfcount_group *group,
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unsigned int counter)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_perfcount_register *reg = &group->regs[counter];
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u32 hi, lo;
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/* freeze counter */
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kgsl_regwrite(device, reg->select, 0);
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kgsl_regread(device, reg->offset, &lo);
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kgsl_regread(device, reg->offset_hi, &hi);
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/* un-freeze counter */
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kgsl_regwrite(device, reg->select, 1);
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return ((((u64) hi) << 32) | lo) + reg->value;
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}
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/*
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* Define the available perfcounter groups - these get used by
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* adreno_perfcounter_get and adreno_perfcounter_put
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*/
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static struct adreno_perfcount_register a3xx_perfcounters_cp[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_CP_0_LO,
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A3XX_RBBM_PERFCTR_CP_0_HI, 0, A3XX_CP_PERFCOUNTER_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_rbbm[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_0_LO,
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A3XX_RBBM_PERFCTR_RBBM_0_HI, 1, A3XX_RBBM_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_1_LO,
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A3XX_RBBM_PERFCTR_RBBM_1_HI, 2, A3XX_RBBM_PERFCOUNTER1_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_pc[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_0_LO,
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A3XX_RBBM_PERFCTR_PC_0_HI, 3, A3XX_PC_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_1_LO,
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A3XX_RBBM_PERFCTR_PC_1_HI, 4, A3XX_PC_PERFCOUNTER1_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_2_LO,
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A3XX_RBBM_PERFCTR_PC_2_HI, 5, A3XX_PC_PERFCOUNTER2_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_3_LO,
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A3XX_RBBM_PERFCTR_PC_3_HI, 6, A3XX_PC_PERFCOUNTER3_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_vfd[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_0_LO,
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A3XX_RBBM_PERFCTR_VFD_0_HI, 7, A3XX_VFD_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_1_LO,
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A3XX_RBBM_PERFCTR_VFD_1_HI, 8, A3XX_VFD_PERFCOUNTER1_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_hlsq[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_0_LO,
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A3XX_RBBM_PERFCTR_HLSQ_0_HI, 9,
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A3XX_HLSQ_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_1_LO,
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A3XX_RBBM_PERFCTR_HLSQ_1_HI, 10,
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A3XX_HLSQ_PERFCOUNTER1_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_2_LO,
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A3XX_RBBM_PERFCTR_HLSQ_2_HI, 11,
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A3XX_HLSQ_PERFCOUNTER2_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_3_LO,
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A3XX_RBBM_PERFCTR_HLSQ_3_HI, 12,
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A3XX_HLSQ_PERFCOUNTER3_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_4_LO,
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A3XX_RBBM_PERFCTR_HLSQ_4_HI, 13,
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A3XX_HLSQ_PERFCOUNTER4_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_5_LO,
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A3XX_RBBM_PERFCTR_HLSQ_5_HI, 14,
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A3XX_HLSQ_PERFCOUNTER5_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_vpc[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_0_LO,
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A3XX_RBBM_PERFCTR_VPC_0_HI, 15, A3XX_VPC_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_1_LO,
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A3XX_RBBM_PERFCTR_VPC_1_HI, 16, A3XX_VPC_PERFCOUNTER1_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_tse[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_0_LO,
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A3XX_RBBM_PERFCTR_TSE_0_HI, 17, A3XX_GRAS_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_1_LO,
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A3XX_RBBM_PERFCTR_TSE_1_HI, 18, A3XX_GRAS_PERFCOUNTER1_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_ras[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_0_LO,
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A3XX_RBBM_PERFCTR_RAS_0_HI, 19, A3XX_GRAS_PERFCOUNTER2_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_1_LO,
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A3XX_RBBM_PERFCTR_RAS_1_HI, 20, A3XX_GRAS_PERFCOUNTER3_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_uche[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_0_LO,
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A3XX_RBBM_PERFCTR_UCHE_0_HI, 21,
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A3XX_UCHE_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_1_LO,
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A3XX_RBBM_PERFCTR_UCHE_1_HI, 22,
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A3XX_UCHE_PERFCOUNTER1_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_2_LO,
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A3XX_RBBM_PERFCTR_UCHE_2_HI, 23,
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A3XX_UCHE_PERFCOUNTER2_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_3_LO,
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A3XX_RBBM_PERFCTR_UCHE_3_HI, 24,
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A3XX_UCHE_PERFCOUNTER3_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_4_LO,
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A3XX_RBBM_PERFCTR_UCHE_4_HI, 25,
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A3XX_UCHE_PERFCOUNTER4_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_5_LO,
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A3XX_RBBM_PERFCTR_UCHE_5_HI, 26,
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A3XX_UCHE_PERFCOUNTER5_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_tp[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_0_LO,
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A3XX_RBBM_PERFCTR_TP_0_HI, 27, A3XX_TP_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_1_LO,
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A3XX_RBBM_PERFCTR_TP_1_HI, 28, A3XX_TP_PERFCOUNTER1_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_2_LO,
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A3XX_RBBM_PERFCTR_TP_2_HI, 29, A3XX_TP_PERFCOUNTER2_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_3_LO,
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A3XX_RBBM_PERFCTR_TP_3_HI, 30, A3XX_TP_PERFCOUNTER3_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_4_LO,
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A3XX_RBBM_PERFCTR_TP_4_HI, 31, A3XX_TP_PERFCOUNTER4_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_5_LO,
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A3XX_RBBM_PERFCTR_TP_5_HI, 32, A3XX_TP_PERFCOUNTER5_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_sp[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_0_LO,
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A3XX_RBBM_PERFCTR_SP_0_HI, 33, A3XX_SP_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_1_LO,
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A3XX_RBBM_PERFCTR_SP_1_HI, 34, A3XX_SP_PERFCOUNTER1_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_2_LO,
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A3XX_RBBM_PERFCTR_SP_2_HI, 35, A3XX_SP_PERFCOUNTER2_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_3_LO,
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A3XX_RBBM_PERFCTR_SP_3_HI, 36, A3XX_SP_PERFCOUNTER3_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_4_LO,
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A3XX_RBBM_PERFCTR_SP_4_HI, 37, A3XX_SP_PERFCOUNTER4_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_5_LO,
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A3XX_RBBM_PERFCTR_SP_5_HI, 38, A3XX_SP_PERFCOUNTER5_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_6_LO,
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A3XX_RBBM_PERFCTR_SP_6_HI, 39, A3XX_SP_PERFCOUNTER6_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_7_LO,
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A3XX_RBBM_PERFCTR_SP_7_HI, 40, A3XX_SP_PERFCOUNTER7_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_rb[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_0_LO,
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A3XX_RBBM_PERFCTR_RB_0_HI, 41, A3XX_RB_PERFCOUNTER0_SELECT },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_1_LO,
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A3XX_RBBM_PERFCTR_RB_1_HI, 42, A3XX_RB_PERFCOUNTER1_SELECT },
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};
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static struct adreno_perfcount_register a3xx_perfcounters_pwr[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PWR_0_LO,
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A3XX_RBBM_PERFCTR_PWR_0_HI, -1, 0 },
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/*
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* A3XX_RBBM_PERFCTR_PWR_1_LO is used for frequency scaling and removed
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* from the pool of available counters
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*/
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};
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static struct adreno_perfcount_register a3xx_perfcounters_vbif2[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW0,
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A3XX_VBIF2_PERF_CNT_HIGH0, -1, A3XX_VBIF2_PERF_CNT_SEL0 },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW1,
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A3XX_VBIF2_PERF_CNT_HIGH1, -1, A3XX_VBIF2_PERF_CNT_SEL1 },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW2,
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A3XX_VBIF2_PERF_CNT_HIGH2, -1, A3XX_VBIF2_PERF_CNT_SEL2 },
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW3,
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A3XX_VBIF2_PERF_CNT_HIGH3, -1, A3XX_VBIF2_PERF_CNT_SEL3 },
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};
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/*
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* Placing EN register in select field since vbif perf counters
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* don't have select register to program
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*/
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static struct adreno_perfcount_register a3xx_perfcounters_vbif2_pwr[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0,
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0, A3XX_VBIF2_PERF_PWR_CNT_LOW0,
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A3XX_VBIF2_PERF_PWR_CNT_HIGH0, -1,
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A3XX_VBIF2_PERF_PWR_CNT_EN0 },
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{ KGSL_PERFCOUNTER_NOT_USED, 0,
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0, A3XX_VBIF2_PERF_PWR_CNT_LOW1,
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A3XX_VBIF2_PERF_PWR_CNT_HIGH1, -1,
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A3XX_VBIF2_PERF_PWR_CNT_EN1 },
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{ KGSL_PERFCOUNTER_NOT_USED, 0,
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0, A3XX_VBIF2_PERF_PWR_CNT_LOW2,
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A3XX_VBIF2_PERF_PWR_CNT_HIGH2, -1,
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A3XX_VBIF2_PERF_PWR_CNT_EN2 },
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};
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#define A3XX_PERFCOUNTER_GROUP(offset, name, enable, read, load) \
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ADRENO_PERFCOUNTER_GROUP(a3xx, offset, name, enable, read, load)
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#define A3XX_PERFCOUNTER_GROUP_FLAGS(offset, name, flags, enable, read, load) \
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ADRENO_PERFCOUNTER_GROUP_FLAGS(a3xx, offset, name, flags, enable, read, load)
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#define A3XX_REGULAR_PERFCOUNTER_GROUP(offset, name) \
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A3XX_PERFCOUNTER_GROUP(offset, name, a3xx_counter_enable,\
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a3xx_counter_read, a3xx_counter_load)
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|
|
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static const struct adreno_perfcount_group
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a3xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_MAX] = {
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A3XX_REGULAR_PERFCOUNTER_GROUP(CP, cp),
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A3XX_REGULAR_PERFCOUNTER_GROUP(RBBM, rbbm),
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A3XX_REGULAR_PERFCOUNTER_GROUP(PC, pc),
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A3XX_REGULAR_PERFCOUNTER_GROUP(VFD, vfd),
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A3XX_REGULAR_PERFCOUNTER_GROUP(HLSQ, hlsq),
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A3XX_REGULAR_PERFCOUNTER_GROUP(VPC, vpc),
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A3XX_REGULAR_PERFCOUNTER_GROUP(TSE, tse),
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A3XX_REGULAR_PERFCOUNTER_GROUP(RAS, ras),
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A3XX_REGULAR_PERFCOUNTER_GROUP(UCHE, uche),
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A3XX_REGULAR_PERFCOUNTER_GROUP(TP, tp),
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A3XX_REGULAR_PERFCOUNTER_GROUP(SP, sp),
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A3XX_REGULAR_PERFCOUNTER_GROUP(RB, rb),
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A3XX_PERFCOUNTER_GROUP_FLAGS(PWR, pwr,
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ADRENO_PERFCOUNTER_GROUP_FIXED,
|
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a3xx_counter_pwr_enable, a3xx_counter_pwr_read, NULL),
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A3XX_PERFCOUNTER_GROUP(VBIF, vbif2,
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a3xx_counter_vbif_enable, a3xx_counter_vbif_read, NULL),
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A3XX_PERFCOUNTER_GROUP_FLAGS(VBIF_PWR, vbif2_pwr,
|
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ADRENO_PERFCOUNTER_GROUP_FIXED,
|
|
a3xx_counter_vbif_pwr_enable, a3xx_counter_vbif_pwr_read,
|
|
NULL),
|
|
|
|
};
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|
|
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const struct adreno_perfcounters adreno_a3xx_perfcounters = {
|
|
a3xx_perfcounter_groups,
|
|
ARRAY_SIZE(a3xx_perfcounter_groups),
|
|
};
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