c3c6bc1e5c
Add regtable definitions for chipsets AR6004,AR6320,AR900B,
AR9888,IPQ4019,QCA9888,QCA9984
Change-Id: Ic018a1396aa36f61ead6d8607feda4711e2a2b07
Acked-by: Venkateswara Swamy Bandaru <vbandaru@codeaurora.org>
CRs-Fixed: 1009050
74 lines
2.5 KiB
C
74 lines
2.5 KiB
C
/*
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* Copyright (c) 2013,2016 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#if defined(AR6320_HEADERS_DEF)
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#define AR6320 1
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#define WLAN_HEADERS 1
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#include "common_drv.h"
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#include "AR6320/hw/apb_map.h"
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#include "AR6320/hw/gpio_reg.h"
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#include "AR6320/hw/rtc_reg.h"
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#include "AR6320/extra/hw/si_reg.h"
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#include "AR6320/hw/mbox_reg.h"
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#include "AR6320/extra/hw/ce_reg_csr.h"
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#include "AR6320/hw/mbox_wlan_host_reg.h"
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#include "soc_addrs.h"
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#include "AR6320/extra/hw/soc_core_reg.h"
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#include "AR6320/hw/pcie_local_reg.h"
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#include "AR6320/hw/soc_pcie_reg.h"
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#ifndef SYSTEM_SLEEP_OFFSET
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#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
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#endif
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#ifndef WLAN_SYSTEM_SLEEP_OFFSET
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#define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
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#endif
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#ifndef WLAN_RESET_CONTROL_OFFSET
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#define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
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#endif
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#ifndef RESET_CONTROL_SI0_RST_MASK
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#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
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#endif
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#ifndef SI_BASE_ADDRESS
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#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
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#endif
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#ifndef PCIE_LOCAL_BASE_ADDRESS
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/* TBDXXX: Eventually, this Base Address will be defined in HW header files */
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#define PCIE_LOCAL_BASE_ADDRESS 0x80000
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#endif
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#ifndef RTC_STATE_V_ON
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#define RTC_STATE_V_ON 3
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#endif
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#define MY_TARGET_DEF AR6320_TARGETdef
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#define MY_HOST_DEF AR6320_HOSTdef
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#define MY_CEREG_DEF AR6320_CE_TARGETdef
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#define MY_TARGET_BOARD_DATA_SZ AR6320_BOARD_DATA_SZ
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#define MY_TARGET_BOARD_EXT_DATA_SZ AR6320_BOARD_EXT_DATA_SZ
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#define DRAM_BASE_ADDRESS TARG_DRAM_START
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#include "targetdef.h"
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#include "hostdef.h"
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#else
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#include "common_drv.h"
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#include "targetdef.h"
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#include "hostdef.h"
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struct targetdef_s *AR6320_TARGETdef;
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struct hostdef_s *AR6320_HOSTdef;
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#endif /* AR6320_HEADERS_DEF */
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