sheenam monga d87a3b89cb qcacld-3.0: Handle bus bandwidth in start and stop modules ...

Currently, bus bandwidth is initialized and deinitialized in
different memory domains which may cause leaks due to async bandwidth
init and deinit.

Fix is to initialize and de-initialize bus bandwidth in active domain.

Change-Id: I67cf9ecdd47c8f3ca6e9b272ca379f0cac9a6c7b
CRs-Fixed: 2568881

2019-12-21 12:15:05 -08:00

..

inc

qcacld-3.0: Remove enable_snr_monitoring from hdd_config struct

2019-12-18 18:56:56 -08:00

src

qcacld-3.0: Handle bus bandwidth in start and stop modules

2019-12-21 12:15:05 -08:00