
Add all drivers for new platforms. Change-Id: Ie9947b0c6f8ddfee7dab6dfa80d6aca62323f4da Signed-off-by: Fei Mao <feim1@codeaurora.org>
214 lines
6.6 KiB
C
214 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* FTS Capacitive touch screen controller (FingerTipS)
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*
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* Copyright (C) 2016-2019, STMicroelectronics Limited.
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* Authors: AMG(Analog Mems Group) <marco.cali@st.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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**************************************************************************
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** STMicroelectronics **
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**************************************************************************
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** marco.cali@st.com **
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**************************************************************************
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* *
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* HW related data **
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* *
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**************************************************************************
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**************************************************************************
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*/
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#ifndef __FTS_HARDWARE_H
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#define __FTS_HARDWARE_H
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//DUMMY BYTES DATA
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#define DUMMY_HW_REG 1
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#define DUMMY_FRAMEBUFFER 1
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#define DUMMY_MEMORY 1
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//DIGITAL CHIP INFO
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#ifdef FTM3_CHIP
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#define DCHIP_ID_0 0x39
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#define DCHIP_ID_1 0x6C
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#else
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#define DCHIP_ID_0 0x36
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#define DCHIP_ID_1 0x70
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#endif
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#ifdef FTM3_CHIP
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#define DCHIP_ID_ADDR 0x0007
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#define DCHIP_FW_VER_ADDR 0x000A
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#else
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#define DCHIP_ID_ADDR 0x0004
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#define DCHIP_FW_VER_ADDR 0x0008
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#endif
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#define DCHIP_FW_VER_BYTE 2
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//CHUNKS
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#define READ_CHUNK (2 * 1024)
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#define WRITE_CHUNK (2 * 1024)
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#define MEMORY_CHUNK (2 * 1024)
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//PROTOCOL INFO
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#ifdef FTM3_CHIP
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#define I2C_SAD 0x49
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#else
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#define I2C_SAD 0x49
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#endif
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#define I2C_INTERFACE //comment if the chip use SPI
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#define ICR_ADDR 0x0024
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#define ICR_SPI_VALUE 0x02
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//SYSTEM RESET INFO
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#ifdef FTM3_CHIP
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#define SYSTEM_RESET_ADDRESS 0x0023
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#define SYSTEM_RESET_VALUE 0x01
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#else
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#define SYSTEM_RESET_ADDRESS 0x0028
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#define SYSTEM_RESET_VALUE 0x80
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#endif
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//INTERRUPT INFO
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#ifdef FTM3_CHIP
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#define IER_ADDR 0x001C
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#else
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#define IER_ADDR 0x002C
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#endif
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#define IER_ENABLE 0x41
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#define IER_DISABLE 0x00
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//FLASH COMMAND
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#define FLASH_CMD_UNLOCK 0xF7
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#ifdef FTM3_CHIP
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#define FLASH_CMD_WRITE_LOWER_64 0xF0
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#define FLASH_CMD_WRITE_UPPER_64 0xF1
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#define FLASH_CMD_BURN 0xF2
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#define FLASH_CMD_ERASE 0xF3
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#define FLASH_CMD_READSTATUS 0xF4
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#else
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#define FLASH_CMD_WRITE_64K 0xF8
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#define FLASH_CMD_READ_REGISTER 0xF9
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#define FLASH_CMD_WRITE_REGISTER 0xFA
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#endif
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//FLASH UNLOCK PARAMETER
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#define FLASH_UNLOCK_CODE0 0x74
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#define FLASH_UNLOCK_CODE1 0x45
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#ifndef FTM3_CHIP
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//FLASH ERASE and DMA PARAMETER
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#define FLASH_ERASE_UNLOCK_CODE0 0x72
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#define FLASH_ERASE_UNLOCK_CODE1 0x03
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#define FLASH_ERASE_UNLOCK_CODE2 0x02
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#define FLASH_ERASE_CODE0 0x02
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#define FLASH_ERASE_CODE1 0xC0
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#define FLASH_DMA_CODE0 0x05
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#define FLASH_DMA_CODE1 0xC0
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#define FLASH_DMA_CONFIG 0x06
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#define FLASH_ERASE_START 0x80
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#define FLASH_NUM_PAGE 64//number of pages
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#define FLASH_CX_PAGE_START 61
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#define FLASH_CX_PAGE_END 62
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#endif
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//FLASH ADDRESS
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#ifdef FTM3_CHIP
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#define FLASH_ADDR_SWITCH_CMD 0x00010000
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#define FLASH_ADDR_CODE 0x00000000
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#define FLASH_ADDR_CONFIG 0x0001E800
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#define FLASH_ADDR_CX 0x0001F000
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#else
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#define ADDR_WARM_BOOT 0x001E
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#define WARM_BOOT_VALUE 0x38
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#define FLASH_ADDR_CODE 0x00000000
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#define FLASH_ADDR_CONFIG 0x0000FC00
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#endif
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//CRC ADDR
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#ifdef FTM3_CHIP
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#define ADDR_CRC_BYTE0 0x00
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#define ADDR_CRC_BYTE1 0x86
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#define CRC_MASK 0x02
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#else
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#define ADDR_CRC_BYTE0 0x00
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#define ADDR_CRC_BYTE1 0x74
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#define CRC_MASK 0x03
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#endif
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//SIZES FW, CODE, CONFIG, MEMH
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#ifdef FTM3_CHIP
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#define FW_HEADER_SIZE 32
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#define FW_SIZE (int)(128*1024)
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#define FW_CODE_SIZE (int)(122*1024)
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#define FW_CONFIG_SIZE (int)(2*1024)
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#define FW_CX_SIZE (int)(FW_SIZE-FW_CODE_SIZE-FW_CONFIG_SIZE)
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#define FW_VER_MEMH_BYTE1 193
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#define FW_VER_MEMH_BYTE0 192
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#define FW_OFF_CONFID_MEMH_BYTE1 2
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#define FW_OFF_CONFID_MEMH_BYTE0 1
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#define FW_BIN_VER_OFFSET 4
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#define FW_BIN_CONFIG_VER_OFFSET (FW_HEADER_SIZE+FW_CODE_SIZE+1)
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#else
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#define FW_HEADER_SIZE 64
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#define FW_HEADER_SIGNATURE 0xAA55AA55
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#define FW_FTB_VER 0x00000001
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#define FW_BYTES_ALIGN 4
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#define FW_BIN_VER_OFFSET 16
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#define FW_BIN_CONFIG_VER_OFFSET 20
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#endif
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//FIFO
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#define FIFO_EVENT_SIZE 8
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#ifdef FTM3_CHIP
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#define FIFO_DEPTH 32
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#else
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#define FIFO_DEPTH 64
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#endif
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#define FIFO_CMD_READONE 0x85
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#define FIFO_CMD_READALL 0x86
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#define FIFO_CMD_LAST 0x87
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#define FIFO_CMD_FLUSH 0xA1
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//CONSTANT TOTAL CX
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#ifdef FTM3_CHIP
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#define CX1_WEIGHT 4
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#define CX2_WEIGHT 1
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#else
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#define CX1_WEIGHT 8
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#define CX2_WEIGHT 1
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#endif
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//OP CODES FOR MEMORY (based on protocol)
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#define FTS_CMD_HW_REG_R 0xB6
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#define FTS_CMD_HW_REG_W 0xB6
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#define FTS_CMD_FRAMEBUFFER_R 0xD0
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#define FTS_CMD_FRAMEBUFFER_W 0xD0
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#endif
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