58e80d75bd
Fix typographical errors spanned over various files in cmn. Change-Id: I9fcf3b7f9bb7d7dd406e6576a60aa4eb783c9ceb CRs-Fixed: 3529628
484 lines
14 KiB
C
484 lines
14 KiB
C
/*
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* Copyright (c) 2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
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*/
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#ifndef _HAL_5332_TX_H_
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#define _HAL_5332_TX_H_
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#include "tcl_data_cmd.h"
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#include "phyrx_rssi_legacy.h"
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#include "hal_internal.h"
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#include "qdf_trace.h"
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#include "hal_rx.h"
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#include "hal_tx.h"
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#include "hal_api_mon.h"
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#include <hal_be_tx.h>
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#define DSCP_TID_TABLE_SIZE 24
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#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
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#define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
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/**
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* hal_tx_set_dscp_tid_map_5332() - Configure default DSCP to TID map table
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* @hal_soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id: mapping table ID - 0-31
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*
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* DSCP are mapped to 8 TID values using TID values programmed
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* in any of the 32 DSCP_TID_MAPS (id = 0-31).
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*
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* Return: none
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*/
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static void hal_tx_set_dscp_tid_map_5332(struct hal_soc *hal_soc, uint8_t *map,
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uint8_t id)
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{
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int i;
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uint32_t addr, cmn_reg_addr;
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uint32_t value = 0, regval;
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uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
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struct hal_soc *soc = (struct hal_soc *)hal_soc;
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if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS_5332)
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return;
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cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
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MAC_TCL_REG_REG_BASE);
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addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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MAC_TCL_REG_REG_BASE,
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id * NUM_WORDS_PER_DSCP_TID_TABLE);
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/* Enable read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval |=
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(1 <<
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HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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/* Write 8 (24 bits) DSCP-TID mappings in each iteration */
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for (i = 0; i < 64; i += 8) {
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value = (map[i] |
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(map[i + 1] << 0x3) |
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(map[i + 2] << 0x6) |
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(map[i + 3] << 0x9) |
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(map[i + 4] << 0xc) |
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(map[i + 5] << 0xf) |
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(map[i + 6] << 0x12) |
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(map[i + 7] << 0x15));
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qdf_mem_copy(&val[cnt], (void *)&value, 3);
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cnt += 3;
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}
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for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
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regval = *(uint32_t *)(val + i);
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HAL_REG_WRITE(soc, addr,
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(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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addr += 4;
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}
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/* Disable read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval &=
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~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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}
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/**
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* hal_tx_update_dscp_tid_5332() - Update the dscp tid map table as updated
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* by the user
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* @soc: HAL SoC context
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* @tid: TID
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* @id: MAP ID
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* @dscp: DSCP_TID map index
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*
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* Return: void
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*/
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static void hal_tx_update_dscp_tid_5332(struct hal_soc *soc, uint8_t tid,
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uint8_t id, uint8_t dscp)
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{
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uint32_t addr, addr1, cmn_reg_addr;
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uint32_t start_value = 0, end_value = 0;
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uint32_t regval;
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uint8_t end_bits = 0;
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uint8_t start_bits = 0;
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uint32_t start_index, end_index;
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cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
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MAC_TCL_REG_REG_BASE);
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addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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MAC_TCL_REG_REG_BASE,
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id * NUM_WORDS_PER_DSCP_TID_TABLE);
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start_index = dscp * HAL_TX_BITS_PER_TID;
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end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
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% HAL_TX_NUM_DSCP_REGISTER_SIZE;
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start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
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addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
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HAL_TX_NUM_DSCP_REGISTER_SIZE));
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if (end_index < start_index) {
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end_bits = end_index + 1;
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start_bits = HAL_TX_BITS_PER_TID - end_bits;
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start_value = tid << start_index;
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end_value = tid >> start_bits;
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addr1 = addr + 4;
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} else {
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start_bits = HAL_TX_BITS_PER_TID - end_bits;
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start_value = tid << start_index;
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addr1 = 0;
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}
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/* Enable read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval |=
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(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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regval = HAL_REG_READ(soc, addr);
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if (end_index < start_index)
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regval &= (~0) >> start_bits;
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else
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regval &= ~(7 << start_index);
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regval |= start_value;
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HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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if (addr1) {
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regval = HAL_REG_READ(soc, addr1);
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regval &= (~0) << end_bits;
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regval |= end_value;
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HAL_REG_WRITE(soc, addr1, (regval &
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HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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}
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/* Disable read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval &=
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~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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}
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#ifdef DP_TX_IMPLICIT_RBM_MAPPING
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#define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
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#define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
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#define RBM_TCL_CMD_CREDIT_OFFSET \
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(HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
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/**
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* hal_tx_config_rbm_mapping_be_5332() - Update return buffer manager ring id
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* @hal_soc_hdl: HAL SoC context
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* @hal_ring_hdl: Source ring pointer
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* @rbm_id: return buffer manager ring id
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*
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* Return: void
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*/
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static inline void
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hal_tx_config_rbm_mapping_be_5332(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl,
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uint8_t rbm_id)
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{
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struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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uint32_t reg_addr = 0;
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uint32_t reg_val = 0;
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uint32_t val = 0;
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uint8_t ring_num;
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enum hal_ring_type ring_type;
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ring_type = srng->ring_type;
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ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id;
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ring_num = srng->ring_id - ring_num;
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reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE);
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if (ring_type == TCL_CMD_CREDIT)
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ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET;
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/* get current value stored in register address */
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val = HAL_REG_READ(hal_soc, reg_addr);
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/* mask out other stored value */
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val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num)));
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reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) <<
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(RBM_MAPPING_SHFT * ring_num));
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/* write rbm mapped value to register address */
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HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
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}
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#else
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static inline void
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hal_tx_config_rbm_mapping_be_5332(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl,
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uint8_t rbm_id)
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{
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}
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#endif
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/**
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* hal_tx_init_cmd_credit_ring_5332() - Initialize command/credit SRNG
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* @hal_soc_hdl: Handle to HAL SoC structure
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* @hal_ring_hdl: Handle to HAL SRNG structure
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*
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* Return: none
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*/
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static inline void
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hal_tx_init_cmd_credit_ring_5332(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl)
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{
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}
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/* TX MONITOR */
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#if defined(WLAN_PKT_CAPTURE_TX_2_0) && defined(TX_MONITOR_WORD_MASK)
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#define TX_FES_SETUP_MASK 0x3
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typedef struct tx_fes_setup_compact_5332 hal_tx_fes_setup_t;
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struct tx_fes_setup_compact_5332 {
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/* DWORD - 0 */
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uint32_t schedule_id;
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/* DWORD - 1 */
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uint32_t reserved_1a : 7, // [0: 6]
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transmit_start_reason : 3, // [7: 9]
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reserved_1b : 13, // [10: 22]
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number_of_users : 6, // [28: 23]
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mu_type : 1, // [29]
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reserved_1c : 2; // [30]
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/* DWORD - 2 */
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uint32_t reserved_2a : 4, // [0: 3]
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ndp_frame : 2, // [4: 5]
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txbf : 1, // [6]
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reserved_2b : 3, // [7: 9]
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static_bandwidth : 3, // [12: 10]
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reserved_2c : 1, // [13]
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transmission_contains_mu_rts : 1, // [14]
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reserved_2d : 17; // [15: 31]
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/* DWORD - 3 */
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uint32_t reserved_3a : 15, // [0: 14]
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mu_ndp : 1, // [15]
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reserved_3b : 11, // [16: 26]
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ndpa : 1, // [27]
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reserved_3c : 4; // [28: 31]
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};
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#define TX_PEER_ENTRY_MASK 0x103
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typedef struct tx_peer_entry_compact_5332 hal_tx_peer_entry_t;
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struct tx_peer_entry_compact_5332 {
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/* DWORD - 0 */
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uint32_t mac_addr_a_31_0 : 32;
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/* DWORD - 1 */
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uint32_t mac_addr_a_47_32 : 16,
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mac_addr_b_15_0 : 16;
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/* DWORD - 2 */
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uint32_t mac_addr_b_47_16 : 32;
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/* DWORD - 3 */
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uint32_t reserved_3 : 32;
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/* DWORD - 16 */
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uint32_t reserved_16 : 32;
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/* DWORD - 17 */
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uint32_t multi_link_addr_crypto_enable : 1,
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reserved_17_a : 15,
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sw_peer_id : 16;
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};
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#define TX_QUEUE_EXT_MASK 0x1
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typedef struct tx_queue_ext_compact_5332 hal_tx_queue_ext_t;
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struct tx_queue_ext_compact_5332 {
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/* DWORD - 0 */
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uint32_t frame_ctl : 16,
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qos_ctl : 16;
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/* DWORD - 1 */
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uint32_t ampdu_flag : 1,
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reserved_1 : 31;
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};
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#define TX_MSDU_START_MASK 0x1
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typedef struct tx_msdu_start_compact_5332 hal_tx_msdu_start_t;
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struct tx_msdu_start_compact_5332 {
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/* DWORD - 0 */
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uint32_t reserved_0 : 32;
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/* DWORD - 1 */
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uint32_t reserved_1 : 32;
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};
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#define TX_MPDU_START_MASK 0x3
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typedef struct tx_mpdu_start_compact_5332 hal_tx_mpdu_start_t;
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struct tx_mpdu_start_compact_5332 {
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/* DWORD - 0 */
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uint32_t mpdu_length : 14,
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frame_not_from_tqm : 1,
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vht_control_present : 1,
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mpdu_header_length : 8,
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retry_count : 7,
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wds : 1;
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/* DWORD - 1 */
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uint32_t pn_31_0 : 32;
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/* DWORD - 2 */
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uint32_t pn_47_32 : 16,
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mpdu_sequence_number : 12,
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raw_already_encrypted : 1,
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frame_type : 2,
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txdma_dropped_mpdu_warning : 1;
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/* DWORD - 3 */
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uint32_t reserved_3 : 32;
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};
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typedef struct rxpcu_user_setup_compact_5332 hal_rxpcu_user_setup_t;
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struct rxpcu_user_setup_compact_5332 {
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};
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#define TX_FES_STATUS_END_MASK 0x7
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typedef struct tx_fes_status_end_compact_5332 hal_tx_fes_status_end_t;
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struct tx_fes_status_end_compact_5332 {
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/* DWORD - 0 */
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uint32_t reserved_0 : 32;
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/* DWORD - 1 */
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struct {
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uint16_t phytx_abort_reason : 8,
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user_number : 6,
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reserved_1a : 2;
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} phytx_abort_request_info_details;
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uint16_t reserved_1b : 12,
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phytx_abort_request_info_valid : 1,
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reserved_1c : 3;
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/* DWORD - 2 */
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uint32_t start_of_frame_timestamp_15_0 : 16,
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start_of_frame_timestamp_31_16 : 16;
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/* DWORD - 3 */
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uint32_t end_of_frame_timestamp_15_0 : 16,
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end_of_frame_timestamp_31_16 : 16;
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/* DWORD - 4 */
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uint32_t terminate_ranging_sequence : 1,
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reserved_4a : 7,
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timing_status : 2,
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response_type : 5,
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r2r_end_status_to_follow : 1,
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transmit_delay : 16;
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/* DWORD - 5 */
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uint32_t reserved_5 : 32;
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};
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#define RESPONSE_END_STATUS_MASK 0xD
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typedef struct response_end_status_compact_5332 hal_response_end_status_t;
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struct response_end_status_compact_5332 {
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/* DWORD - 0 */
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uint32_t coex_bt_tx_while_wlan_tx : 1,
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coex_wan_tx_while_wlan_tx : 1,
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coex_wlan_tx_while_wlan_tx : 1,
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global_data_underflow_warning : 1,
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response_transmit_status : 4,
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phytx_pkt_end_info_valid : 1,
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phytx_abort_request_info_valid : 1,
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generated_response : 3,
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mba_user_count : 7,
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mba_fake_bitmap_count : 7,
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coex_based_tx_bw : 3,
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trig_response_related : 1,
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dpdtrain_done : 1;
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/* DWORD - 1 */
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uint32_t reserved_1 : 32;
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/* DWORD - 4 */
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uint32_t reserved_4 : 32;
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/* DWORD - 5 */
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uint32_t start_of_frame_timestamp_15_0 : 16,
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start_of_frame_timestamp_31_16 : 16;
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/* DWORD - 6 */
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uint32_t end_of_frame_timestamp_15_0 : 16,
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end_of_frame_timestamp_31_16 : 16;
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/* DWORD - 7 */
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uint32_t reserved_7 : 32;
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};
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#define TX_FES_STATUS_PROT_MASK 0x2
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typedef struct tx_fes_status_prot_compact_5332 hal_tx_fes_status_prot_t;
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struct tx_fes_status_prot_compact_5332 {
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/* DWORD - 2 */
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uint32_t start_of_frame_timestamp_15_0 : 16,
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start_of_frame_timestamp_31_16 : 16;
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/* DWROD - 3 */
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uint32_t end_of_frame_timestamp_15_0 : 16,
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end_of_frame_timestamp_31_16 : 16;
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};
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#define PCU_PPDU_SETUP_INIT_MASK 0x1E800000
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typedef struct pcu_ppdu_setup_init_compact_5332 hal_pcu_ppdu_setup_t;
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struct pcu_ppdu_setup_init_compact_5332 {
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/* DWORD - 46 */
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uint32_t reserved_46 : 32;
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/* DWORD - 47 */
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uint32_t r2r_group_id : 6,
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r2r_response_frame_type : 4,
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r2r_sta_partial_aid : 11,
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use_address_fields_for_protection : 1,
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r2r_set_required_response_time : 1,
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reserved_47 : 9;
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/* DWORD - 50 */
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uint32_t reserved_50 : 32;
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/* DWORD - 51 */
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uint32_t protection_frame_ad1_31_0 : 32;
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/* DWORD - 52 */
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uint32_t protection_frame_ad1_47_32 : 16,
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|
protection_frame_ad2_15_0 : 16;
|
|
/* DWORD - 53 */
|
|
uint32_t protection_frame_ad2_47_16 : 32;
|
|
/* DWORD - 54 */
|
|
uint32_t reserved_54 : 32;
|
|
/* DWORD - 55 */
|
|
uint32_t protection_frame_ad3_31_0 : 32;
|
|
/* DWORD - 56 */
|
|
uint32_t protection_frame_ad3_47_32 : 16,
|
|
protection_frame_ad4_15_0 : 16;
|
|
/* DWORD - 57 */
|
|
uint32_t protection_frame_ad4_47_16 : 32;
|
|
};
|
|
|
|
/**
|
|
* hal_txmon_get_word_mask_qca5332() - api to get word mask for tx monitor
|
|
* @wmask: pointer to hal_txmon_word_mask_config_t
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline
|
|
void hal_txmon_get_word_mask_qca5332(void *wmask)
|
|
{
|
|
hal_txmon_word_mask_config_t *word_mask = NULL;
|
|
|
|
word_mask = (hal_txmon_word_mask_config_t *)wmask;
|
|
|
|
word_mask->compaction_enable = 1;
|
|
word_mask->tx_fes_setup = TX_FES_SETUP_MASK;
|
|
word_mask->tx_peer_entry = TX_PEER_ENTRY_MASK;
|
|
word_mask->tx_queue_ext = TX_QUEUE_EXT_MASK;
|
|
word_mask->tx_msdu_start = TX_MSDU_START_MASK;
|
|
word_mask->pcu_ppdu_setup_init = PCU_PPDU_SETUP_INIT_MASK;
|
|
word_mask->tx_mpdu_start = TX_MPDU_START_MASK;
|
|
word_mask->rxpcu_user_setup = 0xFF;
|
|
word_mask->tx_fes_status_end = TX_FES_STATUS_END_MASK;
|
|
word_mask->response_end_status = RESPONSE_END_STATUS_MASK;
|
|
word_mask->tx_fes_status_prot = TX_FES_STATUS_PROT_MASK;
|
|
}
|
|
#endif /* WLAN_PKT_CAPTURE_TX_2_0 && TX_MONITOR_WORD_MASK */
|
|
#endif /* _HAL_5332_TX_H_ */
|