c42af1f62f
Rx patch changes for multichip MLO 1. Create ini for rx ring mask for each chip 2. Configure hash based routing for each chip based on lmac_peer_id_msb 3. Peer setup changes to configure lmac_peer_id_msb to enable hash based routing 4. Rx Replenish changes to provide buffers back to owner SOC of reo ring Change-Id: Ibbe6e81f9e62d88d9bb289a082dd14b4362252c4
83 lines
2.8 KiB
C
83 lines
2.8 KiB
C
/*
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* Copyright (c) 2017-2019, 2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HAL_REO_BE_H_
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#define _HAL_REO_BE_H_
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#include "hal_be_hw_headers.h"
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#include "hal_rx.h"
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#include "hal_reo.h"
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#define HAL_REO_QUEUE_EXT_DESC 10
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#define HAL_MAX_REO2SW_RINGS 8
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#define HAL_NUM_RX_RING_PER_IX_MAP 8
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/* Proto-types */
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void hal_get_ba_aging_timeout_be(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
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uint32_t *value);
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void hal_set_ba_aging_timeout_be(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
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uint32_t value);
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uint32_t hal_get_reo_reg_base_offset_be(void);
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int hal_reo_send_cmd_be(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl,
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enum hal_reo_cmd_type cmd,
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void *params);
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/* REO status ring routines */
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void
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hal_reo_queue_stats_status_be(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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void
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hal_reo_flush_queue_status_be(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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void
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hal_reo_flush_cache_status_be(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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void
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hal_reo_unblock_cache_status_be(hal_ring_desc_t ring_desc,
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hal_soc_handle_t hal_soc_hdl,
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void *st_handle);
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void hal_reo_flush_timeout_list_status_be(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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void hal_reo_desc_thres_reached_status_be(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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void
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hal_reo_rx_update_queue_status_be(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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/**
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* hal_reo_init_cmd_ring_be() - Initialize descriptors of REO command SRNG
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* with command number
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* @hal_soc: Handle to HAL SoC structure
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* @hal_ring: Handle to HAL SRNG structure
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*
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* Return: none
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*/
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void hal_reo_init_cmd_ring_be(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl);
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uint8_t hal_get_tlv_hdr_size_be(void);
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#endif /* _HAL_REO_BE_H_ */
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