b7c18849ae
Replace QCA_WIFI_QCA8074_VP with CONFIG_WIFI_EMULATION_WIFI_3_0 since VP platform is not being used anymore. Most of the parameters present inside QCA_WIFI_QCA8074_VP are related to emulation timeouts. Hence replacing it with a more meaningful flag. Change-Id: I22a0e5803e765333947f1613b376dcc6bd25b5af
860 baris
22 KiB
C
860 baris
22 KiB
C
/*
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* Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/**
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* DOC: if_ahb.c
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*
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* c file for ahb specific implementations.
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*/
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#include "hif.h"
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#include "target_type.h"
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#include "hif_main.h"
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#include "hif_debug.h"
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#include "hif_io32.h"
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#include "ce_main.h"
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#include "ce_api.h"
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#include "ce_tasklet.h"
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#include "if_ahb.h"
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#include "if_pci.h"
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#include "ahb_api.h"
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#include "pci_api.h"
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#include "hif_napi.h"
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#include "qal_vbus_dev.h"
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
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#define IRQF_DISABLED 0x00000020
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#endif
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#define HIF_IC_CE0_IRQ_OFFSET 4
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#define HIF_IC_MAX_IRQ 52
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static uint8_t ic_irqnum[HIF_IC_MAX_IRQ];
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/* integrated chip irq names */
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const char *ic_irqname[HIF_IC_MAX_IRQ] = {
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"misc-pulse1",
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"misc-latch",
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"sw-exception",
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"watchdog",
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"ce0",
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"ce1",
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"ce2",
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"ce3",
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"ce4",
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"ce5",
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"ce6",
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"ce7",
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"ce8",
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"ce9",
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"ce10",
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"ce11",
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"host2wbm-desc-feed",
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"host2reo-re-injection",
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"host2reo-command",
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"host2rxdma-monitor-ring3",
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"host2rxdma-monitor-ring2",
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"host2rxdma-monitor-ring1",
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"reo2ost-exception",
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"wbm2host-rx-release",
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"reo2host-status",
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"reo2host-destination-ring4",
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"reo2host-destination-ring3",
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"reo2host-destination-ring2",
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"reo2host-destination-ring1",
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"rxdma2host-monitor-destination-mac3",
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"rxdma2host-monitor-destination-mac2",
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"rxdma2host-monitor-destination-mac1",
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"ppdu-end-interrupts-mac3",
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"ppdu-end-interrupts-mac2",
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"ppdu-end-interrupts-mac1",
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"rxdma2host-monitor-status-ring-mac3",
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"rxdma2host-monitor-status-ring-mac2",
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"rxdma2host-monitor-status-ring-mac1",
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"host2rxdma-host-buf-ring-mac3",
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"host2rxdma-host-buf-ring-mac2",
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"host2rxdma-host-buf-ring-mac1",
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"rxdma2host-destination-ring-mac3",
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"rxdma2host-destination-ring-mac2",
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"rxdma2host-destination-ring-mac1",
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"host2tcl-input-ring4",
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"host2tcl-input-ring3",
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"host2tcl-input-ring2",
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"host2tcl-input-ring1",
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"wbm2host-tx-completions-ring3",
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"wbm2host-tx-completions-ring2",
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"wbm2host-tx-completions-ring1",
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"tcl2host-status-ring",
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};
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/** hif_ahb_get_irq_name() - get irqname
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* This function gives irqnumber to irqname
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* mapping.
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*
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* @irq_no: irq number
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*
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* Return: irq name
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*/
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const char *hif_ahb_get_irq_name(int irq_no)
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{
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return ic_irqname[irq_no];
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}
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/**
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* hif_disable_isr() - disable isr
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*
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* This function disables isr and kills tasklets
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*
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* @hif_ctx: struct hif_softc
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*
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* Return: void
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*/
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void hif_ahb_disable_isr(struct hif_softc *scn)
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{
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struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
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hif_exec_kill(&scn->osc);
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hif_nointrs(scn);
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ce_tasklet_kill(scn);
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tasklet_kill(&sc->intr_tq);
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qdf_atomic_set(&scn->active_tasklet_cnt, 0);
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qdf_atomic_set(&scn->active_grp_tasklet_cnt, 0);
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}
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/**
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* hif_dump_registers() - dump bus debug registers
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* @scn: struct hif_opaque_softc
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*
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* This function dumps hif bus debug registers
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*
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* Return: 0 for success or error code
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*/
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int hif_ahb_dump_registers(struct hif_softc *hif_ctx)
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{
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int status;
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struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx);
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status = hif_dump_ce_registers(scn);
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if (status)
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HIF_ERROR("%s: Dump CE Registers Failed status %d", __func__,
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status);
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return 0;
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}
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/**
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* hif_ahb_close() - hif_bus_close
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* @scn: pointer to the hif context.
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*
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* This is a callback function for hif_bus_close.
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*
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*
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* Return: n/a
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*/
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void hif_ahb_close(struct hif_softc *scn)
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{
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hif_ce_close(scn);
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}
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/**
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* hif_bus_open() - hif_ahb open
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* @hif_ctx: hif context
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* @bus_type: bus type
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*
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* This is a callback function for hif_bus_open.
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*
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* Return: n/a
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*/
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QDF_STATUS hif_ahb_open(struct hif_softc *hif_ctx, enum qdf_bus_type bus_type)
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{
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struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx);
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qdf_spinlock_create(&sc->irq_lock);
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return hif_ce_open(hif_ctx);
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}
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/**
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* hif_bus_configure() - Configure the bus
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* @scn: pointer to the hif context.
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*
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* This function configure the ahb bus
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*
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* return: 0 for success. nonzero for failure.
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*/
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int hif_ahb_bus_configure(struct hif_softc *scn)
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{
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return hif_pci_bus_configure(scn);
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}
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/**
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* hif_configure_msi_ahb - Configure MSI interrupts
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* @sc : pointer to the hif context
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*
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* return: 0 for success. nonzero for failure.
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*/
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int hif_configure_msi_ahb(struct hif_pci_softc *sc)
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{
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return 0;
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}
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/**
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* hif_ahb_configure_legacy_irq() - Configure Legacy IRQ
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* @sc: pointer to the hif context.
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*
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* This function registers the irq handler and enables legacy interrupts
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*
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* return: 0 for success. nonzero for failure.
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*/
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int hif_ahb_configure_legacy_irq(struct hif_pci_softc *sc)
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{
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int ret = 0;
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struct hif_softc *scn = HIF_GET_SOFTC(sc);
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struct platform_device *pdev = (struct platform_device *)sc->pdev;
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int irq = 0;
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/* do not support MSI or MSI IRQ failed */
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tasklet_init(&sc->intr_tq, wlan_tasklet, (unsigned long)sc);
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qal_vbus_get_irq((struct qdf_pfm_hndl *)pdev, "legacy", &irq);
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if (irq < 0) {
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dev_err(&pdev->dev, "Unable to get irq\n");
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ret = -EFAULT;
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goto end;
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}
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ret = request_irq(irq, hif_pci_legacy_ce_interrupt_handler,
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IRQF_DISABLED, "wlan_ahb", sc);
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if (ret) {
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dev_err(&pdev->dev, "ath_request_irq failed\n");
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ret = -EFAULT;
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goto end;
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}
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sc->irq = irq;
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/* Use Legacy PCI Interrupts */
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hif_write32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS |
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PCIE_INTR_ENABLE_ADDRESS),
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PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
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/* read once to flush */
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hif_read32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS |
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PCIE_INTR_ENABLE_ADDRESS));
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end:
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return ret;
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}
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int hif_ahb_configure_irq(struct hif_pci_softc *sc)
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{
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int ret = 0;
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struct hif_softc *scn = HIF_GET_SOFTC(sc);
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struct platform_device *pdev = (struct platform_device *)sc->pdev;
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struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
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struct CE_attr *host_ce_conf = hif_state->host_ce_config;
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int irq = 0;
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int i;
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/* configure per CE interrupts */
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for (i = 0; i < scn->ce_count; i++) {
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if (host_ce_conf[i].flags & CE_ATTR_DISABLE_INTR)
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continue;
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ret = pfrm_get_irq(&pdev->dev, (struct qdf_pfm_hndl *)pdev,
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ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i],
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HIF_IC_CE0_IRQ_OFFSET + i, &irq);
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if (ret) {
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dev_err(&pdev->dev, "get irq failed\n");
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ret = -EFAULT;
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goto end;
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}
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ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i] = irq;
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ret = pfrm_request_irq(&pdev->dev, irq,
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hif_ahb_interrupt_handler,
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IRQF_TRIGGER_RISING,
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ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i],
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&hif_state->tasklets[i]);
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if (ret) {
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dev_err(&pdev->dev, "ath_request_irq failed\n");
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ret = -EFAULT;
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goto end;
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}
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hif_ahb_irq_enable(scn, i);
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}
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end:
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return ret;
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}
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int hif_ahb_configure_grp_irq(struct hif_softc *scn,
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struct hif_exec_context *hif_ext_group)
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{
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int ret = 0;
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struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
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struct platform_device *pdev = (struct platform_device *)sc->pdev;
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int irq = 0;
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int j;
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/* configure external interrupts */
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hif_ext_group->irq_enable = &hif_ahb_exec_grp_irq_enable;
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hif_ext_group->irq_disable = &hif_ahb_exec_grp_irq_disable;
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hif_ext_group->irq_name = &hif_ahb_get_irq_name;
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hif_ext_group->work_complete = &hif_dummy_grp_done;
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for (j = 0; j < hif_ext_group->numirq; j++) {
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ret = pfrm_get_irq(&pdev->dev, (struct qdf_pfm_hndl *)pdev,
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ic_irqname[hif_ext_group->irq[j]],
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hif_ext_group->irq[j], &irq);
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if (ret) {
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dev_err(&pdev->dev, "get irq failed\n");
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ret = -EFAULT;
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goto end;
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}
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ic_irqnum[hif_ext_group->irq[j]] = irq;
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hif_ext_group->os_irq[j] = irq;
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}
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qdf_spin_lock_irqsave(&hif_ext_group->irq_lock);
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for (j = 0; j < hif_ext_group->numirq; j++) {
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irq = hif_ext_group->os_irq[j];
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irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
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ret = pfrm_request_irq(scn->qdf_dev->dev,
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irq, hif_ext_group_interrupt_handler,
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IRQF_TRIGGER_RISING,
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ic_irqname[hif_ext_group->irq[j]],
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hif_ext_group);
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if (ret) {
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dev_err(&pdev->dev, "ath_request_irq failed\n");
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ret = -EFAULT;
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goto end;
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}
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}
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qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock);
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qdf_spin_lock_irqsave(&hif_ext_group->irq_lock);
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hif_ext_group->irq_requested = true;
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end:
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qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock);
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return ret;
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}
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void hif_ahb_deconfigure_grp_irq(struct hif_softc *scn)
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{
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struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
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struct hif_exec_context *hif_ext_group;
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int i, j;
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int irq = 0;
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/* configure external interrupts */
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for (i = 0; i < hif_state->hif_num_extgroup; i++) {
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hif_ext_group = hif_state->hif_ext_group[i];
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if (hif_ext_group->irq_requested == true) {
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qdf_spin_lock_irqsave(&hif_ext_group->irq_lock);
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hif_ext_group->irq_requested = false;
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for (j = 0; j < hif_ext_group->numirq; j++) {
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irq = hif_ext_group->os_irq[j];
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hif_ext_group->irq_enabled = false;
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irq_clear_status_flags(irq,
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IRQ_DISABLE_UNLAZY);
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}
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qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock);
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/* Avoid holding the irq_lock while freeing the irq
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* as the same lock is being held by the irq handler
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* while disabling the irq. This causes a deadlock
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* between free_irq and irq_handler.
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*/
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for (j = 0; j < hif_ext_group->numirq; j++) {
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irq = hif_ext_group->os_irq[j];
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pfrm_free_irq(scn->qdf_dev->dev,
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irq, hif_ext_group);
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}
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}
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}
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}
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irqreturn_t hif_ahb_interrupt_handler(int irq, void *context)
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{
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struct ce_tasklet_entry *tasklet_entry = context;
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return ce_dispatch_interrupt(tasklet_entry->ce_id, tasklet_entry);
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}
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/**
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* hif_target_sync() : ensure the target is ready
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* @scn: hif control structure
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*
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* Informs fw that we plan to use legacy interupts so that
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* it can begin booting. Ensures that the fw finishes booting
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* before continuing. Should be called before trying to write
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* to the targets other registers for the first time.
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*
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* Return: none
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*/
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int hif_target_sync_ahb(struct hif_softc *scn)
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{
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int val = 0;
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int limit = 0;
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while (limit < 50) {
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hif_write32_mb(scn, scn->mem +
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(SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS),
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PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
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qdf_mdelay(10);
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val = hif_read32_mb(scn, scn->mem +
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(SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS));
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if (val == 0)
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break;
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limit++;
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}
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hif_write32_mb(scn, scn->mem +
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(SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS),
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PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
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hif_write32_mb(scn, scn->mem + FW_INDICATOR_ADDRESS, FW_IND_HOST_READY);
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if (HAS_FW_INDICATOR) {
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int wait_limit = 500;
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int fw_ind = 0;
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while (1) {
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fw_ind = hif_read32_mb(scn, scn->mem +
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FW_INDICATOR_ADDRESS);
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if (fw_ind & FW_IND_INITIALIZED)
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break;
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if (wait_limit-- < 0)
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break;
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hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS |
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PCIE_INTR_ENABLE_ADDRESS),
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PCIE_INTR_FIRMWARE_MASK);
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qdf_mdelay(10);
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}
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if (wait_limit < 0) {
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HIF_TRACE("%s: FW signal timed out", __func__);
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return -EIO;
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}
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HIF_TRACE("%s: Got FW signal, retries = %x", __func__,
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500-wait_limit);
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}
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return 0;
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}
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|
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/**
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* hif_disable_bus() - Disable the bus
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* @scn : pointer to the hif context
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*
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* This function disables the bus and helds the target in reset state
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*
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* Return: none
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*/
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void hif_ahb_disable_bus(struct hif_softc *scn)
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{
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struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
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void __iomem *mem;
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struct platform_device *pdev = (struct platform_device *)sc->pdev;
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struct resource *memres = NULL;
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int mem_pa_size = 0;
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struct hif_target_info *tgt_info = NULL;
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struct qdf_vbus_resource *vmres = NULL;
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QDF_STATUS status;
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tgt_info = &scn->target_info;
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/*Disable WIFI clock input*/
|
|
if (sc->mem) {
|
|
status = pfrm_platform_get_resource(
|
|
scn->qdf_dev->dev,
|
|
(struct qdf_pfm_hndl *)pdev, &vmres,
|
|
IORESOURCE_MEM, 0);
|
|
if (QDF_IS_STATUS_ERROR(status)) {
|
|
HIF_INFO("%s: Failed to get IORESOURCE_MEM\n",
|
|
__func__);
|
|
return;
|
|
}
|
|
memres = (struct resource *)vmres;
|
|
if (memres)
|
|
mem_pa_size = memres->end - memres->start + 1;
|
|
|
|
/* Should not be executed on 8074 platform */
|
|
if ((tgt_info->target_type != TARGET_TYPE_QCA8074) &&
|
|
(tgt_info->target_type != TARGET_TYPE_QCA8074V2) &&
|
|
(tgt_info->target_type != TARGET_TYPE_QCA6018)) {
|
|
hif_ahb_clk_enable_disable(&pdev->dev, 0);
|
|
|
|
hif_ahb_device_reset(scn);
|
|
}
|
|
mem = (void __iomem *)sc->mem;
|
|
if (mem) {
|
|
pfrm_devm_iounmap(&pdev->dev, mem);
|
|
pfrm_devm_release_mem_region(&pdev->dev, scn->mem_pa,
|
|
mem_pa_size);
|
|
sc->mem = NULL;
|
|
}
|
|
}
|
|
scn->mem = NULL;
|
|
}
|
|
|
|
/**
|
|
* hif_enable_bus() - Enable the bus
|
|
* @dev: dev
|
|
* @bdev: bus dev
|
|
* @bid: bus id
|
|
* @type: bus type
|
|
*
|
|
* This function enables the radio bus by enabling necessary
|
|
* clocks and waits for the target to get ready to proceed futher
|
|
*
|
|
* Return: QDF_STATUS
|
|
*/
|
|
QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
|
|
struct device *dev, void *bdev,
|
|
const struct hif_bus_id *bid,
|
|
enum hif_enable_type type)
|
|
{
|
|
int ret = 0;
|
|
int hif_type;
|
|
int target_type;
|
|
const struct platform_device_id *id = (struct platform_device_id *)bid;
|
|
struct platform_device *pdev = bdev;
|
|
struct hif_target_info *tgt_info = NULL;
|
|
struct resource *memres = NULL;
|
|
void __iomem *mem = NULL;
|
|
uint32_t revision_id = 0;
|
|
struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(ol_sc);
|
|
QDF_STATUS status;
|
|
struct qdf_vbus_resource *vmres = NULL;
|
|
|
|
sc->pdev = (struct pci_dev *)pdev;
|
|
sc->dev = &pdev->dev;
|
|
sc->devid = id->driver_data;
|
|
|
|
ret = hif_get_device_type(id->driver_data, revision_id,
|
|
&hif_type, &target_type);
|
|
if (ret < 0) {
|
|
HIF_ERROR("%s: invalid device ret %d id %d revision_id %d",
|
|
__func__, ret, (int)id->driver_data, revision_id);
|
|
return QDF_STATUS_E_FAILURE;
|
|
}
|
|
|
|
status = pfrm_platform_get_resource(&pdev->dev,
|
|
(struct qdf_pfm_hndl *)pdev,
|
|
&vmres,
|
|
IORESOURCE_MEM, 0);
|
|
if (QDF_IS_STATUS_ERROR(status)) {
|
|
HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", __func__);
|
|
return -EIO;
|
|
}
|
|
memres = (struct resource *)vmres;
|
|
if (!memres) {
|
|
HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", __func__);
|
|
return -EIO;
|
|
}
|
|
|
|
ret = pfrm_dma_set_mask(dev, 32);
|
|
if (ret) {
|
|
HIF_INFO("ath: 32-bit DMA not available\n");
|
|
goto err_cleanup1;
|
|
}
|
|
|
|
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
|
|
ret = pfrm_dma_set_mask_and_coherent(dev, 32);
|
|
#else
|
|
ret = pfrm_dma_set_coherent_mask(dev, 32);
|
|
#endif
|
|
if (ret) {
|
|
HIF_ERROR("%s: failed to set dma mask error = %d",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
/* Arrange for access to Target SoC registers. */
|
|
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
|
|
status = pfrm_devm_ioremap_resource(dev,
|
|
(struct qdf_vbus_resource *)memres,
|
|
&mem);
|
|
#else
|
|
status = pfrm_devm_request_and_ioremap(
|
|
dev,
|
|
(struct qdf_vbus_resource *)memres,
|
|
&mem);
|
|
#endif
|
|
if (QDF_IS_STATUS_ERROR(status)) {
|
|
HIF_INFO("ath: ioremap error\n");
|
|
ret = PTR_ERR(mem);
|
|
goto err_cleanup1;
|
|
}
|
|
|
|
sc->mem = mem;
|
|
ol_sc->mem = mem;
|
|
ol_sc->mem_pa = memres->start;
|
|
|
|
tgt_info = hif_get_target_info_handle((struct hif_opaque_softc *)ol_sc);
|
|
|
|
tgt_info->target_type = target_type;
|
|
hif_register_tbl_attach(ol_sc, hif_type);
|
|
hif_target_register_tbl_attach(ol_sc, target_type);
|
|
|
|
if ((tgt_info->target_type != TARGET_TYPE_QCA8074) &&
|
|
(tgt_info->target_type != TARGET_TYPE_QCA8074V2) &&
|
|
(tgt_info->target_type != TARGET_TYPE_QCA6018)) {
|
|
if (hif_ahb_enable_radio(sc, pdev, id) != 0) {
|
|
HIF_INFO("error in enabling soc\n");
|
|
return -EIO;
|
|
}
|
|
|
|
if (hif_target_sync_ahb(ol_sc) < 0) {
|
|
ret = -EIO;
|
|
goto err_target_sync;
|
|
}
|
|
}
|
|
HIF_TRACE("%s: X - hif_type = 0x%x, target_type = 0x%x",
|
|
__func__, hif_type, target_type);
|
|
|
|
return QDF_STATUS_SUCCESS;
|
|
err_target_sync:
|
|
if ((tgt_info->target_type != TARGET_TYPE_QCA8074) &&
|
|
(tgt_info->target_type != TARGET_TYPE_QCA8074V2) &&
|
|
(tgt_info->target_type != TARGET_TYPE_QCA6018)) {
|
|
HIF_INFO("Error: Disabling target\n");
|
|
hif_ahb_disable_bus(ol_sc);
|
|
}
|
|
err_cleanup1:
|
|
return ret;
|
|
}
|
|
|
|
|
|
/**
|
|
* hif_reset_soc() - reset soc
|
|
*
|
|
* @hif_ctx: HIF context
|
|
*
|
|
* This function resets soc and helds the
|
|
* target in reset state
|
|
*
|
|
* Return: void
|
|
*/
|
|
/* Function to reset SoC */
|
|
void hif_ahb_reset_soc(struct hif_softc *hif_ctx)
|
|
{
|
|
hif_ahb_device_reset(hif_ctx);
|
|
}
|
|
|
|
|
|
/**
|
|
* hif_nointrs() - disable IRQ
|
|
*
|
|
* @scn: struct hif_softc
|
|
*
|
|
* This function stops interrupt(s)
|
|
*
|
|
* Return: none
|
|
*/
|
|
void hif_ahb_nointrs(struct hif_softc *scn)
|
|
{
|
|
int i;
|
|
struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
|
|
struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
|
|
struct CE_attr *host_ce_conf = hif_state->host_ce_config;
|
|
|
|
ce_unregister_irq(hif_state, CE_ALL_BITMAP);
|
|
|
|
if (scn->request_irq_done == false)
|
|
return;
|
|
|
|
if (sc->num_msi_intrs > 0) {
|
|
/* MSI interrupt(s) */
|
|
for (i = 0; i < sc->num_msi_intrs; i++) {
|
|
pfrm_free_irq(scn->qdf_dev->dev, sc->irq + i, sc);
|
|
}
|
|
sc->num_msi_intrs = 0;
|
|
} else {
|
|
if (!scn->per_ce_irq) {
|
|
pfrm_free_irq(scn->qdf_dev->dev, sc->irq, sc);
|
|
} else {
|
|
for (i = 0; i < scn->ce_count; i++) {
|
|
if (host_ce_conf[i].flags
|
|
& CE_ATTR_DISABLE_INTR)
|
|
continue;
|
|
|
|
pfrm_free_irq(
|
|
scn->qdf_dev->dev,
|
|
ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i],
|
|
&hif_state->tasklets[i]);
|
|
}
|
|
hif_ahb_deconfigure_grp_irq(scn);
|
|
}
|
|
}
|
|
scn->request_irq_done = false;
|
|
|
|
}
|
|
|
|
/**
|
|
* ce_irq_enable() - enable copy engine IRQ
|
|
* @scn: struct hif_softc
|
|
* @ce_id: ce_id
|
|
*
|
|
* This function enables the interrupt for the radio.
|
|
*
|
|
* Return: N/A
|
|
*/
|
|
void hif_ahb_irq_enable(struct hif_softc *scn, int ce_id)
|
|
{
|
|
uint32_t regval;
|
|
uint32_t reg_offset = 0;
|
|
struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
|
|
struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id];
|
|
struct hif_target_info *tgt_info = &scn->target_info;
|
|
|
|
if (scn->per_ce_irq) {
|
|
if (target_ce_conf->pipedir & PIPEDIR_OUT) {
|
|
reg_offset = HOST_IE_ADDRESS;
|
|
qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
|
|
regval = hif_read32_mb(scn, scn->mem + reg_offset);
|
|
regval |= HOST_IE_REG1_CE_BIT(ce_id);
|
|
hif_write32_mb(scn, scn->mem + reg_offset, regval);
|
|
qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
|
|
}
|
|
if (target_ce_conf->pipedir & PIPEDIR_IN) {
|
|
reg_offset = HOST_IE_ADDRESS_2;
|
|
qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
|
|
regval = hif_read32_mb(scn, scn->mem + reg_offset);
|
|
regval |= HOST_IE_REG2_CE_BIT(ce_id);
|
|
hif_write32_mb(scn, scn->mem + reg_offset, regval);
|
|
if (tgt_info->target_type == TARGET_TYPE_QCA8074 ||
|
|
tgt_info->target_type == TARGET_TYPE_QCA8074V2 ||
|
|
tgt_info->target_type == TARGET_TYPE_QCA6018) {
|
|
/* Enable destination ring interrupts for
|
|
* 8074, 8074V2 and 6018
|
|
*/
|
|
regval = hif_read32_mb(scn, scn->mem +
|
|
HOST_IE_ADDRESS_3);
|
|
regval |= HOST_IE_REG3_CE_BIT(ce_id);
|
|
|
|
hif_write32_mb(scn, scn->mem +
|
|
HOST_IE_ADDRESS_3, regval);
|
|
}
|
|
qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
|
|
}
|
|
} else {
|
|
hif_pci_irq_enable(scn, ce_id);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ce_irq_disable() - disable copy engine IRQ
|
|
* @scn: struct hif_softc
|
|
* @ce_id: ce_id
|
|
*
|
|
* Return: N/A
|
|
*/
|
|
void hif_ahb_irq_disable(struct hif_softc *scn, int ce_id)
|
|
{
|
|
uint32_t regval;
|
|
uint32_t reg_offset = 0;
|
|
struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
|
|
struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id];
|
|
struct hif_target_info *tgt_info = &scn->target_info;
|
|
|
|
if (scn->per_ce_irq) {
|
|
if (target_ce_conf->pipedir & PIPEDIR_OUT) {
|
|
reg_offset = HOST_IE_ADDRESS;
|
|
qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
|
|
regval = hif_read32_mb(scn, scn->mem + reg_offset);
|
|
regval &= ~HOST_IE_REG1_CE_BIT(ce_id);
|
|
hif_write32_mb(scn, scn->mem + reg_offset, regval);
|
|
qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
|
|
}
|
|
if (target_ce_conf->pipedir & PIPEDIR_IN) {
|
|
reg_offset = HOST_IE_ADDRESS_2;
|
|
qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
|
|
regval = hif_read32_mb(scn, scn->mem + reg_offset);
|
|
regval &= ~HOST_IE_REG2_CE_BIT(ce_id);
|
|
hif_write32_mb(scn, scn->mem + reg_offset, regval);
|
|
if (tgt_info->target_type == TARGET_TYPE_QCA8074 ||
|
|
tgt_info->target_type == TARGET_TYPE_QCA8074V2 ||
|
|
tgt_info->target_type == TARGET_TYPE_QCA6018) {
|
|
/* Disable destination ring interrupts for
|
|
* 8074, 8074V2 and 6018
|
|
*/
|
|
regval = hif_read32_mb(scn, scn->mem +
|
|
HOST_IE_ADDRESS_3);
|
|
regval &= ~HOST_IE_REG3_CE_BIT(ce_id);
|
|
|
|
hif_write32_mb(scn, scn->mem +
|
|
HOST_IE_ADDRESS_3, regval);
|
|
}
|
|
qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
|
|
}
|
|
}
|
|
}
|
|
|
|
void hif_ahb_exec_grp_irq_disable(struct hif_exec_context *hif_ext_group)
|
|
{
|
|
int i;
|
|
|
|
qdf_spin_lock_irqsave(&hif_ext_group->irq_lock);
|
|
if (hif_ext_group->irq_enabled) {
|
|
for (i = 0; i < hif_ext_group->numirq; i++) {
|
|
disable_irq_nosync(hif_ext_group->os_irq[i]);
|
|
}
|
|
hif_ext_group->irq_enabled = false;
|
|
}
|
|
qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock);
|
|
}
|
|
|
|
void hif_ahb_exec_grp_irq_enable(struct hif_exec_context *hif_ext_group)
|
|
{
|
|
int i;
|
|
|
|
qdf_spin_lock_irqsave(&hif_ext_group->irq_lock);
|
|
if (hif_ext_group->irq_requested && !hif_ext_group->irq_enabled) {
|
|
for (i = 0; i < hif_ext_group->numirq; i++) {
|
|
enable_irq(hif_ext_group->os_irq[i]);
|
|
}
|
|
hif_ext_group->irq_enabled = true;
|
|
}
|
|
qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock);
|
|
}
|
|
|
|
/**
|
|
* hif_ahb_needs_bmi() - return true if the soc needs bmi through the driver
|
|
* @scn: hif context
|
|
*
|
|
* Return: true if soc needs driver bmi otherwise false
|
|
*/
|
|
bool hif_ahb_needs_bmi(struct hif_softc *scn)
|
|
{
|
|
return !ce_srng_based(scn);
|
|
}
|
|
|
|
void hif_ahb_display_stats(struct hif_softc *scn)
|
|
{
|
|
if (!scn) {
|
|
HIF_ERROR("%s, hif_scn null", __func__);
|
|
return;
|
|
}
|
|
hif_display_ce_stats(scn);
|
|
}
|
|
|
|
void hif_ahb_clear_stats(struct hif_softc *scn)
|
|
{
|
|
struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
|
|
|
|
if (!hif_state) {
|
|
HIF_ERROR("%s, hif_state null", __func__);
|
|
return;
|
|
}
|
|
hif_clear_ce_stats(hif_state);
|
|
}
|